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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-11-27 11:25:20 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-11-27 11:25:20 -0500
commit842f57baab186417d89810f3dd6147f1ef3009dd (patch)
tree63150a49c6ce3ba28d5a98abbab780b4fe8022dc
parentfc625960edecfb57e62c2975d1f155155e28e6ba (diff)
parenteee47538ec1f26198cf5da675975b61d7f16135b (diff)
Merge tag 'for-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-testing
Kishon writes: Improvements in phy-core specifically on PHY core finds the PHY in the case of non-dt boot. Adds three new PHY drivers using the PHY framework and some miscellaneous fixes and cleanups.
Diffstat
-rw-r--r--Documentation/devicetree/bindings/ata/marvell.txt6
-rw-r--r--Documentation/devicetree/bindings/phy/berlin-sata-phy.txt4
-rw-r--r--Documentation/devicetree/bindings/phy/berlin-usb-phy.txt16
-rw-r--r--Documentation/devicetree/bindings/phy/phy-miphy28lp.txt128
-rw-r--r--Documentation/devicetree/bindings/phy/phy-mvebu.txt43
-rw-r--r--Documentation/devicetree/bindings/phy/samsung-phy.txt6
-rw-r--r--Documentation/phy.txt60
-rw-r--r--drivers/phy/Kconfig23
-rw-r--r--drivers/phy/Makefile3
-rw-r--r--drivers/phy/phy-armada375-usb2.c158
-rw-r--r--drivers/phy/phy-bcm-kona-usb2.c2
-rw-r--r--drivers/phy/phy-berlin-sata.c36
-rw-r--r--drivers/phy/phy-berlin-usb.c223
-rw-r--r--drivers/phy/phy-core.c115
-rw-r--r--drivers/phy/phy-exynos-dp-video.c2
-rw-r--r--drivers/phy/phy-exynos-mipi-video.c2
-rw-r--r--drivers/phy/phy-exynos5-usbdrd.c139
-rw-r--r--drivers/phy/phy-exynos5250-sata.c2
-rw-r--r--drivers/phy/phy-hix5hd2-sata.c7
-rw-r--r--drivers/phy/phy-miphy28lp.c1283
-rw-r--r--drivers/phy/phy-miphy365x.c7
-rw-r--r--drivers/phy/phy-mvebu-sata.c2
-rw-r--r--drivers/phy/phy-omap-usb2.c2
-rw-r--r--drivers/phy/phy-qcom-apq8064-sata.c3
-rw-r--r--drivers/phy/phy-qcom-ipq806x-sata.c3
-rw-r--r--drivers/phy/phy-rcar-gen2.c2
-rw-r--r--drivers/phy/phy-samsung-usb2.c3
-rw-r--r--drivers/phy/phy-spear1310-miphy.c2
-rw-r--r--drivers/phy/phy-spear1340-miphy.c2
-rw-r--r--drivers/phy/phy-stih407-usb.c2
-rw-r--r--drivers/phy/phy-stih41x-usb.c7
-rw-r--r--drivers/phy/phy-sun4i-usb.c11
-rw-r--r--drivers/phy/phy-ti-pipe3.c2
-rw-r--r--drivers/phy/phy-twl4030-usb.c9
-rw-r--r--drivers/phy/phy-xgene.c2
-rw-r--r--drivers/pinctrl/pinctrl-tegra-xusb.c4
-rw-r--r--drivers/usb/dwc3/host.c22
-rw-r--r--include/dt-bindings/phy/phy.h19
-rw-r--r--include/linux/phy/phy.h52
39 files changed, 2210 insertions, 204 deletions
diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt
index 1c8351604d38..b460edd12766 100644
--- a/Documentation/devicetree/bindings/ata/marvell.txt
+++ b/Documentation/devicetree/bindings/ata/marvell.txt
@@ -6,11 +6,17 @@ Required Properties:
6- interrupts : Interrupt controller is using 6- interrupts : Interrupt controller is using
7- nr-ports : Number of SATA ports in use. 7- nr-ports : Number of SATA ports in use.
8 8
9Optional Properties:
10- phys : List of phandles to sata phys
11- phy-names : Should be "0", "1", etc, one number per phandle
12
9Example: 13Example:
10 14
11 sata@80000 { 15 sata@80000 {
12 compatible = "marvell,orion-sata"; 16 compatible = "marvell,orion-sata";
13 reg = <0x80000 0x5000>; 17 reg = <0x80000 0x5000>;
14 interrupts = <21>; 18 interrupts = <21>;
19 phys = <&sata_phy0>, <&sata_phy1>;
20 phy-names = "0", "1";
15 nr-ports = <2>; 21 nr-ports = <2>;
16 } 22 }
diff --git a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
index 88f8c23384c0..c0155f842f62 100644
--- a/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
+++ b/Documentation/devicetree/bindings/phy/berlin-sata-phy.txt
@@ -2,7 +2,9 @@ Berlin SATA PHY
2--------------- 2---------------
3 3
4Required properties: 4Required properties:
5- compatible: should be "marvell,berlin2q-sata-phy" 5- compatible: should be one of
6 "marvell,berlin2-sata-phy"
7 "marvell,berlin2q-sata-phy"
6- address-cells: should be 1 8- address-cells: should be 1
7- size-cells: should be 0 9- size-cells: should be 0
8- phy-cells: from the generic PHY bindings, must be 1 10- phy-cells: from the generic PHY bindings, must be 1
diff --git a/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
new file mode 100644
index 000000000000..be33780f668e
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/berlin-usb-phy.txt
@@ -0,0 +1,16 @@
1* Marvell Berlin USB PHY
2
3Required properties:
4- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"
5- reg: base address and length of the registers
6- #phys-cells: should be 0
7- resets: reference to the reset controller
8
9Example:
10
11 usb-phy@f774000 {
12 compatible = "marvell,berlin2-usb-phy";
13 reg = <0xf774000 0x128>;
14 #phy-cells = <0>;
15 resets = <&chip 0x104 14>;
16 };
diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
new file mode 100644
index 000000000000..46a135dae6b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt
@@ -0,0 +1,128 @@
1STMicroelectronics STi MIPHY28LP PHY binding
2============================================
3
4This binding describes a miphy device that is used to control PHY hardware
5for SATA, PCIe or USB3.
6
7Required properties (controller (parent) node):
8- compatible : Should be "st,miphy28lp-phy".
9- st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
11
12Required nodes : A sub-node is required for each channel the controller
13 provides. Address range information including the usual
14 'reg' and 'reg-names' properties are used inside these
15 nodes to describe the controller's topology. These nodes
16 are translated by the driver's .xlate() function.
17
18Required properties (port (child) node):
19- #phy-cells : Should be 1 (See second example)
20 Cell after port phandle is device type from:
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
24- reg : Address and length of the register set for the device.
25- reg-names : The names of the register addresses corresponding to the registers
26 filled in "reg". It can also contain the offset of the system configuration
27 registers used as glue-logic to setup the device for SATA/PCIe or USB3
28 devices.
29- resets : phandle to the parent reset controller.
30- reset-names : Associated name must be "miphy-sw-rst".
31
32Optional properties (port (child) node):
33- st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This
34 is not available in all the MiPHY. For example, for STiH407, only the
35 MiPHY0 has this bit.
36- st,osc-force-ext : to select the external oscillator. This can change from
37 different MiPHY inside the same SoC.
38- st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config
39 register.
40- st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
41 line).
42- st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe).
43- st,tx-impedance-comp : to compensate tx impedance avoiding out of range values.
44
45example:
46
47 miphy28lp_phy: miphy28lp@9b22000 {
48 compatible = "st,miphy28lp-phy";
49 st,syscfg = <&syscfg_core>;
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 phy_port0: port@9b22000 {
55 reg = <0x9b22000 0xff>,
56 <0x9b09000 0xff>,
57 <0x9b04000 0xff>,
58 <0x114 0x4>, /* sysctrl MiPHY cntrl */
59 <0x818 0x4>, /* sysctrl MiPHY status*/
60 <0xe0 0x4>, /* sysctrl PCIe */
61 <0xec 0x4>; /* sysctrl SATA */
62 reg-names = "sata-up",
63 "pcie-up",
64 "pipew",
65 "miphy-ctrl-glue",
66 "miphy-status-glue",
67 "pcie-glue",
68 "sata-glue";
69 #phy-cells = <1>;
70 st,osc-rdy;
71 reset-names = "miphy-sw-rst";
72 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
73 };
74
75 phy_port1: port@9b2a000 {
76 reg = <0x9b2a000 0xff>,
77 <0x9b19000 0xff>,
78 <0x9b14000 0xff>,
79 <0x118 0x4>,
80 <0x81c 0x4>,
81 <0xe4 0x4>,
82 <0xf0 0x4>;
83 reg-names = "sata-up",
84 "pcie-up",
85 "pipew",
86 "miphy-ctrl-glue",
87 "miphy-status-glue",
88 "pcie-glue",
89 "sata-glue";
90 #phy-cells = <1>;
91 st,osc-force-ext;
92 reset-names = "miphy-sw-rst";
93 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
94 };
95
96 phy_port2: port@8f95000 {
97 reg = <0x8f95000 0xff>,
98 <0x8f90000 0xff>,
99 <0x11c 0x4>,
100 <0x820 0x4>;
101 reg-names = "pipew",
102 "usb3-up",
103 "miphy-ctrl-glue",
104 "miphy-status-glue";
105 #phy-cells = <1>;
106 reset-names = "miphy-sw-rst";
107 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
108 };
109 };
110
111
112Specifying phy control of devices
113=================================
114
115Device nodes should specify the configuration required in their "phys"
116property, containing a phandle to the miphy device node and an index
117specifying which configuration to use, as described in phy-bindings.txt.
118
119example:
120 sata0: sata@9b20000 {
121 ...
122 phys = <&phy_port0 PHY_TYPE_SATA>;
123 ...
124 };
125
126Macro definitions for the supported miphy configuration can be found in:
127
128include/dt-bindings/phy/phy-miphy28lp.h
diff --git a/Documentation/devicetree/bindings/phy/phy-mvebu.txt b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
new file mode 100644
index 000000000000..f95b6260a3b3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mvebu.txt
@@ -0,0 +1,43 @@
1* Marvell MVEBU SATA PHY
2
3Power control for the SATA phy found on Marvell MVEBU SoCs.
4
5This document extends the binding described in phy-bindings.txt
6
7Required properties :
8
9 - reg : Offset and length of the register set for the SATA device
10 - compatible : Should be "marvell,mvebu-sata-phy"
11 - clocks : phandle of clock and specifier that supplies the device
12 - clock-names : Should be "sata"
13
14Example:
15 sata-phy@84000 {
16 compatible = "marvell,mvebu-sata-phy";
17 reg = <0x84000 0x0334>;
18 clocks = <&gate_clk 15>;
19 clock-names = "sata";
20 #phy-cells = <0>;
21 status = "ok";
22 };
23
24Armada 375 USB cluster
25----------------------
26
27Armada 375 comes with an USB2 host and device controller and an USB3
28controller. The USB cluster control register allows to manage common
29features of both USB controllers.
30
31Required properties:
32
33- compatible: "marvell,armada-375-usb-cluster"
34- reg: Should contain usb cluster register location and length.
35- #phy-cells : from the generic phy bindings, must be 1. Possible
36values are 1 (USB2), 2 (USB3).
37
38Example:
39 usbcluster: usb-cluster@18400 {
40 compatible = "marvell,armada-375-usb-cluster";
41 reg = <0x18400 0x4>;
42 #phy-cells = <1>
43 };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 15e0f2c7130f..d5bad920827f 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -128,6 +128,7 @@ Required properties:
128- compatible : Should be set to one of the following supported values: 128- compatible : Should be set to one of the following supported values:
129 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC, 129 - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
130 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC. 130 - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
131 - "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
131- reg : Register offset and length of USB DRD PHY register set; 132- reg : Register offset and length of USB DRD PHY register set;
132- clocks: Clock IDs array as required by the controller 133- clocks: Clock IDs array as required by the controller
133- clock-names: names of clocks correseponding to IDs in the clock property; 134- clock-names: names of clocks correseponding to IDs in the clock property;
@@ -138,6 +139,11 @@ Required properties:
138 PHY operations, associated by phy name. It is used to 139 PHY operations, associated by phy name. It is used to
139 determine bit values for clock settings register. 140 determine bit values for clock settings register.
140 For Exynos5420 this is given as 'sclk_usbphy30' in CMU. 141 For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
142 - optional clocks: Exynos7 SoC has now following additional
143 gate clocks available:
144 - phy_pipe: for PIPE3 phy
145 - phy_utmi: for UTMI+ phy
146 - itp: for ITP generation
141- samsung,pmu-syscon: phandle for PMU system controller interface, used to 147- samsung,pmu-syscon: phandle for PMU system controller interface, used to
142 control pmu registers for power isolation. 148 control pmu registers for power isolation.
143- #phy-cells : from the generic PHY bindings, must be 1; 149- #phy-cells : from the generic PHY bindings, must be 1;
diff --git a/Documentation/phy.txt b/Documentation/phy.txt
index c6594af94d25..371361c69a4b 100644
--- a/Documentation/phy.txt
+++ b/Documentation/phy.txt
@@ -54,18 +54,14 @@ The PHY driver should create the PHY in order for other peripheral controllers
54to make use of it. The PHY framework provides 2 APIs to create the PHY. 54to make use of it. The PHY framework provides 2 APIs to create the PHY.
55 55
56struct phy *phy_create(struct device *dev, struct device_node *node, 56struct phy *phy_create(struct device *dev, struct device_node *node,
57 const struct phy_ops *ops, 57 const struct phy_ops *ops);
58 struct phy_init_data *init_data);
59struct phy *devm_phy_create(struct device *dev, struct device_node *node, 58struct phy *devm_phy_create(struct device *dev, struct device_node *node,
60 const struct phy_ops *ops, 59 const struct phy_ops *ops);
61 struct phy_init_data *init_data);
62 60
63The PHY drivers can use one of the above 2 APIs to create the PHY by passing 61The PHY drivers can use one of the above 2 APIs to create the PHY by passing
64the device pointer, phy ops and init_data. 62the device pointer and phy ops.
65phy_ops is a set of function pointers for performing PHY operations such as 63phy_ops is a set of function pointers for performing PHY operations such as
66init, exit, power_on and power_off. *init_data* is mandatory to get a reference 64init, exit, power_on and power_off.
67to the PHY in the case of non-dt boot. See section *Board File Initialization*
68on how init_data should be used.
69 65
70Inorder to dereference the private data (in phy_ops), the phy provider driver 66Inorder to dereference the private data (in phy_ops), the phy provider driver
71can use phy_set_drvdata() after creating the PHY and use phy_get_drvdata() in 67can use phy_set_drvdata() after creating the PHY and use phy_get_drvdata() in
@@ -137,42 +133,18 @@ There are exported APIs like phy_pm_runtime_get, phy_pm_runtime_get_sync,
137phy_pm_runtime_put, phy_pm_runtime_put_sync, phy_pm_runtime_allow and 133phy_pm_runtime_put, phy_pm_runtime_put_sync, phy_pm_runtime_allow and
138phy_pm_runtime_forbid for performing PM operations. 134phy_pm_runtime_forbid for performing PM operations.
139 135
1408. Board File Initialization 1368. PHY Mappings
141 137
142Certain board file initialization is necessary in order to get a reference 138In order to get reference to a PHY without help from DeviceTree, the framework
143to the PHY in the case of non-dt boot. 139offers lookups which can be compared to clkdev that allow clk structures to be
144Say we have a single device that implements 3 PHYs that of USB, SATA and PCIe, 140bound to devices. A lookup can be made be made during runtime when a handle to
145then in the board file the following initialization should be done. 141the struct phy already exists.
146 142
147struct phy_consumer consumers[] = { 143The framework offers the following API for registering and unregistering the
148 PHY_CONSUMER("dwc3.0", "usb"), 144lookups.
149 PHY_CONSUMER("pcie.0", "pcie"), 145
150 PHY_CONSUMER("sata.0", "sata"), 146int phy_create_lookup(struct phy *phy, const char *con_id, const char *dev_id);
151}; 147void phy_remove_lookup(struct phy *phy, const char *con_id, const char *dev_id);
152PHY_CONSUMER takes 2 parameters, first is the device name of the controller
153(PHY consumer) and second is the port name.
154
155struct phy_init_data init_data = {
156 .consumers = consumers,
157 .num_consumers = ARRAY_SIZE(consumers),
158};
159
160static const struct platform_device pipe3_phy_dev = {
161 .name = "pipe3-phy",
162 .id = -1,
163 .dev = {
164 .platform_data = {
165 .init_data = &init_data,
166 },
167 },
168};
169
170then, while doing phy_create, the PHY driver should pass this init_data
171 phy_create(dev, ops, pdata->init_data);
172
173and the controller driver (phy consumer) should pass the port name along with
174the device to get a reference to the PHY
175 phy_get(dev, "pcie");
176 148
1779. DeviceTree Binding 1499. DeviceTree Binding
178 150
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2a436e607f99..ccad8809ecb1 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -15,6 +15,13 @@ config GENERIC_PHY
15 phy users can obtain reference to the PHY. All the users of this 15 phy users can obtain reference to the PHY. All the users of this
16 framework should select this config. 16 framework should select this config.
17 17
18config PHY_BERLIN_USB
19 tristate "Marvell Berlin USB PHY Driver"
20 depends on ARCH_BERLIN && RESET_CONTROLLER && HAS_IOMEM && OF
21 select GENERIC_PHY
22 help
23 Enable this to support the USB PHY on Marvell Berlin SoCs.
24
18config PHY_BERLIN_SATA 25config PHY_BERLIN_SATA
19 tristate "Marvell Berlin SATA PHY driver" 26 tristate "Marvell Berlin SATA PHY driver"
20 depends on ARCH_BERLIN && HAS_IOMEM && OF 27 depends on ARCH_BERLIN && HAS_IOMEM && OF
@@ -22,6 +29,12 @@ config PHY_BERLIN_SATA
22 help 29 help
23 Enable this to support the SATA PHY on Marvell Berlin SoCs. 30 Enable this to support the SATA PHY on Marvell Berlin SoCs.
24 31
32config ARMADA375_USBCLUSTER_PHY
33 def_bool y
34 depends on MACH_ARMADA_375 || COMPILE_TEST
35 depends on OF
36 select GENERIC_PHY
37
25config PHY_EXYNOS_MIPI_VIDEO 38config PHY_EXYNOS_MIPI_VIDEO
26 tristate "S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver" 39 tristate "S5P/EXYNOS SoC series MIPI CSI-2/DSI PHY driver"
27 depends on HAS_IOMEM 40 depends on HAS_IOMEM
@@ -38,6 +51,14 @@ config PHY_MVEBU_SATA
38 depends on OF 51 depends on OF
39 select GENERIC_PHY 52 select GENERIC_PHY
40 53
54config PHY_MIPHY28LP
55 tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407"
56 depends on ARCH_STI
57 select GENERIC_PHY
58 help
59 Enable this to support the miphy transceiver (for SATA/PCIE/USB3)
60 that is part of STMicroelectronics STiH407 SoC.
61
41config PHY_MIPHY365X 62config PHY_MIPHY365X
42 tristate "STMicroelectronics MIPHY365X PHY driver for STiH41x series" 63 tristate "STMicroelectronics MIPHY365X PHY driver for STiH41x series"
43 depends on ARCH_STI 64 depends on ARCH_STI
@@ -193,7 +214,7 @@ config PHY_EXYNOS5250_USB2
193 214
194config PHY_EXYNOS5_USBDRD 215config PHY_EXYNOS5_USBDRD
195 tristate "Exynos5 SoC series USB DRD PHY driver" 216 tristate "Exynos5 SoC series USB DRD PHY driver"
196 depends on ARCH_EXYNOS5 && OF 217 depends on ARCH_EXYNOS && OF
197 depends on HAS_IOMEM 218 depends on HAS_IOMEM
198 depends on USB_DWC3_EXYNOS 219 depends on USB_DWC3_EXYNOS
199 select GENERIC_PHY 220 select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c4590fce082f..aa74f961e44e 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -3,11 +3,14 @@
3# 3#
4 4
5obj-$(CONFIG_GENERIC_PHY) += phy-core.o 5obj-$(CONFIG_GENERIC_PHY) += phy-core.o
6obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
6obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o 7obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
8obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o
7obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o 9obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
8obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o 10obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
9obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o 11obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
10obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o 12obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
13obj-$(CONFIG_PHY_MIPHY28LP) += phy-miphy28lp.o
11obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o 14obj-$(CONFIG_PHY_MIPHY365X) += phy-miphy365x.o
12obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o 15obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o
13obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o 16obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
diff --git a/drivers/phy/phy-armada375-usb2.c b/drivers/phy/phy-armada375-usb2.c
new file mode 100644
index 000000000000..ac7d99d01cb3
--- /dev/null
+++ b/drivers/phy/phy-armada375-usb2.c
@@ -0,0 +1,158 @@
1/*
2 * USB cluster support for Armada 375 platform.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 *
12 * Armada 375 comes with an USB2 host and device controller and an
13 * USB3 controller. The USB cluster control register allows to manage
14 * common features of both USB controllers.
15 */
16
17#include <dt-bindings/phy/phy.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of_address.h>
23#include <linux/phy/phy.h>
24#include <linux/platform_device.h>
25
26#define USB2_PHY_CONFIG_DISABLE BIT(0)
27
28struct armada375_cluster_phy {
29 struct phy *phy;
30 void __iomem *reg;
31 bool use_usb3;
32 int phy_provided;
33};
34
35static int armada375_usb_phy_init(struct phy *phy)
36{
37 struct armada375_cluster_phy *cluster_phy;
38 u32 reg;
39
40 cluster_phy = dev_get_drvdata(phy->dev.parent);
41 if (!cluster_phy)
42 return -ENODEV;
43
44 reg = readl(cluster_phy->reg);
45 if (cluster_phy->use_usb3)
46 reg |= USB2_PHY_CONFIG_DISABLE;
47 else
48 reg &= ~USB2_PHY_CONFIG_DISABLE;
49 writel(reg, cluster_phy->reg);
50
51 return 0;
52}
53
54static struct phy_ops armada375_usb_phy_ops = {
55 .init = armada375_usb_phy_init,
56 .owner = THIS_MODULE,
57};
58
59/*
60 * Only one controller can use this PHY. We shouldn't have the case
61 * when two controllers want to use this PHY. But if this case occurs
62 * then we provide a phy to the first one and return an error for the
63 * next one. This error has also to be an error returned by
64 * devm_phy_optional_get() so different from ENODEV for USB2. In the
65 * USB3 case it still optional and we use ENODEV.
66 */
67static struct phy *armada375_usb_phy_xlate(struct device *dev,
68 struct of_phandle_args *args)
69{
70 struct armada375_cluster_phy *cluster_phy = dev_get_drvdata(dev);
71
72 if (!cluster_phy)
73 return ERR_PTR(-ENODEV);
74
75 /*
76 * Either the phy had never been requested and then the first
77 * usb claiming it can get it, or it had already been
78 * requested in this case, we only allow to use it with the
79 * same configuration.
80 */
81 if (WARN_ON((cluster_phy->phy_provided != PHY_NONE) &&
82 (cluster_phy->phy_provided != args->args[0]))) {
83 dev_err(dev, "This PHY has already been provided!\n");
84 dev_err(dev, "Check your device tree, only one controller can use it\n.");
85 if (args->args[0] == PHY_TYPE_USB2)
86 return ERR_PTR(-EBUSY);
87 else
88 return ERR_PTR(-ENODEV);
89 }
90
91 if (args->args[0] == PHY_TYPE_USB2)
92 cluster_phy->use_usb3 = false;
93 else if (args->args[0] == PHY_TYPE_USB3)
94 cluster_phy->use_usb3 = true;
95 else {
96 dev_err(dev, "Invalid PHY mode\n");
97 return ERR_PTR(-ENODEV);
98 }
99
100 /* Store which phy mode is used for next test */
101 cluster_phy->phy_provided = args->args[0];
102
103 return cluster_phy->phy;
104}
105
106static int armada375_usb_phy_probe(struct platform_device *pdev)
107{
108 struct device *dev = &pdev->dev;
109 struct phy *phy;
110 struct phy_provider *phy_provider;
111 void __iomem *usb_cluster_base;
112 struct resource *res;
113 struct armada375_cluster_phy *cluster_phy;
114
115 cluster_phy = devm_kzalloc(dev, sizeof(*cluster_phy), GFP_KERNEL);
116 if (!cluster_phy)
117 return -ENOMEM;
118
119 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
120 usb_cluster_base = devm_ioremap_resource(&pdev->dev, res);
121 if (!usb_cluster_base)
122 return -ENOMEM;
123
124 phy = devm_phy_create(dev, NULL, &armada375_usb_phy_ops);
125 if (IS_ERR(phy)) {
126 dev_err(dev, "failed to create PHY\n");
127 return PTR_ERR(phy);
128 }
129
130 cluster_phy->phy = phy;
131 cluster_phy->reg = usb_cluster_base;
132
133 dev_set_drvdata(dev, cluster_phy);
134
135 phy_provider = devm_of_phy_provider_register(&pdev->dev,
136 armada375_usb_phy_xlate);
137 return PTR_ERR_OR_ZERO(phy_provider);
138}
139
140static const struct of_device_id of_usb_cluster_table[] = {
141 { .compatible = "marvell,armada-375-usb-cluster", },
142 { /* end of list */ },
143};
144MODULE_DEVICE_TABLE(of, of_usb_cluster_table);
145
146static struct platform_driver armada375_usb_phy_driver = {
147 .probe = armada375_usb_phy_probe,
148 .driver = {
149 .of_match_table = of_usb_cluster_table,
150 .name = "armada-375-usb-cluster",
151 .owner = THIS_MODULE,
152 }
153};
154module_platform_driver(armada375_usb_phy_driver);
155
156MODULE_DESCRIPTION("Armada 375 USB cluster driver");
157MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
158MODULE_LICENSE("GPL");
diff --git a/drivers/phy/phy-bcm-kona-usb2.c b/drivers/phy/phy-bcm-kona-usb2.c
index c1e0ca335c0e..ef2dc1aab2b9 100644
--- a/drivers/phy/phy-bcm-kona-usb2.c
+++ b/drivers/phy/phy-bcm-kona-usb2.c
@@ -117,7 +117,7 @@ static int bcm_kona_usb2_probe(struct platform_device *pdev)
117 117
118 platform_set_drvdata(pdev, phy); 118 platform_set_drvdata(pdev, phy);
119 119
120 gphy = devm_phy_create(dev, NULL, &ops, NULL); 120 gphy = devm_phy_create(dev, NULL, &ops);
121 if (IS_ERR(gphy)) 121 if (IS_ERR(gphy))
122 return PTR_ERR(gphy); 122 return PTR_ERR(gphy);
123 123
diff --git a/drivers/phy/phy-berlin-sata.c b/drivers/phy/phy-berlin-sata.c
index 69ced52d72aa..099eee8851e5 100644
--- a/drivers/phy/phy-berlin-sata.c
+++ b/drivers/phy/phy-berlin-sata.c
@@ -30,7 +30,8 @@
30#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16) 30#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
31#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19) 31#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
32 32
33#define PHY_BASE 0x200 33#define BG2_PHY_BASE 0x080
34#define BG2Q_PHY_BASE 0x200
34 35
35/* register 0x01 */ 36/* register 0x01 */
36#define REF_FREF_SEL_25 BIT(0) 37#define REF_FREF_SEL_25 BIT(0)
@@ -61,15 +62,16 @@ struct phy_berlin_priv {
61 struct clk *clk; 62 struct clk *clk;
62 struct phy_berlin_desc **phys; 63 struct phy_berlin_desc **phys;
63 unsigned nphys; 64 unsigned nphys;
65 u32 phy_base;
64}; 66};
65 67
66static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, u32 reg, 68static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
67 u32 mask, u32 val) 69 u32 phy_base, u32 reg, u32 mask, u32 val)
68{ 70{
69 u32 regval; 71 u32 regval;
70 72
71 /* select register */ 73 /* select register */
72 writel(PHY_BASE + reg, ctrl_reg + PORT_VSR_ADDR); 74 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
73 75
74 /* set bits */ 76 /* set bits */
75 regval = readl(ctrl_reg + PORT_VSR_DATA); 77 regval = readl(ctrl_reg + PORT_VSR_DATA);
@@ -103,17 +105,20 @@ static int phy_berlin_sata_power_on(struct phy *phy)
103 writel(regval, priv->base + HOST_VSA_DATA); 105 writel(regval, priv->base + HOST_VSA_DATA);
104 106
105 /* set PHY mode and ref freq to 25 MHz */ 107 /* set PHY mode and ref freq to 25 MHz */
106 phy_berlin_sata_reg_setbits(ctrl_reg, 0x1, 0xff, 108 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
107 REF_FREF_SEL_25 | PHY_MODE_SATA); 109 0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA);
108 110
109 /* set PHY up to 6 Gbps */ 111 /* set PHY up to 6 Gbps */
110 phy_berlin_sata_reg_setbits(ctrl_reg, 0x25, 0xc00, PHY_GEN_MAX_6_0); 112 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
113 0x0c00, PHY_GEN_MAX_6_0);
111 114
112 /* set 40 bits width */ 115 /* set 40 bits width */
113 phy_berlin_sata_reg_setbits(ctrl_reg, 0x23, 0xc00, DATA_BIT_WIDTH_40); 116 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
117 0x0c00, DATA_BIT_WIDTH_40);
114 118
115 /* use max pll rate */ 119 /* use max pll rate */
116 phy_berlin_sata_reg_setbits(ctrl_reg, 0x2, 0x0, USE_MAX_PLL_RATE); 120 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
121 0x0000, USE_MAX_PLL_RATE);
117 122
118 /* set Gen3 controller speed */ 123 /* set Gen3 controller speed */
119 regval = readl(ctrl_reg + PORT_SCR_CTL); 124 regval = readl(ctrl_reg + PORT_SCR_CTL);
@@ -218,6 +223,11 @@ static int phy_berlin_sata_probe(struct platform_device *pdev)
218 if (!priv->phys) 223 if (!priv->phys)
219 return -ENOMEM; 224 return -ENOMEM;
220 225
226 if (of_device_is_compatible(dev->of_node, "marvell,berlin2-sata-phy"))
227 priv->phy_base = BG2_PHY_BASE;
228 else
229 priv->phy_base = BG2Q_PHY_BASE;
230
221 dev_set_drvdata(dev, priv); 231 dev_set_drvdata(dev, priv);
222 spin_lock_init(&priv->lock); 232 spin_lock_init(&priv->lock);
223 233
@@ -239,7 +249,7 @@ static int phy_berlin_sata_probe(struct platform_device *pdev)
239 if (!phy_desc) 249 if (!phy_desc)
240 return -ENOMEM; 250 return -ENOMEM;
241 251
242 phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops, NULL); 252 phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops);
243 if (IS_ERR(phy)) { 253 if (IS_ERR(phy)) {
244 dev_err(dev, "failed to create PHY %d\n", phy_id); 254 dev_err(dev, "failed to create PHY %d\n", phy_id);
245 return PTR_ERR(phy); 255 return PTR_ERR(phy);
@@ -258,13 +268,11 @@ static int phy_berlin_sata_probe(struct platform_device *pdev)
258 268
259 phy_provider = 269 phy_provider =
260 devm_of_phy_provider_register(dev, phy_berlin_sata_phy_xlate); 270 devm_of_phy_provider_register(dev, phy_berlin_sata_phy_xlate);
261 if (IS_ERR(phy_provider)) 271 return PTR_ERR_OR_ZERO(phy_provider);
262 return PTR_ERR(phy_provider);
263
264 return 0;
265} 272}
266 273
267static const struct of_device_id phy_berlin_sata_of_match[] = { 274static const struct of_device_id phy_berlin_sata_of_match[] = {
275 { .compatible = "marvell,berlin2-sata-phy" },
268 { .compatible = "marvell,berlin2q-sata-phy" }, 276 { .compatible = "marvell,berlin2q-sata-phy" },
269 { }, 277 { },
270}; 278};
diff --git a/drivers/phy/phy-berlin-usb.c b/drivers/phy/phy-berlin-usb.c
new file mode 100644
index 000000000000..c8a8d53a6ece
--- /dev/null
+++ b/drivers/phy/phy-berlin-usb.c
@@ -0,0 +1,223 @@
1/*
2 * Copyright (C) 2014 Marvell Technology Group Ltd.
3 *
4 * Antoine Tenart <antoine.tenart@free-electrons.com>
5 * Jisheng Zhang <jszhang@marvell.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/gpio.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/of_gpio.h>
17#include <linux/phy/phy.h>
18#include <linux/platform_device.h>
19#include <linux/reset.h>
20
21#define USB_PHY_PLL 0x04
22#define USB_PHY_PLL_CONTROL 0x08
23#define USB_PHY_TX_CTRL0 0x10
24#define USB_PHY_TX_CTRL1 0x14
25#define USB_PHY_TX_CTRL2 0x18
26#define USB_PHY_RX_CTRL 0x20
27#define USB_PHY_ANALOG 0x34
28
29/* USB_PHY_PLL */
30#define CLK_REF_DIV(x) ((x) << 4)
31#define FEEDBACK_CLK_DIV(x) ((x) << 8)
32
33/* USB_PHY_PLL_CONTROL */
34#define CLK_STABLE BIT(0)
35#define PLL_CTRL_PIN BIT(1)
36#define PLL_CTRL_REG BIT(2)
37#define PLL_ON BIT(3)
38#define PHASE_OFF_TOL_125 (0x0 << 5)
39#define PHASE_OFF_TOL_250 BIT(5)
40#define KVC0_CALIB (0x0 << 9)
41#define KVC0_REG_CTRL BIT(9)
42#define KVC0_HIGH (0x0 << 10)
43#define KVC0_LOW (0x3 << 10)
44#define CLK_BLK_EN BIT(13)
45
46/* USB_PHY_TX_CTRL0 */
47#define EXT_HS_RCAL_EN BIT(3)
48#define EXT_FS_RCAL_EN BIT(4)
49#define IMPCAL_VTH_DIV(x) ((x) << 5)
50#define EXT_RS_RCAL_DIV(x) ((x) << 8)
51#define EXT_FS_RCAL_DIV(x) ((x) << 12)
52
53/* USB_PHY_TX_CTRL1 */
54#define TX_VDD15_14 (0x0 << 4)
55#define TX_VDD15_15 BIT(4)
56#define TX_VDD15_16 (0x2 << 4)
57#define TX_VDD15_17 (0x3 << 4)
58#define TX_VDD12_VDD (0x0 << 6)
59#define TX_VDD12_11 BIT(6)
60#define TX_VDD12_12 (0x2 << 6)
61#define TX_VDD12_13 (0x3 << 6)
62#define LOW_VDD_EN BIT(8)
63#define TX_OUT_AMP(x) ((x) << 9)
64
65/* USB_PHY_TX_CTRL2 */
66#define TX_CHAN_CTRL_REG(x) ((x) << 0)
67#define DRV_SLEWRATE(x) ((x) << 4)
68#define IMP_CAL_FS_HS_DLY_0 (0x0 << 6)
69#define IMP_CAL_FS_HS_DLY_1 BIT(6)
70#define IMP_CAL_FS_HS_DLY_2 (0x2 << 6)
71#define IMP_CAL_FS_HS_DLY_3 (0x3 << 6)
72#define FS_DRV_EN_MASK(x) ((x) << 8)
73#define HS_DRV_EN_MASK(x) ((x) << 12)
74
75/* USB_PHY_RX_CTRL */
76#define PHASE_FREEZE_DLY_2_CL (0x0 << 0)
77#define PHASE_FREEZE_DLY_4_CL BIT(0)
78#define ACK_LENGTH_8_CL (0x0 << 2)
79#define ACK_LENGTH_12_CL BIT(2)
80#define ACK_LENGTH_16_CL (0x2 << 2)
81#define ACK_LENGTH_20_CL (0x3 << 2)
82#define SQ_LENGTH_3 (0x0 << 4)
83#define SQ_LENGTH_6 BIT(4)
84#define SQ_LENGTH_9 (0x2 << 4)
85#define SQ_LENGTH_12 (0x3 << 4)
86#define DISCON_THRESHOLD_260 (0x0 << 6)
87#define DISCON_THRESHOLD_270 BIT(6)
88#define DISCON_THRESHOLD_280 (0x2 << 6)
89#define DISCON_THRESHOLD_290 (0x3 << 6)
90#define SQ_THRESHOLD(x) ((x) << 8)
91#define LPF_COEF(x) ((x) << 12)
92#define INTPL_CUR_10 (0x0 << 14)
93#define INTPL_CUR_20 BIT(14)
94#define INTPL_CUR_30 (0x2 << 14)
95#define INTPL_CUR_40 (0x3 << 14)
96
97/* USB_PHY_ANALOG */
98#define ANA_PWR_UP BIT(1)
99#define ANA_PWR_DOWN BIT(2)
100#define V2I_VCO_RATIO(x) ((x) << 7)
101#define R_ROTATE_90 (0x0 << 10)
102#define R_ROTATE_0 BIT(10)
103#define MODE_TEST_EN BIT(11)
104#define ANA_TEST_DC_CTRL(x) ((x) << 12)
105
106#define to_phy_berlin_usb_priv(p) \
107 container_of((p), struct phy_berlin_usb_priv, phy)
108
109static const u32 phy_berlin_pll_dividers[] = {
110 /* Berlin 2 */
111 CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
112 /* Berlin 2CD */
113 CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55),
114};
115
116struct phy_berlin_usb_priv {
117 void __iomem *base;
118 struct phy *phy;
119 struct reset_control *rst_ctrl;
120 u32 pll_divider;
121};
122
123static int phy_berlin_usb_power_on(struct phy *phy)
124{
125 struct phy_berlin_usb_priv *priv = dev_get_drvdata(phy->dev.parent);
126
127 reset_control_reset(priv->rst_ctrl);
128
129 writel(priv->pll_divider,
130 priv->base + USB_PHY_PLL);
131 writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
132 CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL);
133 writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
134 priv->base + USB_PHY_ANALOG);
135 writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
136 DISCON_THRESHOLD_260 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) |
137 INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL);
138
139 writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
140 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
141 priv->base + USB_PHY_TX_CTRL0);
142
143 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
144 EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0);
145
146 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
147 priv->base + USB_PHY_TX_CTRL0);
148 writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
149 FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2);
150
151 return 0;
152}
153
154static struct phy_ops phy_berlin_usb_ops = {
155 .power_on = phy_berlin_usb_power_on,
156 .owner = THIS_MODULE,
157};
158
159static const struct of_device_id phy_berlin_sata_of_match[] = {
160 {
161 .compatible = "marvell,berlin2-usb-phy",
162 .data = &phy_berlin_pll_dividers[0],
163 },
164 {
165 .compatible = "marvell,berlin2cd-usb-phy",
166 .data = &phy_berlin_pll_dividers[1],
167 },
168 { },
169};
170MODULE_DEVICE_TABLE(of, phy_berlin_sata_of_match);
171
172static int phy_berlin_usb_probe(struct platform_device *pdev)
173{
174 const struct of_device_id *match =
175 of_match_device(phy_berlin_sata_of_match, &pdev->dev);
176 struct phy_berlin_usb_priv *priv;
177 struct resource *res;
178 struct phy_provider *phy_provider;
179
180 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
181 if (!priv)
182 return -ENOMEM;
183
184 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
185 priv->base = devm_ioremap_resource(&pdev->dev, res);
186 if (IS_ERR(priv->base))
187 return PTR_ERR(priv->base);
188
189 priv->rst_ctrl = devm_reset_control_get(&pdev->dev, NULL);
190 if (IS_ERR(priv->rst_ctrl))
191 return PTR_ERR(priv->rst_ctrl);
192
193 priv->pll_divider = *((u32 *)match->data);
194
195 priv->phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
196 if (IS_ERR(priv->phy)) {
197 dev_err(&pdev->dev, "failed to create PHY\n");
198 return PTR_ERR(priv->phy);
199 }
200
201 platform_set_drvdata(pdev, priv);
202
203 phy_provider =
204 devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
205 if (IS_ERR(phy_provider))
206 return PTR_ERR(phy_provider);
207
208 return 0;
209}
210
211static struct platform_driver phy_berlin_usb_driver = {
212 .probe = phy_berlin_usb_probe,
213 .driver = {
214 .name = "phy-berlin-usb",
215 .owner = THIS_MODULE,
216 .of_match_table = phy_berlin_sata_of_match,
217 },
218};
219module_platform_driver(phy_berlin_usb_driver);
220
221MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
222MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB");
223MODULE_LICENSE("GPL");
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index ff5eec5af817..a12d35338313 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -26,6 +26,7 @@
26static struct class *phy_class; 26static struct class *phy_class;
27static DEFINE_MUTEX(phy_provider_mutex); 27static DEFINE_MUTEX(phy_provider_mutex);
28static LIST_HEAD(phy_provider_list); 28static LIST_HEAD(phy_provider_list);
29static LIST_HEAD(phys);
29static DEFINE_IDA(phy_ida); 30static DEFINE_IDA(phy_ida);
30 31
31static void devm_phy_release(struct device *dev, void *res) 32static void devm_phy_release(struct device *dev, void *res)
@@ -54,34 +55,79 @@ static int devm_phy_match(struct device *dev, void *res, void *match_data)
54 return res == match_data; 55 return res == match_data;
55} 56}
56 57
57static struct phy *phy_lookup(struct device *device, const char *port) 58/**
59 * phy_create_lookup() - allocate and register PHY/device association
60 * @phy: the phy of the association
61 * @con_id: connection ID string on device
62 * @dev_id: the device of the association
63 *
64 * Creates and registers phy_lookup entry.
65 */
66int phy_create_lookup(struct phy *phy, const char *con_id, const char *dev_id)
58{ 67{
59 unsigned int count; 68 struct phy_lookup *pl;
60 struct phy *phy;
61 struct device *dev;
62 struct phy_consumer *consumers;
63 struct class_dev_iter iter;
64 69
65 class_dev_iter_init(&iter, phy_class, NULL, NULL); 70 if (!phy || !dev_id || !con_id)
66 while ((dev = class_dev_iter_next(&iter))) { 71 return -EINVAL;
67 phy = to_phy(dev);
68 72
69 if (!phy->init_data) 73 pl = kzalloc(sizeof(*pl), GFP_KERNEL);
70 continue; 74 if (!pl)
71 count = phy->init_data->num_consumers; 75 return -ENOMEM;
72 consumers = phy->init_data->consumers; 76
73 while (count--) { 77 pl->dev_id = dev_id;
74 if (!strcmp(consumers->dev_name, dev_name(device)) && 78 pl->con_id = con_id;
75 !strcmp(consumers->port, port)) { 79 pl->phy = phy;
76 class_dev_iter_exit(&iter); 80
77 return phy; 81 mutex_lock(&phy_provider_mutex);
78 } 82 list_add_tail(&pl->node, &phys);
79 consumers++; 83 mutex_unlock(&phy_provider_mutex);
84
85 return 0;
86}
87EXPORT_SYMBOL_GPL(phy_create_lookup);
88
89/**
90 * phy_remove_lookup() - find and remove PHY/device association
91 * @phy: the phy of the association
92 * @con_id: connection ID string on device
93 * @dev_id: the device of the association
94 *
95 * Finds and unregisters phy_lookup entry that was created with
96 * phy_create_lookup().
97 */
98void phy_remove_lookup(struct phy *phy, const char *con_id, const char *dev_id)
99{
100 struct phy_lookup *pl;
101
102 if (!phy || !dev_id || !con_id)
103 return;
104
105 mutex_lock(&phy_provider_mutex);
106 list_for_each_entry(pl, &phys, node)
107 if (pl->phy == phy && !strcmp(pl->dev_id, dev_id) &&
108 !strcmp(pl->con_id, con_id)) {
109 list_del(&pl->node);
110 kfree(pl);
111 break;
80 } 112 }
81 } 113 mutex_unlock(&phy_provider_mutex);
114}
115EXPORT_SYMBOL_GPL(phy_remove_lookup);
82 116
83 class_dev_iter_exit(&iter); 117static struct phy *phy_find(struct device *dev, const char *con_id)
84 return ERR_PTR(-ENODEV); 118{
119 const char *dev_id = dev_name(dev);
120 struct phy_lookup *p, *pl = NULL;
121
122 mutex_lock(&phy_provider_mutex);
123 list_for_each_entry(p, &phys, node)
124 if (!strcmp(p->dev_id, dev_id) && !strcmp(p->con_id, con_id)) {
125 pl = p;
126 break;
127 }
128 mutex_unlock(&phy_provider_mutex);
129
130 return pl ? pl->phy : ERR_PTR(-ENODEV);
85} 131}
86 132
87static struct phy_provider *of_phy_provider_lookup(struct device_node *node) 133static struct phy_provider *of_phy_provider_lookup(struct device_node *node)
@@ -414,21 +460,13 @@ struct phy *of_phy_simple_xlate(struct device *dev, struct of_phandle_args
414{ 460{
415 struct phy *phy; 461 struct phy *phy;
416 struct class_dev_iter iter; 462 struct class_dev_iter iter;
417 struct device_node *node = dev->of_node;
418 struct device_node *child;
419 463
420 class_dev_iter_init(&iter, phy_class, NULL, NULL); 464 class_dev_iter_init(&iter, phy_class, NULL, NULL);
421 while ((dev = class_dev_iter_next(&iter))) { 465 while ((dev = class_dev_iter_next(&iter))) {
422 phy = to_phy(dev); 466 phy = to_phy(dev);
423 if (node != phy->dev.of_node) { 467 if (args->np != phy->dev.of_node)
424 for_each_child_of_node(node, child) {
425 if (child == phy->dev.of_node)
426 goto phy_found;
427 }
428 continue; 468 continue;
429 }
430 469
431phy_found:
432 class_dev_iter_exit(&iter); 470 class_dev_iter_exit(&iter);
433 return phy; 471 return phy;
434 } 472 }
@@ -463,7 +501,7 @@ struct phy *phy_get(struct device *dev, const char *string)
463 string); 501 string);
464 phy = _of_phy_get(dev->of_node, index); 502 phy = _of_phy_get(dev->of_node, index);
465 } else { 503 } else {
466 phy = phy_lookup(dev, string); 504 phy = phy_find(dev, string);
467 } 505 }
468 if (IS_ERR(phy)) 506 if (IS_ERR(phy))
469 return phy; 507 return phy;
@@ -588,13 +626,11 @@ EXPORT_SYMBOL_GPL(devm_of_phy_get);
588 * @dev: device that is creating the new phy 626 * @dev: device that is creating the new phy
589 * @node: device node of the phy 627 * @node: device node of the phy
590 * @ops: function pointers for performing phy operations 628 * @ops: function pointers for performing phy operations
591 * @init_data: contains the list of PHY consumers or NULL
592 * 629 *
593 * Called to create a phy using phy framework. 630 * Called to create a phy using phy framework.
594 */ 631 */
595struct phy *phy_create(struct device *dev, struct device_node *node, 632struct phy *phy_create(struct device *dev, struct device_node *node,
596 const struct phy_ops *ops, 633 const struct phy_ops *ops)
597 struct phy_init_data *init_data)
598{ 634{
599 int ret; 635 int ret;
600 int id; 636 int id;
@@ -632,7 +668,6 @@ struct phy *phy_create(struct device *dev, struct device_node *node,
632 phy->dev.of_node = node ?: dev->of_node; 668 phy->dev.of_node = node ?: dev->of_node;
633 phy->id = id; 669 phy->id = id;
634 phy->ops = ops; 670 phy->ops = ops;
635 phy->init_data = init_data;
636 671
637 ret = dev_set_name(&phy->dev, "phy-%s.%d", dev_name(dev), id); 672 ret = dev_set_name(&phy->dev, "phy-%s.%d", dev_name(dev), id);
638 if (ret) 673 if (ret)
@@ -667,7 +702,6 @@ EXPORT_SYMBOL_GPL(phy_create);
667 * @dev: device that is creating the new phy 702 * @dev: device that is creating the new phy
668 * @node: device node of the phy 703 * @node: device node of the phy
669 * @ops: function pointers for performing phy operations 704 * @ops: function pointers for performing phy operations
670 * @init_data: contains the list of PHY consumers or NULL
671 * 705 *
672 * Creates a new PHY device adding it to the PHY class. 706 * Creates a new PHY device adding it to the PHY class.
673 * While at that, it also associates the device with the phy using devres. 707 * While at that, it also associates the device with the phy using devres.
@@ -675,8 +709,7 @@ EXPORT_SYMBOL_GPL(phy_create);
675 * then, devres data is freed. 709 * then, devres data is freed.
676 */ 710 */
677struct phy *devm_phy_create(struct device *dev, struct device_node *node, 711struct phy *devm_phy_create(struct device *dev, struct device_node *node,
678 const struct phy_ops *ops, 712 const struct phy_ops *ops)
679 struct phy_init_data *init_data)
680{ 713{
681 struct phy **ptr, *phy; 714 struct phy **ptr, *phy;
682 715
@@ -684,7 +717,7 @@ struct phy *devm_phy_create(struct device *dev, struct device_node *node,
684 if (!ptr) 717 if (!ptr)
685 return ERR_PTR(-ENOMEM); 718 return ERR_PTR(-ENOMEM);
686 719
687 phy = phy_create(dev, node, ops, init_data); 720 phy = phy_create(dev, node, ops);
688 if (!IS_ERR(phy)) { 721 if (!IS_ERR(phy)) {
689 *ptr = phy; 722 *ptr = phy;
690 devres_add(dev, ptr); 723 devres_add(dev, ptr);
diff --git a/drivers/phy/phy-exynos-dp-video.c b/drivers/phy/phy-exynos-dp-video.c
index 84f49e5a3f24..f86cbe68ddaf 100644
--- a/drivers/phy/phy-exynos-dp-video.c
+++ b/drivers/phy/phy-exynos-dp-video.c
@@ -112,7 +112,7 @@ static int exynos_dp_video_phy_probe(struct platform_device *pdev)
112 match = of_match_node(exynos_dp_video_phy_of_match, dev->of_node); 112 match = of_match_node(exynos_dp_video_phy_of_match, dev->of_node);
113 state->drvdata = match->data; 113 state->drvdata = match->data;
114 114
115 phy = devm_phy_create(dev, NULL, &exynos_dp_video_phy_ops, NULL); 115 phy = devm_phy_create(dev, NULL, &exynos_dp_video_phy_ops);
116 if (IS_ERR(phy)) { 116 if (IS_ERR(phy)) {
117 dev_err(dev, "failed to create Display Port PHY\n"); 117 dev_err(dev, "failed to create Display Port PHY\n");
118 return PTR_ERR(phy); 118 return PTR_ERR(phy);
diff --git a/drivers/phy/phy-exynos-mipi-video.c b/drivers/phy/phy-exynos-mipi-video.c
index 6a9bef138617..943e0f88a120 100644
--- a/drivers/phy/phy-exynos-mipi-video.c
+++ b/drivers/phy/phy-exynos-mipi-video.c
@@ -137,7 +137,7 @@ static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
137 137
138 for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) { 138 for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) {
139 struct phy *phy = devm_phy_create(dev, NULL, 139 struct phy *phy = devm_phy_create(dev, NULL,
140 &exynos_mipi_video_phy_ops, NULL); 140 &exynos_mipi_video_phy_ops);
141 if (IS_ERR(phy)) { 141 if (IS_ERR(phy)) {
142 dev_err(dev, "failed to create PHY %d\n", i); 142 dev_err(dev, "failed to create PHY %d\n", i);
143 return PTR_ERR(phy); 143 return PTR_ERR(phy);
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index f756aca871db..04374018425f 100644
--- a/drivers/phy/phy-exynos5-usbdrd.c
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -141,6 +141,7 @@ struct exynos5_usbdrd_phy_drvdata {
141 const struct exynos5_usbdrd_phy_config *phy_cfg; 141 const struct exynos5_usbdrd_phy_config *phy_cfg;
142 u32 pmu_offset_usbdrd0_phy; 142 u32 pmu_offset_usbdrd0_phy;
143 u32 pmu_offset_usbdrd1_phy; 143 u32 pmu_offset_usbdrd1_phy;
144 bool has_common_clk_gate;
144}; 145};
145 146
146/** 147/**
@@ -148,6 +149,9 @@ struct exynos5_usbdrd_phy_drvdata {
148 * @dev: pointer to device instance of this platform device 149 * @dev: pointer to device instance of this platform device
149 * @reg_phy: usb phy controller register memory base 150 * @reg_phy: usb phy controller register memory base
150 * @clk: phy clock for register access 151 * @clk: phy clock for register access
152 * @pipeclk: clock for pipe3 phy
153 * @utmiclk: clock for utmi+ phy
154 * @itpclk: clock for ITP generation
151 * @drv_data: pointer to SoC level driver data structure 155 * @drv_data: pointer to SoC level driver data structure
152 * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY 156 * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
153 * instances each with its 'phy' and 'phy_cfg'. 157 * instances each with its 'phy' and 'phy_cfg'.
@@ -155,12 +159,16 @@ struct exynos5_usbdrd_phy_drvdata {
155 * reference clocks' for SS and HS operations 159 * reference clocks' for SS and HS operations
156 * @ref_clk: reference clock to PHY block from which PHY's 160 * @ref_clk: reference clock to PHY block from which PHY's
157 * operational clocks are derived 161 * operational clocks are derived
158 * @ref_rate: rate of above reference clock 162 * vbus: VBUS regulator for phy
163 * vbus_boost: Boost regulator for VBUS present on few Exynos boards
159 */ 164 */
160struct exynos5_usbdrd_phy { 165struct exynos5_usbdrd_phy {
161 struct device *dev; 166 struct device *dev;
162 void __iomem *reg_phy; 167 void __iomem *reg_phy;
163 struct clk *clk; 168 struct clk *clk;
169 struct clk *pipeclk;
170 struct clk *utmiclk;
171 struct clk *itpclk;
164 const struct exynos5_usbdrd_phy_drvdata *drv_data; 172 const struct exynos5_usbdrd_phy_drvdata *drv_data;
165 struct phy_usb_instance { 173 struct phy_usb_instance {
166 struct phy *phy; 174 struct phy *phy;
@@ -172,6 +180,7 @@ struct exynos5_usbdrd_phy {
172 u32 extrefclk; 180 u32 extrefclk;
173 struct clk *ref_clk; 181 struct clk *ref_clk;
174 struct regulator *vbus; 182 struct regulator *vbus;
183 struct regulator *vbus_boost;
175}; 184};
176 185
177static inline 186static inline
@@ -447,13 +456,27 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
447 dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); 456 dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
448 457
449 clk_prepare_enable(phy_drd->ref_clk); 458 clk_prepare_enable(phy_drd->ref_clk);
459 if (!phy_drd->drv_data->has_common_clk_gate) {
460 clk_prepare_enable(phy_drd->pipeclk);
461 clk_prepare_enable(phy_drd->utmiclk);
462 clk_prepare_enable(phy_drd->itpclk);
463 }
450 464
451 /* Enable VBUS supply */ 465 /* Enable VBUS supply */
466 if (phy_drd->vbus_boost) {
467 ret = regulator_enable(phy_drd->vbus_boost);
468 if (ret) {
469 dev_err(phy_drd->dev,
470 "Failed to enable VBUS boost supply\n");
471 goto fail_vbus;
472 }
473 }
474
452 if (phy_drd->vbus) { 475 if (phy_drd->vbus) {
453 ret = regulator_enable(phy_drd->vbus); 476 ret = regulator_enable(phy_drd->vbus);
454 if (ret) { 477 if (ret) {
455 dev_err(phy_drd->dev, "Failed to enable VBUS supply\n"); 478 dev_err(phy_drd->dev, "Failed to enable VBUS supply\n");
456 goto fail_vbus; 479 goto fail_vbus_boost;
457 } 480 }
458 } 481 }
459 482
@@ -462,8 +485,17 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
462 485
463 return 0; 486 return 0;
464 487
488fail_vbus_boost:
489 if (phy_drd->vbus_boost)
490 regulator_disable(phy_drd->vbus_boost);
491
465fail_vbus: 492fail_vbus:
466 clk_disable_unprepare(phy_drd->ref_clk); 493 clk_disable_unprepare(phy_drd->ref_clk);
494 if (!phy_drd->drv_data->has_common_clk_gate) {
495 clk_disable_unprepare(phy_drd->itpclk);
496 clk_disable_unprepare(phy_drd->utmiclk);
497 clk_disable_unprepare(phy_drd->pipeclk);
498 }
467 499
468 return ret; 500 return ret;
469} 501}
@@ -481,8 +513,15 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
481 /* Disable VBUS supply */ 513 /* Disable VBUS supply */
482 if (phy_drd->vbus) 514 if (phy_drd->vbus)
483 regulator_disable(phy_drd->vbus); 515 regulator_disable(phy_drd->vbus);
516 if (phy_drd->vbus_boost)
517 regulator_disable(phy_drd->vbus_boost);
484 518
485 clk_disable_unprepare(phy_drd->ref_clk); 519 clk_disable_unprepare(phy_drd->ref_clk);
520 if (!phy_drd->drv_data->has_common_clk_gate) {
521 clk_disable_unprepare(phy_drd->itpclk);
522 clk_disable_unprepare(phy_drd->pipeclk);
523 clk_disable_unprepare(phy_drd->utmiclk);
524 }
486 525
487 return 0; 526 return 0;
488} 527}
@@ -506,6 +545,57 @@ static struct phy_ops exynos5_usbdrd_phy_ops = {
506 .owner = THIS_MODULE, 545 .owner = THIS_MODULE,
507}; 546};
508 547
548static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
549{
550 unsigned long ref_rate;
551 int ret;
552
553 phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
554 if (IS_ERR(phy_drd->clk)) {
555 dev_err(phy_drd->dev, "Failed to get phy clock\n");
556 return PTR_ERR(phy_drd->clk);
557 }
558
559 phy_drd->ref_clk = devm_clk_get(phy_drd->dev, "ref");
560 if (IS_ERR(phy_drd->ref_clk)) {
561 dev_err(phy_drd->dev, "Failed to get phy reference clock\n");
562 return PTR_ERR(phy_drd->ref_clk);
563 }
564 ref_rate = clk_get_rate(phy_drd->ref_clk);
565
566 ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
567 if (ret) {
568 dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
569 ref_rate);
570 return ret;
571 }
572
573 if (!phy_drd->drv_data->has_common_clk_gate) {
574 phy_drd->pipeclk = devm_clk_get(phy_drd->dev, "phy_pipe");
575 if (IS_ERR(phy_drd->pipeclk)) {
576 dev_info(phy_drd->dev,
577 "PIPE3 phy operational clock not specified\n");
578 phy_drd->pipeclk = NULL;
579 }
580
581 phy_drd->utmiclk = devm_clk_get(phy_drd->dev, "phy_utmi");
582 if (IS_ERR(phy_drd->utmiclk)) {
583 dev_info(phy_drd->dev,
584 "UTMI phy operational clock not specified\n");
585 phy_drd->utmiclk = NULL;
586 }
587
588 phy_drd->itpclk = devm_clk_get(phy_drd->dev, "itp");
589 if (IS_ERR(phy_drd->itpclk)) {
590 dev_info(phy_drd->dev,
591 "ITP clock from main OSC not specified\n");
592 phy_drd->itpclk = NULL;
593 }
594 }
595
596 return 0;
597}
598
509static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = { 599static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = {
510 { 600 {
511 .id = EXYNOS5_DRDPHY_UTMI, 601 .id = EXYNOS5_DRDPHY_UTMI,
@@ -525,11 +615,19 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
525 .phy_cfg = phy_cfg_exynos5, 615 .phy_cfg = phy_cfg_exynos5,
526 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, 616 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
527 .pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL, 617 .pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL,
618 .has_common_clk_gate = true,
528}; 619};
529 620
530static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = { 621static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
531 .phy_cfg = phy_cfg_exynos5, 622 .phy_cfg = phy_cfg_exynos5,
532 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, 623 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
624 .has_common_clk_gate = true,
625};
626
627static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = {
628 .phy_cfg = phy_cfg_exynos5,
629 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL,
630 .has_common_clk_gate = false,
533}; 631};
534 632
535static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { 633static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
@@ -539,6 +637,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
539 }, { 637 }, {
540 .compatible = "samsung,exynos5420-usbdrd-phy", 638 .compatible = "samsung,exynos5420-usbdrd-phy",
541 .data = &exynos5420_usbdrd_phy 639 .data = &exynos5420_usbdrd_phy
640 }, {
641 .compatible = "samsung,exynos7-usbdrd-phy",
642 .data = &exynos7_usbdrd_phy
542 }, 643 },
543 { }, 644 { },
544}; 645};
@@ -555,7 +656,6 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
555 const struct exynos5_usbdrd_phy_drvdata *drv_data; 656 const struct exynos5_usbdrd_phy_drvdata *drv_data;
556 struct regmap *reg_pmu; 657 struct regmap *reg_pmu;
557 u32 pmu_offset; 658 u32 pmu_offset;
558 unsigned long ref_rate;
559 int i, ret; 659 int i, ret;
560 int channel; 660 int channel;
561 661
@@ -576,23 +676,9 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
576 drv_data = match->data; 676 drv_data = match->data;
577 phy_drd->drv_data = drv_data; 677 phy_drd->drv_data = drv_data;
578 678
579 phy_drd->clk = devm_clk_get(dev, "phy"); 679 ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
580 if (IS_ERR(phy_drd->clk)) {
581 dev_err(dev, "Failed to get clock of phy controller\n");
582 return PTR_ERR(phy_drd->clk);
583 }
584
585 phy_drd->ref_clk = devm_clk_get(dev, "ref");
586 if (IS_ERR(phy_drd->ref_clk)) {
587 dev_err(dev, "Failed to get reference clock of usbdrd phy\n");
588 return PTR_ERR(phy_drd->ref_clk);
589 }
590 ref_rate = clk_get_rate(phy_drd->ref_clk);
591
592 ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
593 if (ret) { 680 if (ret) {
594 dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n", 681 dev_err(dev, "Failed to initialize clocks\n");
595 ref_rate);
596 return ret; 682 return ret;
597 } 683 }
598 684
@@ -622,7 +708,7 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
622 break; 708 break;
623 } 709 }
624 710
625 /* Get Vbus regulator */ 711 /* Get Vbus regulators */
626 phy_drd->vbus = devm_regulator_get(dev, "vbus"); 712 phy_drd->vbus = devm_regulator_get(dev, "vbus");
627 if (IS_ERR(phy_drd->vbus)) { 713 if (IS_ERR(phy_drd->vbus)) {
628 ret = PTR_ERR(phy_drd->vbus); 714 ret = PTR_ERR(phy_drd->vbus);
@@ -633,12 +719,21 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
633 phy_drd->vbus = NULL; 719 phy_drd->vbus = NULL;
634 } 720 }
635 721
722 phy_drd->vbus_boost = devm_regulator_get(dev, "vbus-boost");
723 if (IS_ERR(phy_drd->vbus_boost)) {
724 ret = PTR_ERR(phy_drd->vbus_boost);
725 if (ret == -EPROBE_DEFER)
726 return ret;
727
728 dev_warn(dev, "Failed to get VBUS boost supply regulator\n");
729 phy_drd->vbus_boost = NULL;
730 }
731
636 dev_vdbg(dev, "Creating usbdrd_phy phy\n"); 732 dev_vdbg(dev, "Creating usbdrd_phy phy\n");
637 733
638 for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) { 734 for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {
639 struct phy *phy = devm_phy_create(dev, NULL, 735 struct phy *phy = devm_phy_create(dev, NULL,
640 &exynos5_usbdrd_phy_ops, 736 &exynos5_usbdrd_phy_ops);
641 NULL);
642 if (IS_ERR(phy)) { 737 if (IS_ERR(phy)) {
643 dev_err(dev, "Failed to create usbdrd_phy phy\n"); 738 dev_err(dev, "Failed to create usbdrd_phy phy\n");
644 return PTR_ERR(phy); 739 return PTR_ERR(phy);
diff --git a/drivers/phy/phy-exynos5250-sata.c b/drivers/phy/phy-exynos5250-sata.c
index 54cf4ae60d29..bc858cc800a1 100644
--- a/drivers/phy/phy-exynos5250-sata.c
+++ b/drivers/phy/phy-exynos5250-sata.c
@@ -210,7 +210,7 @@ static int exynos_sata_phy_probe(struct platform_device *pdev)
210 return ret; 210 return ret;
211 } 211 }
212 212
213 sata_phy->phy = devm_phy_create(dev, NULL, &exynos_sata_phy_ops, NULL); 213 sata_phy->phy = devm_phy_create(dev, NULL, &exynos_sata_phy_ops);
214 if (IS_ERR(sata_phy->phy)) { 214 if (IS_ERR(sata_phy->phy)) {
215 clk_disable_unprepare(sata_phy->phyclk); 215 clk_disable_unprepare(sata_phy->phyclk);
216 dev_err(dev, "failed to create PHY\n"); 216 dev_err(dev, "failed to create PHY\n");
diff --git a/drivers/phy/phy-hix5hd2-sata.c b/drivers/phy/phy-hix5hd2-sata.c
index d5d978085c6d..34915b4202f1 100644
--- a/drivers/phy/phy-hix5hd2-sata.c
+++ b/drivers/phy/phy-hix5hd2-sata.c
@@ -156,7 +156,7 @@ static int hix5hd2_sata_phy_probe(struct platform_device *pdev)
156 if (IS_ERR(priv->peri_ctrl)) 156 if (IS_ERR(priv->peri_ctrl))
157 priv->peri_ctrl = NULL; 157 priv->peri_ctrl = NULL;
158 158
159 phy = devm_phy_create(dev, NULL, &hix5hd2_sata_phy_ops, NULL); 159 phy = devm_phy_create(dev, NULL, &hix5hd2_sata_phy_ops);
160 if (IS_ERR(phy)) { 160 if (IS_ERR(phy)) {
161 dev_err(dev, "failed to create PHY\n"); 161 dev_err(dev, "failed to create PHY\n");
162 return PTR_ERR(phy); 162 return PTR_ERR(phy);
@@ -164,10 +164,7 @@ static int hix5hd2_sata_phy_probe(struct platform_device *pdev)
164 164
165 phy_set_drvdata(phy, priv); 165 phy_set_drvdata(phy, priv);
166 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 166 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
167 if (IS_ERR(phy_provider)) 167 return PTR_ERR_OR_ZERO(phy_provider);
168 return PTR_ERR(phy_provider);
169
170 return 0;
171} 168}
172 169
173static const struct of_device_id hix5hd2_sata_phy_of_match[] = { 170static const struct of_device_id hix5hd2_sata_phy_of_match[] = {
diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c
new file mode 100644
index 000000000000..e34da13885e8
--- /dev/null
+++ b/drivers/phy/phy-miphy28lp.c
@@ -0,0 +1,1283 @@
1/*
2 * Copyright (C) 2014 STMicroelectronics
3 *
4 * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407).
5 *
6 * Author: Alexandre Torgue <alexandre.torgue@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2, as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/platform_device.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_platform.h>
20#include <linux/of_address.h>
21#include <linux/clk.h>
22#include <linux/phy/phy.h>
23#include <linux/delay.h>
24#include <linux/mfd/syscon.h>
25#include <linux/regmap.h>
26#include <linux/reset.h>
27
28#include <dt-bindings/phy/phy.h>
29
30/* MiPHY registers */
31#define MIPHY_CONF_RESET 0x00
32#define RST_APPLI_SW BIT(0)
33#define RST_CONF_SW BIT(1)
34#define RST_MACRO_SW BIT(2)
35
36#define MIPHY_RESET 0x01
37#define RST_PLL_SW BIT(0)
38#define RST_COMP_SW BIT(2)
39
40#define MIPHY_STATUS_1 0x02
41#define PHY_RDY BIT(0)
42#define HFC_RDY BIT(1)
43#define HFC_PLL BIT(2)
44
45#define MIPHY_CONTROL 0x04
46#define TERM_EN_SW BIT(2)
47#define DIS_LINK_RST BIT(3)
48#define AUTO_RST_RX BIT(4)
49#define PX_RX_POL BIT(5)
50
51#define MIPHY_BOUNDARY_SEL 0x0a
52#define TX_SEL BIT(6)
53#define SSC_SEL BIT(4)
54#define GENSEL_SEL BIT(0)
55
56#define MIPHY_BOUNDARY_1 0x0b
57#define MIPHY_BOUNDARY_2 0x0c
58#define SSC_EN_SW BIT(2)
59
60#define MIPHY_PLL_CLKREF_FREQ 0x0d
61#define MIPHY_SPEED 0x0e
62#define TX_SPDSEL_80DEC 0
63#define TX_SPDSEL_40DEC 1
64#define TX_SPDSEL_20DEC 2
65#define RX_SPDSEL_80DEC 0
66#define RX_SPDSEL_40DEC (1 << 2)
67#define RX_SPDSEL_20DEC (2 << 2)
68
69#define MIPHY_CONF 0x0f
70#define MIPHY_CTRL_TEST_SEL 0x20
71#define MIPHY_CTRL_TEST_1 0x21
72#define MIPHY_CTRL_TEST_2 0x22
73#define MIPHY_CTRL_TEST_3 0x23
74#define MIPHY_CTRL_TEST_4 0x24
75#define MIPHY_FEEDBACK_TEST 0x25
76#define MIPHY_DEBUG_BUS 0x26
77#define MIPHY_DEBUG_STATUS_MSB 0x27
78#define MIPHY_DEBUG_STATUS_LSB 0x28
79#define MIPHY_PWR_RAIL_1 0x29
80#define MIPHY_PWR_RAIL_2 0x2a
81#define MIPHY_SYNCHAR_CONTROL 0x30
82
83#define MIPHY_COMP_FSM_1 0x3a
84#define COMP_START BIT(6)
85
86#define MIPHY_COMP_FSM_6 0x3f
87#define COMP_DONE BIT(7)
88
89#define MIPHY_COMP_POSTP 0x42
90#define MIPHY_TX_CTRL_1 0x49
91#define TX_REG_STEP_0V 0
92#define TX_REG_STEP_P_25MV 1
93#define TX_REG_STEP_P_50MV 2
94#define TX_REG_STEP_N_25MV 7
95#define TX_REG_STEP_N_50MV 6
96#define TX_REG_STEP_N_75MV 5
97
98#define MIPHY_TX_CTRL_2 0x4a
99#define TX_SLEW_SW_40_PS 0
100#define TX_SLEW_SW_80_PS 1
101#define TX_SLEW_SW_120_PS 2
102
103#define MIPHY_TX_CTRL_3 0x4b
104#define MIPHY_TX_CAL_MAN 0x4e
105#define TX_SLEW_CAL_MAN_EN BIT(0)
106
107#define MIPHY_TST_BIAS_BOOST_2 0x62
108#define MIPHY_BIAS_BOOST_1 0x63
109#define MIPHY_BIAS_BOOST_2 0x64
110#define MIPHY_RX_DESBUFF_FDB_2 0x67
111#define MIPHY_RX_DESBUFF_FDB_3 0x68
112#define MIPHY_SIGDET_COMPENS1 0x69
113#define MIPHY_SIGDET_COMPENS2 0x6a
114#define MIPHY_JITTER_PERIOD 0x6b
115#define MIPHY_JITTER_AMPLITUDE_1 0x6c
116#define MIPHY_JITTER_AMPLITUDE_2 0x6d
117#define MIPHY_JITTER_AMPLITUDE_3 0x6e
118#define MIPHY_RX_K_GAIN 0x78
119#define MIPHY_RX_BUFFER_CTRL 0x7a
120#define VGA_GAIN BIT(0)
121#define EQ_DC_GAIN BIT(2)
122#define EQ_BOOST_GAIN BIT(3)
123
124#define MIPHY_RX_VGA_GAIN 0x7b
125#define MIPHY_RX_EQU_GAIN_1 0x7f
126#define MIPHY_RX_EQU_GAIN_2 0x80
127#define MIPHY_RX_EQU_GAIN_3 0x81
128#define MIPHY_RX_CAL_CTRL_1 0x97
129#define MIPHY_RX_CAL_CTRL_2 0x98
130
131#define MIPHY_RX_CAL_OFFSET_CTRL 0x99
132#define CAL_OFFSET_VGA_64 (0x03 << 0)
133#define CAL_OFFSET_THRESHOLD_64 (0x03 << 2)
134#define VGA_OFFSET_POLARITY BIT(4)
135#define OFFSET_COMPENSATION_EN BIT(6)
136
137#define MIPHY_RX_CAL_VGA_STEP 0x9a
138#define MIPHY_RX_CAL_EYE_MIN 0x9d
139#define MIPHY_RX_CAL_OPT_LENGTH 0x9f
140#define MIPHY_RX_LOCK_CTRL_1 0xc1
141#define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2
142#define MIPHY_RX_LOCK_STEP 0xc4
143
144#define MIPHY_RX_SIGDET_SLEEP_OA 0xc9
145#define MIPHY_RX_SIGDET_SLEEP_SEL 0xca
146#define MIPHY_RX_SIGDET_WAIT_SEL 0xcb
147#define MIPHY_RX_SIGDET_DATA_SEL 0xcc
148#define EN_ULTRA_LOW_POWER BIT(0)
149#define EN_FIRST_HALF BIT(1)
150#define EN_SECOND_HALF BIT(2)
151#define EN_DIGIT_SIGNAL_CHECK BIT(3)
152
153#define MIPHY_RX_POWER_CTRL_1 0xcd
154#define MIPHY_RX_POWER_CTRL_2 0xce
155#define MIPHY_PLL_CALSET_CTRL 0xd3
156#define MIPHY_PLL_CALSET_1 0xd4
157#define MIPHY_PLL_CALSET_2 0xd5
158#define MIPHY_PLL_CALSET_3 0xd6
159#define MIPHY_PLL_CALSET_4 0xd7
160#define MIPHY_PLL_SBR_1 0xe3
161#define SET_NEW_CHANGE BIT(1)
162
163#define MIPHY_PLL_SBR_2 0xe4
164#define MIPHY_PLL_SBR_3 0xe5
165#define MIPHY_PLL_SBR_4 0xe6
166#define MIPHY_PLL_COMMON_MISC_2 0xe9
167#define START_ACT_FILT BIT(6)
168
169#define MIPHY_PLL_SPAREIN 0xeb
170
171/*
172 * On STiH407 the glue logic can be different among MiPHY devices; for example:
173 * MiPHY0: OSC_FORCE_EXT means:
174 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
175 * MiPHY1: OSC_FORCE_EXT means:
176 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
177 * Some devices have not the possibility to check if the osc is ready.
178 */
179#define MIPHY_OSC_FORCE_EXT BIT(3)
180#define MIPHY_OSC_RDY BIT(5)
181
182#define MIPHY_CTRL_MASK 0x0f
183#define MIPHY_CTRL_DEFAULT 0
184#define MIPHY_CTRL_SYNC_D_EN BIT(2)
185
186/* SATA / PCIe defines */
187#define SATA_CTRL_MASK 0x07
188#define PCIE_CTRL_MASK 0xff
189#define SATA_CTRL_SELECT_SATA 1
190#define SATA_CTRL_SELECT_PCIE 0
191#define SYSCFG_PCIE_PCIE_VAL 0x80
192#define SATA_SPDMODE 1
193
194#define MIPHY_SATA_BANK_NB 3
195#define MIPHY_PCIE_BANK_NB 2
196
197struct miphy28lp_phy {
198 struct phy *phy;
199 struct miphy28lp_dev *phydev;
200 void __iomem *base;
201 void __iomem *pipebase;
202
203 bool osc_force_ext;
204 bool osc_rdy;
205 bool px_rx_pol_inv;
206 bool ssc;
207 bool tx_impedance;
208
209 struct reset_control *miphy_rst;
210
211 u32 sata_gen;
212
213 /* Sysconfig registers offsets needed to configure the device */
214 u32 syscfg_miphy_ctrl;
215 u32 syscfg_miphy_status;
216 u32 syscfg_pci;
217 u32 syscfg_sata;
218 u8 type;
219};
220
221struct miphy28lp_dev {
222 struct device *dev;
223 struct regmap *regmap;
224 struct mutex miphy_mutex;
225 struct miphy28lp_phy **phys;
226};
227
228struct miphy_initval {
229 u16 reg;
230 u16 val;
231};
232
233enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 };
234
235static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
236
237struct pll_ratio {
238 int clk_ref;
239 int calset_1;
240 int calset_2;
241 int calset_3;
242 int calset_4;
243 int cal_ctrl;
244};
245
246static struct pll_ratio sata_pll_ratio = {
247 .clk_ref = 0x1e,
248 .calset_1 = 0xc8,
249 .calset_2 = 0x00,
250 .calset_3 = 0x00,
251 .calset_4 = 0x00,
252 .cal_ctrl = 0x00,
253};
254
255static struct pll_ratio pcie_pll_ratio = {
256 .clk_ref = 0x1e,
257 .calset_1 = 0xa6,
258 .calset_2 = 0xaa,
259 .calset_3 = 0xaa,
260 .calset_4 = 0x00,
261 .cal_ctrl = 0x00,
262};
263
264static struct pll_ratio usb3_pll_ratio = {
265 .clk_ref = 0x1e,
266 .calset_1 = 0xa6,
267 .calset_2 = 0xaa,
268 .calset_3 = 0xaa,
269 .calset_4 = 0x04,
270 .cal_ctrl = 0x00,
271};
272
273struct miphy28lp_pll_gen {
274 int bank;
275 int speed;
276 int bias_boost_1;
277 int bias_boost_2;
278 int tx_ctrl_1;
279 int tx_ctrl_2;
280 int tx_ctrl_3;
281 int rx_k_gain;
282 int rx_vga_gain;
283 int rx_equ_gain_1;
284 int rx_equ_gain_2;
285 int rx_equ_gain_3;
286 int rx_buff_ctrl;
287};
288
289static struct miphy28lp_pll_gen sata_pll_gen[] = {
290 {
291 .bank = 0x00,
292 .speed = TX_SPDSEL_80DEC | RX_SPDSEL_80DEC,
293 .bias_boost_1 = 0x00,
294 .bias_boost_2 = 0xae,
295 .tx_ctrl_2 = 0x53,
296 .tx_ctrl_3 = 0x00,
297 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
298 .rx_vga_gain = 0x00,
299 .rx_equ_gain_1 = 0x7d,
300 .rx_equ_gain_2 = 0x56,
301 .rx_equ_gain_3 = 0x00,
302 },
303 {
304 .bank = 0x01,
305 .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC,
306 .bias_boost_1 = 0x00,
307 .bias_boost_2 = 0xae,
308 .tx_ctrl_2 = 0x72,
309 .tx_ctrl_3 = 0x20,
310 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
311 .rx_vga_gain = 0x00,
312 .rx_equ_gain_1 = 0x7d,
313 .rx_equ_gain_2 = 0x56,
314 .rx_equ_gain_3 = 0x00,
315 },
316 {
317 .bank = 0x02,
318 .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC,
319 .bias_boost_1 = 0x00,
320 .bias_boost_2 = 0xae,
321 .tx_ctrl_2 = 0xc0,
322 .tx_ctrl_3 = 0x20,
323 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
324 .rx_vga_gain = 0x00,
325 .rx_equ_gain_1 = 0x7d,
326 .rx_equ_gain_2 = 0x56,
327 .rx_equ_gain_3 = 0x00,
328 },
329};
330
331static struct miphy28lp_pll_gen pcie_pll_gen[] = {
332 {
333 .bank = 0x00,
334 .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC,
335 .bias_boost_1 = 0x00,
336 .bias_boost_2 = 0xa5,
337 .tx_ctrl_1 = TX_REG_STEP_N_25MV,
338 .tx_ctrl_2 = 0x71,
339 .tx_ctrl_3 = 0x60,
340 .rx_k_gain = 0x98,
341 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
342 .rx_vga_gain = 0x00,
343 .rx_equ_gain_1 = 0x79,
344 .rx_equ_gain_2 = 0x56,
345 },
346 {
347 .bank = 0x01,
348 .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC,
349 .bias_boost_1 = 0x00,
350 .bias_boost_2 = 0xa5,
351 .tx_ctrl_1 = TX_REG_STEP_N_25MV,
352 .tx_ctrl_2 = 0x70,
353 .tx_ctrl_3 = 0x60,
354 .rx_k_gain = 0xcc,
355 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN,
356 .rx_vga_gain = 0x00,
357 .rx_equ_gain_1 = 0x78,
358 .rx_equ_gain_2 = 0x07,
359 },
360};
361
362static inline void miphy28lp_set_reset(struct miphy28lp_phy *miphy_phy)
363{
364 void *base = miphy_phy->base;
365 u8 val;
366
367 /* Putting Macro in reset */
368 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
369
370 val = RST_APPLI_SW | RST_CONF_SW;
371 writeb_relaxed(val, base + MIPHY_CONF_RESET);
372
373 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
374
375 /* Bringing the MIPHY-CPU registers out of reset */
376 if (miphy_phy->type == PHY_TYPE_PCIE) {
377 val = AUTO_RST_RX | TERM_EN_SW;
378 writeb_relaxed(val, base + MIPHY_CONTROL);
379 } else {
380 val = AUTO_RST_RX | TERM_EN_SW | DIS_LINK_RST;
381 writeb_relaxed(val, base + MIPHY_CONTROL);
382 }
383}
384
385static inline void miphy28lp_pll_calibration(struct miphy28lp_phy *miphy_phy,
386 struct pll_ratio *pll_ratio)
387{
388 void *base = miphy_phy->base;
389 u8 val;
390
391 /* Applying PLL Settings */
392 writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
393 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
394
395 /* PLL Ratio */
396 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1);
397 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2);
398 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3);
399 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4);
400 writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL);
401
402 writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL);
403
404 val = (0x68 << 1) | TX_SLEW_CAL_MAN_EN;
405 writeb_relaxed(val, base + MIPHY_TX_CAL_MAN);
406
407 val = VGA_OFFSET_POLARITY | CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64;
408
409 if (miphy_phy->type != PHY_TYPE_SATA)
410 val |= OFFSET_COMPENSATION_EN;
411
412 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
413
414 if (miphy_phy->type == PHY_TYPE_USB3) {
415 writeb_relaxed(0x00, base + MIPHY_CONF);
416 writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP);
417 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA);
418 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL);
419 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL);
420
421 val = EN_DIGIT_SIGNAL_CHECK | EN_FIRST_HALF;
422 writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL);
423 }
424
425}
426
427static inline void miphy28lp_sata_config_gen(struct miphy28lp_phy *miphy_phy)
428{
429 void __iomem *base = miphy_phy->base;
430 int i;
431
432 for (i = 0; i < ARRAY_SIZE(sata_pll_gen); i++) {
433 struct miphy28lp_pll_gen *gen = &sata_pll_gen[i];
434
435 /* Banked settings */
436 writeb_relaxed(gen->bank, base + MIPHY_CONF);
437 writeb_relaxed(gen->speed, base + MIPHY_SPEED);
438 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
439 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
440
441 /* TX buffer Settings */
442 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
443 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
444
445 /* RX Buffer Settings */
446 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
447 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
448 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
449 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
450 writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3);
451 }
452}
453
454static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy *miphy_phy)
455{
456 void __iomem *base = miphy_phy->base;
457 int i;
458
459 for (i = 0; i < ARRAY_SIZE(pcie_pll_gen); i++) {
460 struct miphy28lp_pll_gen *gen = &pcie_pll_gen[i];
461
462 /* Banked settings */
463 writeb_relaxed(gen->bank, base + MIPHY_CONF);
464 writeb_relaxed(gen->speed, base + MIPHY_SPEED);
465 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
466 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
467
468 /* TX buffer Settings */
469 writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1);
470 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
471 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
472
473 writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN);
474
475 /* RX Buffer Settings */
476 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
477 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
478 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
479 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
480 }
481}
482
483static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy)
484{
485 unsigned long finish = jiffies + 5 * HZ;
486 u8 val;
487
488 /* Waiting for Compensation to complete */
489 do {
490 val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6);
491
492 if (time_after_eq(jiffies, finish))
493 return -EBUSY;
494 cpu_relax();
495 } while (!(val & COMP_DONE));
496
497 return 0;
498}
499
500
501static inline int miphy28lp_compensation(struct miphy28lp_phy *miphy_phy,
502 struct pll_ratio *pll_ratio)
503{
504 void __iomem *base = miphy_phy->base;
505
506 /* Poll for HFC ready after reset release */
507 /* Compensation measurement */
508 writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET);
509
510 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
511 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
512 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
513
514 if (miphy_phy->type == PHY_TYPE_PCIE)
515 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
516
517 writeb_relaxed(0x00, base + MIPHY_RESET);
518 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
519 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
520
521 /* TX compensation offset to re-center TX impedance */
522 writeb_relaxed(0x00, base + MIPHY_COMP_POSTP);
523
524 if (miphy_phy->type == PHY_TYPE_PCIE)
525 return miphy28lp_wait_compensation(miphy_phy);
526
527 return 0;
528}
529
530static inline void miphy28_usb3_miphy_reset(struct miphy28lp_phy *miphy_phy)
531{
532 void __iomem *base = miphy_phy->base;
533 u8 val;
534
535 /* MIPHY Reset */
536 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
537 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
538 writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET);
539
540 val = RST_COMP_SW | RST_PLL_SW;
541 writeb_relaxed(val, base + MIPHY_RESET);
542
543 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
544 writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
545 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
546 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
547 writeb_relaxed(0x00, base + MIPHY_RESET);
548 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
549 writeb_relaxed(0x00, base + MIPHY_CONF);
550 writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1);
551 writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2);
552 writeb_relaxed(0x00, base + MIPHY_CONF);
553 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
554 writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS);
555 writeb_relaxed(0x00, base + MIPHY_CONF);
556}
557
558static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
559{
560 void __iomem *base = miphy_phy->base;
561 u8 val;
562
563 /* Compensate Tx impedance to avoid out of range values */
564 /*
565 * Enable the SSC on PLL for all banks
566 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
567 */
568 val = readb_relaxed(base + MIPHY_BOUNDARY_2);
569 val |= SSC_EN_SW;
570 writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
571
572 val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
573 val |= SSC_SEL;
574 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
575
576 for (val = 0; val < MIPHY_SATA_BANK_NB; val++) {
577 writeb_relaxed(val, base + MIPHY_CONF);
578
579 /* Add value to each reference clock cycle */
580 /* and define the period length of the SSC */
581 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
582 writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3);
583 writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4);
584
585 /* Clear any previous request */
586 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
587
588 /* requests the PLL to take in account new parameters */
589 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
590
591 /* To be sure there is no other pending requests */
592 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
593 }
594}
595
596static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
597{
598 void __iomem *base = miphy_phy->base;
599 u8 val;
600
601 /* Compensate Tx impedance to avoid out of range values */
602 /*
603 * Enable the SSC on PLL for all banks
604 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp
605 */
606 val = readb_relaxed(base + MIPHY_BOUNDARY_2);
607 val |= SSC_EN_SW;
608 writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
609
610 val = readb_relaxed(base + MIPHY_BOUNDARY_SEL);
611 val |= SSC_SEL;
612 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
613
614 for (val = 0; val < MIPHY_PCIE_BANK_NB; val++) {
615 writeb_relaxed(val, base + MIPHY_CONF);
616
617 /* Validate Step component */
618 writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3);
619 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
620
621 /* Validate Period component */
622 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
623 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
624
625 /* Clear any previous request */
626 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
627
628 /* requests the PLL to take in account new parameters */
629 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
630
631 /* To be sure there is no other pending requests */
632 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
633 }
634}
635
636static inline void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy)
637{
638 /* Compensate Tx impedance to avoid out of range values */
639 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);
640}
641
642static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
643{
644 void __iomem *base = miphy_phy->base;
645 int err;
646 u8 val;
647
648 /* Putting Macro in reset */
649 miphy28lp_set_reset(miphy_phy);
650
651 /* PLL calibration */
652 miphy28lp_pll_calibration(miphy_phy, &sata_pll_ratio);
653
654 /* Banked settings Gen1/Gen2/Gen3 */
655 miphy28lp_sata_config_gen(miphy_phy);
656
657 /* Power control */
658 /* Input bridge enable, manual input bridge control */
659 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
660
661 /* Macro out of reset */
662 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
663
664 /* Poll for HFC ready after reset release */
665 /* Compensation measurement */
666 err = miphy28lp_compensation(miphy_phy, &sata_pll_ratio);
667 if (err)
668 return err;
669
670 if (miphy_phy->px_rx_pol_inv) {
671 /* Invert Rx polarity */
672 val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL);
673 val |= PX_RX_POL;
674 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
675 }
676
677 if (miphy_phy->ssc)
678 miphy_sata_tune_ssc(miphy_phy);
679
680 if (miphy_phy->tx_impedance)
681 miphy_tune_tx_impedance(miphy_phy);
682
683 return 0;
684}
685
686static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
687{
688 void __iomem *base = miphy_phy->base;
689 int err;
690
691 /* Putting Macro in reset */
692 miphy28lp_set_reset(miphy_phy);
693
694 /* PLL calibration */
695 miphy28lp_pll_calibration(miphy_phy, &pcie_pll_ratio);
696
697 /* Banked settings Gen1/Gen2 */
698 miphy28lp_pcie_config_gen(miphy_phy);
699
700 /* Power control */
701 /* Input bridge enable, manual input bridge control */
702 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
703
704 /* Macro out of reset */
705 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
706
707 /* Poll for HFC ready after reset release */
708 /* Compensation measurement */
709 err = miphy28lp_compensation(miphy_phy, &pcie_pll_ratio);
710 if (err)
711 return err;
712
713 if (miphy_phy->ssc)
714 miphy_pcie_tune_ssc(miphy_phy);
715
716 if (miphy_phy->tx_impedance)
717 miphy_tune_tx_impedance(miphy_phy);
718
719 return 0;
720}
721
722
723static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy)
724{
725 void __iomem *base = miphy_phy->base;
726 u8 val;
727
728 /* Putting Macro in reset */
729 miphy28lp_set_reset(miphy_phy);
730
731 /* PLL calibration */
732 miphy28lp_pll_calibration(miphy_phy, &usb3_pll_ratio);
733
734 /* Writing The Speed Rate */
735 writeb_relaxed(0x00, base + MIPHY_CONF);
736
737 val = RX_SPDSEL_20DEC | TX_SPDSEL_20DEC;
738 writeb_relaxed(val, base + MIPHY_SPEED);
739
740 /* RX Channel compensation and calibration */
741 writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT);
742 writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1);
743 writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2);
744
745 val = OFFSET_COMPENSATION_EN | VGA_OFFSET_POLARITY |
746 CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64;
747 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
748 writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP);
749 writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH);
750
751 val = EQ_DC_GAIN | VGA_GAIN;
752 writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL);
753 writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);
754 writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL);
755
756 /* TX compensation offset to re-center TX impedance */
757 writeb_relaxed(0x02, base + MIPHY_COMP_POSTP);
758
759 /* Enable GENSEL_SEL and SSC */
760 /* TX_SEL=0 swing preemp forced by pipe registres */
761 val = SSC_SEL | GENSEL_SEL;
762 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
763
764 /* MIPHY Bias boost */
765 writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
766 writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2);
767
768 /* SSC modulation */
769 writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2);
770
771 /* MIPHY TX control */
772 writeb_relaxed(0x00, base + MIPHY_CONF);
773
774 /* Validate Step component */
775 writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3);
776 writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4);
777
778 /* Validate Period component */
779 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
780 writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4);
781
782 /* Clear any previous request */
783 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
784
785 /* requests the PLL to take in account new parameters */
786 writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
787
788 /* To be sure there is no other pending requests */
789 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
790
791 /* Rx PI controller settings */
792 writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN);
793
794 /* MIPHY RX input bridge control */
795 /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */
796 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
797 writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1);
798 writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2);
799
800 /* MIPHY Reset for usb3 */
801 miphy28_usb3_miphy_reset(miphy_phy);
802}
803
804static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy)
805{
806 unsigned long finish = jiffies + 5 * HZ;
807 u8 mask = HFC_PLL | HFC_RDY;
808 u8 val;
809
810 /*
811 * For PCIe and USB3 check only that PLL and HFC are ready
812 * For SATA check also that phy is ready!
813 */
814 if (miphy_phy->type == PHY_TYPE_SATA)
815 mask |= PHY_RDY;
816
817 do {
818 val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1);
819 if ((val & mask) != mask)
820 cpu_relax();
821 else
822 return 0;
823 } while (!time_after_eq(jiffies, finish));
824
825 return -EBUSY;
826}
827
828static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy)
829{
830 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
831 unsigned long finish = jiffies + 5 * HZ;
832 u32 val;
833
834 if (!miphy_phy->osc_rdy)
835 return 0;
836
837 if (!miphy_phy->syscfg_miphy_status)
838 return -EINVAL;
839
840 do {
841 regmap_read(miphy_dev->regmap, miphy_phy->syscfg_miphy_status,
842 &val);
843
844 if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY)
845 cpu_relax();
846 else
847 return 0;
848 } while (!time_after_eq(jiffies, finish));
849
850 return -EBUSY;
851}
852
853static int miphy28lp_get_resource_byname(struct device_node *child,
854 char *rname, struct resource *res)
855{
856 int index;
857
858 index = of_property_match_string(child, "reg-names", rname);
859 if (index < 0)
860 return -ENODEV;
861
862 return of_address_to_resource(child, index, res);
863}
864
865static int miphy28lp_get_one_addr(struct device *dev,
866 struct device_node *child, char *rname,
867 void __iomem **base)
868{
869 struct resource res;
870 int ret;
871
872 ret = miphy28lp_get_resource_byname(child, rname, &res);
873 if (!ret) {
874 *base = devm_ioremap(dev, res.start, resource_size(&res));
875 if (!*base) {
876 dev_err(dev, "failed to ioremap %s address region\n"
877 , rname);
878 return -ENOENT;
879 }
880 }
881
882 return 0;
883}
884
885/* MiPHY reset and sysconf setup */
886static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val)
887{
888 int err;
889 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
890
891 if (!miphy_phy->syscfg_miphy_ctrl)
892 return -EINVAL;
893
894 err = reset_control_assert(miphy_phy->miphy_rst);
895 if (err) {
896 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
897 return err;
898 }
899
900 if (miphy_phy->osc_force_ext)
901 miphy_val |= MIPHY_OSC_FORCE_EXT;
902
903 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_miphy_ctrl,
904 MIPHY_CTRL_MASK, miphy_val);
905
906 err = reset_control_deassert(miphy_phy->miphy_rst);
907 if (err) {
908 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
909 return err;
910 }
911
912 return miphy_osc_is_ready(miphy_phy);
913}
914
915static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
916{
917 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
918 int err, sata_conf = SATA_CTRL_SELECT_SATA;
919
920 if ((!miphy_phy->syscfg_sata) || (!miphy_phy->syscfg_pci)
921 || (!miphy_phy->base))
922 return -EINVAL;
923
924 dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base);
925
926 /* Configure the glue-logic */
927 sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE);
928
929 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_sata,
930 SATA_CTRL_MASK, sata_conf);
931
932 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_pci,
933 PCIE_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
934
935 /* MiPHY path and clocking init */
936 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
937
938 if (err) {
939 dev_err(miphy_dev->dev, "SATA phy setup failed\n");
940 return err;
941 }
942
943 /* initialize miphy */
944 miphy28lp_configure_sata(miphy_phy);
945
946 return miphy_is_ready(miphy_phy);
947}
948
949static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy)
950{
951 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
952 int err;
953
954 if ((!miphy_phy->syscfg_sata) || (!miphy_phy->syscfg_pci)
955 || (!miphy_phy->base) || (!miphy_phy->pipebase))
956 return -EINVAL;
957
958 dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base);
959
960 /* Configure the glue-logic */
961 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_sata,
962 SATA_CTRL_MASK, SATA_CTRL_SELECT_PCIE);
963
964 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_pci,
965 PCIE_CTRL_MASK, SYSCFG_PCIE_PCIE_VAL);
966
967 /* MiPHY path and clocking init */
968 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
969
970 if (err) {
971 dev_err(miphy_dev->dev, "PCIe phy setup failed\n");
972 return err;
973 }
974
975 /* initialize miphy */
976 err = miphy28lp_configure_pcie(miphy_phy);
977 if (err)
978 return err;
979
980 /* PIPE Wrapper Configuration */
981 writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */
982 writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */
983 writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */
984 writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */
985 writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */
986 writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */
987
988 /* Wait for phy_ready */
989 return miphy_is_ready(miphy_phy);
990}
991
992static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy)
993{
994 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
995 int err;
996
997 if ((!miphy_phy->base) || (!miphy_phy->pipebase))
998 return -EINVAL;
999
1000 dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base);
1001
1002 /* MiPHY path and clocking init */
1003 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN);
1004 if (err) {
1005 dev_err(miphy_dev->dev, "USB3 phy setup failed\n");
1006 return err;
1007 }
1008
1009 /* initialize miphy */
1010 miphy28lp_configure_usb3(miphy_phy);
1011
1012 /* PIPE Wrapper Configuration */
1013 writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);
1014 writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);
1015 writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);
1016 writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);
1017 writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);
1018 writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);
1019
1020 /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */
1021 writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);
1022 writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);
1023 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);
1024 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);
1025 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);
1026 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);
1027 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);
1028 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);
1029
1030 return miphy_is_ready(miphy_phy);
1031}
1032
1033static int miphy28lp_init(struct phy *phy)
1034{
1035 struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy);
1036 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1037 int ret;
1038
1039 mutex_lock(&miphy_dev->miphy_mutex);
1040
1041 switch (miphy_phy->type) {
1042
1043 case PHY_TYPE_SATA:
1044 ret = miphy28lp_init_sata(miphy_phy);
1045 break;
1046 case PHY_TYPE_PCIE:
1047 ret = miphy28lp_init_pcie(miphy_phy);
1048 break;
1049 case PHY_TYPE_USB3:
1050 ret = miphy28lp_init_usb3(miphy_phy);
1051 break;
1052 default:
1053 return -EINVAL;
1054 }
1055
1056 mutex_unlock(&miphy_dev->miphy_mutex);
1057
1058 return ret;
1059}
1060
1061static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy)
1062{
1063 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1064 struct device_node *phynode = miphy_phy->phy->dev.of_node;
1065 int err;
1066
1067 if ((miphy_phy->type != PHY_TYPE_SATA) &&
1068 (miphy_phy->type != PHY_TYPE_PCIE) &&
1069 (miphy_phy->type != PHY_TYPE_USB3)) {
1070 return -EINVAL;
1071 }
1072
1073 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode,
1074 PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA],
1075 &miphy_phy->base);
1076 if (err)
1077 return err;
1078
1079 if ((miphy_phy->type == PHY_TYPE_PCIE) ||
1080 (miphy_phy->type == PHY_TYPE_USB3)) {
1081 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew",
1082 &miphy_phy->pipebase);
1083 if (err)
1084 return err;
1085 }
1086
1087 return 0;
1088}
1089
1090static struct phy *miphy28lp_xlate(struct device *dev,
1091 struct of_phandle_args *args)
1092{
1093 struct miphy28lp_dev *miphy_dev = dev_get_drvdata(dev);
1094 struct miphy28lp_phy *miphy_phy = NULL;
1095 struct device_node *phynode = args->np;
1096 int ret, index = 0;
1097
1098 if (!of_device_is_available(phynode)) {
1099 dev_warn(dev, "Requested PHY is disabled\n");
1100 return ERR_PTR(-ENODEV);
1101 }
1102
1103 if (args->args_count != 1) {
1104 dev_err(dev, "Invalid number of cells in 'phy' property\n");
1105 return ERR_PTR(-EINVAL);
1106 }
1107
1108 for (index = 0; index < of_get_child_count(dev->of_node); index++)
1109 if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
1110 miphy_phy = miphy_dev->phys[index];
1111 break;
1112 }
1113
1114 if (!miphy_phy) {
1115 dev_err(dev, "Failed to find appropriate phy\n");
1116 return ERR_PTR(-EINVAL);
1117 }
1118
1119 miphy_phy->type = args->args[0];
1120
1121 ret = miphy28lp_get_addr(miphy_phy);
1122 if (ret < 0)
1123 return ERR_PTR(ret);
1124
1125 return miphy_phy->phy;
1126}
1127
1128static struct phy_ops miphy28lp_ops = {
1129 .init = miphy28lp_init,
1130};
1131
1132static int miphy28lp_probe_resets(struct device_node *node,
1133 struct miphy28lp_phy *miphy_phy)
1134{
1135 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1136 int err;
1137
1138 miphy_phy->miphy_rst = of_reset_control_get(node, "miphy-sw-rst");
1139
1140 if (IS_ERR(miphy_phy->miphy_rst)) {
1141 dev_err(miphy_dev->dev,
1142 "miphy soft reset control not defined\n");
1143 return PTR_ERR(miphy_phy->miphy_rst);
1144 }
1145
1146 err = reset_control_deassert(miphy_phy->miphy_rst);
1147 if (err) {
1148 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n");
1149 return err;
1150 }
1151
1152 return 0;
1153}
1154
1155static int miphy28lp_of_probe(struct device_node *np,
1156 struct miphy28lp_phy *miphy_phy)
1157{
1158 struct resource res;
1159
1160 miphy_phy->osc_force_ext =
1161 of_property_read_bool(np, "st,osc-force-ext");
1162
1163 miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy");
1164
1165 miphy_phy->px_rx_pol_inv =
1166 of_property_read_bool(np, "st,px_rx_pol_inv");
1167
1168 miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
1169
1170 miphy_phy->tx_impedance =
1171 of_property_read_bool(np, "st,tx-impedance-comp");
1172
1173 of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
1174 if (!miphy_phy->sata_gen)
1175 miphy_phy->sata_gen = SATA_GEN1;
1176
1177 if (!miphy28lp_get_resource_byname(np, "miphy-ctrl-glue", &res))
1178 miphy_phy->syscfg_miphy_ctrl = res.start;
1179
1180 if (!miphy28lp_get_resource_byname(np, "miphy-status-glue", &res))
1181 miphy_phy->syscfg_miphy_status = res.start;
1182
1183 if (!miphy28lp_get_resource_byname(np, "pcie-glue", &res))
1184 miphy_phy->syscfg_pci = res.start;
1185
1186 if (!miphy28lp_get_resource_byname(np, "sata-glue", &res))
1187 miphy_phy->syscfg_sata = res.start;
1188
1189
1190 return 0;
1191}
1192
1193static int miphy28lp_probe(struct platform_device *pdev)
1194{
1195 struct device_node *child, *np = pdev->dev.of_node;
1196 struct miphy28lp_dev *miphy_dev;
1197 struct phy_provider *provider;
1198 struct phy *phy;
1199 int chancount, port = 0;
1200 int ret;
1201
1202 miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
1203 if (!miphy_dev)
1204 return -ENOMEM;
1205
1206 chancount = of_get_child_count(np);
1207 miphy_dev->phys = devm_kzalloc(&pdev->dev, sizeof(phy) * chancount,
1208 GFP_KERNEL);
1209 if (!miphy_dev->phys)
1210 return -ENOMEM;
1211
1212 miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1213 if (IS_ERR(miphy_dev->regmap)) {
1214 dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
1215 return PTR_ERR(miphy_dev->regmap);
1216 }
1217
1218 miphy_dev->dev = &pdev->dev;
1219
1220 dev_set_drvdata(&pdev->dev, miphy_dev);
1221
1222 mutex_init(&miphy_dev->miphy_mutex);
1223
1224 for_each_child_of_node(np, child) {
1225 struct miphy28lp_phy *miphy_phy;
1226
1227 miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
1228 GFP_KERNEL);
1229 if (!miphy_phy)
1230 return -ENOMEM;
1231
1232 miphy_dev->phys[port] = miphy_phy;
1233
1234 phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops);
1235 if (IS_ERR(phy)) {
1236 dev_err(&pdev->dev, "failed to create PHY\n");
1237 return PTR_ERR(phy);
1238 }
1239
1240 miphy_dev->phys[port]->phy = phy;
1241 miphy_dev->phys[port]->phydev = miphy_dev;
1242
1243 ret = miphy28lp_of_probe(child, miphy_phy);
1244 if (ret)
1245 return ret;
1246
1247 ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]);
1248 if (ret)
1249 return ret;
1250
1251 phy_set_drvdata(phy, miphy_dev->phys[port]);
1252 port++;
1253
1254 }
1255
1256 provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate);
1257 if (IS_ERR(provider))
1258 return PTR_ERR(provider);
1259
1260 return 0;
1261}
1262
1263static const struct of_device_id miphy28lp_of_match[] = {
1264 {.compatible = "st,miphy28lp-phy", },
1265 {},
1266};
1267
1268MODULE_DEVICE_TABLE(of, miphy28lp_of_match);
1269
1270static struct platform_driver miphy28lp_driver = {
1271 .probe = miphy28lp_probe,
1272 .driver = {
1273 .name = "miphy28lp-phy",
1274 .owner = THIS_MODULE,
1275 .of_match_table = miphy28lp_of_match,
1276 }
1277};
1278
1279module_platform_driver(miphy28lp_driver);
1280
1281MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>");
1282MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver");
1283MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
index 801afaf2d449..6ab43a814ad2 100644
--- a/drivers/phy/phy-miphy365x.c
+++ b/drivers/phy/phy-miphy365x.c
@@ -593,7 +593,7 @@ static int miphy365x_probe(struct platform_device *pdev)
593 593
594 miphy_dev->phys[port] = miphy_phy; 594 miphy_dev->phys[port] = miphy_phy;
595 595
596 phy = devm_phy_create(&pdev->dev, child, &miphy365x_ops, NULL); 596 phy = devm_phy_create(&pdev->dev, child, &miphy365x_ops);
597 if (IS_ERR(phy)) { 597 if (IS_ERR(phy)) {
598 dev_err(&pdev->dev, "failed to create PHY\n"); 598 dev_err(&pdev->dev, "failed to create PHY\n");
599 return PTR_ERR(phy); 599 return PTR_ERR(phy);
@@ -610,10 +610,7 @@ static int miphy365x_probe(struct platform_device *pdev)
610 } 610 }
611 611
612 provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate); 612 provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
613 if (IS_ERR(provider)) 613 return PTR_ERR_OR_ZERO(provider);
614 return PTR_ERR(provider);
615
616 return 0;
617} 614}
618 615
619static const struct of_device_id miphy365x_of_match[] = { 616static const struct of_device_id miphy365x_of_match[] = {
diff --git a/drivers/phy/phy-mvebu-sata.c b/drivers/phy/phy-mvebu-sata.c
index d395558cb12e..03b94f92e6f1 100644
--- a/drivers/phy/phy-mvebu-sata.c
+++ b/drivers/phy/phy-mvebu-sata.c
@@ -101,7 +101,7 @@ static int phy_mvebu_sata_probe(struct platform_device *pdev)
101 if (IS_ERR(priv->clk)) 101 if (IS_ERR(priv->clk))
102 return PTR_ERR(priv->clk); 102 return PTR_ERR(priv->clk);
103 103
104 phy = devm_phy_create(&pdev->dev, NULL, &phy_mvebu_sata_ops, NULL); 104 phy = devm_phy_create(&pdev->dev, NULL, &phy_mvebu_sata_ops);
105 if (IS_ERR(phy)) 105 if (IS_ERR(phy))
106 return PTR_ERR(phy); 106 return PTR_ERR(phy);
107 107
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 08f2da270837..4e489a8850e5 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -256,7 +256,7 @@ static int omap_usb2_probe(struct platform_device *pdev)
256 platform_set_drvdata(pdev, phy); 256 platform_set_drvdata(pdev, phy);
257 pm_runtime_enable(phy->dev); 257 pm_runtime_enable(phy->dev);
258 258
259 generic_phy = devm_phy_create(phy->dev, NULL, &ops, NULL); 259 generic_phy = devm_phy_create(phy->dev, NULL, &ops);
260 if (IS_ERR(generic_phy)) { 260 if (IS_ERR(generic_phy)) {
261 pm_runtime_disable(phy->dev); 261 pm_runtime_disable(phy->dev);
262 return PTR_ERR(generic_phy); 262 return PTR_ERR(generic_phy);
diff --git a/drivers/phy/phy-qcom-apq8064-sata.c b/drivers/phy/phy-qcom-apq8064-sata.c
index 7b3ddfb65898..4b243f7a10e4 100644
--- a/drivers/phy/phy-qcom-apq8064-sata.c
+++ b/drivers/phy/phy-qcom-apq8064-sata.c
@@ -228,8 +228,7 @@ static int qcom_apq8064_sata_phy_probe(struct platform_device *pdev)
228 if (IS_ERR(phy->mmio)) 228 if (IS_ERR(phy->mmio))
229 return PTR_ERR(phy->mmio); 229 return PTR_ERR(phy->mmio);
230 230
231 generic_phy = devm_phy_create(dev, NULL, &qcom_apq8064_sata_phy_ops, 231 generic_phy = devm_phy_create(dev, NULL, &qcom_apq8064_sata_phy_ops);
232 NULL);
233 if (IS_ERR(generic_phy)) { 232 if (IS_ERR(generic_phy)) {
234 dev_err(dev, "%s: failed to create phy\n", __func__); 233 dev_err(dev, "%s: failed to create phy\n", __func__);
235 return PTR_ERR(generic_phy); 234 return PTR_ERR(generic_phy);
diff --git a/drivers/phy/phy-qcom-ipq806x-sata.c b/drivers/phy/phy-qcom-ipq806x-sata.c
index 759b0bf5b6b3..6f2fe2627916 100644
--- a/drivers/phy/phy-qcom-ipq806x-sata.c
+++ b/drivers/phy/phy-qcom-ipq806x-sata.c
@@ -150,8 +150,7 @@ static int qcom_ipq806x_sata_phy_probe(struct platform_device *pdev)
150 if (IS_ERR(phy->mmio)) 150 if (IS_ERR(phy->mmio))
151 return PTR_ERR(phy->mmio); 151 return PTR_ERR(phy->mmio);
152 152
153 generic_phy = devm_phy_create(dev, NULL, &qcom_ipq806x_sata_phy_ops, 153 generic_phy = devm_phy_create(dev, NULL, &qcom_ipq806x_sata_phy_ops);
154 NULL);
155 if (IS_ERR(generic_phy)) { 154 if (IS_ERR(generic_phy)) {
156 dev_err(dev, "%s: failed to create phy\n", __func__); 155 dev_err(dev, "%s: failed to create phy\n", __func__);
157 return PTR_ERR(generic_phy); 156 return PTR_ERR(generic_phy);
diff --git a/drivers/phy/phy-rcar-gen2.c b/drivers/phy/phy-rcar-gen2.c
index 2793af17799f..778276aba3aa 100644
--- a/drivers/phy/phy-rcar-gen2.c
+++ b/drivers/phy/phy-rcar-gen2.c
@@ -304,7 +304,7 @@ static int rcar_gen2_phy_probe(struct platform_device *pdev)
304 phy->select_value = select_value[channel_num][n]; 304 phy->select_value = select_value[channel_num][n];
305 305
306 phy->phy = devm_phy_create(dev, NULL, 306 phy->phy = devm_phy_create(dev, NULL,
307 &rcar_gen2_phy_ops, NULL); 307 &rcar_gen2_phy_ops);
308 if (IS_ERR(phy->phy)) { 308 if (IS_ERR(phy->phy)) {
309 dev_err(dev, "Failed to create PHY\n"); 309 dev_err(dev, "Failed to create PHY\n");
310 return PTR_ERR(phy->phy); 310 return PTR_ERR(phy->phy);
diff --git a/drivers/phy/phy-samsung-usb2.c b/drivers/phy/phy-samsung-usb2.c
index 908949dfb4db..4a12f66b7fb5 100644
--- a/drivers/phy/phy-samsung-usb2.c
+++ b/drivers/phy/phy-samsung-usb2.c
@@ -202,8 +202,7 @@ static int samsung_usb2_phy_probe(struct platform_device *pdev)
202 struct samsung_usb2_phy_instance *p = &drv->instances[i]; 202 struct samsung_usb2_phy_instance *p = &drv->instances[i];
203 203
204 dev_dbg(dev, "Creating phy \"%s\"\n", label); 204 dev_dbg(dev, "Creating phy \"%s\"\n", label);
205 p->phy = devm_phy_create(dev, NULL, &samsung_usb2_phy_ops, 205 p->phy = devm_phy_create(dev, NULL, &samsung_usb2_phy_ops);
206 NULL);
207 if (IS_ERR(p->phy)) { 206 if (IS_ERR(p->phy)) {
208 dev_err(drv->dev, "Failed to create usb2_phy \"%s\"\n", 207 dev_err(drv->dev, "Failed to create usb2_phy \"%s\"\n",
209 label); 208 label);
diff --git a/drivers/phy/phy-spear1310-miphy.c b/drivers/phy/phy-spear1310-miphy.c
index 5f4c586ee951..9f47fae7eecb 100644
--- a/drivers/phy/phy-spear1310-miphy.c
+++ b/drivers/phy/phy-spear1310-miphy.c
@@ -227,7 +227,7 @@ static int spear1310_miphy_probe(struct platform_device *pdev)
227 return -EINVAL; 227 return -EINVAL;
228 } 228 }
229 229
230 priv->phy = devm_phy_create(dev, NULL, &spear1310_miphy_ops, NULL); 230 priv->phy = devm_phy_create(dev, NULL, &spear1310_miphy_ops);
231 if (IS_ERR(priv->phy)) { 231 if (IS_ERR(priv->phy)) {
232 dev_err(dev, "failed to create SATA PCIe PHY\n"); 232 dev_err(dev, "failed to create SATA PCIe PHY\n");
233 return PTR_ERR(priv->phy); 233 return PTR_ERR(priv->phy);
diff --git a/drivers/phy/phy-spear1340-miphy.c b/drivers/phy/phy-spear1340-miphy.c
index 1ecd0945bad3..e42bc200275f 100644
--- a/drivers/phy/phy-spear1340-miphy.c
+++ b/drivers/phy/phy-spear1340-miphy.c
@@ -259,7 +259,7 @@ static int spear1340_miphy_probe(struct platform_device *pdev)
259 return PTR_ERR(priv->misc); 259 return PTR_ERR(priv->misc);
260 } 260 }
261 261
262 priv->phy = devm_phy_create(dev, NULL, &spear1340_miphy_ops, NULL); 262 priv->phy = devm_phy_create(dev, NULL, &spear1340_miphy_ops);
263 if (IS_ERR(priv->phy)) { 263 if (IS_ERR(priv->phy)) {
264 dev_err(dev, "failed to create SATA PCIe PHY\n"); 264 dev_err(dev, "failed to create SATA PCIe PHY\n");
265 return PTR_ERR(priv->phy); 265 return PTR_ERR(priv->phy);
diff --git a/drivers/phy/phy-stih407-usb.c b/drivers/phy/phy-stih407-usb.c
index 42428d4181ea..74f0fab3cd8a 100644
--- a/drivers/phy/phy-stih407-usb.c
+++ b/drivers/phy/phy-stih407-usb.c
@@ -137,7 +137,7 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
137 } 137 }
138 phy_dev->param = res->start; 138 phy_dev->param = res->start;
139 139
140 phy = devm_phy_create(dev, NULL, &stih407_usb2_picophy_data, NULL); 140 phy = devm_phy_create(dev, NULL, &stih407_usb2_picophy_data);
141 if (IS_ERR(phy)) { 141 if (IS_ERR(phy)) {
142 dev_err(dev, "failed to create Display Port PHY\n"); 142 dev_err(dev, "failed to create Display Port PHY\n");
143 return PTR_ERR(phy); 143 return PTR_ERR(phy);
diff --git a/drivers/phy/phy-stih41x-usb.c b/drivers/phy/phy-stih41x-usb.c
index 9f16cb8e01f4..a603801293ff 100644
--- a/drivers/phy/phy-stih41x-usb.c
+++ b/drivers/phy/phy-stih41x-usb.c
@@ -148,7 +148,7 @@ static int stih41x_usb_phy_probe(struct platform_device *pdev)
148 return PTR_ERR(phy_dev->clk); 148 return PTR_ERR(phy_dev->clk);
149 } 149 }
150 150
151 phy = devm_phy_create(dev, NULL, &stih41x_usb_phy_ops, NULL); 151 phy = devm_phy_create(dev, NULL, &stih41x_usb_phy_ops);
152 152
153 if (IS_ERR(phy)) { 153 if (IS_ERR(phy)) {
154 dev_err(dev, "failed to create phy\n"); 154 dev_err(dev, "failed to create phy\n");
@@ -160,10 +160,7 @@ static int stih41x_usb_phy_probe(struct platform_device *pdev)
160 phy_set_drvdata(phy, phy_dev); 160 phy_set_drvdata(phy, phy_dev);
161 161
162 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 162 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
163 if (IS_ERR(phy_provider)) 163 return PTR_ERR_OR_ZERO(phy_provider);
164 return PTR_ERR(phy_provider);
165
166 return 0;
167} 164}
168 165
169static const struct of_device_id stih41x_usb_phy_of_match[] = { 166static const struct of_device_id stih41x_usb_phy_of_match[] = {
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 0baf5efc8a40..fb02a67c9181 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -157,6 +157,10 @@ static int sun4i_usb_phy_init(struct phy *_phy)
157 return ret; 157 return ret;
158 } 158 }
159 159
160 /* Enable USB 45 Ohm resistor calibration */
161 if (phy->index == 0)
162 sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
163
160 /* Adjust PHY's magnitude and rate */ 164 /* Adjust PHY's magnitude and rate */
161 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5); 165 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
162 166
@@ -213,7 +217,7 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
213{ 217{
214 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev); 218 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
215 219
216 if (WARN_ON(args->args[0] == 0 || args->args[0] >= data->num_phys)) 220 if (args->args[0] >= data->num_phys)
217 return ERR_PTR(-ENODEV); 221 return ERR_PTR(-ENODEV);
218 222
219 return data->phys[args->args[0]].phy; 223 return data->phys[args->args[0]].phy;
@@ -255,8 +259,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
255 if (IS_ERR(data->base)) 259 if (IS_ERR(data->base))
256 return PTR_ERR(data->base); 260 return PTR_ERR(data->base);
257 261
258 /* Skip 0, 0 is the phy for otg which is not yet supported. */ 262 for (i = 0; i < data->num_phys; i++) {
259 for (i = 1; i < data->num_phys; i++) {
260 struct sun4i_usb_phy *phy = data->phys + i; 263 struct sun4i_usb_phy *phy = data->phys + i;
261 char name[16]; 264 char name[16];
262 265
@@ -295,7 +298,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
295 return PTR_ERR(phy->pmu); 298 return PTR_ERR(phy->pmu);
296 } 299 }
297 300
298 phy->phy = devm_phy_create(dev, NULL, &sun4i_usb_phy_ops, NULL); 301 phy->phy = devm_phy_create(dev, NULL, &sun4i_usb_phy_ops);
299 if (IS_ERR(phy->phy)) { 302 if (IS_ERR(phy->phy)) {
300 dev_err(dev, "failed to create PHY %d\n", i); 303 dev_err(dev, "failed to create PHY %d\n", i);
301 return PTR_ERR(phy->phy); 304 return PTR_ERR(phy->phy);
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index ab1e22d9a1e8..c297b7a10d30 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -399,7 +399,7 @@ static int ti_pipe3_probe(struct platform_device *pdev)
399 platform_set_drvdata(pdev, phy); 399 platform_set_drvdata(pdev, phy);
400 pm_runtime_enable(phy->dev); 400 pm_runtime_enable(phy->dev);
401 401
402 generic_phy = devm_phy_create(phy->dev, NULL, &ops, NULL); 402 generic_phy = devm_phy_create(phy->dev, NULL, &ops);
403 if (IS_ERR(generic_phy)) 403 if (IS_ERR(generic_phy))
404 return PTR_ERR(generic_phy); 404 return PTR_ERR(generic_phy);
405 405
diff --git a/drivers/phy/phy-twl4030-usb.c b/drivers/phy/phy-twl4030-usb.c
index e2698d29f436..8e87f54671f3 100644
--- a/drivers/phy/phy-twl4030-usb.c
+++ b/drivers/phy/phy-twl4030-usb.c
@@ -644,7 +644,6 @@ static int twl4030_usb_probe(struct platform_device *pdev)
644 struct usb_otg *otg; 644 struct usb_otg *otg;
645 struct device_node *np = pdev->dev.of_node; 645 struct device_node *np = pdev->dev.of_node;
646 struct phy_provider *phy_provider; 646 struct phy_provider *phy_provider;
647 struct phy_init_data *init_data = NULL;
648 647
649 twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL); 648 twl = devm_kzalloc(&pdev->dev, sizeof(*twl), GFP_KERNEL);
650 if (!twl) 649 if (!twl)
@@ -655,7 +654,6 @@ static int twl4030_usb_probe(struct platform_device *pdev)
655 (enum twl4030_usb_mode *)&twl->usb_mode); 654 (enum twl4030_usb_mode *)&twl->usb_mode);
656 else if (pdata) { 655 else if (pdata) {
657 twl->usb_mode = pdata->usb_mode; 656 twl->usb_mode = pdata->usb_mode;
658 init_data = pdata->init_data;
659 } else { 657 } else {
660 dev_err(&pdev->dev, "twl4030 initialized without pdata\n"); 658 dev_err(&pdev->dev, "twl4030 initialized without pdata\n");
661 return -EINVAL; 659 return -EINVAL;
@@ -680,7 +678,7 @@ static int twl4030_usb_probe(struct platform_device *pdev)
680 otg->set_host = twl4030_set_host; 678 otg->set_host = twl4030_set_host;
681 otg->set_peripheral = twl4030_set_peripheral; 679 otg->set_peripheral = twl4030_set_peripheral;
682 680
683 phy = devm_phy_create(twl->dev, NULL, &ops, init_data); 681 phy = devm_phy_create(twl->dev, NULL, &ops);
684 if (IS_ERR(phy)) { 682 if (IS_ERR(phy)) {
685 dev_dbg(&pdev->dev, "Failed to create PHY\n"); 683 dev_dbg(&pdev->dev, "Failed to create PHY\n");
686 return PTR_ERR(phy); 684 return PTR_ERR(phy);
@@ -733,6 +731,11 @@ static int twl4030_usb_probe(struct platform_device *pdev)
733 return status; 731 return status;
734 } 732 }
735 733
734 if (pdata)
735 err = phy_create_lookup(phy, "usb", "musb-hdrc.0");
736 if (err)
737 return err;
738
736 pm_runtime_mark_last_busy(&pdev->dev); 739 pm_runtime_mark_last_busy(&pdev->dev);
737 pm_runtime_put_autosuspend(twl->dev); 740 pm_runtime_put_autosuspend(twl->dev);
738 741
diff --git a/drivers/phy/phy-xgene.c b/drivers/phy/phy-xgene.c
index f8a51b16ade8..29214a36ea28 100644
--- a/drivers/phy/phy-xgene.c
+++ b/drivers/phy/phy-xgene.c
@@ -1707,7 +1707,7 @@ static int xgene_phy_probe(struct platform_device *pdev)
1707 ctx->dev = &pdev->dev; 1707 ctx->dev = &pdev->dev;
1708 platform_set_drvdata(pdev, ctx); 1708 platform_set_drvdata(pdev, ctx);
1709 1709
1710 ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops, NULL); 1710 ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops);
1711 if (IS_ERR(ctx->phy)) { 1711 if (IS_ERR(ctx->phy)) {
1712 dev_dbg(&pdev->dev, "Failed to create PHY\n"); 1712 dev_dbg(&pdev->dev, "Failed to create PHY\n");
1713 rc = PTR_ERR(ctx->phy); 1713 rc = PTR_ERR(ctx->phy);
diff --git a/drivers/pinctrl/pinctrl-tegra-xusb.c b/drivers/pinctrl/pinctrl-tegra-xusb.c
index 1631ec94fb02..a84299b922c8 100644
--- a/drivers/pinctrl/pinctrl-tegra-xusb.c
+++ b/drivers/pinctrl/pinctrl-tegra-xusb.c
@@ -910,7 +910,7 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev)
910 goto reset; 910 goto reset;
911 } 911 }
912 912
913 phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops, NULL); 913 phy = devm_phy_create(&pdev->dev, NULL, &pcie_phy_ops);
914 if (IS_ERR(phy)) { 914 if (IS_ERR(phy)) {
915 err = PTR_ERR(phy); 915 err = PTR_ERR(phy);
916 goto unregister; 916 goto unregister;
@@ -919,7 +919,7 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev)
919 padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy; 919 padctl->phys[TEGRA_XUSB_PADCTL_PCIE] = phy;
920 phy_set_drvdata(phy, padctl); 920 phy_set_drvdata(phy, padctl);
921 921
922 phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops, NULL); 922 phy = devm_phy_create(&pdev->dev, NULL, &sata_phy_ops);
923 if (IS_ERR(phy)) { 923 if (IS_ERR(phy)) {
924 err = PTR_ERR(phy); 924 err = PTR_ERR(phy);
925 goto unregister; 925 goto unregister;
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index dcb8ca084598..12bfd3c5405e 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -29,8 +29,7 @@ int dwc3_host_init(struct dwc3 *dwc)
29 xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO); 29 xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO);
30 if (!xhci) { 30 if (!xhci) {
31 dev_err(dwc->dev, "couldn't allocate xHCI device\n"); 31 dev_err(dwc->dev, "couldn't allocate xHCI device\n");
32 ret = -ENOMEM; 32 return -ENOMEM;
33 goto err0;
34 } 33 }
35 34
36 dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask); 35 dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
@@ -60,22 +59,33 @@ int dwc3_host_init(struct dwc3 *dwc)
60 goto err1; 59 goto err1;
61 } 60 }
62 61
62 phy_create_lookup(dwc->usb2_generic_phy, "usb2-phy",
63 dev_name(&xhci->dev));
64 phy_create_lookup(dwc->usb3_generic_phy, "usb3-phy",
65 dev_name(&xhci->dev));
66
63 ret = platform_device_add(xhci); 67 ret = platform_device_add(xhci);
64 if (ret) { 68 if (ret) {
65 dev_err(dwc->dev, "failed to register xHCI device\n"); 69 dev_err(dwc->dev, "failed to register xHCI device\n");
66 goto err1; 70 goto err2;
67 } 71 }
68 72
69 return 0; 73 return 0;
70 74err2:
75 phy_remove_lookup(dwc->usb2_generic_phy, "usb2-phy",
76 dev_name(&xhci->dev));
77 phy_remove_lookup(dwc->usb3_generic_phy, "usb3-phy",
78 dev_name(&xhci->dev));
71err1: 79err1:
72 platform_device_put(xhci); 80 platform_device_put(xhci);
73
74err0:
75 return ret; 81 return ret;
76} 82}
77 83
78void dwc3_host_exit(struct dwc3 *dwc) 84void dwc3_host_exit(struct dwc3 *dwc)
79{ 85{
86 phy_remove_lookup(dwc->usb2_generic_phy, "usb2-phy",
87 dev_name(&dwc->xhci->dev));
88 phy_remove_lookup(dwc->usb3_generic_phy, "usb3-phy",
89 dev_name(&dwc->xhci->dev));
80 platform_device_unregister(dwc->xhci); 90 platform_device_unregister(dwc->xhci);
81} 91}
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
new file mode 100644
index 000000000000..6c901930eb3e
--- /dev/null
+++ b/include/dt-bindings/phy/phy.h
@@ -0,0 +1,19 @@
1/*
2 *
3 * This header provides constants for the phy framework
4 *
5 * Copyright (C) 2014 STMicroelectronics
6 * Author: Gabriel Fernandez <gabriel.fernandez@st.com>
7 * License terms: GNU General Public License (GPL), version 2
8 */
9
10#ifndef _DT_BINDINGS_PHY
11#define _DT_BINDINGS_PHY
12
13#define PHY_NONE 0
14#define PHY_TYPE_SATA 1
15#define PHY_TYPE_PCIE 2
16#define PHY_TYPE_USB2 3
17#define PHY_TYPE_USB3 4
18
19#endif /* _DT_BINDINGS_PHY */
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 8cb6f815475b..a0197fa1b116 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -61,7 +61,6 @@ struct phy {
61 struct device dev; 61 struct device dev;
62 int id; 62 int id;
63 const struct phy_ops *ops; 63 const struct phy_ops *ops;
64 struct phy_init_data *init_data;
65 struct mutex mutex; 64 struct mutex mutex;
66 int init_count; 65 int init_count;
67 int power_count; 66 int power_count;
@@ -84,33 +83,14 @@ struct phy_provider {
84 struct of_phandle_args *args); 83 struct of_phandle_args *args);
85}; 84};
86 85
87/** 86struct phy_lookup {
88 * struct phy_consumer - represents the phy consumer 87 struct list_head node;
89 * @dev_name: the device name of the controller that will use this PHY device 88 const char *dev_id;
90 * @port: name given to the consumer port 89 const char *con_id;
91 */ 90 struct phy *phy;
92struct phy_consumer {
93 const char *dev_name;
94 const char *port;
95};
96
97/**
98 * struct phy_init_data - contains the list of PHY consumers
99 * @num_consumers: number of consumers for this PHY device
100 * @consumers: list of PHY consumers
101 */
102struct phy_init_data {
103 unsigned int num_consumers;
104 struct phy_consumer *consumers;
105}; 91};
106 92
107#define PHY_CONSUMER(_dev_name, _port) \ 93#define to_phy(a) (container_of((a), struct phy, dev))
108{ \
109 .dev_name = _dev_name, \
110 .port = _port, \
111}
112
113#define to_phy(dev) (container_of((dev), struct phy, dev))
114 94
115#define of_phy_provider_register(dev, xlate) \ 95#define of_phy_provider_register(dev, xlate) \
116 __of_phy_provider_register((dev), THIS_MODULE, (xlate)) 96 __of_phy_provider_register((dev), THIS_MODULE, (xlate))
@@ -159,10 +139,9 @@ struct phy *of_phy_get(struct device_node *np, const char *con_id);
159struct phy *of_phy_simple_xlate(struct device *dev, 139struct phy *of_phy_simple_xlate(struct device *dev,
160 struct of_phandle_args *args); 140 struct of_phandle_args *args);
161struct phy *phy_create(struct device *dev, struct device_node *node, 141struct phy *phy_create(struct device *dev, struct device_node *node,
162 const struct phy_ops *ops, 142 const struct phy_ops *ops);
163 struct phy_init_data *init_data);
164struct phy *devm_phy_create(struct device *dev, struct device_node *node, 143struct phy *devm_phy_create(struct device *dev, struct device_node *node,
165 const struct phy_ops *ops, struct phy_init_data *init_data); 144 const struct phy_ops *ops);
166void phy_destroy(struct phy *phy); 145void phy_destroy(struct phy *phy);
167void devm_phy_destroy(struct device *dev, struct phy *phy); 146void devm_phy_destroy(struct device *dev, struct phy *phy);
168struct phy_provider *__of_phy_provider_register(struct device *dev, 147struct phy_provider *__of_phy_provider_register(struct device *dev,
@@ -174,6 +153,8 @@ struct phy_provider *__devm_of_phy_provider_register(struct device *dev,
174void of_phy_provider_unregister(struct phy_provider *phy_provider); 153void of_phy_provider_unregister(struct phy_provider *phy_provider);
175void devm_of_phy_provider_unregister(struct device *dev, 154void devm_of_phy_provider_unregister(struct device *dev,
176 struct phy_provider *phy_provider); 155 struct phy_provider *phy_provider);
156int phy_create_lookup(struct phy *phy, const char *con_id, const char *dev_id);
157void phy_remove_lookup(struct phy *phy, const char *con_id, const char *dev_id);
177#else 158#else
178static inline int phy_pm_runtime_get(struct phy *phy) 159static inline int phy_pm_runtime_get(struct phy *phy)
179{ 160{
@@ -301,16 +282,14 @@ static inline struct phy *of_phy_simple_xlate(struct device *dev,
301 282
302static inline struct phy *phy_create(struct device *dev, 283static inline struct phy *phy_create(struct device *dev,
303 struct device_node *node, 284 struct device_node *node,
304 const struct phy_ops *ops, 285 const struct phy_ops *ops)
305 struct phy_init_data *init_data)
306{ 286{
307 return ERR_PTR(-ENOSYS); 287 return ERR_PTR(-ENOSYS);
308} 288}
309 289
310static inline struct phy *devm_phy_create(struct device *dev, 290static inline struct phy *devm_phy_create(struct device *dev,
311 struct device_node *node, 291 struct device_node *node,
312 const struct phy_ops *ops, 292 const struct phy_ops *ops)
313 struct phy_init_data *init_data)
314{ 293{
315 return ERR_PTR(-ENOSYS); 294 return ERR_PTR(-ENOSYS);
316} 295}
@@ -345,6 +324,13 @@ static inline void devm_of_phy_provider_unregister(struct device *dev,
345 struct phy_provider *phy_provider) 324 struct phy_provider *phy_provider)
346{ 325{
347} 326}
327static inline int
328phy_create_lookup(struct phy *phy, const char *con_id, const char *dev_id)
329{
330 return 0;
331}
332static inline void phy_remove_lookup(struct phy *phy, const char *con_id,
333 const char *dev_id) { }
348#endif 334#endif
349 335
350#endif /* __DRIVERS_PHY_H */ 336#endif /* __DRIVERS_PHY_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-23 17:48:45 -0400