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authorOliver Endriss <o.endriss@gmx.de>2009-12-19 02:54:44 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-02-26 13:10:53 -0500
commit83f3c7157e087ace8fc67fd759bc3d7b3b64531e (patch)
treea35d48a58a8d8d1fa78138c3818c50b3a27cd37f
parentdae52d009fc950b5c209260d50fcc000f5becd3c (diff)
V4L/DVB: ngene: Driver compiles now
Remove LNBH21 routines, disable code which broke compilation. Signed-off-by: Oliver Endriss <o.endriss@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat
-rw-r--r--drivers/media/dvb/Kconfig4
-rw-r--r--drivers/media/dvb/Makefile3
-rw-r--r--drivers/media/dvb/ngene/Kconfig9
-rw-r--r--drivers/media/dvb/ngene/Makefile11
-rw-r--r--drivers/media/dvb/ngene/ngene-core.c1409
-rw-r--r--drivers/media/dvb/ngene/ngene.h29
6 files changed, 35 insertions, 1430 deletions
diff --git a/drivers/media/dvb/Kconfig b/drivers/media/dvb/Kconfig
index cf8f65f309da..161ccfd471cb 100644
--- a/drivers/media/dvb/Kconfig
+++ b/drivers/media/dvb/Kconfig
@@ -76,6 +76,10 @@ comment "Supported Mantis Adapters"
76 depends on DVB_CORE && PCI && I2C 76 depends on DVB_CORE && PCI && I2C
77 source "drivers/media/dvb/mantis/Kconfig" 77 source "drivers/media/dvb/mantis/Kconfig"
78 78
79comment "Supported nGene Adapters"
80 depends on DVB_CORE && PCI && I2C
81 source "drivers/media/dvb/ngene/Kconfig"
82
79comment "Supported DVB Frontends" 83comment "Supported DVB Frontends"
80 depends on DVB_CORE 84 depends on DVB_CORE
81source "drivers/media/dvb/frontends/Kconfig" 85source "drivers/media/dvb/frontends/Kconfig"
diff --git a/drivers/media/dvb/Makefile b/drivers/media/dvb/Makefile
index c12922c3659b..a1a08758a6f2 100644
--- a/drivers/media/dvb/Makefile
+++ b/drivers/media/dvb/Makefile
@@ -14,6 +14,7 @@ obj-y := dvb-core/ \
14 siano/ \ 14 siano/ \
15 dm1105/ \ 15 dm1105/ \
16 pt1/ \ 16 pt1/ \
17 mantis/ 17 mantis/ \
18 ngene/
18 19
19obj-$(CONFIG_DVB_FIREDTV) += firewire/ 20obj-$(CONFIG_DVB_FIREDTV) += firewire/
diff --git a/drivers/media/dvb/ngene/Kconfig b/drivers/media/dvb/ngene/Kconfig
new file mode 100644
index 000000000000..3ec8e6fcbb1d
--- /dev/null
+++ b/drivers/media/dvb/ngene/Kconfig
@@ -0,0 +1,9 @@
1config DVB_NGENE
2 tristate "Micronas nGene support"
3 depends on DVB_CORE && PCI && I2C
4 select DVB_LNBP21 if !DVB_FE_CUSTOMISE
5 select DVB_STV6110x if !DVB_FE_CUSTOMISE
6 select DVB_STV090x if !DVB_FE_CUSTOMISE
7 ---help---
8 Support for Micronas PCI express cards with nGene bridge.
9
diff --git a/drivers/media/dvb/ngene/Makefile b/drivers/media/dvb/ngene/Makefile
new file mode 100644
index 000000000000..40435cad4819
--- /dev/null
+++ b/drivers/media/dvb/ngene/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the nGene device driver
3#
4
5ngene-objs := ngene-core.o
6
7obj-$(CONFIG_DVB_NGENE) += ngene.o
8
9EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/
10EXTRA_CFLAGS += -Idrivers/media/dvb/frontends/
11
diff --git a/drivers/media/dvb/ngene/ngene-core.c b/drivers/media/dvb/ngene/ngene-core.c
index 744a232bd100..c0ef11c77f59 100644
--- a/drivers/media/dvb/ngene/ngene-core.c
+++ b/drivers/media/dvb/ngene/ngene-core.c
@@ -48,14 +48,12 @@
48#include "ngene-ioctls.h" 48#include "ngene-ioctls.h"
49#endif 49#endif
50 50
51#define FW_INC 1 51/* #define FW_INC 1 */
52#ifdef FW_INC 52#ifdef FW_INC
53#include "ngene_fw_15.h" 53#include "ngene_fw_15.h"
54#include "ngene_fw_16.h" 54#include "ngene_fw_16.h"
55#include "ngene_fw_17.h" 55#include "ngene_fw_17.h"
56 56
57DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
58
59static int load_firmware; 57static int load_firmware;
60module_param(load_firmware, int, 0444); 58module_param(load_firmware, int, 0444);
61MODULE_PARM_DESC(load_firmware, "Try to load firmware from file."); 59MODULE_PARM_DESC(load_firmware, "Try to load firmware from file.");
@@ -73,6 +71,8 @@ static int debug;
73module_param(debug, int, 0444); 71module_param(debug, int, 0444);
74MODULE_PARM_DESC(debug, "Print debugging information."); 72MODULE_PARM_DESC(debug, "Print debugging information.");
75 73
74DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
75
76#define dprintk if (debug) printk 76#define dprintk if (debug) printk
77 77
78#define DEVICE_NAME "ngene" 78#define DEVICE_NAME "ngene"
@@ -670,15 +670,6 @@ static void FillTSBuffer(void *Buffer, int Length, u32 Flags)
670 } 670 }
671} 671}
672 672
673static void clear_tsin(struct ngene_channel *chan)
674{
675 struct SBufferHeader *Cur = chan->nextBuffer;
676
677 do {
678 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR));
679 Cur = Cur->Next;
680 } while (Cur != chan->nextBuffer);
681}
682 673
683static void flush_buffers(struct ngene_channel *chan) 674static void flush_buffers(struct ngene_channel *chan)
684{ 675{
@@ -952,37 +943,6 @@ done:
952} 943}
953 944
954 945
955static int ngene_i2c_algo_control(struct i2c_adapter *adap,
956 unsigned int cmd, unsigned long arg)
957{
958 struct ngene_channel *chan =
959 (struct ngene_channel *)i2c_get_adapdata(adap);
960
961 switch (cmd) {
962 case IOCTL_MIC_TUN_RDY:
963 chan->tun_rdy = 1;
964 if (chan->dec_rdy == 1)
965 chan->tun_dec_rdy = 1;
966 break;
967
968 case IOCTL_MIC_DEC_RDY:
969 chan->dec_rdy = 1;
970 if (chan->tun_rdy == 1)
971 chan->tun_dec_rdy = 1;
972 break;
973
974 case IOCTL_MIC_TUN_DETECT:
975 {
976 int *palorbtsc = (int *)arg;
977 *palorbtsc = chan->dev->card_info->ntsc;
978 break;
979 }
980
981 default:
982 break;
983 }
984 return 0;
985}
986 946
987static u32 ngene_i2c_functionality(struct i2c_adapter *adap) 947static u32 ngene_i2c_functionality(struct i2c_adapter *adap)
988{ 948{
@@ -994,16 +954,6 @@ struct i2c_algorithm ngene_i2c_algo = {
994 .functionality = ngene_i2c_functionality, 954 .functionality = ngene_i2c_functionality,
995}; 955};
996 956
997static int ngene_i2c_attach(struct i2c_client *client)
998{
999 return 0;
1000}
1001
1002static int ngene_i2c_detach(struct i2c_client *client)
1003{
1004 return 0;
1005}
1006
1007static int ngene_i2c_init(struct ngene *dev, int dev_nr) 957static int ngene_i2c_init(struct ngene *dev, int dev_nr)
1008{ 958{
1009 struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter); 959 struct i2c_adapter *adap = &(dev->channel[dev_nr].i2c_adapter);
@@ -1018,8 +968,6 @@ static int ngene_i2c_init(struct ngene *dev, int dev_nr)
1018 strcpy(adap->name, "nGene"); 968 strcpy(adap->name, "nGene");
1019 969
1020 adap->id = I2C_HW_SAA7146; 970 adap->id = I2C_HW_SAA7146;
1021 adap->client_register = ngene_i2c_attach;
1022 adap->client_unregister = ngene_i2c_detach;
1023 adap->algo = &ngene_i2c_algo; 971 adap->algo = &ngene_i2c_algo;
1024 adap->algo_data = (void *)&(dev->channel[dev_nr]); 972 adap->algo_data = (void *)&(dev->channel[dev_nr]);
1025 973
@@ -1040,20 +988,6 @@ int i2c_write(struct i2c_adapter *adapter, u8 adr, u8 data)
1040 return 0; 988 return 0;
1041} 989}
1042 990
1043static int i2c_write_register(struct i2c_adapter *adapter,
1044 u8 adr, u8 reg, u8 data)
1045{
1046 u8 m[2] = {reg, data};
1047 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = m, .len = 2};
1048
1049 if (i2c_transfer(adapter, &msg, 1) != 1) {
1050 printk(KERN_ERR DEVICE_NAME
1051 ": Failed to write to I2C register %02x@%02x!\n",
1052 reg, adr);
1053 return -1;
1054 }
1055 return 0;
1056}
1057 991
1058static int i2c_write_read(struct i2c_adapter *adapter, 992static int i2c_write_read(struct i2c_adapter *adapter,
1059 u8 adr, u8 *w, u8 wlen, u8 *r, u8 rlen) 993 u8 adr, u8 *w, u8 wlen, u8 *r, u8 rlen)
@@ -1143,146 +1077,6 @@ static int i2c_read_eeprom(struct i2c_adapter *adapter,
1143 return 0; 1077 return 0;
1144} 1078}
1145 1079
1146static int ReadEEProm(struct i2c_adapter *adapter,
1147 u16 Tag, u32 MaxLen, u8 *data, u32 *pLength)
1148{
1149 int status = 0;
1150 u16 Addr = MICNG_EE_START, Length, tag = 0;
1151 u8 EETag[3];
1152
1153 while (Addr + sizeof(u16) + 1 < MICNG_EE_END) {
1154 if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag)))
1155 return -1;
1156 tag = (EETag[0] << 8) | EETag[1];
1157 if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1)
1158 return -1;
1159 if (tag == Tag)
1160 break;
1161 Addr += sizeof(u16) + 1 + EETag[2];
1162 }
1163 if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) {
1164 printk(KERN_ERR DEVICE_NAME
1165 ": Reached EOEE @ Tag = %04x Length = %3d\n",
1166 tag, EETag[2]);
1167 return -1;
1168 }
1169 Length = EETag[2];
1170 if (Length > MaxLen)
1171 Length = (u16) MaxLen;
1172 if (Length > 0) {
1173 Addr += sizeof(u16) + 1;
1174 status = i2c_read_eeprom(adapter, 0x50, Addr, data, Length);
1175 if (!status) {
1176 *pLength = EETag[2];
1177 if (Length < EETag[2])
1178 ; /*status=STATUS_BUFFER_OVERFLOW; */
1179 }
1180 }
1181 return status;
1182}
1183
1184static int WriteEEProm(struct i2c_adapter *adapter,
1185 u16 Tag, u32 Length, u8 *data)
1186{
1187 int status = 0;
1188 u16 Addr = MICNG_EE_START;
1189 u8 EETag[3];
1190 u16 tag = 0;
1191 int retry, i;
1192
1193 while (Addr + sizeof(u16) + 1 < MICNG_EE_END) {
1194 if (i2c_read_eeprom(adapter, 0x50, Addr, EETag, sizeof(EETag)))
1195 return -1;
1196 tag = (EETag[0] << 8) | EETag[1];
1197 if (tag == MICNG_EETAG_END0 || tag == MICNG_EETAG_END1)
1198 return -1;
1199 if (tag == Tag)
1200 break;
1201 Addr += sizeof(u16) + 1 + EETag[2];
1202 }
1203 if (Addr + sizeof(u16) + 1 + EETag[2] > MICNG_EE_END) {
1204 printk(KERN_ERR DEVICE_NAME
1205 ": Reached EOEE @ Tag = %04x Length = %3d\n",
1206 tag, EETag[2]);
1207 return -1;
1208 }
1209
1210 if (Length > EETag[2])
1211 return -EINVAL;
1212 /* Note: We write the data one byte at a time to avoid
1213 issues with page sizes. (which are different for
1214 each manufacture and eeprom size)
1215 */
1216 Addr += sizeof(u16) + 1;
1217 for (i = 0; i < Length; i++, Addr++) {
1218 status = i2c_write_eeprom(adapter, 0x50, Addr, data[i]);
1219
1220 if (status)
1221 break;
1222
1223 /* Poll for finishing write cycle */
1224 retry = 10;
1225 while (retry) {
1226 u8 Tmp;
1227
1228 msleep(50);
1229 status = i2c_read_eeprom(adapter, 0x50, Addr, &Tmp, 1);
1230 if (status)
1231 break;
1232 if (Tmp != data[i])
1233 printk(KERN_ERR DEVICE_NAME
1234 "eeprom write error\n");
1235 retry -= 1;
1236 }
1237 if (status) {
1238 printk(KERN_ERR DEVICE_NAME
1239 ": Timeout polling eeprom\n");
1240 break;
1241 }
1242 }
1243 return status;
1244}
1245
1246static void i2c_init_eeprom(struct i2c_adapter *adapter)
1247{
1248 u8 tags[] = {0x10, 0x00, 0x02, 0x00, 0x00,
1249 0x10, 0x01, 0x02, 0x00, 0x00,
1250 0x00, 0x00, 0x00};
1251
1252 int i;
1253
1254 for (i = 0; i < sizeof(tags); i++)
1255 i2c_write_eeprom(adapter, 0x50, 0x0100 + i, tags[i]);
1256}
1257
1258static int eeprom_read_ushort(struct i2c_adapter *adapter, u16 tag, u16 *data)
1259{
1260 int stat;
1261 u8 buf[2];
1262 u32 len = 0;
1263
1264 stat = ReadEEProm(adapter, tag, 2, buf, &len);
1265 if (stat)
1266 return stat;
1267 if (len != 2)
1268 return -EINVAL;
1269
1270 *data = (buf[0] << 8) | buf[1];
1271 return 0;
1272}
1273
1274static int eeprom_write_ushort(struct i2c_adapter *adapter, u16 tag, u16 data)
1275{
1276 int stat;
1277 u8 buf[2];
1278
1279 buf[0] = data >> 8;
1280 buf[1] = data & 0xff;
1281 stat = WriteEEProm(adapter, tag, 2, buf);
1282 if (stat)
1283 return stat;
1284 return 0;
1285}
1286 1080
1287static int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr) 1081static int i2c_dump_eeprom(struct i2c_adapter *adapter, u8 adr)
1288{ 1082{
@@ -1665,36 +1459,6 @@ static void swap_buffer(u32 *p, u32 len)
1665 } 1459 }
1666} 1460}
1667 1461
1668static void *ain_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
1669{
1670 struct ngene_channel *chan = priv;
1671 struct ngene *dev = chan->dev;
1672
1673 if (dvb_ringbuffer_free(&dev->ain_rbuf) >= len) {
1674 dvb_ringbuffer_write(&dev->ain_rbuf, buf, len);
1675 wake_up_interruptible(&dev->ain_rbuf.queue);
1676 } else
1677 printk(KERN_INFO DEVICE_NAME ": Dropped ain packet.\n");
1678
1679 return 0;
1680}
1681
1682static void *vcap_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
1683{
1684
1685 struct ngene_channel *chan = priv;
1686 struct ngene *dev = chan->dev;
1687
1688 if (len >= 1920 * 1080)
1689 len = 1920 * 1080;
1690 if (dvb_ringbuffer_free(&dev->vin_rbuf) >= len) {
1691 dvb_ringbuffer_write(&dev->vin_rbuf, buf, len);
1692 wake_up_interruptible(&dev->vin_rbuf.queue);
1693 } else {
1694 ;/*printk(KERN_INFO DEVICE_NAME ": Dropped vcap packet.\n"); */
1695 }
1696 return 0;
1697}
1698 1462
1699static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags) 1463static void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags)
1700{ 1464{
@@ -1728,15 +1492,6 @@ static void *tsout_exchange(void *priv, void *buf, u32 len,
1728 return buf; 1492 return buf;
1729} 1493}
1730 1494
1731static void set_dto(struct ngene_channel *chan, u32 rate)
1732{
1733 u64 val = rate * 0x89705f41ULL; /* times val for 2^26 Hz */
1734
1735 val = ((val >> 25) + 1) >> 1;
1736 chan->AudioDTOValue = (u32) val;
1737 /* chan->AudioDTOUpdated=1; */
1738 /* printk(KERN_INFO DEVICE_NAME ": Setting DTO to %08x\n", val); */
1739}
1740 1495
1741static void set_transfer(struct ngene_channel *chan, int state) 1496static void set_transfer(struct ngene_channel *chan, int state)
1742{ 1497{
@@ -1814,6 +1569,7 @@ static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
1814{ 1569{
1815 struct dvb_demux *dvbdmx = dvbdmxfeed->demux; 1570 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1816 struct ngene_channel *chan = dvbdmx->priv; 1571 struct ngene_channel *chan = dvbdmx->priv;
1572#ifdef NGENE_COMMAND_API
1817 struct ngene *dev = chan->dev; 1573 struct ngene *dev = chan->dev;
1818 1574
1819 if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) { 1575 if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) {
@@ -1838,6 +1594,7 @@ static int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed)
1838 } 1594 }
1839 1595
1840 } 1596 }
1597#endif
1841 1598
1842 if (chan->users == 0) { 1599 if (chan->users == 0) {
1843 set_transfer(chan, 1); 1600 set_transfer(chan, 1);
@@ -1851,6 +1608,7 @@ static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
1851{ 1608{
1852 struct dvb_demux *dvbdmx = dvbdmxfeed->demux; 1609 struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
1853 struct ngene_channel *chan = dvbdmx->priv; 1610 struct ngene_channel *chan = dvbdmx->priv;
1611#ifdef NGENE_COMMAND_API
1854 struct ngene *dev = chan->dev; 1612 struct ngene *dev = chan->dev;
1855 1613
1856 if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) { 1614 if (dev->card_info->io_type[chan->number] & NGENE_IO_TSOUT) {
@@ -1870,6 +1628,7 @@ static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
1870 } 1628 }
1871 1629
1872 } 1630 }
1631#endif
1873 1632
1874 if (--chan->users) 1633 if (--chan->users)
1875 return chan->users; 1634 return chan->users;
@@ -1879,186 +1638,7 @@ static int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
1879 return 0; 1638 return 0;
1880} 1639}
1881 1640
1882static int write_demod(struct i2c_adapter *adapter, u8 adr, u16 reg, u16 data)
1883{
1884 u8 mm[5] = { 0x10, (reg >> 8) & 0xff, reg & 0xff,
1885 (data >> 8) & 0xff, data & 0xff};
1886 struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = mm, .len = 5 };
1887 1641
1888 if (i2c_transfer(adapter, &msg, 1) != 1) {
1889 printk(KERN_ERR DEVICE_NAME ": error in write_demod\n");
1890 return -1;
1891 }
1892 return 0;
1893}
1894
1895
1896static int ngene_drxd_pll_set(struct ngene_channel *chan,
1897 u8 *pll, u8 *aux, u8 plladr)
1898{
1899 struct i2c_adapter *adap = &chan->i2c_adapter;
1900 struct i2c_msg msg_pll = {.addr = plladr, .flags = 0, .buf = pll,
1901 .len = 4};
1902 struct i2c_msg msg_aux = {.addr = plladr, .flags = 0, .buf = aux,
1903 .len = 2};
1904 int err = 0;
1905
1906 if (chan->dev->card_info->i2c_access & 1)
1907 down(&chan->dev->pll_mutex);
1908
1909 chan->fe->ops.i2c_gate_ctrl(chan->fe, 1);
1910 err = i2c_transfer(adap, &msg_pll, 1);
1911 if (err != 1)
1912 goto error;
1913 if (aux)
1914 err = i2c_transfer(adap, &msg_aux, 1);
1915error:
1916 chan->fe->ops.i2c_gate_ctrl(chan->fe, 0);
1917 if (chan->dev->card_info->i2c_access & 1)
1918 up(&chan->dev->pll_mutex);
1919 return err;
1920}
1921
1922static int ngene_pll_set_th_dtt7520x(void *priv, void *priv_params,
1923 u8 plladr, u8 dadr, s32 *off)
1924{
1925 struct dvb_frontend_parameters *params = priv_params;
1926 struct ngene_channel *chan = priv;
1927
1928 u32 freq = params->frequency;
1929 u8 pll[4], aux[2];
1930 u8 c1, c2;
1931 u32 div;
1932
1933 if (freq < 185000000 || freq > 900000000)
1934 return -EINVAL;
1935
1936 if (freq < 465000000)
1937 c2 = 0x12;
1938 else
1939 c2 = 0x18;
1940
1941 if (freq < 305000000)
1942 c1 = 0xb4;
1943 else if (freq < 405000000)
1944 c1 = 0xbc;
1945 else if (freq < 445000000)
1946 c1 = 0xf4;
1947 else if (freq < 465000000)
1948 c1 = 0xfc;
1949 else if (freq < 735000000)
1950 c1 = 0xbc;
1951 else if (freq < 835000000)
1952 c1 = 0xf4;
1953 else
1954 c1 = 0xfc;
1955
1956 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ)
1957 c2 ^= 0x10;
1958
1959 div = (freq + 36000000 + 166667 / 2) / 166667;
1960 *off = ((s32) div) * 166667 - (s32) freq - 36000000;
1961
1962 pll[0] = (div >> 8) & 0x7f;
1963 pll[1] = div & 0xff;
1964 pll[2] = c1;
1965 pll[3] = c2;
1966
1967 aux[0] = (c1 & 0xc7) | 0x98;
1968 aux[1] = 0x30;
1969
1970 return ngene_drxd_pll_set(chan, pll, aux, plladr);
1971}
1972
1973static int ngene_pll_set_mt_3x0823(void *priv,
1974 void *priv_params,
1975 u8 plladr, u8 dadr, s32 *off)
1976{
1977 struct dvb_frontend_parameters *params = priv_params;
1978 struct ngene_channel *chan = priv;
1979 struct i2c_adapter *adap = &chan->i2c_adapter;
1980 u32 freq = params->frequency;
1981 u8 pll[4];
1982 u8 aux[2];
1983 u8 c1, c2;
1984 u32 div;
1985
1986 if (freq < 47125000 || freq > 855250000)
1987 return -EINVAL;
1988 else if (freq < 120000000) {
1989 c1 = 0xcc;
1990 c2 = 0x01;
1991 } else if (freq < 155500000) {
1992 c1 = 0xfc;
1993 c2 = 0x01;
1994 } else if (freq < 300000000) {
1995 c1 = 0xbc;
1996 c2 = 0x02;
1997 } else if (freq < 467000000) {
1998 c1 = 0xcc;
1999 c2 = 0x02;
2000 } else {
2001 c1 = 0xcc;
2002 c2 = 0x04;
2003 }
2004
2005 if (params->u.ofdm.bandwidth == BANDWIDTH_8_MHZ)
2006 c2 |= 0x08;
2007
2008#define INTERFREQ (36000000)
2009
2010 div = (freq + INTERFREQ + 166667 / 2) / 166667;
2011
2012 *off = ((s32) div) * 166667 - (s32) freq - INTERFREQ;
2013
2014 pll[0] = (div >> 8) & 0x7f;
2015 pll[1] = div & 0xff;
2016 pll[2] = c1;
2017 pll[3] = c2;
2018
2019 aux[0] = (c1 & 0xc7) | 0x98;
2020 aux[1] = 0x20;
2021
2022 write_demod(adap, dadr, 0x1007, 0xc27);
2023
2024 switch (params->u.ofdm.bandwidth) {
2025 case BANDWIDTH_7_MHZ:
2026 write_demod(adap, dadr, 0x0020, 0x103);
2027 break;
2028 case BANDWIDTH_AUTO:
2029 case BANDWIDTH_8_MHZ:
2030 write_demod(adap, dadr, 0x0020, 0x003);
2031 break;
2032 case BANDWIDTH_6_MHZ:
2033 write_demod(adap, dadr, 0x0020, 0x002);
2034 /*write_demod(adap, dadr, 0x1022, 397);*/
2035 break;
2036 }
2037
2038 return ngene_drxd_pll_set(chan, pll, aux, plladr);
2039
2040}
2041
2042static s16 osc_deviation(void *priv, s16 deviation, int flag)
2043{
2044 struct ngene_channel *chan = priv;
2045 struct i2c_adapter *adap = &chan->i2c_adapter;
2046 u16 data = 0;
2047
2048 if (flag) {
2049 data = (u16) deviation;
2050 printk(KERN_INFO DEVICE_NAME ": write deviation %d\n",
2051 deviation);
2052 eeprom_write_ushort(adap, 0x1000 + chan->number, data);
2053 } else {
2054 if (eeprom_read_ushort(adap, 0x1000 + chan->number, &data))
2055 data = 0;
2056 printk(KERN_INFO DEVICE_NAME ": read deviation %d\n",
2057 (s16) data);
2058 }
2059
2060 return (s16) data;
2061}
2062 1642
2063static int write_to_decoder(struct dvb_demux_feed *feed, 1643static int write_to_decoder(struct dvb_demux_feed *feed,
2064 const u8 *buf, size_t len) 1644 const u8 *buf, size_t len)
@@ -2175,8 +1755,6 @@ int dec_fw_boot(struct ngene *dev)
2175 u32 size; 1755 u32 size;
2176 const struct firmware *fw = NULL; 1756 const struct firmware *fw = NULL;
2177 u8 *dec_fw; 1757 u8 *dec_fw;
2178 char *fw_name;
2179 int err, version;
2180 1758
2181 if (request_firmware(&fw, DECYPHER_FW, &dev->pci_dev->dev) < 0) { 1759 if (request_firmware(&fw, DECYPHER_FW, &dev->pci_dev->dev) < 0) {
2182 printk(KERN_ERR DEVICE_NAME 1760 printk(KERN_ERR DEVICE_NAME
@@ -2188,7 +1766,7 @@ int dec_fw_boot(struct ngene *dev)
2188 DECYPHER_FW); 1766 DECYPHER_FW);
2189 1767
2190 size = fw->size; 1768 size = fw->size;
2191 dec_fw = fw->data; 1769 dec_fw = (u8 *)fw->data;
2192 dec_fw_send(dev, dec_fw, size); 1770 dec_fw_send(dev, dec_fw, size);
2193 release_firmware(fw); 1771 release_firmware(fw);
2194 return 0; 1772 return 0;
@@ -2487,83 +2065,6 @@ static u32 Buffer2Sizes[MAX_STREAM] = {
2487 0 2065 0
2488}; 2066};
2489 2067
2490static int allocate_buffer(struct pci_dev *pci_dev, dma_addr_t of,
2491 struct SRingBufferDescriptor *rbuf,
2492 u32 entries, u32 size1, u32 size2)
2493{
2494 if (create_ring_buffer(pci_dev, rbuf, entries) < 0)
2495 return -ENOMEM;
2496
2497 if (AllocateRingBuffers(pci_dev, of, rbuf, size1, size2) < 0)
2498 return -ENOMEM;
2499
2500 return 0;
2501}
2502
2503static int channel_allocate_buffers(struct ngene_channel *chan)
2504{
2505 struct ngene *dev = chan->dev;
2506 int type = dev->card_info->io_type[chan->number];
2507 int status;
2508
2509 chan->State = KSSTATE_STOP;
2510
2511 if (type & (NGENE_IO_TV | NGENE_IO_HDTV | NGENE_IO_AIN)) {
2512 status = create_ring_buffer(dev->pci_dev,
2513 &chan->RingBuffer,
2514 RingBufferSizes[chan->number]);
2515 if (status < 0)
2516 return -ENOMEM;
2517
2518 if (type & (NGENE_IO_TV | NGENE_IO_AIN)) {
2519 status = AllocateRingBuffers(dev->pci_dev,
2520 dev->PAOverflowBuffer,
2521 &chan->RingBuffer,
2522 Buffer1Sizes[chan->number],
2523 Buffer2Sizes[chan->
2524 number]);
2525 if (status < 0)
2526 return -ENOMEM;
2527 } else if (type & NGENE_IO_HDTV) {
2528 status = AllocateRingBuffers(dev->pci_dev,
2529 dev->PAOverflowBuffer,
2530 &chan->RingBuffer,
2531 MAX_HDTV_BUFFER_SIZE, 0);
2532 if (status < 0)
2533 return -ENOMEM;
2534 }
2535 }
2536
2537 if (type & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) {
2538
2539 status = create_ring_buffer(dev->pci_dev,
2540 &chan->TSRingBuffer, RING_SIZE_TS);
2541 if (status < 0)
2542 return -ENOMEM;
2543
2544 status = AllocateRingBuffers(dev->pci_dev,
2545 dev->PAOverflowBuffer,
2546 &chan->TSRingBuffer,
2547 MAX_TS_BUFFER_SIZE, 0);
2548 if (status)
2549 return -ENOMEM;
2550 }
2551
2552 if (type & NGENE_IO_TSOUT) {
2553 status = create_ring_buffer(dev->pci_dev,
2554 &chan->TSIdleBuffer, 1);
2555 if (status < 0)
2556 return -ENOMEM;
2557 status = AllocateRingBuffers(dev->pci_dev,
2558 dev->PAOverflowBuffer,
2559 &chan->TSIdleBuffer,
2560 MAX_TS_BUFFER_SIZE, 0);
2561 if (status)
2562 return -ENOMEM;
2563 FillTSIdleBuffer(&chan->TSIdleBuffer, &chan->TSRingBuffer);
2564 }
2565 return 0;
2566}
2567 2068
2568static int AllocCommonBuffers(struct ngene *dev) 2069static int AllocCommonBuffers(struct ngene *dev)
2569{ 2070{
@@ -2737,18 +2238,12 @@ static int ngene_load_firm(struct ngene *dev)
2737 default: 2238 default:
2738 case 15: 2239 case 15:
2739 version = 15; 2240 version = 15;
2740 ngene_fw = FW15;
2741 size = sizeof(FW15);
2742 fw_name = "ngene_15.fw"; 2241 fw_name = "ngene_15.fw";
2743 break; 2242 break;
2744 case 16: 2243 case 16:
2745 ngene_fw = FW16;
2746 size = sizeof(FW16);
2747 fw_name = "ngene_16.fw"; 2244 fw_name = "ngene_16.fw";
2748 break; 2245 break;
2749 case 17: 2246 case 17:
2750 ngene_fw = FW17;
2751 size = sizeof(FW17);
2752 fw_name = "ngene_17.fw"; 2247 fw_name = "ngene_17.fw";
2753 break; 2248 break;
2754 } 2249 }
@@ -2776,7 +2271,7 @@ static int ngene_load_firm(struct ngene *dev)
2776 } 2271 }
2777 printk(KERN_INFO DEVICE_NAME ": Loading firmware file %s.\n", fw_name); 2272 printk(KERN_INFO DEVICE_NAME ": Loading firmware file %s.\n", fw_name);
2778 size = fw->size; 2273 size = fw->size;
2779 ngene_fw = fw->data; 2274 ngene_fw = (u8 *) fw->data;
2780 err = ngene_command_load_firmware(dev, ngene_fw, size); 2275 err = ngene_command_load_firmware(dev, ngene_fw, size);
2781 release_firmware(fw); 2276 release_firmware(fw);
2782#endif 2277#endif
@@ -2843,9 +2338,6 @@ static int ngene_start(struct ngene *dev)
2843 {6144 / 64, 0, 0, 2048 / 64, 2048 / 64, 2048 / 64}; 2338 {6144 / 64, 0, 0, 2048 / 64, 2048 / 64, 2048 / 64};
2844 u8 tsin4_config[6] = 2339 u8 tsin4_config[6] =
2845 {3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0}; 2340 {3072 / 64, 3072 / 64, 0, 3072 / 64, 3072 / 64, 0};
2846 u8 ts5_config[6] =
2847 {2048 / 64, 2048 / 64, 0, 2048 / 64, 2048 / 64,
2848 2048 / 64};
2849 u8 default_config[6] = 2341 u8 default_config[6] =
2850 {4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0}; 2342 {4096 / 64, 4096 / 64, 0, 2048 / 64, 2048 / 64, 0};
2851 u8 *bconf = default_config; 2343 u8 *bconf = default_config;
@@ -2883,540 +2375,17 @@ fail:
2883 return stat; 2375 return stat;
2884} 2376}
2885 2377
2886/****************************************************************************/
2887/* DVB audio/video device functions *****************************************/
2888/****************************************************************************/
2889 2378
2890static ssize_t audio_write(struct file *file,
2891 const char *buf, size_t count, loff_t *ppos)
2892{
2893 return -EINVAL;
2894}
2895
2896ssize_t audio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
2897{
2898 struct dvb_device *dvbdev = file->private_data;
2899 struct ngene_channel *chan = dvbdev->priv;
2900 struct ngene *dev = chan->dev;
2901 int left;
2902 int avail;
2903
2904 left = count;
2905 while (left) {
2906 if (wait_event_interruptible(
2907 dev->ain_rbuf.queue,
2908 dvb_ringbuffer_avail(&dev->ain_rbuf) > 0) < 0)
2909 return -EAGAIN;
2910 avail = dvb_ringbuffer_avail(&dev->ain_rbuf);
2911 if (avail > left)
2912 avail = left;
2913 dvb_ringbuffer_read_user(&dev->ain_rbuf, buf, avail);
2914 left -= avail;
2915 buf += avail;
2916 }
2917 return count;
2918}
2919
2920static int audio_open(struct inode *inode, struct file *file)
2921{
2922 struct dvb_device *dvbdev = file->private_data;
2923 struct ngene_channel *chan = dvbdev->priv;
2924 struct ngene *dev = chan->dev;
2925 struct ngene_channel *chan2 = &chan->dev->channel[2];
2926 int ret;
2927
2928 ret = dvb_generic_open(inode, file);
2929 if (ret < 0)
2930 return ret;
2931 my_dvb_ringbuffer_flush(&dev->ain_rbuf);
2932
2933 chan2->Capture1Length = MAX_AUDIO_BUFFER_SIZE;
2934 chan2->pBufferExchange = ain_exchange;
2935 ngene_command_stream_control(chan2->dev, chan2->number, 0x80,
2936 SMODE_AUDIO_CAPTURE, 0);
2937 return ret;
2938}
2939
2940static int audio_release(struct inode *inode, struct file *file)
2941{
2942 struct dvb_device *dvbdev = file->private_data;
2943 struct ngene_channel *chan = dvbdev->priv;
2944 struct ngene *dev = chan->dev;
2945 struct ngene_channel *chan2 = &chan->dev->channel[2];
2946
2947 ngene_command_stream_control(dev, 2, 0, 0, 0);
2948 chan2->pBufferExchange = 0;
2949
2950 return dvb_generic_release(inode, file);
2951}
2952
2953static const struct file_operations audio_fops = {
2954 .owner = THIS_MODULE,
2955 .read = audio_read,
2956 .write = audio_write,
2957 .open = audio_open,
2958 .release = audio_release,
2959};
2960
2961static struct dvb_device dvbdev_audio = {
2962 .priv = 0,
2963 .readers = -1,
2964 .writers = 1,
2965 .users = 1,
2966 .fops = &audio_fops,
2967};
2968
2969static int video_open(struct inode *inode, struct file *file)
2970{
2971 struct dvb_device *dvbdev = file->private_data;
2972 struct ngene_channel *chan = dvbdev->priv;
2973 struct ngene *dev = chan->dev;
2974 struct ngene_channel *chan0 = &chan->dev->channel[0];
2975 int ret;
2976
2977 ret = dvb_generic_open(inode, file);
2978 if (ret < 0)
2979 return ret;
2980 if ((file->f_flags & O_ACCMODE) != O_RDONLY)
2981 return ret;
2982 my_dvb_ringbuffer_flush(&dev->vin_rbuf);
2983
2984 chan0->nBytesPerLine = 1920 * 2;
2985 chan0->nLines = 540;
2986 chan0->Capture1Length = 1920 * 2 * 540;
2987 chan0->pBufferExchange = vcap_exchange;
2988 chan0->itumode = 2;
2989 ngene_command_stream_control(chan0->dev, chan0->number,
2990 0x80, SMODE_VIDEO_CAPTURE, 0);
2991 return ret;
2992}
2993
2994static int video_release(struct inode *inode, struct file *file)
2995{
2996 struct dvb_device *dvbdev = file->private_data;
2997 struct ngene_channel *chan = dvbdev->priv;
2998 struct ngene *dev = chan->dev;
2999 struct ngene_channel *chan0 = &chan->dev->channel[0];
3000
3001 ngene_command_stream_control(dev, 0, 0, 0, 0);
3002 chan0->pBufferExchange = 0;
3003
3004 return dvb_generic_release(inode, file);
3005}
3006
3007static ssize_t video_write(struct file *file,
3008 const char *buf, size_t count, loff_t *ppos)
3009{
3010 return -EINVAL;
3011}
3012
3013ssize_t video_read(struct file *file, char *buf, size_t count, loff_t *ppos)
3014{
3015 struct dvb_device *dvbdev = file->private_data;
3016 struct ngene_channel *chan = dvbdev->priv;
3017 struct ngene *dev = chan->dev;
3018 int left, avail;
3019
3020 left = count;
3021 while (left) {
3022 if (wait_event_interruptible(
3023 dev->vin_rbuf.queue,
3024 dvb_ringbuffer_avail(&dev->vin_rbuf) > 0) < 0)
3025 return -EAGAIN;
3026 avail = dvb_ringbuffer_avail(&dev->vin_rbuf);
3027 if (avail > left)
3028 avail = left;
3029 dvb_ringbuffer_read_user(&dev->vin_rbuf, buf, avail);
3030 left -= avail;
3031 buf += avail;
3032 }
3033 return count;
3034}
3035
3036/* Why is this not exported from dvb_core ?!?! */
3037
3038static int dvb_usercopy2(struct inode *inode, struct file *file,
3039 unsigned int cmd, unsigned long arg,
3040 int (*func)(struct inode *inode, struct file *file,
3041 unsigned int cmd, void *arg))
3042{
3043 char sbuf[128];
3044 void *mbuf = NULL;
3045 void *parg = NULL;
3046 int err = -EINVAL;
3047
3048 /* Copy arguments into temp kernel buffer */
3049 switch (_IOC_DIR(cmd)) {
3050 case _IOC_NONE:
3051 /*
3052 * For this command, the pointer is actually an integer
3053 * argument.
3054 */
3055 parg = (void *)arg;
3056 break;
3057 case _IOC_READ: /* some v4l ioctls are marked wrong ... */
3058 case _IOC_WRITE:
3059 case (_IOC_WRITE | _IOC_READ):
3060 if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
3061 parg = sbuf;
3062 } else {
3063 /* too big to allocate from stack */
3064 mbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL);
3065 if (NULL == mbuf)
3066 return -ENOMEM;
3067 parg = mbuf;
3068 }
3069
3070 err = -EFAULT;
3071 if (copy_from_user(parg, (void __user *)arg, _IOC_SIZE(cmd)))
3072 goto out;
3073 break;
3074 }
3075
3076 /* call driver */
3077 err = func(inode, file, cmd, parg);
3078 if (err == -ENOIOCTLCMD)
3079 err = -EINVAL;
3080
3081 if (err < 0)
3082 goto out;
3083
3084 /* Copy results into user buffer */
3085 switch (_IOC_DIR(cmd)) {
3086 case _IOC_READ:
3087 case (_IOC_WRITE | _IOC_READ):
3088 if (copy_to_user((void __user *)arg, parg, _IOC_SIZE(cmd)))
3089 err = -EFAULT;
3090 break;
3091 }
3092
3093out:
3094 kfree(mbuf);
3095 return err;
3096}
3097
3098static int video_do_ioctl(struct inode *inode, struct file *file,
3099 unsigned int cmd, void *parg)
3100{
3101 struct dvb_device *dvbdev = file->private_data;
3102 struct ngene_channel *chan = dvbdev->priv;
3103 struct ngene *dev = chan->dev;
3104 int ret = 0;
3105 unsigned long arg = (unsigned long)parg;
3106
3107 switch (cmd) {
3108 case VIDEO_SET_STREAMTYPE:
3109 switch (arg) {
3110 case VIDEO_CAP_MPEG2:
3111 /* printk(KERN_INFO DEVICE_NAME ": setting MPEG2\n"); */
3112 send_cli(dev, "vdec mpeg2\n");
3113 break;
3114 case VIDEO_CAP_AVC:
3115 /* printk(KERN_INFO DEVICE_NAME ": setting H264\n"); */
3116 send_cli(dev, "vdec h264\n");
3117 break;
3118 case VIDEO_CAP_VC1:
3119 /* printk(KERN_INFO DEVICE_NAME ": setting VC1\n"); */
3120 send_cli(dev, "vdec vc1\n");
3121 break;
3122 default:
3123 ret = -EINVAL;
3124 break;
3125 }
3126 break;
3127 default:
3128 ret = -ENOIOCTLCMD;
3129 return -EINVAL;
3130 }
3131 return ret;
3132}
3133
3134static int video_ioctl(struct inode *inode, struct file *file,
3135 unsigned int cmd, unsigned long arg)
3136{
3137 return dvb_usercopy2(inode, file, cmd, arg, video_do_ioctl);
3138}
3139
3140static const struct file_operations video_fops = {
3141 .owner = THIS_MODULE,
3142 .read = video_read,
3143 .write = video_write,
3144 .open = video_open,
3145 .release = video_release,
3146 .ioctl = video_ioctl,
3147};
3148
3149static struct dvb_device dvbdev_video = {
3150 .priv = 0,
3151 .readers = -1,
3152 .writers = 1,
3153 .users = -1,
3154 .fops = &video_fops,
3155};
3156
3157/****************************************************************************/
3158/* LNBH21 *******************************************************************/
3159/****************************************************************************/
3160
3161static int lnbh21_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
3162{
3163 struct ngene_channel *chan =
3164 *(struct ngene_channel **) fe->demodulator_priv;
3165
3166 switch (voltage) {
3167 case SEC_VOLTAGE_OFF:
3168 chan->lnbh &= 0xf3;
3169 break;
3170 case SEC_VOLTAGE_13:
3171 chan->lnbh |= 0x04;
3172 chan->lnbh &= ~0x08;
3173 break;
3174 case SEC_VOLTAGE_18:
3175 chan->lnbh |= 0x0c;
3176 break;
3177 default:
3178 return -EINVAL;
3179 };
3180 chan->lnbh |= 0x10;
3181 return i2c_write(&chan->i2c_adapter,
3182 chan->dev->card_info->lnb[chan->number], chan->lnbh);
3183}
3184
3185static int lnbh21_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
3186{
3187 struct ngene_channel *chan =
3188 *(struct ngene_channel **)fe->demodulator_priv;
3189
3190 switch (tone) {
3191 case SEC_TONE_ON:
3192 chan->lnbh |= 0x20;
3193 break;
3194 case SEC_TONE_OFF:
3195 chan->lnbh &= 0xdf;
3196 break;
3197 default:
3198 return -EINVAL;
3199 }
3200 return i2c_write(&chan->i2c_adapter,
3201 chan->dev->card_info->lnb[chan->number], chan->lnbh);
3202}
3203 2379
3204/****************************************************************************/ 2380/****************************************************************************/
3205/* Switch control (I2C gates, etc.) *****************************************/ 2381/* Switch control (I2C gates, etc.) *****************************************/
3206/****************************************************************************/ 2382/****************************************************************************/
3207 2383
3208static int avf_output(struct ngene_channel *chan, int state)
3209{
3210 if (chan->dev->card_info->avf[chan->number])
3211 i2c_write_register(&chan->i2c_adapter,
3212 chan->dev->card_info->avf[chan->number],
3213 0xf2, state ? 0x89 : 0x80);
3214 return 0;
3215}
3216
3217/* Viper expander: sw11,sw12,sw21,sw22,i2csw1,i2csw2,tsen1,tsen2 */
3218
3219static int exp_set(struct ngene *dev)
3220{
3221 return i2c_write(&dev->channel[0].i2c_adapter,
3222 dev->card_info->exp, dev->exp_val);
3223}
3224
3225static int exp_init(struct ngene *dev)
3226{
3227 if (!dev->card_info->exp)
3228 return 0;
3229 dev->exp_val = dev->card_info->exp_init;
3230 return exp_set(dev);
3231}
3232
3233static int exp_set_bit(struct ngene *dev, int bit, int val)
3234{
3235 if (val)
3236 set_bit(bit, &dev->exp_val);
3237 else
3238 clear_bit(bit, &dev->exp_val);
3239 return exp_set(dev);
3240}
3241
3242static int viper_switch_ctrl(struct ngene_channel *chan, int type, int val)
3243{
3244 switch (type) {
3245 case 0: /* I2C tuner gate on/off */
3246 return exp_set_bit(chan->dev, 4 + chan->number, val);
3247 case 1: /* Stream: 0=TS 1=ITU */
3248 avf_output(chan, val);
3249 return exp_set_bit(chan->dev, 6 + chan->number, val);
3250 case 2: /* Input: 0=digital 1=analog antenna input */
3251 exp_set_bit(chan->dev, 0 + chan->number * 2, val ? 0 : 1);
3252 exp_set_bit(chan->dev, 1 + chan->number * 2, val ? 1 : 0);
3253 break;
3254 }
3255 return 0;
3256}
3257
3258static int viper_switch_ctrl2(struct ngene_channel *chan, int type, int val)
3259{
3260 switch (type) {
3261 case 0: /* I2C tuner gate on/off */
3262 return exp_set_bit(chan->dev, 4 + chan->number, val);
3263 case 1: /* Stream: 0=TS 1=ITU */
3264 avf_output(chan, val);
3265 return exp_set_bit(chan->dev, 6 + chan->number, val);
3266 case 2: /* Input: 0=digital 1=analog antenna input */
3267 exp_set_bit(chan->dev, 0 + chan->number * 2, val ? 0 : 1);
3268 exp_set_bit(chan->dev, 1 + chan->number * 2, 0);
3269 break;
3270 }
3271 return 0;
3272}
3273
3274static int viper_gate_ctrl(struct dvb_frontend *fe, int enable)
3275{
3276 /* Well, just abuse sec :-) */
3277 struct ngene_channel *chan = fe->sec_priv;
3278 struct ngene *dev = chan->dev;
3279
3280 return dev->card_info->switch_ctrl(chan, 0, enable);
3281}
3282
3283static int python_switch_ctrl(struct ngene_channel *chan, int type, int val)
3284{
3285 switch (type) {
3286 case 0: /* I2C tuner gate on/off */
3287 if (chan->number > 1)
3288 return -EINVAL;
3289 return ngene_command_gpio_set(chan->dev, 3 + chan->number, val);
3290 case 1: /* Stream: 0=TS 1=ITU */
3291 avf_output(chan, val);
3292 return 0;
3293 }
3294 return 0;
3295}
3296
3297static int viper_reset_xc(struct dvb_frontend *fe)
3298{
3299 struct ngene_channel *chan = fe->sec_priv;
3300 struct ngene *dev = chan->dev;
3301
3302 printk(KERN_INFO DEVICE_NAME ": Reset XC3028\n");
3303
3304 if (chan->number > 1)
3305 return -EINVAL;
3306
3307 ngene_command_gpio_set(dev, 3 + chan->number, 0);
3308 msleep(150);
3309 ngene_command_gpio_set(dev, 3 + chan->number, 1);
3310 return 0;
3311}
3312
3313static int python_gate_ctrl(struct dvb_frontend *fe, int enable)
3314{
3315 struct ngene_channel *chan = fe->sec_priv;
3316 struct ngene *dev = chan->dev;
3317
3318 if (chan->number == 0)
3319 return ngene_command_gpio_set(dev, 3, enable);
3320 if (chan->number == 1)
3321 return ngene_command_gpio_set(dev, 4, enable);
3322 return -EINVAL;
3323}
3324 2384
3325/****************************************************************************/ 2385/****************************************************************************/
3326/* Demod/tuner attachment ***************************************************/ 2386/* Demod/tuner attachment ***************************************************/
3327/****************************************************************************/ 2387/****************************************************************************/
3328 2388
3329static int tuner_attach_mt2060(struct ngene_channel *chan)
3330{
3331 struct ngene *dev = chan->dev;
3332 void *tconf = dev->card_info->tuner_config[chan->number];
3333 u8 drxa = dev->card_info->demoda[chan->number];
3334 struct dvb_frontend *fe = chan->fe, *fe2;
3335
3336 fe->sec_priv = chan;
3337 fe->ops.i2c_gate_ctrl = dev->card_info->gate_ctrl;
3338
3339 dev->card_info->gate_ctrl(fe, 1);
3340 fe2 = mt2060_attach(fe, &chan->i2c_adapter, tconf, 1220);
3341 dev->card_info->gate_ctrl(fe, 0);
3342
3343 i2c_write_register(&chan->i2c_adapter, drxa, 3, 4);
3344 write_demod(&chan->i2c_adapter, drxa, 0x1012, 15);
3345 write_demod(&chan->i2c_adapter, drxa, 0x1007, 0xc27);
3346 write_demod(&chan->i2c_adapter, drxa, 0x0020, 0x003);
3347
3348 return fe2 ? 0 : -ENODEV;
3349}
3350
3351static int tuner_attach_xc3028(struct ngene_channel *chan)
3352{
3353 struct ngene *dev = chan->dev;
3354 void *tconf = dev->card_info->tuner_config[chan->number];
3355 struct dvb_frontend *fe = chan->fe, *fe2;
3356
3357 fe->sec_priv = chan;
3358 fe->ops.i2c_gate_ctrl = dev->card_info->gate_ctrl;
3359
3360 dev->card_info->gate_ctrl(fe, 1);
3361 fe2 = xc3028_attach(fe, &chan->i2c_adapter, tconf);
3362 dev->card_info->gate_ctrl(fe, 0);
3363
3364 /*chan->fe->ops.tuner_ops.set_frequency(chan->fe,231250000);*/
3365
3366 return fe2 ? 0 : -ENODEV;
3367}
3368
3369static int demod_attach_drxd(struct ngene_channel *chan)
3370{
3371 void *feconf = chan->dev->card_info->fe_config[chan->number];
3372
3373 chan->fe = drxd_attach(feconf,
3374 chan, &chan->i2c_adapter,
3375 &chan->dev->pci_dev->dev);
3376 return (chan->fe) ? 0 : -ENODEV;
3377}
3378
3379static int demod_attach_drxh(struct ngene_channel *chan)
3380{
3381 void *feconf = chan->dev->card_info->fe_config[chan->number];
3382
3383 chan->fe = drxh_attach(feconf, chan,
3384 &chan->i2c_adapter, &chan->dev->pci_dev->dev);
3385 return (chan->fe) ? 0 : -ENODEV;
3386}
3387
3388static int demod_attach_stb0899(struct ngene_channel *chan)
3389{
3390 void *feconf = chan->dev->card_info->fe_config[chan->number];
3391
3392 chan->fe = stb0899_attach(feconf,
3393 chan, &chan->i2c_adapter,
3394 &chan->dev->pci_dev->dev);
3395 if (chan->fe) {
3396 chan->set_tone = chan->fe->ops.set_tone;
3397 chan->fe->ops.set_tone = lnbh21_set_tone;
3398 chan->fe->ops.set_voltage = lnbh21_set_voltage;
3399 }
3400
3401 return (chan->fe) ? 0 : -ENODEV;
3402}
3403
3404static int demod_attach_stv0900(struct ngene_channel *chan)
3405{
3406 void *feconf = chan->dev->card_info->fe_config[chan->number];
3407
3408 chan->fe = stv0900_attach(feconf,
3409 chan, &chan->i2c_adapter,
3410 &chan->dev->pci_dev->dev);
3411
3412 if (chan->fe) {
3413 chan->set_tone = chan->fe->ops.set_tone;
3414 chan->fe->ops.set_tone = lnbh21_set_tone;
3415 chan->fe->ops.set_voltage = lnbh21_set_voltage;
3416 }
3417
3418 return (chan->fe) ? 0 : -ENODEV;
3419}
3420 2389
3421/****************************************************************************/ 2390/****************************************************************************/
3422/****************************************************************************/ 2391/****************************************************************************/
@@ -3436,10 +2405,6 @@ static void release_channel(struct ngene_channel *chan)
3436 if (chan->command_dev) 2405 if (chan->command_dev)
3437 dvb_unregister_device(chan->command_dev); 2406 dvb_unregister_device(chan->command_dev);
3438#endif 2407#endif
3439 if (chan->audio_dev)
3440 dvb_unregister_device(chan->audio_dev);
3441 if (chan->video_dev)
3442 dvb_unregister_device(chan->video_dev);
3443 if (chan->fe) { 2408 if (chan->fe) {
3444 dvb_unregister_frontend(chan->fe); 2409 dvb_unregister_frontend(chan->fe);
3445 /*dvb_frontend_detach(chan->fe); */ 2410 /*dvb_frontend_detach(chan->fe); */
@@ -3457,10 +2422,6 @@ static void release_channel(struct ngene_channel *chan)
3457#endif 2422#endif
3458 } 2423 }
3459 2424
3460 if (io & (NGENE_IO_AIN)) {
3461 ngene_snd_exit(chan);
3462 kfree(chan->soundbuffer);
3463 }
3464} 2425}
3465 2426
3466static int init_channel(struct ngene_channel *chan) 2427static int init_channel(struct ngene_channel *chan)
@@ -3502,13 +2463,6 @@ static int init_channel(struct ngene_channel *chan)
3502 &chan->mem_frontend, adapter); 2463 &chan->mem_frontend, adapter);
3503 if (io & NGENE_IO_TSOUT) { 2464 if (io & NGENE_IO_TSOUT) {
3504 dvbdemux->write_to_decoder = write_to_decoder; 2465 dvbdemux->write_to_decoder = write_to_decoder;
3505 dvb_register_device(adapter, &chan->audio_dev,
3506 &dvbdev_audio, (void *)chan,
3507 DVB_DEVICE_AUDIO);
3508 dvb_register_device(adapter, &chan->video_dev,
3509 &dvbdev_video, (void *)chan,
3510 DVB_DEVICE_VIDEO);
3511
3512 } 2466 }
3513#ifdef NGENE_COMMAND_API 2467#ifdef NGENE_COMMAND_API
3514 dvb_register_device(adapter, &chan->command_dev, 2468 dvb_register_device(adapter, &chan->command_dev,
@@ -3536,19 +2490,6 @@ static int init_channel(struct ngene_channel *chan)
3536 } 2490 }
3537 } 2491 }
3538 2492
3539 if (io & (NGENE_IO_AIN)) {
3540 ngene_snd_init(chan);
3541#ifdef NGENE_V4L
3542 spin_lock_init(&chan->s_lock);
3543 init_MUTEX(&chan->reslock);
3544 INIT_LIST_HEAD(&chan->capture);
3545#endif
3546
3547 chan->soundbuffer = kmalloc(MAX_AUDIO_BUFFER_SIZE, GFP_KERNEL);
3548 if (!chan->soundbuffer)
3549 return -ENOMEM;
3550 memset(chan->soundbuffer, 0, MAX_AUDIO_BUFFER_SIZE);
3551 }
3552 return ret; 2493 return ret;
3553} 2494}
3554 2495
@@ -3616,8 +2557,6 @@ static int __devinit ngene_probe(struct pci_dev *pci_dev,
3616 goto fail1; 2557 goto fail1;
3617 2558
3618 dev->i2c_current_bus = -1; 2559 dev->i2c_current_bus = -1;
3619 exp_init(dev);
3620
3621 /* Disable analog TV decoder chips if present */ 2560 /* Disable analog TV decoder chips if present */
3622 if (copy_eeprom) { 2561 if (copy_eeprom) {
3623 i2c_copy_eeprom(&dev->channel[0].i2c_adapter, 0x50, 0x52); 2562 i2c_copy_eeprom(&dev->channel[0].i2c_adapter, 0x50, 0x52);
@@ -3648,321 +2587,6 @@ fail1:
3648/* Card configs *************************************************************/ 2587/* Card configs *************************************************************/
3649/****************************************************************************/ 2588/****************************************************************************/
3650 2589
3651static struct drxd_config fe_terratec_dvbt_0 = {
3652 .index = 0,
3653 .demod_address = 0x70,
3654 .demod_revision = 0xa2,
3655 .demoda_address = 0x00,
3656 .pll_address = 0x60,
3657 .pll_type = DRXD_PLL_DTT7520X,
3658 .clock = 20000,
3659 .pll_set = ngene_pll_set_th_dtt7520x,
3660 .osc_deviation = osc_deviation,
3661};
3662
3663static struct drxd_config fe_terratec_dvbt_1 = {
3664 .index = 1,
3665 .demod_address = 0x71,
3666 .demod_revision = 0xa2,
3667 .demoda_address = 0x00,
3668 .pll_address = 0x60,
3669 .pll_type = DRXD_PLL_DTT7520X,
3670 .clock = 20000,
3671 .pll_set = ngene_pll_set_th_dtt7520x,
3672 .osc_deviation = osc_deviation,
3673};
3674
3675static struct ngene_info ngene_info_terratec = {
3676 .type = NGENE_TERRATEC,
3677 .name = "Terratec Integra/Cinergy2400i Dual DVB-T",
3678 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
3679 .demod_attach = {demod_attach_drxd, demod_attach_drxd},
3680 .fe_config = {&fe_terratec_dvbt_0, &fe_terratec_dvbt_1},
3681 .i2c_access = 1,
3682};
3683
3684/****************************************************************************/
3685
3686static struct mt2060_config tuner_python_0 = {
3687 .i2c_address = 0x60,
3688 .clock_out = 3,
3689 .input = 0
3690};
3691
3692static struct mt2060_config tuner_python_1 = {
3693 .i2c_address = 0x61,
3694 .clock_out = 3,
3695 .input = 1
3696};
3697
3698static struct drxd_config fe_python_0 = {
3699 .index = 0,
3700 .demod_address = 0x71,
3701 .demod_revision = 0xb1,
3702 .demoda_address = 0x41,
3703 .clock = 16000,
3704 .osc_deviation = osc_deviation,
3705};
3706
3707static struct drxd_config fe_python_1 = {
3708 .index = 1,
3709 .demod_address = 0x70,
3710 .demod_revision = 0xb1,
3711 .demoda_address = 0x45,
3712 .clock = 16000,
3713 .osc_deviation = osc_deviation,
3714};
3715
3716static struct ngene_info ngene_info_python = {
3717 .type = NGENE_PYTHON,
3718 .name = "Micronas MicPython/Hedgehog Dual DVB-T",
3719 .io_type = {NGENE_IO_TSIN | NGENE_IO_TV,
3720 NGENE_IO_TSIN | NGENE_IO_TV,
3721 NGENE_IO_AIN, NGENE_IO_AIN},
3722 .demod_attach = {demod_attach_drxd, demod_attach_drxd},
3723 .tuner_attach = {tuner_attach_mt2060, tuner_attach_mt2060},
3724 .fe_config = {&fe_python_0, &fe_python_1},
3725 .tuner_config = {&tuner_python_0, &tuner_python_1},
3726 .avf = {0x43, 0x47},
3727 .msp = {0x40, 0x42},
3728 .demoda = {0x41, 0x45},
3729 .gate_ctrl = python_gate_ctrl,
3730 .switch_ctrl = python_switch_ctrl,
3731};
3732
3733/****************************************************************************/
3734
3735static struct drxd_config fe_appb_dvbt_0 = {
3736 .index = 0,
3737 .demod_address = 0x71,
3738 .demod_revision = 0xa2,
3739 .demoda_address = 0x41,
3740 .pll_address = 0x63,
3741 .pll_type = DRXD_PLL_MT3X0823,
3742 .clock = 20000,
3743 .pll_set = ngene_pll_set_mt_3x0823,
3744 .osc_deviation = osc_deviation,
3745};
3746
3747static struct drxd_config fe_appb_dvbt_1 = {
3748 .index = 1,
3749 .demod_address = 0x70,
3750 .demod_revision = 0xa2,
3751 .demoda_address = 0x45,
3752 .pll_address = 0x60,
3753 .pll_type = DRXD_PLL_MT3X0823,
3754 .clock = 20000,
3755 .pll_set = ngene_pll_set_mt_3x0823,
3756 .osc_deviation = osc_deviation,
3757};
3758
3759static struct ngene_info ngene_info_appboard = {
3760 .type = NGENE_APP,
3761 .name = "Micronas Application Board Dual DVB-T",
3762 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
3763 .demod_attach = {demod_attach_drxd, demod_attach_drxd},
3764 .fe_config = {&fe_appb_dvbt_0, &fe_appb_dvbt_1},
3765 .avf = {0x43, 0x47},
3766};
3767
3768static struct ngene_info ngene_info_appboard_ntsc = {
3769 .type = NGENE_APP,
3770 .name = "Micronas Application Board Dual DVB-T",
3771 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
3772 .demod_attach = {demod_attach_drxd, demod_attach_drxd},
3773 .fe_config = {&fe_appb_dvbt_0, &fe_appb_dvbt_1},
3774 .avf = {0x43, 0x47},
3775 .ntsc = 1,
3776};
3777
3778/****************************************************************************/
3779
3780static struct stb0899_config fe_sidewinder_0 = {
3781 .demod_address = 0x68,
3782 .pll_address = 0x63,
3783};
3784
3785static struct stb0899_config fe_sidewinder_1 = {
3786 .demod_address = 0x6b,
3787 .pll_address = 0x60,
3788};
3789
3790static struct ngene_info ngene_info_sidewinder = {
3791 .type = NGENE_SIDEWINDER,
3792 .name = "Micronas MicSquirrel/Sidewinder Dual DVB-S2",
3793 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN},
3794 .demod_attach = {demod_attach_stb0899, demod_attach_stb0899},
3795 .fe_config = {&fe_sidewinder_0, &fe_sidewinder_1},
3796 .lnb = {0x0b, 0x08},
3797};
3798
3799/****************************************************************************/
3800/* Yet unnamed S2 card with dual DVB-S2 demod */
3801/****************************************************************************/
3802
3803static struct stv0900_config fe_s2_0 = {
3804 .addr = 0x68,
3805 .pll = 0x63,
3806 .pll_type = 0,
3807 .nr = 0,
3808};
3809
3810static struct stv0900_config fe_s2_1 = {
3811 .addr = 0x68,
3812 .pll = 0x60,
3813 .pll_type = 0,
3814 .nr = 1,
3815};
3816
3817static struct ngene_info ngene_info_s2 = {
3818 .type = NGENE_SIDEWINDER,
3819 .name = "S2",
3820 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN,
3821 NGENE_IO_TSIN, NGENE_IO_TSIN},
3822 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900},
3823 .fe_config = {&fe_s2_0, &fe_s2_1},
3824 .lnb = {0x0b, 0x08},
3825 .tsf = {3, 3},
3826 .fw_version = 15,
3827};
3828
3829static struct stv0900_config fe_s2b_0 = {
3830 .addr = 0x68,
3831 .pll = 0x60,
3832 .pll_type = 0x10,
3833 .nr = 0,
3834};
3835
3836static struct stv0900_config fe_s2b_1 = {
3837 .addr = 0x68,
3838 .pll = 0x63,
3839 .pll_type = 0x10,
3840 .nr = 1,
3841};
3842
3843static struct ngene_info ngene_info_s2_b = {
3844 .type = NGENE_SIDEWINDER,
3845 .name = "S2 V2",
3846 .io_type = {NGENE_IO_TSIN, NGENE_IO_TSIN,
3847 NGENE_IO_TSIN, NGENE_IO_TSIN},
3848 .demod_attach = {demod_attach_stv0900, demod_attach_stv0900},
3849 .fe_config = {&fe_s2b_0, &fe_s2b_1},
3850 .lnb = {0x0b, 0x08},
3851 .tsf = {3, 3},
3852 .fw_version = 17,
3853};
3854
3855/****************************************************************************/
3856
3857static struct xc3028_config tuner_viper_0 = {
3858 .adr = 0x61,
3859 .reset = viper_reset_xc
3860};
3861
3862static struct xc3028_config tuner_viper_1 = {
3863 .adr = 0x64,
3864 .reset = viper_reset_xc
3865};
3866
3867static struct drxh_config fe_viper_h_0 = {.adr = 0x2b};
3868
3869static struct drxh_config fe_viper_h_1 = {.adr = 0x29};
3870
3871static struct drxh_config fe_viper_l_0 = {.adr = 0x2b, .type = 3931};
3872
3873static struct drxh_config fe_viper_l_1 = {.adr = 0x29, .type = 3931};
3874
3875static struct ngene_info ngene_info_viper_v1 = {
3876 .type = NGENE_VIPER,
3877 .name = "Micronas MicViper Dual ATSC DRXH",
3878 .io_type = {NGENE_IO_TSIN | NGENE_IO_TV,
3879 NGENE_IO_TSIN | NGENE_IO_TV,
3880 NGENE_IO_AIN, NGENE_IO_AIN},
3881 .demod_attach = {demod_attach_drxh, demod_attach_drxh},
3882 .fe_config = {&fe_viper_h_0, &fe_viper_h_1},
3883 .tuner_config = {&tuner_viper_0, &tuner_viper_1},
3884 .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028},
3885 .avf = {0x43, 0x47},
3886 .msp = {0x40, 0x42},
3887 .exp = 0x20,
3888 .exp_init = 0xf5,
3889 .gate_ctrl = viper_gate_ctrl,
3890 .switch_ctrl = viper_switch_ctrl,
3891 .tsf = {2, 2},
3892};
3893
3894static struct ngene_info ngene_info_viper_v2 = {
3895 .type = NGENE_VIPER,
3896 .name = "Micronas MicViper Dual ATSC DRXL",
3897 .io_type = {NGENE_IO_TSIN | NGENE_IO_TV,
3898 NGENE_IO_TSIN | NGENE_IO_TV,
3899 NGENE_IO_AIN, NGENE_IO_AIN},
3900 .demod_attach = {demod_attach_drxh, demod_attach_drxh},
3901 .fe_config = {&fe_viper_l_0, &fe_viper_l_1},
3902 .tuner_config = {&tuner_viper_0, &tuner_viper_1},
3903 .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028},
3904 .avf = {0x43, 0x47},
3905 .msp = {0x40, 0x42},
3906 .exp = 0x38,
3907 .exp_init = 0xf5,
3908 .gate_ctrl = viper_gate_ctrl,
3909 .switch_ctrl = viper_switch_ctrl,
3910 .tsf = {2, 2},
3911};
3912
3913/****************************************************************************/
3914
3915static struct ngene_info ngene_info_vbox_v1 = {
3916 .type = NGENE_VBOX_V1,
3917 .name = "VBox Cat's Eye 164E",
3918 .io_type = {NGENE_IO_TSIN | NGENE_IO_TV,
3919 NGENE_IO_TSIN | NGENE_IO_TV,
3920 NGENE_IO_AIN, NGENE_IO_AIN},
3921 .demod_attach = {demod_attach_drxh, demod_attach_drxh},
3922 .fe_config = {&fe_viper_h_0, &fe_viper_h_1},
3923 .tuner_config = {&tuner_viper_0, &tuner_viper_1},
3924 .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028},
3925 .avf = {0x43, 0x47},
3926 .msp = {0x40, 0x42},
3927 .exp = 0x20,
3928 .exp_init = 0xf5,
3929 .gate_ctrl = viper_gate_ctrl,
3930 .switch_ctrl = viper_switch_ctrl,
3931 .tsf = {2, 2},
3932};
3933
3934/****************************************************************************/
3935
3936static struct ngene_info ngene_info_vbox_v2 = {
3937 .type = NGENE_VBOX_V2,
3938 .name = "VBox Cat's Eye 164E",
3939 .io_type = {NGENE_IO_TSIN | NGENE_IO_TV,
3940 NGENE_IO_TSIN | NGENE_IO_TV,
3941 NGENE_IO_AIN, NGENE_IO_AIN},
3942 .demod_attach = {demod_attach_drxh, demod_attach_drxh},
3943 .fe_config = {&fe_viper_h_0, &fe_viper_h_1},
3944 .tuner_config = {&tuner_viper_0, &tuner_viper_1},
3945 .tuner_attach = {tuner_attach_xc3028, tuner_attach_xc3028},
3946 .avf = {0x43, 0x47},
3947 .msp = {0x40, 0x42},
3948 .exp = 0x20,
3949 .exp_init = 0xf5,
3950 .gate_ctrl = viper_gate_ctrl,
3951 .switch_ctrl = viper_switch_ctrl2,
3952 .tsf = {2, 2},
3953};
3954
3955/****************************************************************************/
3956
3957static struct ngene_info ngene_info_racer = {
3958 .type = NGENE_RACER,
3959 .name = "Micronas MicRacer HDTV Decoder Card",
3960 .io_type = {NGENE_IO_HDTV, NGENE_IO_NONE,
3961 NGENE_IO_AIN, NGENE_IO_NONE,
3962 NGENE_IO_TSOUT},
3963 .i2s = {0, 0, 1, 0},
3964 .fw_version = 17,
3965};
3966 2590
3967 2591
3968/****************************************************************************/ 2592/****************************************************************************/
@@ -3977,21 +2601,6 @@ static struct ngene_info ngene_info_racer = {
3977/****************************************************************************/ 2601/****************************************************************************/
3978 2602
3979static const struct pci_device_id ngene_id_tbl[] __devinitdata = { 2603static const struct pci_device_id ngene_id_tbl[] __devinitdata = {
3980 NGENE_ID(0x18c3, 0x0000, ngene_info_appboard),
3981 NGENE_ID(0x18c3, 0x0004, ngene_info_appboard),
3982 NGENE_ID(0x18c3, 0x8011, ngene_info_appboard),
3983 NGENE_ID(0x18c3, 0x8015, ngene_info_appboard_ntsc),
3984 NGENE_ID(0x153b, 0x1167, ngene_info_terratec),
3985 NGENE_ID(0x18c3, 0x0030, ngene_info_python),
3986 NGENE_ID(0x18c3, 0x0052, ngene_info_sidewinder),
3987 NGENE_ID(0x18c3, 0x8f00, ngene_info_racer),
3988 NGENE_ID(0x18c3, 0x0041, ngene_info_viper_v1),
3989 NGENE_ID(0x18c3, 0x0042, ngene_info_viper_v2),
3990 NGENE_ID(0x14f3, 0x0041, ngene_info_vbox_v1),
3991 NGENE_ID(0x14f3, 0x0043, ngene_info_vbox_v2),
3992 NGENE_ID(0x18c3, 0xabcd, ngene_info_s2),
3993 NGENE_ID(0x18c3, 0xabc2, ngene_info_s2_b),
3994 NGENE_ID(0x18c3, 0xabc3, ngene_info_s2_b),
3995 {0} 2604 {0}
3996}; 2605};
3997 2606
diff --git a/drivers/media/dvb/ngene/ngene.h b/drivers/media/dvb/ngene/ngene.h
index 9b48250fdbf8..74c6dab220a3 100644
--- a/drivers/media/dvb/ngene/ngene.h
+++ b/drivers/media/dvb/ngene/ngene.h
@@ -25,8 +25,6 @@
25#define _NGENE_H_ 25#define _NGENE_H_
26 26
27#define ONE_ADAPTER 27#define ONE_ADAPTER
28#define NGENE_COMMAND_API
29/*#define NGENE_V4L*/
30 28
31#include <linux/types.h> 29#include <linux/types.h>
32#include <linux/sched.h> 30#include <linux/sched.h>
@@ -34,35 +32,14 @@
34#include <linux/i2c.h> 32#include <linux/i2c.h>
35#include <asm/dma.h> 33#include <asm/dma.h>
36#include <asm/scatterlist.h> 34#include <asm/scatterlist.h>
37#include <sound/driver.h>
38#include <sound/core.h>
39#include <sound/initval.h>
40#include <sound/control.h>
41#include <sound/pcm.h>
42#include <sound/pcm_params.h>
43 35
44#include <linux/dvb/frontend.h> 36#include <linux/dvb/frontend.h>
45#include <linux/dvb/ca.h>
46#include <linux/dvb/video.h>
47#include <linux/dvb/audio.h>
48 37
49#include "dmxdev.h" 38#include "dmxdev.h"
50#include "dvbdev.h" 39#include "dvbdev.h"
51#include "dvb_demux.h" 40#include "dvb_demux.h"
52#include "dvb_frontend.h" 41#include "dvb_frontend.h"
53#include "dvb_ringbuffer.h" 42#include "dvb_ringbuffer.h"
54#include "drxd.h"
55#include "drxh.h"
56#include "xc3028.h"
57#include "stb0899.h"
58#include "stv0900.h"
59#include "mt2060.h"
60
61#ifdef NGENE_V4L
62#include <media/v4l2-dev.h>
63#include <media/videobuf-core.h>
64#include <linux/videodev.h>
65#endif
66 43
67#define NGENE_VID 0x18c3 44#define NGENE_VID 0x18c3
68#define NGENE_PID 0x0720 45#define NGENE_PID 0x0720
@@ -675,9 +652,6 @@ struct ngene_channel {
675#ifndef ONE_ADAPTER 652#ifndef ONE_ADAPTER
676 struct dvb_adapter dvb_adapter; 653 struct dvb_adapter dvb_adapter;
677#endif 654#endif
678 struct dvb_device *command_dev;
679 struct dvb_device *audio_dev;
680 struct dvb_device *video_dev;
681 struct tasklet_struct demux_tasklet; 655 struct tasklet_struct demux_tasklet;
682 656
683 struct SBufferHeader *nextBuffer; 657 struct SBufferHeader *nextBuffer;
@@ -715,7 +689,6 @@ struct ngene_channel {
715 struct mychip *mychip; 689 struct mychip *mychip;
716 struct snd_card *soundcard; 690 struct snd_card *soundcard;
717 u8 *evenbuffer; 691 u8 *evenbuffer;
718 u8 *soundbuffer;
719 u8 dma_on; 692 u8 dma_on;
720 int soundstreamon; 693 int soundstreamon;
721 int audiomute; 694 int audiomute;
@@ -887,8 +860,6 @@ struct ngene_info {
887 u8 lnb[4]; 860 u8 lnb[4];
888 int i2c_access; 861 int i2c_access;
889 u8 ntsc; 862 u8 ntsc;
890 u8 exp;
891 u8 exp_init;
892 u8 tsf[4]; 863 u8 tsf[4];
893 u8 i2s[4]; 864 u8 i2s[4];
894 865
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 13:25:21 -0500