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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-12 16:25:24 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-12 16:25:24 -0400
commit82afee684fe3badaf5ee3fc5b6fda687d558bfb5 (patch)
tree295abb35451a7eb1e46d6066e536e23d1a75668b
parent068345f4a873e8b0b511e8f94a595a20e176eeff (diff)
parentf4d640c9be1979a603ed017e1e03a16ba3a4d7a1 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (30 commits) Blackfin serial driver: supporting BF548-EZKIT serial port Video Console: Blackfin doesnt support VGA console Blackfin arch: Add peripheral io API to gpio header file Blackfin arch: set up gpio interrupt IRQ_PJ9 for BF54x ATAPI PATA driver Blackfin arch: add missing CONFIG_LARGE_ALLOCS when upstream merging Blackfin arch: as pointed out by Robert P. J. Day, update the CPU_FREQ name to match current Kconfig Blackfin arch: extract the entry point from the linked kernel Blackfin arch: clean up some coding style issues Blackfin arch: combine the common code of free_initrd_mem and free_initmem Blackfin arch: Add Support for Peripheral PortMux and resouce allocation Blackfin arch: use PAGE_SIZE when doing aligns rather than hardcoded values Blackfin arch: fix bug set dma_address properly in dma_map_sg Blackfin arch: Disable CACHELINE_ALIGNED_L1 for BF54x by default Blackfin arch: Port the dm9000 driver to Blackfin by using the correct low-level io routines Blackfin arch: There is no CDPRIO Bit in the EBIU_AMGCTL Register of BF54x arch Blackfin arch: scrub dead code Blackfin arch: Fix Warning add some defines in BF54x header file Blackfin arch: add BF54x missing GPIO access functions Blackfin arch: Some memory and code optimizations - Fix SYS_IRQS Blackfin arch: Enable BF54x PIN/GPIO interrupts ...
Diffstat
-rw-r--r--Documentation/blackfin/kgdb.txt155
-rw-r--r--arch/blackfin/Kconfig59
-rw-r--r--arch/blackfin/Makefile2
-rw-r--r--arch/blackfin/boot/Makefile3
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig1100
-rw-r--r--arch/blackfin/kernel/Makefile7
-rw-r--r--arch/blackfin/kernel/asm-offsets.c7
-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c251
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c11
-rw-r--r--arch/blackfin/kernel/bfin_ksyms.c5
-rw-r--r--arch/blackfin/kernel/cacheinit.c66
-rw-r--r--arch/blackfin/kernel/cplbinit.c433
-rw-r--r--arch/blackfin/kernel/dma-mapping.c13
-rw-r--r--arch/blackfin/kernel/dualcore_test.c6
-rw-r--r--arch/blackfin/kernel/fixed_code.S132
-rw-r--r--arch/blackfin/kernel/flat.c55
-rw-r--r--arch/blackfin/kernel/irqchip.c2
-rw-r--r--arch/blackfin/kernel/kgdb.c421
-rw-r--r--arch/blackfin/kernel/module.c32
-rw-r--r--arch/blackfin/kernel/process.c75
-rw-r--r--arch/blackfin/kernel/ptrace.c6
-rw-r--r--arch/blackfin/kernel/setup.c368
-rw-r--r--arch/blackfin/kernel/signal.c10
-rw-r--r--arch/blackfin/kernel/sys_bfin.c8
-rw-r--r--arch/blackfin/kernel/time.c4
-rw-r--r--arch/blackfin/kernel/traps.c62
-rw-r--r--arch/blackfin/kernel/vmlinux.lds.S12
-rw-r--r--arch/blackfin/lib/strcmp.c3
-rw-r--r--arch/blackfin/lib/strcpy.c3
-rw-r--r--arch/blackfin/lib/strncmp.c3
-rw-r--r--arch/blackfin/lib/strncpy.c3
-rw-r--r--arch/blackfin/mach-bf533/Makefile4
-rw-r--r--arch/blackfin/mach-bf533/boards/cm_bf533.c14
-rw-r--r--arch/blackfin/mach-bf533/boards/ezkit.c8
-rw-r--r--arch/blackfin/mach-bf533/boards/generic_board.c6
-rw-r--r--arch/blackfin/mach-bf533/boards/stamp.c30
-rw-r--r--arch/blackfin/mach-bf533/cpu.c3
-rw-r--r--arch/blackfin/mach-bf533/dma.c95
-rw-r--r--arch/blackfin/mach-bf533/head.S5
-rw-r--r--arch/blackfin/mach-bf533/ints-priority.c2
-rw-r--r--arch/blackfin/mach-bf537/Makefile2
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537.c16
-rw-r--r--arch/blackfin/mach-bf537/boards/eth_mac.c5
-rw-r--r--arch/blackfin/mach-bf537/boards/generic_board.c36
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c54
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c77
-rw-r--r--arch/blackfin/mach-bf537/dma.c115
-rw-r--r--arch/blackfin/mach-bf537/head.S6
-rw-r--r--arch/blackfin/mach-bf537/ints-priority.c2
-rw-r--r--arch/blackfin/mach-bf548/Kconfig316
-rw-r--r--arch/blackfin/mach-bf548/Makefile9
-rw-r--r--arch/blackfin/mach-bf548/boards/Makefile5
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c114
-rw-r--r--arch/blackfin/mach-bf548/boards/led.S172
-rw-r--r--arch/blackfin/mach-bf548/cpu.c159
-rw-r--r--arch/blackfin/mach-bf548/dma.c156
-rw-r--r--arch/blackfin/mach-bf548/gpio.c323
-rw-r--r--arch/blackfin/mach-bf548/head.S512
-rw-r--r--arch/blackfin/mach-bf548/ints-priority.c137
-rw-r--r--arch/blackfin/mach-bf561/Makefile2
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c32
-rw-r--r--arch/blackfin/mach-bf561/boards/ezkit.c33
-rw-r--r--arch/blackfin/mach-bf561/boards/generic_board.c6
-rw-r--r--arch/blackfin/mach-bf561/boards/tepla.c6
-rw-r--r--arch/blackfin/mach-bf561/coreb.c18
-rw-r--r--arch/blackfin/mach-bf561/dma.c131
-rw-r--r--arch/blackfin/mach-bf561/head.S6
-rw-r--r--arch/blackfin/mach-bf561/ints-priority.c2
-rw-r--r--arch/blackfin/mach-common/Makefile4
-rw-r--r--arch/blackfin/mach-common/cacheinit.S89
-rw-r--r--arch/blackfin/mach-common/cplbinfo.c13
-rw-r--r--arch/blackfin/mach-common/entry.S76
-rw-r--r--arch/blackfin/mach-common/interrupt.S8
-rw-r--r--arch/blackfin/mach-common/ints-priority-dc.c13
-rw-r--r--arch/blackfin/mach-common/ints-priority-sc.c405
-rw-r--r--arch/blackfin/mach-common/pm.c4
-rw-r--r--arch/blackfin/mm/blackfin_sram.c4
-rw-r--r--arch/blackfin/mm/init.c47
-rw-r--r--arch/blackfin/oprofile/common.c6
-rw-r--r--arch/blackfin/oprofile/op_model_bf533.c6
-rw-r--r--arch/blackfin/oprofile/timer_int.c3
-rw-r--r--drivers/net/Kconfig2
-rw-r--r--drivers/net/dm9000.c17
-rw-r--r--drivers/serial/Kconfig48
-rw-r--r--drivers/serial/bfin_5xx.c182
-rw-r--r--drivers/video/console/Kconfig2
-rw-r--r--include/asm-blackfin/Kbuild2
-rw-r--r--include/asm-blackfin/bfin-global.h12
-rw-r--r--include/asm-blackfin/cplbinit.h133
-rw-r--r--include/asm-blackfin/fixed_code.h20
-rw-r--r--include/asm-blackfin/gpio.h58
-rw-r--r--include/asm-blackfin/hardirq.h4
-rw-r--r--include/asm-blackfin/kgdb.h183
-rw-r--r--include/asm-blackfin/mach-bf533/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf533/portmux.h65
-rw-r--r--include/asm-blackfin/mach-bf537/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf537/portmux.h109
-rw-r--r--include/asm-blackfin/mach-bf548/anomaly.h74
-rw-r--r--include/asm-blackfin/mach-bf548/bf548.h271
-rw-r--r--include/asm-blackfin/mach-bf548/bfin_serial_5xx.h193
-rw-r--r--include/asm-blackfin/mach-bf548/blackfin.h168
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h72
-rw-r--r--include/asm-blackfin/mach-bf548/defBF542.h281
-rw-r--r--include/asm-blackfin/mach-bf548/defBF544.h60
-rw-r--r--include/asm-blackfin/mach-bf548/defBF548.h341
-rw-r--r--include/asm-blackfin/mach-bf548/defBF549.h763
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h1366
-rw-r--r--include/asm-blackfin/mach-bf548/dma.h73
-rw-r--r--include/asm-blackfin/mach-bf548/gpio.h216
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h467
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h189
-rw-r--r--include/asm-blackfin/mach-bf548/mem_map.h97
-rw-r--r--include/asm-blackfin/mach-bf548/portmux.h270
-rw-r--r--include/asm-blackfin/mach-bf561/cdefBF561.h9
-rw-r--r--include/asm-blackfin/mach-bf561/dma.h3
-rw-r--r--include/asm-blackfin/mach-bf561/portmux.h87
-rw-r--r--include/asm-blackfin/mach-common/cdef_LPBlackfin.h23
-rw-r--r--include/asm-blackfin/mman.h2
-rw-r--r--include/asm-blackfin/page.h4
-rw-r--r--include/asm-blackfin/portmux.h1133
-rw-r--r--include/asm-blackfin/trace.h52
121 files changed, 9767 insertions, 3904 deletions
diff --git a/Documentation/blackfin/kgdb.txt b/Documentation/blackfin/kgdb.txt
new file mode 100644
index 000000000000..84f6a484ae9a
--- /dev/null
+++ b/Documentation/blackfin/kgdb.txt
@@ -0,0 +1,155 @@
1 A Simple Guide to Configure KGDB
2
3 Sonic Zhang <sonic.zhang@analog.com>
4 Aug. 24th 2006
5
6
7This KGDB patch enables the kernel developer to do source level debugging on
8the kernel for the Blackfin architecture. The debugging works over either the
9ethernet interface or one of the uarts. Both software breakpoints and
10hardware breakpoints are supported in this version.
11http://docs.blackfin.uclinux.org/doku.php?id=kgdb
12
13
142 known issues:
151. This bug:
16 http://blackfin.uclinux.org/tracker/index.php?func=detail&aid=544&group_id=18&atid=145
17 The GDB client for Blackfin uClinux causes incorrect values of local
18 variables to be displayed when the user breaks the running of kernel in GDB.
192. Because of a hardware bug in Blackfin 533 v1.0.3:
20 05000067 - Watchpoints (Hardware Breakpoints) are not supported
21 Hardware breakpoints cannot be set properly.
22
23
24Debug over Ethernet:
25
261. Compile and install the cross platform version of gdb for blackfin, which
27 can be found at $(BINROOT)/bfin-elf-gdb.
28
292. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
30 "Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
31 With this selected, option "Full Symbolic/Source Debugging support" and
32 "Compile the kernel with frame pointers" are also selected.
33
343. Select option "KGDB: connect over (Ethernet)". Add "kgdboe=@target-IP/,@host-IP/" to
35 the option "Compiled-in Kernel Boot Parameter" under "Kernel hacking".
36
374. Connect minicom to the serial port and boot the kernel image.
38
395. Configure the IP "/> ifconfig eth0 target-IP"
40
416. Start GDB client "bfin-elf-gdb vmlinux".
42
437. Connect to the target "(gdb) target remote udp:target-IP:6443".
44
458. Set software breakpoint "(gdb) break sys_open".
46
479. Continue "(gdb) c".
48
4910. Run ls in the target console "/> ls".
50
5111. Breakpoint hits. "Breakpoint 1: sys_open(..."
52
5312. Display local variables and function paramters.
54 (*) This operation gives wrong results, see known issue 1.
55
5613. Single stepping "(gdb) si".
57
5814. Remove breakpoint 1. "(gdb) del 1"
59
6015. Set hardware breakpoint "(gdb) hbreak sys_open".
61
6216. Continue "(gdb) c".
63
6417. Run ls in the target console "/> ls".
65
6618. Hardware breakpoint hits. "Breakpoint 1: sys_open(...".
67 (*) This hardware breakpoint will not be hit, see known issue 2.
68
6919. Continue "(gdb) c".
70
7120. Interrupt the target in GDB "Ctrl+C".
72
7321. Detach from the target "(gdb) detach".
74
7522. Exit GDB "(gdb) quit".
76
77
78Debug over the UART:
79
801. Compile and install the cross platform version of gdb for blackfin, which
81 can be found at $(BINROOT)/bfin-elf-gdb.
82
832. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
84 "Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
85 With this selected, option "Full Symbolic/Source Debugging support" and
86 "Compile the kernel with frame pointers" are also selected.
87
883. Select option "KGDB: connect over (UART)". Set "KGDB: UART port number" to be
89 a different one from the console. Don't forget to change the mode of
90 blackfin serial driver to PIO. Otherwise kgdb works incorrectly on UART.
91
924. If you want connect to kgdb when the kernel boots, enable
93 "KGDB: Wait for gdb connection early"
94
955. Compile kernel.
96
976. Connect minicom to the serial port of the console and boot the kernel image.
98
997. Start GDB client "bfin-elf-gdb vmlinux".
100
1018. Set the baud rate in GDB "(gdb) set remotebaud 57600".
102
1039. Connect to the target on the second serial port "(gdb) target remote /dev/ttyS1".
104
10510. Set software breakpoint "(gdb) break sys_open".
106
10711. Continue "(gdb) c".
108
10912. Run ls in the target console "/> ls".
110
11113. A breakpoint is hit. "Breakpoint 1: sys_open(..."
112
11314. All other operations are the same as that in KGDB over Ethernet.
114
115
116Debug over the same UART as console:
117
1181. Compile and install the cross platform version of gdb for blackfin, which
119 can be found at $(BINROOT)/bfin-elf-gdb.
120
1212. Apply this patch to the 2.6.x kernel. Select the menuconfig option under
122 "Kernel hacking" -> "Kernel debugging" -> "KGDB: kernel debug with remote gdb".
123 With this selected, option "Full Symbolic/Source Debugging support" and
124 "Compile the kernel with frame pointers" are also selected.
125
1263. Select option "KGDB: connect over UART". Set "KGDB: UART port number" to console.
127 Don't forget to change the mode of blackfin serial driver to PIO.
128 Otherwise kgdb works incorrectly on UART.
129
1304. If you want connect to kgdb when the kernel boots, enable
131 "KGDB: Wait for gdb connection early"
132
1335. Connect minicom to the serial port and boot the kernel image.
134
1356. (Optional) Ask target to wait for gdb connection by entering Ctrl+A. In minicom, you should enter Ctrl+A+A.
136
1377. Start GDB client "bfin-elf-gdb vmlinux".
138
1398. Set the baud rate in GDB "(gdb) set remotebaud 57600".
140
1419. Connect to the target "(gdb) target remote /dev/ttyS0".
142
14310. Set software breakpoint "(gdb) break sys_open".
144
14511. Continue "(gdb) c". Then enter Ctrl+C twice to stop GDB connection.
146
14712. Run ls in the target console "/> ls". Dummy string can be seen on the console.
148
14913. Then connect the gdb to target again. "(gdb) target remote /dev/ttyS0".
150 Now you will find a breakpoint is hit. "Breakpoint 1: sys_open(..."
151
15214. All other operations are the same as that in KGDB over Ethernet. The only
153 difference is that after continue command in GDB, please stop GDB
154 connection by 2 "Ctrl+C"s and connect again after breakpoints are hit or
155 Ctrl+A is entered.
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index d98bafcaca59..017defaa525b 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -71,6 +71,7 @@ config GENERIC_CALIBRATE_DELAY
71 71
72config IRQCHIP_DEMUX_GPIO 72config IRQCHIP_DEMUX_GPIO
73 bool 73 bool
74 depends on (BF53x || BF561 || BF54x)
74 default y 75 default y
75 76
76source "init/Kconfig" 77source "init/Kconfig"
@@ -114,6 +115,26 @@ config BF537
114 help 115 help
115 BF537 Processor Support. 116 BF537 Processor Support.
116 117
118config BF542
119 bool "BF542"
120 help
121 BF542 Processor Support.
122
123config BF544
124 bool "BF544"
125 help
126 BF544 Processor Support.
127
128config BF548
129 bool "BF548"
130 help
131 BF548 Processor Support.
132
133config BF549
134 bool "BF549"
135 help
136 BF549 Processor Support.
137
117config BF561 138config BF561
118 bool "BF561" 139 bool "BF561"
119 help 140 help
@@ -125,6 +146,11 @@ choice
125 prompt "Silicon Rev" 146 prompt "Silicon Rev"
126 default BF_REV_0_2 if BF537 147 default BF_REV_0_2 if BF537
127 default BF_REV_0_3 if BF533 148 default BF_REV_0_3 if BF533
149 default BF_REV_0_0 if BF549
150
151config BF_REV_0_0
152 bool "0.0"
153 depends on (BF549)
128 154
129config BF_REV_0_2 155config BF_REV_0_2
130 bool "0.2" 156 bool "0.2"
@@ -150,6 +176,16 @@ config BF_REV_NONE
150 176
151endchoice 177endchoice
152 178
179config BF53x
180 bool
181 depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
182 default y
183
184config BF54x
185 bool
186 depends on (BF542 || BF544 || BF548 || BF549)
187 default y
188
153config BFIN_DUAL_CORE 189config BFIN_DUAL_CORE
154 bool 190 bool
155 depends on (BF561) 191 depends on (BF561)
@@ -198,6 +234,12 @@ config BFIN537_BLUETECHNIX_CM
198 help 234 help
199 CM-BF537 support for EVAL- and DEV-Board. 235 CM-BF537 support for EVAL- and DEV-Board.
200 236
237config BFIN548_EZKIT
238 bool "BF548-EZKIT"
239 depends on (BF548 || BF549)
240 help
241 BFIN548-EZKIT board Support.
242
201config BFIN561_BLUETECHNIX_CM 243config BFIN561_BLUETECHNIX_CM
202 bool "Bluetechnix CM-BF561" 244 bool "Bluetechnix CM-BF561"
203 depends on (BF561) 245 depends on (BF561)
@@ -265,6 +307,7 @@ config BFIN_SHARED_FLASH_ENET
265source "arch/blackfin/mach-bf533/Kconfig" 307source "arch/blackfin/mach-bf533/Kconfig"
266source "arch/blackfin/mach-bf561/Kconfig" 308source "arch/blackfin/mach-bf561/Kconfig"
267source "arch/blackfin/mach-bf537/Kconfig" 309source "arch/blackfin/mach-bf537/Kconfig"
310source "arch/blackfin/mach-bf548/Kconfig"
268 311
269menu "Board customizations" 312menu "Board customizations"
270 313
@@ -497,7 +540,8 @@ config IP_CHECKSUM_L1
497 540
498config CACHELINE_ALIGNED_L1 541config CACHELINE_ALIGNED_L1
499 bool "Locate cacheline_aligned data to L1 Data Memory" 542 bool "Locate cacheline_aligned data to L1 Data Memory"
500 default y 543 default y if !BF54x
544 default n if BF54x
501 depends on !BF531 545 depends on !BF531
502 help 546 help
503 If enabled cacheline_anligned data is linked 547 If enabled cacheline_anligned data is linked
@@ -541,9 +585,17 @@ endchoice
541 585
542source "mm/Kconfig" 586source "mm/Kconfig"
543 587
588config LARGE_ALLOCS
589 bool "Allow allocating large blocks (> 1MB) of memory"
590 help
591 Allow the slab memory allocator to keep chains for very large
592 memory sizes - upto 32MB. You may need this if your system has
593 a lot of RAM, and you need to able to allocate very large
594 contiguous chunks. If unsure, say N.
595
544config BFIN_DMA_5XX 596config BFIN_DMA_5XX
545 bool "Enable DMA Support" 597 bool "Enable DMA Support"
546 depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561) 598 depends on (BF533 || BF532 || BF531 || BF537 || BF536 || BF534 || BF561 || BF54x)
547 default y 599 default y
548 help 600 help
549 DMA driver for BF5xx. 601 DMA driver for BF5xx.
@@ -686,6 +738,7 @@ config C_AMCKEN
686 738
687config C_CDPRIO 739config C_CDPRIO
688 bool "DMA has priority over core for ext. accesses" 740 bool "DMA has priority over core for ext. accesses"
741 depends on !BF54x
689 default n 742 default n
690 743
691config C_B0PEN 744config C_B0PEN
@@ -839,7 +892,7 @@ endchoice
839 892
840endmenu 893endmenu
841 894
842if (BF537 || BF533) 895if (BF537 || BF533 || BF54x)
843 896
844menu "CPU Frequency scaling" 897menu "CPU Frequency scaling"
845 898
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 6971a4418dfe..1b75672dfc8f 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -24,6 +24,8 @@ machine-$(CONFIG_BF533) := bf533
24machine-$(CONFIG_BF534) := bf537 24machine-$(CONFIG_BF534) := bf537
25machine-$(CONFIG_BF536) := bf537 25machine-$(CONFIG_BF536) := bf537
26machine-$(CONFIG_BF537) := bf537 26machine-$(CONFIG_BF537) := bf537
27machine-$(CONFIG_BF548) := bf548
28machine-$(CONFIG_BF549) := bf548
27machine-$(CONFIG_BF561) := bf561 29machine-$(CONFIG_BF561) := bf561
28MACHINE := $(machine-y) 30MACHINE := $(machine-y)
29export MACHINE 31export MACHINE
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index 49e8098d4c21..8cd33560e817 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -13,7 +13,8 @@ extra-y += vmlinux.bin vmlinux.gz
13 13
14quiet_cmd_uimage = UIMAGE $@ 14quiet_cmd_uimage = UIMAGE $@
15 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \ 15 cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
16 -C gzip -a $(CONFIG_BOOT_LOAD) -e $(CONFIG_BOOT_LOAD) -n 'Linux-$(KERNELRELEASE)' \ 16 -C gzip -n 'Linux-$(KERNELRELEASE)' -a $(CONFIG_BOOT_LOAD) \
17 -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
17 -d $< $@ 18 -d $< $@
18 19
19$(obj)/vmlinux.bin: vmlinux FORCE 20$(obj)/vmlinux.bin: vmlinux FORCE
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
new file mode 100644
index 000000000000..ac8390fafa9c
--- /dev/null
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -0,0 +1,1100 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.21.5
4#
5# CONFIG_MMU is not set
6# CONFIG_FPU is not set
7CONFIG_RWSEM_GENERIC_SPINLOCK=y
8# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
9CONFIG_BLACKFIN=y
10CONFIG_ZONE_DMA=y
11CONFIG_BFIN=y
12CONFIG_SEMAPHORE_SLEEPERS=y
13CONFIG_GENERIC_FIND_NEXT_BIT=y
14CONFIG_GENERIC_HWEIGHT=y
15CONFIG_GENERIC_HARDIRQS=y
16CONFIG_GENERIC_IRQ_PROBE=y
17# CONFIG_GENERIC_TIME is not set
18CONFIG_GENERIC_CALIBRATE_DELAY=y
19CONFIG_FORCE_MAX_ZONEORDER=14
20CONFIG_IRQCHIP_DEMUX_GPIO=y
21CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
22
23#
24# Code maturity level options
25#
26CONFIG_EXPERIMENTAL=y
27CONFIG_BROKEN_ON_SMP=y
28CONFIG_INIT_ENV_ARG_LIMIT=32
29
30#
31# General setup
32#
33CONFIG_LOCALVERSION=""
34CONFIG_LOCALVERSION_AUTO=y
35CONFIG_SYSVIPC=y
36# CONFIG_IPC_NS is not set
37CONFIG_SYSVIPC_SYSCTL=y
38# CONFIG_POSIX_MQUEUE is not set
39# CONFIG_BSD_PROCESS_ACCT is not set
40# CONFIG_TASKSTATS is not set
41# CONFIG_UTS_NS is not set
42# CONFIG_AUDIT is not set
43# CONFIG_IKCONFIG is not set
44CONFIG_SYSFS_DEPRECATED=y
45# CONFIG_RELAY is not set
46CONFIG_BLK_DEV_INITRD=y
47CONFIG_INITRAMFS_SOURCE=""
48# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
49CONFIG_SYSCTL=y
50CONFIG_EMBEDDED=y
51CONFIG_UID16=y
52CONFIG_SYSCTL_SYSCALL=y
53CONFIG_KALLSYMS=y
54# CONFIG_KALLSYMS_ALL is not set
55# CONFIG_KALLSYMS_EXTRA_PASS is not set
56CONFIG_HOTPLUG=y
57CONFIG_PRINTK=y
58CONFIG_BUG=y
59CONFIG_ELF_CORE=y
60CONFIG_BASE_FULL=y
61CONFIG_FUTEX=y
62CONFIG_BIG_ORDER_ALLOC_NOFAIL_MAGIC=3
63# CONFIG_NP2 is not set
64CONFIG_SLAB=y
65CONFIG_VM_EVENT_COUNTERS=y
66CONFIG_RT_MUTEXES=y
67CONFIG_TINY_SHMEM=y
68CONFIG_BASE_SMALL=0
69# CONFIG_SLOB is not set
70
71#
72# Loadable module support
73#
74CONFIG_MODULES=y
75CONFIG_MODULE_UNLOAD=y
76# CONFIG_MODULE_FORCE_UNLOAD is not set
77# CONFIG_MODVERSIONS is not set
78# CONFIG_MODULE_SRCVERSION_ALL is not set
79CONFIG_KMOD=y
80
81#
82# Block layer
83#
84CONFIG_BLOCK=y
85# CONFIG_LBD is not set
86# CONFIG_BLK_DEV_IO_TRACE is not set
87# CONFIG_LSF is not set
88
89#
90# IO Schedulers
91#
92CONFIG_IOSCHED_NOOP=y
93CONFIG_IOSCHED_AS=y
94# CONFIG_IOSCHED_DEADLINE is not set
95CONFIG_IOSCHED_CFQ=y
96CONFIG_DEFAULT_AS=y
97# CONFIG_DEFAULT_DEADLINE is not set
98# CONFIG_DEFAULT_CFQ is not set
99# CONFIG_DEFAULT_NOOP is not set
100CONFIG_DEFAULT_IOSCHED="anticipatory"
101# CONFIG_PREEMPT_NONE is not set
102CONFIG_PREEMPT_VOLUNTARY=y
103# CONFIG_PREEMPT is not set
104
105#
106# Blackfin Processor Options
107#
108
109#
110# Processor and Board Settings
111#
112# CONFIG_BF531 is not set
113# CONFIG_BF532 is not set
114# CONFIG_BF533 is not set
115# CONFIG_BF534 is not set
116# CONFIG_BF536 is not set
117# CONFIG_BF537 is not set
118# CONFIG_BF542 is not set
119# CONFIG_BF544 is not set
120# CONFIG_BF548 is not set
121CONFIG_BF549=y
122# CONFIG_BF561 is not set
123CONFIG_BF_REV_0_0=y
124# CONFIG_BF_REV_0_2 is not set
125# CONFIG_BF_REV_0_3 is not set
126# CONFIG_BF_REV_0_4 is not set
127# CONFIG_BF_REV_0_5 is not set
128# CONFIG_BF_REV_ANY is not set
129# CONFIG_BF_REV_NONE is not set
130CONFIG_BF54x=y
131CONFIG_BFIN_SINGLE_CORE=y
132# CONFIG_BFIN533_EZKIT is not set
133# CONFIG_BFIN533_STAMP is not set
134# CONFIG_BFIN537_STAMP is not set
135# CONFIG_BFIN533_BLUETECHNIX_CM is not set
136# CONFIG_BFIN537_BLUETECHNIX_CM is not set
137CONFIG_BFIN548_EZKIT=y
138# CONFIG_BFIN561_BLUETECHNIX_CM is not set
139# CONFIG_BFIN561_EZKIT is not set
140# CONFIG_BFIN561_TEPLA is not set
141# CONFIG_PNAV10 is not set
142# CONFIG_GENERIC_BOARD is not set
143CONFIG_IRQ_PLL_WAKEUP=7
144CONFIG_IRQ_TIMER0=11
145CONFIG_IRQ_TIMER1=11
146CONFIG_IRQ_TIMER2=11
147CONFIG_IRQ_TIMER3=11
148CONFIG_IRQ_TIMER4=11
149CONFIG_IRQ_TIMER5=11
150CONFIG_IRQ_TIMER6=11
151CONFIG_IRQ_TIMER7=11
152CONFIG_IRQ_TIMER8=11
153CONFIG_IRQ_TIMER9=11
154CONFIG_IRQ_TIMER10=11
155CONFIG_IRQ_RTC=8
156CONFIG_IRQ_SPORT0_RX=9
157CONFIG_IRQ_SPORT0_TX=9
158CONFIG_IRQ_SPORT1_RX=9
159CONFIG_IRQ_SPORT1_TX=9
160CONFIG_IRQ_UART0_RX=10
161CONFIG_IRQ_UART0_TX=10
162CONFIG_IRQ_UART1_RX=10
163CONFIG_IRQ_UART1_TX=10
164
165#
166# BF548 Specific Configuration
167#
168
169#
170# Interrupt Priority Assignment
171#
172
173#
174# Priority
175#
176CONFIG_IRQ_DMAC0_ERR=7
177CONFIG_IRQ_EPPI0_ERR=7
178CONFIG_IRQ_SPORT0_ERR=7
179CONFIG_IRQ_SPORT1_ERR=7
180CONFIG_IRQ_SPI0_ERR=7
181CONFIG_IRQ_UART0_ERR=7
182CONFIG_IRQ_EPPI0=8
183CONFIG_IRQ_SPI0=10
184CONFIG_IRQ_PINT0=12
185CONFIG_IRQ_PINT1=12
186CONFIG_IRQ_MDMAS0=13
187CONFIG_IRQ_MDMAS1=13
188CONFIG_IRQ_WATCHDOG=13
189CONFIG_IRQ_DMAC1_ERR=7
190CONFIG_IRQ_SPORT2_ERR=7
191CONFIG_IRQ_SPORT3_ERR=7
192CONFIG_IRQ_MXVR_DATA=7
193CONFIG_IRQ_SPI1_ERR=7
194CONFIG_IRQ_SPI2_ERR=7
195CONFIG_IRQ_UART1_ERR=7
196CONFIG_IRQ_UART2_ERR=7
197CONFIG_IRQ_CAN0_ERR=7
198CONFIG_IRQ_SPORT2_RX=9
199CONFIG_IRQ_SPORT2_TX=9
200CONFIG_IRQ_SPORT3_RX=9
201CONFIG_IRQ_SPORT3_TX=9
202CONFIG_IRQ_EPPI1=9
203CONFIG_IRQ_EPPI2=9
204CONFIG_IRQ_SPI1=10
205CONFIG_IRQ_SPI2=10
206CONFIG_IRQ_ATAPI_RX=10
207CONFIG_IRQ_ATAPI_TX=10
208CONFIG_IRQ_TWI0=11
209CONFIG_IRQ_TWI1=11
210CONFIG_IRQ_CAN0_RX=11
211CONFIG_IRQ_CAN0_TX=11
212CONFIG_IRQ_MDMAS2=13
213CONFIG_IRQ_MDMAS3=13
214CONFIG_IRQ_MXVR_ERR=11
215CONFIG_IRQ_MXVR_MSG=11
216CONFIG_IRQ_MXVR_PKT=11
217CONFIG_IRQ_EPPI1_ERR=7
218CONFIG_IRQ_EPPI2_ERR=7
219CONFIG_IRQ_UART3_ERR=7
220CONFIG_IRQ_HOST_ERR=7
221CONFIG_IRQ_PIXC_ERR=7
222CONFIG_IRQ_NFC_ERR=7
223CONFIG_IRQ_ATAPI_ERR=7
224CONFIG_IRQ_CAN1_ERR=7
225CONFIG_IRQ_HS_DMA_ERR=7
226CONFIG_IRQ_PIXC_IN0=8
227CONFIG_IRQ_PIXC_IN1=8
228CONFIG_IRQ_PIXC_OUT=8
229CONFIG_IRQ_SDH=8
230CONFIG_IRQ_CNT=8
231CONFIG_IRQ_KEY=8
232CONFIG_IRQ_CAN1_RX=11
233CONFIG_IRQ_CAN1_TX=11
234CONFIG_IRQ_SDH_MASK0=11
235CONFIG_IRQ_SDH_MASK1=11
236CONFIG_IRQ_USB_INT0=11
237CONFIG_IRQ_USB_INT1=11
238CONFIG_IRQ_USB_INT2=11
239CONFIG_IRQ_USB_DMA=11
240CONFIG_IRQ_OTPSEC=11
241CONFIG_IRQ_PINT2=11
242CONFIG_IRQ_PINT3=11
243
244#
245# Board customizations
246#
247# CONFIG_CMDLINE_BOOL is not set
248
249#
250# Board Setup
251#
252CONFIG_CLKIN_HZ=25000000
253CONFIG_MEM_SIZE=64
254CONFIG_MEM_ADD_WIDTH=10
255CONFIG_BOOT_LOAD=0x1000
256
257#
258# Blackfin Kernel Optimizations
259#
260
261#
262# Timer Tick
263#
264# CONFIG_HZ_100 is not set
265CONFIG_HZ_250=y
266# CONFIG_HZ_300 is not set
267# CONFIG_HZ_1000 is not set
268CONFIG_HZ=250
269
270#
271# Memory Optimizations
272#
273CONFIG_I_ENTRY_L1=y
274CONFIG_EXCPT_IRQ_SYSC_L1=y
275CONFIG_DO_IRQ_L1=y
276CONFIG_CORE_TIMER_IRQ_L1=y
277CONFIG_IDLE_L1=y
278CONFIG_SCHEDULE_L1=y
279CONFIG_ARITHMETIC_OPS_L1=y
280CONFIG_ACCESS_OK_L1=y
281CONFIG_MEMSET_L1=y
282CONFIG_MEMCPY_L1=y
283CONFIG_SYS_BFIN_SPINLOCK_L1=y
284# CONFIG_IP_CHECKSUM_L1 is not set
285CONFIG_CACHELINE_ALIGNED_L1=y
286# CONFIG_SYSCALL_TAB_L1 is not set
287# CONFIG_CPLB_SWITCH_TAB_L1 is not set
288CONFIG_RAMKERNEL=y
289# CONFIG_ROMKERNEL is not set
290CONFIG_SELECT_MEMORY_MODEL=y
291CONFIG_FLATMEM_MANUAL=y
292# CONFIG_DISCONTIGMEM_MANUAL is not set
293# CONFIG_SPARSEMEM_MANUAL is not set
294CONFIG_FLATMEM=y
295CONFIG_FLAT_NODE_MEM_MAP=y
296# CONFIG_SPARSEMEM_STATIC is not set
297CONFIG_SPLIT_PTLOCK_CPUS=4
298# CONFIG_RESOURCES_64BIT is not set
299CONFIG_ZONE_DMA_FLAG=1
300CONFIG_LARGE_ALLOCS=y
301CONFIG_BFIN_DMA_5XX=y
302# CONFIG_DMA_UNCACHED_2M is not set
303CONFIG_DMA_UNCACHED_1M=y
304# CONFIG_DMA_UNCACHED_NONE is not set
305
306#
307# Cache Support
308#
309CONFIG_BLKFIN_CACHE=y
310CONFIG_BLKFIN_DCACHE=y
311# CONFIG_BLKFIN_DCACHE_BANKA is not set
312# CONFIG_BLKFIN_CACHE_LOCK is not set
313# CONFIG_BLKFIN_WB is not set
314CONFIG_BLKFIN_WT=y
315CONFIG_L1_MAX_PIECE=16
316
317#
318# Clock Settings
319#
320# CONFIG_BFIN_KERNEL_CLOCK is not set
321
322#
323# Asynchonous Memory Configuration
324#
325
326#
327# EBIU_AMBCTL Global Control
328#
329CONFIG_C_AMCKEN=y
330CONFIG_C_CDPRIO=y
331# CONFIG_C_AMBEN is not set
332# CONFIG_C_AMBEN_B0 is not set
333# CONFIG_C_AMBEN_B0_B1 is not set
334# CONFIG_C_AMBEN_B0_B1_B2 is not set
335CONFIG_C_AMBEN_ALL=y
336
337#
338# EBIU_AMBCTL Control
339#
340CONFIG_BANK_0=0x7BB0
341CONFIG_BANK_1=0x7BB0
342CONFIG_BANK_2=0x7BB0
343CONFIG_BANK_3=0x99B3
344
345#
346# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
347#
348# CONFIG_PCI is not set
349
350#
351# PCCARD (PCMCIA/CardBus) support
352#
353# CONFIG_PCCARD is not set
354
355#
356# PCI Hotplug Support
357#
358
359#
360# Executable file formats
361#
362CONFIG_BINFMT_ELF_FDPIC=y
363CONFIG_BINFMT_FLAT=y
364CONFIG_BINFMT_ZFLAT=y
365# CONFIG_BINFMT_SHARED_FLAT is not set
366# CONFIG_BINFMT_MISC is not set
367
368#
369# Power management options
370#
371# CONFIG_PM is not set
372
373#
374# CPU Frequency scaling
375#
376# CONFIG_CPU_FREQ is not set
377
378#
379# Networking
380#
381CONFIG_NET=y
382
383#
384# Networking options
385#
386# CONFIG_NETDEBUG is not set
387CONFIG_PACKET=y
388# CONFIG_PACKET_MMAP is not set
389CONFIG_UNIX=y
390CONFIG_XFRM=y
391# CONFIG_XFRM_USER is not set
392# CONFIG_XFRM_SUB_POLICY is not set
393# CONFIG_XFRM_MIGRATE is not set
394# CONFIG_NET_KEY is not set
395CONFIG_INET=y
396# CONFIG_IP_MULTICAST is not set
397# CONFIG_IP_ADVANCED_ROUTER is not set
398CONFIG_IP_FIB_HASH=y
399CONFIG_IP_PNP=y
400# CONFIG_IP_PNP_DHCP is not set
401# CONFIG_IP_PNP_BOOTP is not set
402# CONFIG_IP_PNP_RARP is not set
403# CONFIG_NET_IPIP is not set
404# CONFIG_NET_IPGRE is not set
405# CONFIG_ARPD is not set
406CONFIG_SYN_COOKIES=y
407# CONFIG_INET_AH is not set
408# CONFIG_INET_ESP is not set
409# CONFIG_INET_IPCOMP is not set
410# CONFIG_INET_XFRM_TUNNEL is not set
411# CONFIG_INET_TUNNEL is not set
412CONFIG_INET_XFRM_MODE_TRANSPORT=y
413CONFIG_INET_XFRM_MODE_TUNNEL=y
414CONFIG_INET_XFRM_MODE_BEET=y
415CONFIG_INET_DIAG=y
416CONFIG_INET_TCP_DIAG=y
417# CONFIG_TCP_CONG_ADVANCED is not set
418CONFIG_TCP_CONG_CUBIC=y
419CONFIG_DEFAULT_TCP_CONG="cubic"
420# CONFIG_TCP_MD5SIG is not set
421# CONFIG_IPV6 is not set
422# CONFIG_INET6_XFRM_TUNNEL is not set
423# CONFIG_INET6_TUNNEL is not set
424# CONFIG_NETLABEL is not set
425# CONFIG_NETWORK_SECMARK is not set
426# CONFIG_NETFILTER is not set
427
428#
429# DCCP Configuration (EXPERIMENTAL)
430#
431# CONFIG_IP_DCCP is not set
432
433#
434# SCTP Configuration (EXPERIMENTAL)
435#
436# CONFIG_IP_SCTP is not set
437
438#
439# TIPC Configuration (EXPERIMENTAL)
440#
441# CONFIG_TIPC is not set
442# CONFIG_ATM is not set
443# CONFIG_BRIDGE is not set
444# CONFIG_VLAN_8021Q is not set
445# CONFIG_DECNET is not set
446# CONFIG_LLC2 is not set
447# CONFIG_IPX is not set
448# CONFIG_ATALK is not set
449# CONFIG_X25 is not set
450# CONFIG_LAPB is not set
451# CONFIG_ECONET is not set
452# CONFIG_WAN_ROUTER is not set
453
454#
455# QoS and/or fair queueing
456#
457# CONFIG_NET_SCHED is not set
458
459#
460# Network testing
461#
462# CONFIG_NET_PKTGEN is not set
463# CONFIG_HAMRADIO is not set
464# CONFIG_IRDA is not set
465# CONFIG_BT is not set
466# CONFIG_IEEE80211 is not set
467
468#
469# Device Drivers
470#
471
472#
473# Generic Driver Options
474#
475CONFIG_STANDALONE=y
476CONFIG_PREVENT_FIRMWARE_BUILD=y
477# CONFIG_FW_LOADER is not set
478# CONFIG_DEBUG_DRIVER is not set
479# CONFIG_DEBUG_DEVRES is not set
480# CONFIG_SYS_HYPERVISOR is not set
481
482#
483# Connector - unified userspace <-> kernelspace linker
484#
485# CONFIG_CONNECTOR is not set
486
487#
488# Memory Technology Devices (MTD)
489#
490CONFIG_MTD=y
491# CONFIG_MTD_DEBUG is not set
492# CONFIG_MTD_CONCAT is not set
493CONFIG_MTD_PARTITIONS=y
494# CONFIG_MTD_REDBOOT_PARTS is not set
495# CONFIG_MTD_CMDLINE_PARTS is not set
496
497#
498# User Modules And Translation Layers
499#
500# CONFIG_MTD_CHAR is not set
501CONFIG_MTD_BLKDEVS=y
502CONFIG_MTD_BLOCK=y
503# CONFIG_FTL is not set
504# CONFIG_NFTL is not set
505# CONFIG_INFTL is not set
506# CONFIG_RFD_FTL is not set
507# CONFIG_SSFDC is not set
508
509#
510# RAM/ROM/Flash chip drivers
511#
512# CONFIG_MTD_CFI is not set
513# CONFIG_MTD_JEDECPROBE is not set
514CONFIG_MTD_MAP_BANK_WIDTH_1=y
515CONFIG_MTD_MAP_BANK_WIDTH_2=y
516CONFIG_MTD_MAP_BANK_WIDTH_4=y
517# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
518# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
519# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
520CONFIG_MTD_CFI_I1=y
521CONFIG_MTD_CFI_I2=y
522# CONFIG_MTD_CFI_I4 is not set
523# CONFIG_MTD_CFI_I8 is not set
524CONFIG_MTD_RAM=y
525# CONFIG_MTD_ROM is not set
526# CONFIG_MTD_ABSENT is not set
527# CONFIG_MTD_OBSOLETE_CHIPS is not set
528
529#
530# Mapping drivers for chip access
531#
532CONFIG_MTD_COMPLEX_MAPPINGS=y
533# CONFIG_MTD_BF5xx is not set
534CONFIG_MTD_UCLINUX=y
535# CONFIG_MTD_PLATRAM is not set
536
537#
538# Self-contained MTD device drivers
539#
540# CONFIG_MTD_SLRAM is not set
541# CONFIG_MTD_PHRAM is not set
542# CONFIG_MTD_MTDRAM is not set
543# CONFIG_MTD_BLOCK2MTD is not set
544
545#
546# Disk-On-Chip Device Drivers
547#
548# CONFIG_MTD_DOC2000 is not set
549# CONFIG_MTD_DOC2001 is not set
550# CONFIG_MTD_DOC2001PLUS is not set
551
552#
553# NAND Flash Device Drivers
554#
555# CONFIG_MTD_NAND is not set
556
557#
558# OneNAND Flash Device Drivers
559#
560# CONFIG_MTD_ONENAND is not set
561
562#
563# Parallel port support
564#
565# CONFIG_PARPORT is not set
566
567#
568# Plug and Play support
569#
570# CONFIG_PNPACPI is not set
571
572#
573# Block devices
574#
575# CONFIG_BLK_DEV_COW_COMMON is not set
576# CONFIG_BLK_DEV_LOOP is not set
577# CONFIG_BLK_DEV_NBD is not set
578CONFIG_BLK_DEV_RAM=y
579CONFIG_BLK_DEV_RAM_COUNT=16
580CONFIG_BLK_DEV_RAM_SIZE=4096
581CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
582# CONFIG_CDROM_PKTCDVD is not set
583# CONFIG_ATA_OVER_ETH is not set
584
585#
586# Misc devices
587#
588
589#
590# ATA/ATAPI/MFM/RLL support
591#
592# CONFIG_IDE is not set
593
594#
595# SCSI device support
596#
597# CONFIG_RAID_ATTRS is not set
598# CONFIG_SCSI is not set
599# CONFIG_SCSI_NETLINK is not set
600
601#
602# Serial ATA (prod) and Parallel ATA (experimental) drivers
603#
604# CONFIG_ATA is not set
605
606#
607# Multi-device support (RAID and LVM)
608#
609# CONFIG_MD is not set
610
611#
612# Fusion MPT device support
613#
614# CONFIG_FUSION is not set
615
616#
617# IEEE 1394 (FireWire) support
618#
619
620#
621# I2O device support
622#
623
624#
625# Network device support
626#
627CONFIG_NETDEVICES=y
628# CONFIG_DUMMY is not set
629# CONFIG_BONDING is not set
630# CONFIG_EQUALIZER is not set
631# CONFIG_TUN is not set
632
633#
634# PHY device support
635#
636# CONFIG_PHYLIB is not set
637
638#
639# Ethernet (10 or 100Mbit)
640#
641CONFIG_NET_ETHERNET=y
642CONFIG_MII=y
643# CONFIG_SMC91X is not set
644# CONFIG_SMSC911X is not set
645
646#
647# Ethernet (1000 Mbit)
648#
649
650#
651# Ethernet (10000 Mbit)
652#
653
654#
655# Token Ring devices
656#
657
658#
659# Wireless LAN (non-hamradio)
660#
661# CONFIG_NET_RADIO is not set
662
663#
664# Wan interfaces
665#
666# CONFIG_WAN is not set
667# CONFIG_PPP is not set
668# CONFIG_SLIP is not set
669# CONFIG_SHAPER is not set
670# CONFIG_NETCONSOLE is not set
671# CONFIG_NETPOLL is not set
672# CONFIG_NET_POLL_CONTROLLER is not set
673
674#
675# ISDN subsystem
676#
677# CONFIG_ISDN is not set
678
679#
680# Telephony Support
681#
682# CONFIG_PHONE is not set
683
684#
685# Input device support
686#
687CONFIG_INPUT=y
688# CONFIG_INPUT_FF_MEMLESS is not set
689
690#
691# Userland interfaces
692#
693# CONFIG_INPUT_MOUSEDEV is not set
694# CONFIG_INPUT_JOYDEV is not set
695# CONFIG_INPUT_TSDEV is not set
696# CONFIG_INPUT_EVDEV is not set
697# CONFIG_INPUT_EVBUG is not set
698
699#
700# Input Device Drivers
701#
702# CONFIG_INPUT_KEYBOARD is not set
703# CONFIG_INPUT_MOUSE is not set
704# CONFIG_INPUT_JOYSTICK is not set
705# CONFIG_INPUT_TOUCHSCREEN is not set
706CONFIG_INPUT_MISC=y
707# CONFIG_INPUT_UINPUT is not set
708# CONFIG_BF53X_PFBUTTONS is not set
709
710#
711# Hardware I/O ports
712#
713# CONFIG_SERIO is not set
714# CONFIG_GAMEPORT is not set
715
716#
717# Character devices
718#
719# CONFIG_AD9960 is not set
720# CONFIG_SPI_ADC_BF533 is not set
721# CONFIG_BF5xx_PFLAGS is not set
722# CONFIG_BF5xx_PPIFCD is not set
723# CONFIG_BF5xx_TIMERS is not set
724# CONFIG_BF5xx_PPI is not set
725# CONFIG_BFIN_SPORT is not set
726# CONFIG_BFIN_TIMER_LATENCY is not set
727# CONFIG_BF5xx_FBDMA is not set
728# CONFIG_VT is not set
729# CONFIG_SERIAL_NONSTANDARD is not set
730
731#
732# Serial drivers
733#
734# CONFIG_SERIAL_8250 is not set
735
736#
737# Non-8250 serial port support
738#
739CONFIG_SERIAL_BFIN=y
740CONFIG_SERIAL_BFIN_CONSOLE=y
741# CONFIG_SERIAL_BFIN_DMA is not set
742CONFIG_SERIAL_BFIN_PIO=y
743# CONFIG_SERIAL_BFIN_UART0 is not set
744CONFIG_SERIAL_BFIN_UART1=y
745# CONFIG_BFIN_UART1_CTSRTS is not set
746# CONFIG_SERIAL_BFIN_UART2 is not set
747# CONFIG_SERIAL_BFIN_UART3 is not set
748CONFIG_SERIAL_CORE=y
749CONFIG_SERIAL_CORE_CONSOLE=y
750# CONFIG_SERIAL_BFIN_SPORT is not set
751CONFIG_UNIX98_PTYS=y
752# CONFIG_LEGACY_PTYS is not set
753
754#
755# CAN, the car bus and industrial fieldbus
756#
757# CONFIG_CAN4LINUX is not set
758
759#
760# IPMI
761#
762# CONFIG_IPMI_HANDLER is not set
763
764#
765# Watchdog Cards
766#
767# CONFIG_WATCHDOG is not set
768CONFIG_HW_RANDOM=y
769# CONFIG_GEN_RTC is not set
770# CONFIG_DTLK is not set
771# CONFIG_R3964 is not set
772# CONFIG_RAW_DRIVER is not set
773
774#
775# TPM devices
776#
777# CONFIG_TCG_TPM is not set
778
779#
780# I2C support
781#
782# CONFIG_I2C is not set
783
784#
785# SPI support
786#
787# CONFIG_SPI is not set
788# CONFIG_SPI_MASTER is not set
789
790#
791# Dallas's 1-wire bus
792#
793# CONFIG_W1 is not set
794
795#
796# Hardware Monitoring support
797#
798CONFIG_HWMON=y
799# CONFIG_HWMON_VID is not set
800# CONFIG_SENSORS_ABITUGURU is not set
801# CONFIG_SENSORS_F71805F is not set
802# CONFIG_SENSORS_PC87427 is not set
803# CONFIG_SENSORS_VT1211 is not set
804# CONFIG_HWMON_DEBUG_CHIP is not set
805
806#
807# Multifunction device drivers
808#
809# CONFIG_MFD_SM501 is not set
810
811#
812# Multimedia devices
813#
814# CONFIG_VIDEO_DEV is not set
815
816#
817# Digital Video Broadcasting Devices
818#
819# CONFIG_DVB is not set
820
821#
822# Graphics support
823#
824# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
825# CONFIG_FB is not set
826
827#
828# Sound
829#
830# CONFIG_SOUND is not set
831
832#
833# HID Devices
834#
835CONFIG_HID=y
836# CONFIG_HID_DEBUG is not set
837
838#
839# USB support
840#
841CONFIG_USB_ARCH_HAS_HCD=y
842# CONFIG_USB_ARCH_HAS_OHCI is not set
843# CONFIG_USB_ARCH_HAS_EHCI is not set
844# CONFIG_USB is not set
845
846#
847# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
848#
849
850#
851# USB Gadget Support
852#
853# CONFIG_USB_GADGET is not set
854
855#
856# MMC/SD Card support
857#
858# CONFIG_MMC is not set
859
860#
861# LED devices
862#
863# CONFIG_NEW_LEDS is not set
864
865#
866# LED drivers
867#
868
869#
870# LED Triggers
871#
872
873#
874# InfiniBand support
875#
876
877#
878# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
879#
880
881#
882# Real Time Clock
883#
884CONFIG_RTC_LIB=y
885CONFIG_RTC_CLASS=y
886CONFIG_RTC_HCTOSYS=y
887CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
888# CONFIG_RTC_DEBUG is not set
889
890#
891# RTC interfaces
892#
893CONFIG_RTC_INTF_SYSFS=y
894CONFIG_RTC_INTF_PROC=y
895CONFIG_RTC_INTF_DEV=y
896# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
897
898#
899# RTC drivers
900#
901# CONFIG_RTC_DRV_DS1553 is not set
902# CONFIG_RTC_DRV_DS1742 is not set
903# CONFIG_RTC_DRV_M48T86 is not set
904# CONFIG_RTC_DRV_TEST is not set
905# CONFIG_RTC_DRV_V3020 is not set
906CONFIG_RTC_DRV_BFIN=y
907
908#
909# DMA Engine support
910#
911# CONFIG_DMA_ENGINE is not set
912
913#
914# DMA Clients
915#
916
917#
918# DMA Devices
919#
920
921#
922# Auxiliary Display support
923#
924
925#
926# Virtualization
927#
928
929#
930# PBX support
931#
932# CONFIG_PBX is not set
933
934#
935# File systems
936#
937CONFIG_EXT2_FS=y
938CONFIG_EXT2_FS_XATTR=y
939# CONFIG_EXT2_FS_POSIX_ACL is not set
940# CONFIG_EXT2_FS_SECURITY is not set
941# CONFIG_EXT3_FS is not set
942# CONFIG_EXT4DEV_FS is not set
943CONFIG_FS_MBCACHE=y
944# CONFIG_REISERFS_FS is not set
945# CONFIG_JFS_FS is not set
946# CONFIG_FS_POSIX_ACL is not set
947# CONFIG_XFS_FS is not set
948# CONFIG_GFS2_FS is not set
949# CONFIG_OCFS2_FS is not set
950# CONFIG_MINIX_FS is not set
951# CONFIG_ROMFS_FS is not set
952CONFIG_INOTIFY=y
953CONFIG_INOTIFY_USER=y
954# CONFIG_QUOTA is not set
955CONFIG_DNOTIFY=y
956# CONFIG_AUTOFS_FS is not set
957# CONFIG_AUTOFS4_FS is not set
958# CONFIG_FUSE_FS is not set
959
960#
961# CD-ROM/DVD Filesystems
962#
963# CONFIG_ISO9660_FS is not set
964# CONFIG_UDF_FS is not set
965
966#
967# DOS/FAT/NT Filesystems
968#
969# CONFIG_MSDOS_FS is not set
970# CONFIG_VFAT_FS is not set
971# CONFIG_NTFS_FS is not set
972
973#
974# Pseudo filesystems
975#
976CONFIG_PROC_FS=y
977CONFIG_PROC_SYSCTL=y
978CONFIG_SYSFS=y
979# CONFIG_TMPFS is not set
980# CONFIG_HUGETLB_PAGE is not set
981CONFIG_RAMFS=y
982# CONFIG_CONFIGFS_FS is not set
983
984#
985# Miscellaneous filesystems
986#
987# CONFIG_ADFS_FS is not set
988# CONFIG_AFFS_FS is not set
989# CONFIG_HFS_FS is not set
990# CONFIG_HFSPLUS_FS is not set
991# CONFIG_BEFS_FS is not set
992# CONFIG_BFS_FS is not set
993# CONFIG_EFS_FS is not set
994# CONFIG_YAFFS_FS is not set
995# CONFIG_JFFS2_FS is not set
996# CONFIG_CRAMFS is not set
997# CONFIG_VXFS_FS is not set
998# CONFIG_HPFS_FS is not set
999# CONFIG_QNX4FS_FS is not set
1000# CONFIG_SYSV_FS is not set
1001# CONFIG_UFS_FS is not set
1002
1003#
1004# Network File Systems
1005#
1006# CONFIG_NFS_FS is not set
1007# CONFIG_NFSD is not set
1008# CONFIG_SMB_FS is not set
1009# CONFIG_CIFS is not set
1010# CONFIG_NCP_FS is not set
1011# CONFIG_CODA_FS is not set
1012# CONFIG_AFS_FS is not set
1013# CONFIG_9P_FS is not set
1014
1015#
1016# Partition Types
1017#
1018# CONFIG_PARTITION_ADVANCED is not set
1019CONFIG_MSDOS_PARTITION=y
1020
1021#
1022# Native Language Support
1023#
1024# CONFIG_NLS is not set
1025
1026#
1027# Distributed Lock Manager
1028#
1029# CONFIG_DLM is not set
1030
1031#
1032# Profiling support
1033#
1034# CONFIG_PROFILING is not set
1035
1036#
1037# Kernel hacking
1038#
1039# CONFIG_PRINTK_TIME is not set
1040CONFIG_ENABLE_MUST_CHECK=y
1041CONFIG_MAGIC_SYSRQ=y
1042# CONFIG_UNUSED_SYMBOLS is not set
1043# CONFIG_DEBUG_FS is not set
1044# CONFIG_HEADERS_CHECK is not set
1045CONFIG_DEBUG_KERNEL=y
1046# CONFIG_DEBUG_SHIRQ is not set
1047CONFIG_LOG_BUF_SHIFT=14
1048CONFIG_DETECT_SOFTLOCKUP=y
1049# CONFIG_SCHEDSTATS is not set
1050# CONFIG_TIMER_STATS is not set
1051# CONFIG_DEBUG_SLAB is not set
1052# CONFIG_DEBUG_RT_MUTEXES is not set
1053# CONFIG_RT_MUTEX_TESTER is not set
1054# CONFIG_DEBUG_SPINLOCK is not set
1055# CONFIG_DEBUG_MUTEXES is not set
1056# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1057# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1058# CONFIG_DEBUG_KOBJECT is not set
1059# CONFIG_DEBUG_BUGVERBOSE is not set
1060CONFIG_DEBUG_INFO=y
1061# CONFIG_DEBUG_VM is not set
1062# CONFIG_DEBUG_LIST is not set
1063CONFIG_FRAME_POINTER=y
1064CONFIG_FORCED_INLINING=y
1065# CONFIG_RCU_TORTURE_TEST is not set
1066# CONFIG_FAULT_INJECTION is not set
1067CONFIG_DEBUG_HWERR=y
1068# CONFIG_DEBUG_ICACHE_CHECK is not set
1069# CONFIG_DEBUG_KERNEL_START is not set
1070# CONFIG_DEBUG_SERIAL_EARLY_INIT is not set
1071CONFIG_DEBUG_HUNT_FOR_ZERO=y
1072# CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE is not set
1073CONFIG_CPLB_INFO=y
1074CONFIG_ACCESS_CHECK=y
1075
1076#
1077# Security options
1078#
1079# CONFIG_KEYS is not set
1080CONFIG_SECURITY=y
1081# CONFIG_SECURITY_NETWORK is not set
1082CONFIG_SECURITY_CAPABILITIES=y
1083
1084#
1085# Cryptographic options
1086#
1087# CONFIG_CRYPTO is not set
1088
1089#
1090# Library routines
1091#
1092CONFIG_BITREVERSE=y
1093# CONFIG_CRC_CCITT is not set
1094# CONFIG_CRC16 is not set
1095CONFIG_CRC32=y
1096# CONFIG_LIBCRC32C is not set
1097CONFIG_ZLIB_INFLATE=y
1098CONFIG_PLIST=y
1099CONFIG_HAS_IOMEM=y
1100CONFIG_HAS_IOPORT=y
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index f3b7d2f9d49c..f429ebc3a961 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -6,9 +6,12 @@ extra-y := init_task.o vmlinux.lds
6 6
7obj-y := \ 7obj-y := \
8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \ 8 entry.o process.o bfin_ksyms.o ptrace.o setup.o signal.o \
9 sys_bfin.o time.o traps.o irqchip.o dma-mapping.o bfin_gpio.o \ 9 sys_bfin.o time.o traps.o irqchip.o dma-mapping.o flat.o \
10 flat.o 10 fixed_code.o cplbinit.o cacheinit.o
11 11
12obj-$(CONFIG_BF53x) += bfin_gpio.o
13obj-$(CONFIG_BF561) += bfin_gpio.o
12obj-$(CONFIG_MODULES) += module.o 14obj-$(CONFIG_MODULES) += module.o
13obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o 15obj-$(CONFIG_BFIN_DMA_5XX) += bfin_dma_5xx.o
14obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o 16obj-$(CONFIG_DUAL_CORE_TEST_MODULE) += dualcore_test.o
17obj-$(CONFIG_KGDB) += kgdb.o
diff --git a/arch/blackfin/kernel/asm-offsets.c b/arch/blackfin/kernel/asm-offsets.c
index e455f4504509..b56b2741cdea 100644
--- a/arch/blackfin/kernel/asm-offsets.c
+++ b/arch/blackfin/kernel/asm-offsets.c
@@ -32,11 +32,10 @@
32#include <linux/kernel_stat.h> 32#include <linux/kernel_stat.h>
33#include <linux/ptrace.h> 33#include <linux/ptrace.h>
34#include <linux/hardirq.h> 34#include <linux/hardirq.h>
35#include <asm/irq.h> 35#include <linux/irq.h>
36#include <asm/thread_info.h> 36#include <linux/thread_info.h>
37 37
38#define DEFINE(sym, val) \ 38#define DEFINE(sym, val) asm volatile("\n->" #sym " %0 " #val : : "i" (val))
39 asm volatile("\n->" #sym " %0 " #val : : "i" (val))
40 39
41int main(void) 40int main(void)
42{ 41{
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 069a896a8f26..7cf02f02a1db 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -34,6 +34,7 @@
34#include <linux/kernel.h> 34#include <linux/kernel.h>
35#include <linux/param.h> 35#include <linux/param.h>
36 36
37#include <asm/blackfin.h>
37#include <asm/dma.h> 38#include <asm/dma.h>
38#include <asm/cacheflush.h> 39#include <asm/cacheflush.h>
39 40
@@ -45,67 +46,6 @@
45***************************************************************************/ 46***************************************************************************/
46 47
47static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL]; 48static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
48#if defined (CONFIG_BF561)
49static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
50 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
51 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
52 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
53 (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
54 (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
55 (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
56 (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
57 (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
58 (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
59 (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
60 (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
61 (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
62 (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
63 (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
64 (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
65 (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
66 (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
67 (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
68 (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
69 (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
70 (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
71 (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
72 (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
73 (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
74 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
75 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
76 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
77 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
78 (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
79 (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
80 (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
81 (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
82 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
83 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
84 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
85 (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
86};
87#else
88static struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
89 (struct dma_register *) DMA0_NEXT_DESC_PTR,
90 (struct dma_register *) DMA1_NEXT_DESC_PTR,
91 (struct dma_register *) DMA2_NEXT_DESC_PTR,
92 (struct dma_register *) DMA3_NEXT_DESC_PTR,
93 (struct dma_register *) DMA4_NEXT_DESC_PTR,
94 (struct dma_register *) DMA5_NEXT_DESC_PTR,
95 (struct dma_register *) DMA6_NEXT_DESC_PTR,
96 (struct dma_register *) DMA7_NEXT_DESC_PTR,
97#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
98 (struct dma_register *) DMA8_NEXT_DESC_PTR,
99 (struct dma_register *) DMA9_NEXT_DESC_PTR,
100 (struct dma_register *) DMA10_NEXT_DESC_PTR,
101 (struct dma_register *) DMA11_NEXT_DESC_PTR,
102#endif
103 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
104 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
105 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
106 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
107};
108#endif
109 49
110/*------------------------------------------------------------------------------ 50/*------------------------------------------------------------------------------
111 * Set the Buffer Clear bit in the Configuration register of specific DMA 51 * Set the Buffer Clear bit in the Configuration register of specific DMA
@@ -138,149 +78,6 @@ static int __init blackfin_dma_init(void)
138 78
139arch_initcall(blackfin_dma_init); 79arch_initcall(blackfin_dma_init);
140 80
141/*
142 * Form the channel find the irq number for that channel.
143 */
144#if !defined(CONFIG_BF561)
145
146static int bf533_channel2irq(unsigned int channel)
147{
148 int ret_irq = -1;
149
150 switch (channel) {
151 case CH_PPI:
152 ret_irq = IRQ_PPI;
153 break;
154
155#if (defined(CONFIG_BF537) || defined(CONFIG_BF534) || defined(CONFIG_BF536))
156 case CH_EMAC_RX:
157 ret_irq = IRQ_MAC_RX;
158 break;
159
160 case CH_EMAC_TX:
161 ret_irq = IRQ_MAC_TX;
162 break;
163
164 case CH_UART1_RX:
165 ret_irq = IRQ_UART1_RX;
166 break;
167
168 case CH_UART1_TX:
169 ret_irq = IRQ_UART1_TX;
170 break;
171#endif
172
173 case CH_SPORT0_RX:
174 ret_irq = IRQ_SPORT0_RX;
175 break;
176
177 case CH_SPORT0_TX:
178 ret_irq = IRQ_SPORT0_TX;
179 break;
180
181 case CH_SPORT1_RX:
182 ret_irq = IRQ_SPORT1_RX;
183 break;
184
185 case CH_SPORT1_TX:
186 ret_irq = IRQ_SPORT1_TX;
187 break;
188
189 case CH_SPI:
190 ret_irq = IRQ_SPI;
191 break;
192
193 case CH_UART_RX:
194 ret_irq = IRQ_UART_RX;
195 break;
196
197 case CH_UART_TX:
198 ret_irq = IRQ_UART_TX;
199 break;
200
201 case CH_MEM_STREAM0_SRC:
202 case CH_MEM_STREAM0_DEST:
203 ret_irq = IRQ_MEM_DMA0;
204 break;
205
206 case CH_MEM_STREAM1_SRC:
207 case CH_MEM_STREAM1_DEST:
208 ret_irq = IRQ_MEM_DMA1;
209 break;
210 }
211 return ret_irq;
212}
213
214# define channel2irq(channel) bf533_channel2irq(channel)
215
216#else
217
218static int bf561_channel2irq(unsigned int channel)
219{
220 int ret_irq = -1;
221
222 switch (channel) {
223 case CH_PPI0:
224 ret_irq = IRQ_PPI0;
225 break;
226 case CH_PPI1:
227 ret_irq = IRQ_PPI1;
228 break;
229 case CH_SPORT0_RX:
230 ret_irq = IRQ_SPORT0_RX;
231 break;
232 case CH_SPORT0_TX:
233 ret_irq = IRQ_SPORT0_TX;
234 break;
235 case CH_SPORT1_RX:
236 ret_irq = IRQ_SPORT1_RX;
237 break;
238 case CH_SPORT1_TX:
239 ret_irq = IRQ_SPORT1_TX;
240 break;
241 case CH_SPI:
242 ret_irq = IRQ_SPI;
243 break;
244 case CH_UART_RX:
245 ret_irq = IRQ_UART_RX;
246 break;
247 case CH_UART_TX:
248 ret_irq = IRQ_UART_TX;
249 break;
250
251 case CH_MEM_STREAM0_SRC:
252 case CH_MEM_STREAM0_DEST:
253 ret_irq = IRQ_MEM_DMA0;
254 break;
255 case CH_MEM_STREAM1_SRC:
256 case CH_MEM_STREAM1_DEST:
257 ret_irq = IRQ_MEM_DMA1;
258 break;
259 case CH_MEM_STREAM2_SRC:
260 case CH_MEM_STREAM2_DEST:
261 ret_irq = IRQ_MEM_DMA2;
262 break;
263 case CH_MEM_STREAM3_SRC:
264 case CH_MEM_STREAM3_DEST:
265 ret_irq = IRQ_MEM_DMA3;
266 break;
267
268 case CH_IMEM_STREAM0_SRC:
269 case CH_IMEM_STREAM0_DEST:
270 ret_irq = IRQ_IMEM_DMA0;
271 break;
272 case CH_IMEM_STREAM1_SRC:
273 case CH_IMEM_STREAM1_DEST:
274 ret_irq = IRQ_IMEM_DMA1;
275 break;
276 }
277 return ret_irq;
278}
279
280# define channel2irq(channel) bf561_channel2irq(channel)
281
282#endif
283
284/*------------------------------------------------------------------------------ 81/*------------------------------------------------------------------------------
285 * Request the specific DMA channel from the system. 82 * Request the specific DMA channel from the system.
286 *-----------------------------------------------------------------------------*/ 83 *-----------------------------------------------------------------------------*/
@@ -535,7 +332,7 @@ set_bfin_dma_config(char direction, char flow_mode,
535} 332}
536EXPORT_SYMBOL(set_bfin_dma_config); 333EXPORT_SYMBOL(set_bfin_dma_config);
537 334
538void set_dma_sg(unsigned int channel, struct dmasg * sg, int nr_sg) 335void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg)
539{ 336{
540 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE 337 BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
541 && channel < MAX_BLACKFIN_DMA_CHANNEL)); 338 && channel < MAX_BLACKFIN_DMA_CHANNEL));
@@ -604,7 +401,7 @@ static void *__dma_memcpy(void *dest, const void *src, size_t size)
604 401
605 if (size <= 0) 402 if (size <= 0)
606 return NULL; 403 return NULL;
607 404
608 local_irq_save(flags); 405 local_irq_save(flags);
609 406
610 if ((unsigned long)src < memory_end) 407 if ((unsigned long)src < memory_end)
@@ -748,7 +545,6 @@ void *dma_memcpy(void *dest, const void *src, size_t size)
748 addr = __dma_memcpy(dest+bulk, src+bulk, rest); 545 addr = __dma_memcpy(dest+bulk, src+bulk, rest);
749 return addr; 546 return addr;
750} 547}
751
752EXPORT_SYMBOL(dma_memcpy); 548EXPORT_SYMBOL(dma_memcpy);
753 549
754void *safe_dma_memcpy(void *dest, const void *src, size_t size) 550void *safe_dma_memcpy(void *dest, const void *src, size_t size)
@@ -761,14 +557,13 @@ EXPORT_SYMBOL(safe_dma_memcpy);
761 557
762void dma_outsb(void __iomem *addr, const void *buf, unsigned short len) 558void dma_outsb(void __iomem *addr, const void *buf, unsigned short len)
763{ 559{
764
765 unsigned long flags; 560 unsigned long flags;
766 561
767 local_irq_save(flags); 562 local_irq_save(flags);
768
769 blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
770 563
771 bfin_write_MDMA_D0_START_ADDR(addr); 564 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
565
566 bfin_write_MDMA_D0_START_ADDR(addr);
772 bfin_write_MDMA_D0_X_COUNT(len); 567 bfin_write_MDMA_D0_X_COUNT(len);
773 bfin_write_MDMA_D0_X_MODIFY(0); 568 bfin_write_MDMA_D0_X_MODIFY(0);
774 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 569 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -796,9 +591,9 @@ EXPORT_SYMBOL(dma_outsb);
796void dma_insb(const void __iomem *addr, void *buf, unsigned short len) 591void dma_insb(const void __iomem *addr, void *buf, unsigned short len)
797{ 592{
798 unsigned long flags; 593 unsigned long flags;
799 594
800 local_irq_save(flags); 595 local_irq_save(flags);
801 bfin_write_MDMA_D0_START_ADDR(buf); 596 bfin_write_MDMA_D0_START_ADDR(buf);
802 bfin_write_MDMA_D0_X_COUNT(len); 597 bfin_write_MDMA_D0_X_COUNT(len);
803 bfin_write_MDMA_D0_X_MODIFY(1); 598 bfin_write_MDMA_D0_X_MODIFY(1);
804 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 599 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -827,12 +622,12 @@ EXPORT_SYMBOL(dma_insb);
827void dma_outsw(void __iomem *addr, const void *buf, unsigned short len) 622void dma_outsw(void __iomem *addr, const void *buf, unsigned short len)
828{ 623{
829 unsigned long flags; 624 unsigned long flags;
830 625
831 local_irq_save(flags); 626 local_irq_save(flags);
832
833 blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
834 627
835 bfin_write_MDMA_D0_START_ADDR(addr); 628 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
629
630 bfin_write_MDMA_D0_START_ADDR(addr);
836 bfin_write_MDMA_D0_X_COUNT(len); 631 bfin_write_MDMA_D0_X_COUNT(len);
837 bfin_write_MDMA_D0_X_MODIFY(0); 632 bfin_write_MDMA_D0_X_MODIFY(0);
838 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 633 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -859,10 +654,10 @@ EXPORT_SYMBOL(dma_outsw);
859void dma_insw(const void __iomem *addr, void *buf, unsigned short len) 654void dma_insw(const void __iomem *addr, void *buf, unsigned short len)
860{ 655{
861 unsigned long flags; 656 unsigned long flags;
862 657
863 local_irq_save(flags); 658 local_irq_save(flags);
864 659
865 bfin_write_MDMA_D0_START_ADDR(buf); 660 bfin_write_MDMA_D0_START_ADDR(buf);
866 bfin_write_MDMA_D0_X_COUNT(len); 661 bfin_write_MDMA_D0_X_COUNT(len);
867 bfin_write_MDMA_D0_X_MODIFY(2); 662 bfin_write_MDMA_D0_X_MODIFY(2);
868 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 663 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -891,12 +686,12 @@ EXPORT_SYMBOL(dma_insw);
891void dma_outsl(void __iomem *addr, const void *buf, unsigned short len) 686void dma_outsl(void __iomem *addr, const void *buf, unsigned short len)
892{ 687{
893 unsigned long flags; 688 unsigned long flags;
894 689
895 local_irq_save(flags); 690 local_irq_save(flags);
896
897 blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
898 691
899 bfin_write_MDMA_D0_START_ADDR(addr); 692 blackfin_dcache_flush_range((unsigned int)buf, (unsigned int)(buf) + len);
693
694 bfin_write_MDMA_D0_START_ADDR(addr);
900 bfin_write_MDMA_D0_X_COUNT(len); 695 bfin_write_MDMA_D0_X_COUNT(len);
901 bfin_write_MDMA_D0_X_MODIFY(0); 696 bfin_write_MDMA_D0_X_MODIFY(0);
902 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 697 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
@@ -923,10 +718,10 @@ EXPORT_SYMBOL(dma_outsl);
923void dma_insl(const void __iomem *addr, void *buf, unsigned short len) 718void dma_insl(const void __iomem *addr, void *buf, unsigned short len)
924{ 719{
925 unsigned long flags; 720 unsigned long flags;
926 721
927 local_irq_save(flags); 722 local_irq_save(flags);
928 723
929 bfin_write_MDMA_D0_START_ADDR(buf); 724 bfin_write_MDMA_D0_START_ADDR(buf);
930 bfin_write_MDMA_D0_X_COUNT(len); 725 bfin_write_MDMA_D0_X_COUNT(len);
931 bfin_write_MDMA_D0_X_MODIFY(4); 726 bfin_write_MDMA_D0_X_MODIFY(4);
932 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); 727 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index bb1f4fb2467c..bafcfa52142b 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -162,7 +162,7 @@ static void port_setup(unsigned short gpio, unsigned short usage)
162 162
163static void default_gpio(unsigned short gpio) 163static void default_gpio(unsigned short gpio)
164{ 164{
165 unsigned short bank,bitmask; 165 unsigned short bank, bitmask;
166 166
167 bank = gpio_bank(gpio); 167 bank = gpio_bank(gpio);
168 bitmask = gpio_bit(gpio); 168 bitmask = gpio_bit(gpio);
@@ -183,7 +183,7 @@ static int __init bfin_gpio_init(void)
183 183
184 printk(KERN_INFO "Blackfin GPIO Controller\n"); 184 printk(KERN_INFO "Blackfin GPIO Controller\n");
185 185
186 for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) 186 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE)
187 reserved_map[gpio_bank(i)] = 0; 187 reserved_map[gpio_bank(i)] = 0;
188 188
189#if defined(BF537_FAMILY) && (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 189#if defined(BF537_FAMILY) && (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
@@ -478,7 +478,7 @@ u32 gpio_pm_setup(void)
478 u32 sic_iwr = 0; 478 u32 sic_iwr = 0;
479 u16 bank, mask, i, gpio; 479 u16 bank, mask, i, gpio;
480 480
481 for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) { 481 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
482 mask = wakeup_map[gpio_bank(i)]; 482 mask = wakeup_map[gpio_bank(i)];
483 bank = gpio_bank(i); 483 bank = gpio_bank(i);
484 484
@@ -522,12 +522,11 @@ u32 gpio_pm_setup(void)
522 return IWR_ENABLE_ALL; 522 return IWR_ENABLE_ALL;
523} 523}
524 524
525
526void gpio_pm_restore(void) 525void gpio_pm_restore(void)
527{ 526{
528 u16 bank, mask, i; 527 u16 bank, mask, i;
529 528
530 for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=GPIO_BANKSIZE) { 529 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
531 mask = wakeup_map[gpio_bank(i)]; 530 mask = wakeup_map[gpio_bank(i)];
532 bank = gpio_bank(i); 531 bank = gpio_bank(i);
533 532
@@ -591,7 +590,6 @@ int gpio_request(unsigned short gpio, const char *label)
591} 590}
592EXPORT_SYMBOL(gpio_request); 591EXPORT_SYMBOL(gpio_request);
593 592
594
595void gpio_free(unsigned short gpio) 593void gpio_free(unsigned short gpio)
596{ 594{
597 unsigned long flags; 595 unsigned long flags;
@@ -616,7 +614,6 @@ void gpio_free(unsigned short gpio)
616} 614}
617EXPORT_SYMBOL(gpio_free); 615EXPORT_SYMBOL(gpio_free);
618 616
619
620void gpio_direction_input(unsigned short gpio) 617void gpio_direction_input(unsigned short gpio)
621{ 618{
622 unsigned long flags; 619 unsigned long flags;
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index f64ecb638fab..70455949cfd2 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -28,10 +28,11 @@
28 */ 28 */
29 29
30#include <linux/module.h> 30#include <linux/module.h>
31#include <asm/irq.h> 31#include <linux/irq.h>
32#include <linux/uaccess.h>
33
32#include <asm/checksum.h> 34#include <asm/checksum.h>
33#include <asm/cacheflush.h> 35#include <asm/cacheflush.h>
34#include <asm/uaccess.h>
35 36
36/* platform dependent support */ 37/* platform dependent support */
37 38
diff --git a/arch/blackfin/kernel/cacheinit.c b/arch/blackfin/kernel/cacheinit.c
new file mode 100644
index 000000000000..4d41a40e8133
--- /dev/null
+++ b/arch/blackfin/kernel/cacheinit.c
@@ -0,0 +1,66 @@
1/*
2 * Copyright 2004-2007 Analog Devices Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see the file COPYING, or write
16 * to the Free Software Foundation, Inc.,
17 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <linux/cpu.h>
21
22#include <asm/cacheflush.h>
23#include <asm/blackfin.h>
24#include <asm/cplbinit.h>
25
26#if defined(CONFIG_BLKFIN_CACHE)
27void bfin_icache_init(void)
28{
29 unsigned long *table = icplb_table;
30 unsigned long ctrl;
31 int i;
32
33 for (i = 0; i < MAX_CPLBS; i++) {
34 unsigned long addr = *table++;
35 unsigned long data = *table++;
36 if (addr == (unsigned long)-1)
37 break;
38 bfin_write32(ICPLB_ADDR0 + i * 4, addr);
39 bfin_write32(ICPLB_DATA0 + i * 4, data);
40 }
41 ctrl = bfin_read_IMEM_CONTROL();
42 ctrl |= IMC | ENICPLB;
43 bfin_write_IMEM_CONTROL(ctrl);
44}
45#endif
46
47#if defined(CONFIG_BLKFIN_DCACHE)
48void bfin_dcache_init(void)
49{
50 unsigned long *table = dcplb_table;
51 unsigned long ctrl;
52 int i;
53
54 for (i = 0; i < MAX_CPLBS; i++) {
55 unsigned long addr = *table++;
56 unsigned long data = *table++;
57 if (addr == (unsigned long)-1)
58 break;
59 bfin_write32(DCPLB_ADDR0 + i * 4, addr);
60 bfin_write32(DCPLB_DATA0 + i * 4, data);
61 }
62 ctrl = bfin_read_DMEM_CONTROL();
63 ctrl |= DMEM_CNTR;
64 bfin_write_DMEM_CONTROL(ctrl);
65}
66#endif
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c
new file mode 100644
index 000000000000..bbdb403fcb55
--- /dev/null
+++ b/arch/blackfin/kernel/cplbinit.c
@@ -0,0 +1,433 @@
1/*
2 * Blackfin CPLB initialization
3 *
4 * Copyright 2004-2007 Analog Devices Inc.
5 *
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23#include <linux/module.h>
24
25#include <asm/blackfin.h>
26#include <asm/cplbinit.h>
27
28u_long icplb_table[MAX_CPLBS+1];
29u_long dcplb_table[MAX_CPLBS+1];
30
31#ifdef CONFIG_CPLB_SWITCH_TAB_L1
32u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
33u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
34
35#ifdef CONFIG_CPLB_INFO
36u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
37u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
38#endif /* CONFIG_CPLB_INFO */
39
40#else
41
42u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
43u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
44
45#ifdef CONFIG_CPLB_INFO
46u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
47u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
48#endif /* CONFIG_CPLB_INFO */
49
50#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
51
52struct s_cplb {
53 struct cplb_tab init_i;
54 struct cplb_tab init_d;
55 struct cplb_tab switch_i;
56 struct cplb_tab switch_d;
57};
58
59#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
60static struct cplb_desc cplb_data[] = {
61 {
62 .start = 0,
63 .end = SIZE_1K,
64 .psize = SIZE_1K,
65 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
66 .i_conf = SDRAM_OOPS,
67 .d_conf = SDRAM_OOPS,
68#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
69 .valid = 1,
70#else
71 .valid = 0,
72#endif
73 .name = "ZERO Pointer Saveguard",
74 },
75 {
76 .start = L1_CODE_START,
77 .end = L1_CODE_START + L1_CODE_LENGTH,
78 .psize = SIZE_4M,
79 .attr = INITIAL_T | SWITCH_T | I_CPLB,
80 .i_conf = L1_IMEMORY,
81 .d_conf = 0,
82 .valid = 1,
83 .name = "L1 I-Memory",
84 },
85 {
86 .start = L1_DATA_A_START,
87 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
88 .psize = SIZE_4M,
89 .attr = INITIAL_T | SWITCH_T | D_CPLB,
90 .i_conf = 0,
91 .d_conf = L1_DMEMORY,
92#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
93 .valid = 1,
94#else
95 .valid = 0,
96#endif
97 .name = "L1 D-Memory",
98 },
99 {
100 .start = 0,
101 .end = 0, /* dynamic */
102 .psize = 0,
103 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
104 .i_conf = SDRAM_IGENERIC,
105 .d_conf = SDRAM_DGENERIC,
106 .valid = 1,
107 .name = "SDRAM Kernel",
108 },
109 {
110 .start = 0, /* dynamic */
111 .end = 0, /* dynamic */
112 .psize = 0,
113 .attr = INITIAL_T | SWITCH_T | D_CPLB,
114 .i_conf = SDRAM_IGENERIC,
115 .d_conf = SDRAM_DNON_CHBL,
116 .valid = 1,
117 .name = "SDRAM RAM MTD",
118 },
119 {
120 .start = 0, /* dynamic */
121 .end = 0, /* dynamic */
122 .psize = SIZE_1M,
123 .attr = INITIAL_T | SWITCH_T | D_CPLB,
124 .d_conf = SDRAM_DNON_CHBL,
125 .valid = 1,
126 .name = "SDRAM Uncached DMA ZONE",
127 },
128 {
129 .start = 0, /* dynamic */
130 .end = 0, /* dynamic */
131 .psize = 0,
132 .attr = SWITCH_T | D_CPLB,
133 .i_conf = 0, /* dynamic */
134 .d_conf = 0, /* dynamic */
135 .valid = 1,
136 .name = "SDRAM Reserved Memory",
137 },
138 {
139 .start = ASYNC_BANK0_BASE,
140 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
141 .psize = 0,
142 .attr = SWITCH_T | D_CPLB,
143 .d_conf = SDRAM_EBIU,
144 .valid = 1,
145 .name = "ASYNC Memory",
146 },
147 {
148#if defined(CONFIG_BF561)
149 .start = L2_SRAM,
150 .end = L2_SRAM_END,
151 .psize = SIZE_1M,
152 .attr = SWITCH_T | D_CPLB,
153 .i_conf = L2_MEMORY,
154 .d_conf = L2_MEMORY,
155 .valid = 1,
156#else
157 .valid = 0,
158#endif
159 .name = "L2 Memory",
160 }
161};
162
163static u16 __init lock_kernel_check(u32 start, u32 end)
164{
165 if ((start <= (u32) _stext && end >= (u32) _end)
166 || (start >= (u32) _stext && end <= (u32) _end))
167 return IN_KERNEL;
168 return 0;
169}
170
171static unsigned short __init
172fill_cplbtab(struct cplb_tab *table,
173 unsigned long start, unsigned long end,
174 unsigned long block_size, unsigned long cplb_data)
175{
176 int i;
177
178 switch (block_size) {
179 case SIZE_4M:
180 i = 3;
181 break;
182 case SIZE_1M:
183 i = 2;
184 break;
185 case SIZE_4K:
186 i = 1;
187 break;
188 case SIZE_1K:
189 default:
190 i = 0;
191 break;
192 }
193
194 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
195
196 while ((start < end) && (table->pos < table->size)) {
197
198 table->tab[table->pos++] = start;
199
200 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
201 table->tab[table->pos++] =
202 cplb_data | CPLB_LOCK | CPLB_DIRTY;
203 else
204 table->tab[table->pos++] = cplb_data;
205
206 start += block_size;
207 }
208 return 0;
209}
210
211static unsigned short __init
212close_cplbtab(struct cplb_tab *table)
213{
214
215 while (table->pos < table->size) {
216
217 table->tab[table->pos++] = 0;
218 table->tab[table->pos++] = 0; /* !CPLB_VALID */
219 }
220 return 0;
221}
222
223/* helper function */
224static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
225{
226 if (cplb_data[i].psize) {
227 fill_cplbtab(t,
228 cplb_data[i].start,
229 cplb_data[i].end,
230 cplb_data[i].psize,
231 cplb_data[i].i_conf);
232 } else {
233#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
234 if (i == SDRAM_KERN) {
235 fill_cplbtab(t,
236 cplb_data[i].start,
237 cplb_data[i].end,
238 SIZE_4M,
239 cplb_data[i].i_conf);
240 } else
241#endif
242 {
243 fill_cplbtab(t,
244 cplb_data[i].start,
245 a_start,
246 SIZE_1M,
247 cplb_data[i].i_conf);
248 fill_cplbtab(t,
249 a_start,
250 a_end,
251 SIZE_4M,
252 cplb_data[i].i_conf);
253 fill_cplbtab(t, a_end,
254 cplb_data[i].end,
255 SIZE_1M,
256 cplb_data[i].i_conf);
257 }
258 }
259}
260
261static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
262{
263 if (cplb_data[i].psize) {
264 fill_cplbtab(t,
265 cplb_data[i].start,
266 cplb_data[i].end,
267 cplb_data[i].psize,
268 cplb_data[i].d_conf);
269 } else {
270 fill_cplbtab(t,
271 cplb_data[i].start,
272 a_start, SIZE_1M,
273 cplb_data[i].d_conf);
274 fill_cplbtab(t, a_start,
275 a_end, SIZE_4M,
276 cplb_data[i].d_conf);
277 fill_cplbtab(t, a_end,
278 cplb_data[i].end,
279 SIZE_1M,
280 cplb_data[i].d_conf);
281 }
282}
283
284void __init generate_cpl_tables(void)
285{
286
287 u16 i, j, process;
288 u32 a_start, a_end, as, ae, as_1m;
289
290 struct cplb_tab *t_i = NULL;
291 struct cplb_tab *t_d = NULL;
292 struct s_cplb cplb;
293
294 cplb.init_i.size = MAX_CPLBS;
295 cplb.init_d.size = MAX_CPLBS;
296 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
297 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
298
299 cplb.init_i.pos = 0;
300 cplb.init_d.pos = 0;
301 cplb.switch_i.pos = 0;
302 cplb.switch_d.pos = 0;
303
304 cplb.init_i.tab = icplb_table;
305 cplb.init_d.tab = dcplb_table;
306 cplb.switch_i.tab = ipdt_table;
307 cplb.switch_d.tab = dpdt_table;
308
309 cplb_data[SDRAM_KERN].end = memory_end;
310
311#ifdef CONFIG_MTD_UCLINUX
312 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
313 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
314 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
315# if defined(CONFIG_ROMFS_FS)
316 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
317
318 /*
319 * The ROMFS_FS size is often not multiple of 1MB.
320 * This can cause multiple CPLB sets covering the same memory area.
321 * This will then cause multiple CPLB hit exceptions.
322 * Workaround: We ensure a contiguous memory area by extending the kernel
323 * memory section over the mtd section.
324 * For ROMFS_FS memory must be covered with ICPLBs anyways.
325 * So there is no difference between kernel and mtd memory setup.
326 */
327
328 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
329 cplb_data[SDRAM_RAM_MTD].valid = 0;
330
331# endif
332#else
333 cplb_data[SDRAM_RAM_MTD].valid = 0;
334#endif
335
336 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
337 cplb_data[SDRAM_DMAZ].end = _ramend;
338
339 cplb_data[RES_MEM].start = _ramend;
340 cplb_data[RES_MEM].end = physical_mem_end;
341
342 if (reserved_mem_dcache_on)
343 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
344 else
345 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
346
347 if (reserved_mem_icache_on)
348 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
349 else
350 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
351
352 for (i = ZERO_P; i <= L2_MEM; i++) {
353 if (!cplb_data[i].valid)
354 continue;
355
356 as_1m = cplb_data[i].start % SIZE_1M;
357
358 /* We need to make sure all sections are properly 1M aligned
359 * However between Kernel Memory and the Kernel mtd section, depending on the
360 * rootfs size, there can be overlapping memory areas.
361 */
362
363 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
364#ifdef CONFIG_MTD_UCLINUX
365 if (i == SDRAM_RAM_MTD) {
366 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
367 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
368 else
369 cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
370 } else
371#endif
372 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
373 cplb_data[i].name, cplb_data[i].start);
374 }
375
376 as = cplb_data[i].start % SIZE_4M;
377 ae = cplb_data[i].end % SIZE_4M;
378
379 if (as)
380 a_start = cplb_data[i].start + (SIZE_4M - (as));
381 else
382 a_start = cplb_data[i].start;
383
384 a_end = cplb_data[i].end - ae;
385
386 for (j = INITIAL_T; j <= SWITCH_T; j++) {
387
388 switch (j) {
389 case INITIAL_T:
390 if (cplb_data[i].attr & INITIAL_T) {
391 t_i = &cplb.init_i;
392 t_d = &cplb.init_d;
393 process = 1;
394 } else
395 process = 0;
396 break;
397 case SWITCH_T:
398 if (cplb_data[i].attr & SWITCH_T) {
399 t_i = &cplb.switch_i;
400 t_d = &cplb.switch_d;
401 process = 1;
402 } else
403 process = 0;
404 break;
405 default:
406 process = 0;
407 break;
408 }
409
410 if (!process)
411 continue;
412 if (cplb_data[i].attr & I_CPLB)
413 __fill_code_cplbtab(t_i, i, a_start, a_end);
414
415 if (cplb_data[i].attr & D_CPLB)
416 __fill_data_cplbtab(t_d, i, a_start, a_end);
417 }
418 }
419
420/* close tables */
421
422 close_cplbtab(&cplb.init_i);
423 close_cplbtab(&cplb.init_d);
424
425 cplb.init_i.tab[cplb.init_i.pos] = -1;
426 cplb.init_d.tab[cplb.init_d.pos] = -1;
427 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
428 cplb.switch_d.tab[cplb.switch_d.pos] = -1;
429
430}
431
432#endif
433
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
index 539eb24e062f..ea48d5b13f11 100644
--- a/arch/blackfin/kernel/dma-mapping.c
+++ b/arch/blackfin/kernel/dma-mapping.c
@@ -34,8 +34,8 @@
34#include <linux/spinlock.h> 34#include <linux/spinlock.h>
35#include <linux/device.h> 35#include <linux/device.h>
36#include <linux/dma-mapping.h> 36#include <linux/dma-mapping.h>
37#include <linux/io.h>
37#include <asm/cacheflush.h> 38#include <asm/cacheflush.h>
38#include <asm/io.h>
39#include <asm/bfin-global.h> 39#include <asm/bfin-global.h>
40 40
41static spinlock_t dma_page_lock; 41static spinlock_t dma_page_lock;
@@ -159,10 +159,13 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
159 159
160 BUG_ON(direction == DMA_NONE); 160 BUG_ON(direction == DMA_NONE);
161 161
162 for (i = 0; i < nents; i++) 162 for (i = 0; i < nents; i++, sg++) {
163 invalidate_dcache_range(sg_dma_address(&sg[i]), 163 sg->dma_address = page_address(sg->page) + sg->offset;
164 sg_dma_address(&sg[i]) + 164
165 sg_dma_len(&sg[i])); 165 invalidate_dcache_range(sg_dma_address(sg),
166 sg_dma_address(sg) +
167 sg_dma_len(sg));
168 }
166 169
167 return nents; 170 return nents;
168} 171}
diff --git a/arch/blackfin/kernel/dualcore_test.c b/arch/blackfin/kernel/dualcore_test.c
index 8b89c99f9dfa..0fcba74840b7 100644
--- a/arch/blackfin/kernel/dualcore_test.c
+++ b/arch/blackfin/kernel/dualcore_test.c
@@ -30,19 +30,19 @@
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/module.h> 31#include <linux/module.h>
32 32
33static int *testarg = (int*)0xfeb00000; 33static int *testarg = (int *)0xfeb00000;
34 34
35static int test_init(void) 35static int test_init(void)
36{ 36{
37 *testarg = 1; 37 *testarg = 1;
38 printk("Dual core test module inserted: set testarg = [%d]\n @ [%p]\n", 38 printk(KERN_INFO "Dual core test module inserted: set testarg = [%d]\n @ [%p]\n",
39 *testarg, testarg); 39 *testarg, testarg);
40 return 0; 40 return 0;
41} 41}
42 42
43static void test_exit(void) 43static void test_exit(void)
44{ 44{
45 printk("Dual core test module removed: testarg = [%d]\n", *testarg); 45 printk(KERN_INFO "Dual core test module removed: testarg = [%d]\n", *testarg);
46} 46}
47 47
48module_init(test_init); 48module_init(test_init);
diff --git a/arch/blackfin/kernel/fixed_code.S b/arch/blackfin/kernel/fixed_code.S
new file mode 100644
index 000000000000..d8b1ebc70996
--- /dev/null
+++ b/arch/blackfin/kernel/fixed_code.S
@@ -0,0 +1,132 @@
1/*
2 * This file contains sequences of code that will be copied to a
3 * fixed location, defined in <asm/atomic_seq.h>. The interrupt
4 * handlers ensure that these sequences appear to be atomic when
5 * executed from userspace.
6 * These are aligned to 16 bytes, so that we have some space to replace
7 * these sequences with something else (e.g. kernel traps if we ever do
8 * BF561 SMP).
9 */
10#include <linux/linkage.h>
11#include <linux/unistd.h>
12#include <asm/entry.h>
13
14.text
15ENTRY(_fixed_code_start)
16
17.align 16
18ENTRY(_sigreturn_stub)
19 P0 = __NR_rt_sigreturn;
20 EXCPT 0;
21 /* Speculative execution paranoia. */
220: JUMP.S 0b;
23ENDPROC (_sigreturn_stub)
24
25.align 16
26 /*
27 * Atomic swap, 8 bit.
28 * Inputs: P0: memory address to use
29 * R1: value to store
30 * Output: R0: old contents of the memory address, zero extended.
31 */
32ENTRY(_atomic_xchg32)
33 R0 = [P0];
34 [P0] = R1;
35 rts;
36ENDPROC (_atomic_xchg32)
37
38.align 16
39 /*
40 * Compare and swap, 32 bit.
41 * Inputs: P0: memory address to use
42 * R1: compare value
43 * R2: new value to store
44 * The new value is stored if the contents of the memory
45 * address is equal to the compare value.
46 * Output: R0: old contents of the memory address.
47 */
48ENTRY(_atomic_cas32)
49 R0 = [P0];
50 CC = R0 == R1;
51 IF !CC JUMP 1f;
52 [P0] = R2;
531:
54 rts;
55ENDPROC (_atomic_cas32)
56
57.align 16
58 /*
59 * Atomic add, 32 bit.
60 * Inputs: P0: memory address to use
61 * R0: value to add
62 * Outputs: R0: new contents of the memory address.
63 * R1: previous contents of the memory address.
64 */
65ENTRY(_atomic_add32)
66 R1 = [P0];
67 R0 = R1 + R0;
68 [P0] = R0;
69 rts;
70ENDPROC (_atomic_add32)
71
72.align 16
73 /*
74 * Atomic sub, 32 bit.
75 * Inputs: P0: memory address to use
76 * R0: value to subtract
77 * Outputs: R0: new contents of the memory address.
78 * R1: previous contents of the memory address.
79 */
80ENTRY(_atomic_sub32)
81 R1 = [P0];
82 R0 = R1 - R0;
83 [P0] = R0;
84 rts;
85ENDPROC (_atomic_sub32)
86
87.align 16
88 /*
89 * Atomic ior, 32 bit.
90 * Inputs: P0: memory address to use
91 * R0: value to ior
92 * Outputs: R0: new contents of the memory address.
93 * R1: previous contents of the memory address.
94 */
95ENTRY(_atomic_ior32)
96 R1 = [P0];
97 R0 = R1 | R0;
98 [P0] = R0;
99 rts;
100ENDPROC (_atomic_ior32)
101
102.align 16
103 /*
104 * Atomic ior, 32 bit.
105 * Inputs: P0: memory address to use
106 * R0: value to ior
107 * Outputs: R0: new contents of the memory address.
108 * R1: previous contents of the memory address.
109 */
110ENTRY(_atomic_and32)
111 R1 = [P0];
112 R0 = R1 & R0;
113 [P0] = R0;
114 rts;
115ENDPROC (_atomic_ior32)
116
117.align 16
118 /*
119 * Atomic ior, 32 bit.
120 * Inputs: P0: memory address to use
121 * R0: value to ior
122 * Outputs: R0: new contents of the memory address.
123 * R1: previous contents of the memory address.
124 */
125ENTRY(_atomic_xor32)
126 R1 = [P0];
127 R0 = R1 ^ R0;
128 [P0] = R0;
129 rts;
130ENDPROC (_atomic_ior32)
131
132ENTRY(_fixed_code_end)
diff --git a/arch/blackfin/kernel/flat.c b/arch/blackfin/kernel/flat.c
index a92587b628b5..d188b2430536 100644
--- a/arch/blackfin/kernel/flat.c
+++ b/arch/blackfin/kernel/flat.c
@@ -36,24 +36,22 @@ unsigned long bfin_get_addr_from_rp(unsigned long *ptr,
36 unsigned long val; 36 unsigned long val;
37 37
38 switch (type) { 38 switch (type) {
39 case FLAT_BFIN_RELOC_TYPE_16_BIT: 39 case FLAT_BFIN_RELOC_TYPE_16_BIT:
40 case FLAT_BFIN_RELOC_TYPE_16H_BIT: 40 case FLAT_BFIN_RELOC_TYPE_16H_BIT:
41 usptr = (unsigned short *)ptr; 41 usptr = (unsigned short *)ptr;
42 pr_debug("*usptr = %x", get_unaligned(usptr)); 42 pr_debug("*usptr = %x", get_unaligned(usptr));
43 val = get_unaligned(usptr); 43 val = get_unaligned(usptr);
44 val += *persistent; 44 val += *persistent;
45 break; 45 break;
46 46
47 case FLAT_BFIN_RELOC_TYPE_32_BIT: 47 case FLAT_BFIN_RELOC_TYPE_32_BIT:
48 pr_debug("*ptr = %lx", get_unaligned(ptr)); 48 pr_debug("*ptr = %lx", get_unaligned(ptr));
49 val = get_unaligned(ptr); 49 val = get_unaligned(ptr);
50 break; 50 break;
51 51
52 default: 52 default:
53 pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", 53 pr_debug("BINFMT_FLAT: Unknown relocation type %x\n", type);
54 type); 54 return 0;
55
56 return 0;
57 } 55 }
58 56
59 /* 57 /*
@@ -81,21 +79,20 @@ void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr,
81 int type = (relval >> 26) & 7; 79 int type = (relval >> 26) & 7;
82 80
83 switch (type) { 81 switch (type) {
84 case FLAT_BFIN_RELOC_TYPE_16_BIT: 82 case FLAT_BFIN_RELOC_TYPE_16_BIT:
85 put_unaligned(addr, usptr); 83 put_unaligned(addr, usptr);
86 pr_debug("new value %x at %p", get_unaligned(usptr), 84 pr_debug("new value %x at %p", get_unaligned(usptr), usptr);
87 usptr); 85 break;
88 break;
89 86
90 case FLAT_BFIN_RELOC_TYPE_16H_BIT: 87 case FLAT_BFIN_RELOC_TYPE_16H_BIT:
91 put_unaligned(addr >> 16, usptr); 88 put_unaligned(addr >> 16, usptr);
92 pr_debug("new value %x", get_unaligned(usptr)); 89 pr_debug("new value %x", get_unaligned(usptr));
93 break; 90 break;
94 91
95 case FLAT_BFIN_RELOC_TYPE_32_BIT: 92 case FLAT_BFIN_RELOC_TYPE_32_BIT:
96 put_unaligned(addr, ptr); 93 put_unaligned(addr, ptr);
97 pr_debug("new ptr =%lx", get_unaligned(ptr)); 94 pr_debug("new ptr =%lx", get_unaligned(ptr));
98 break; 95 break;
99 } 96 }
100} 97}
101EXPORT_SYMBOL(bfin_put_addr_at_rp); 98EXPORT_SYMBOL(bfin_put_addr_at_rp);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 80996a1a94ca..1fc001c7abda 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -82,7 +82,7 @@ int show_interrupts(struct seq_file *p, void *v)
82 seq_printf(p, ", %s", action->name); 82 seq_printf(p, ", %s", action->name);
83 83
84 seq_putc(p, '\n'); 84 seq_putc(p, '\n');
85 unlock: 85 unlock:
86 spin_unlock_irqrestore(&irq_desc[i].lock, flags); 86 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
87 } else if (i == NR_IRQS) { 87 } else if (i == NR_IRQS) {
88 seq_printf(p, "Err: %10lu\n", irq_err_count); 88 seq_printf(p, "Err: %10lu\n", irq_err_count);
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
new file mode 100644
index 000000000000..a9c15515bfd7
--- /dev/null
+++ b/arch/blackfin/kernel/kgdb.c
@@ -0,0 +1,421 @@
1/*
2 * File: arch/blackfin/kernel/kgdb.c
3 * Based on:
4 * Author: Sonic Zhang
5 *
6 * Created:
7 * Description:
8 *
9 * Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
10 *
11 * Modified:
12 * Copyright 2005-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see the file COPYING, or write
28 * to the Free Software Foundation, Inc.,
29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 */
31
32#include <linux/string.h>
33#include <linux/kernel.h>
34#include <linux/sched.h>
35#include <linux/smp.h>
36#include <linux/spinlock.h>
37#include <linux/delay.h>
38#include <linux/ptrace.h> /* for linux pt_regs struct */
39#include <linux/kgdb.h>
40#include <linux/console.h>
41#include <linux/init.h>
42#include <linux/debugger.h>
43#include <linux/errno.h>
44#include <linux/irq.h>
45#include <asm/system.h>
46#include <asm/traps.h>
47#include <asm/blackfin.h>
48
49/* Put the error code here just in case the user cares. */
50int gdb_bf533errcode;
51/* Likewise, the vector number here (since GDB only gets the signal
52 number through the usual means, and that's not very specific). */
53int gdb_bf533vector = -1;
54
55#if KGDB_MAX_NO_CPUS != 8
56#error change the definition of slavecpulocks
57#endif
58
59void regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
60{
61 gdb_regs[BFIN_R0] = regs->r0;
62 gdb_regs[BFIN_R1] = regs->r1;
63 gdb_regs[BFIN_R2] = regs->r2;
64 gdb_regs[BFIN_R3] = regs->r3;
65 gdb_regs[BFIN_R4] = regs->r4;
66 gdb_regs[BFIN_R5] = regs->r5;
67 gdb_regs[BFIN_R6] = regs->r6;
68 gdb_regs[BFIN_R7] = regs->r7;
69 gdb_regs[BFIN_P0] = regs->p0;
70 gdb_regs[BFIN_P1] = regs->p1;
71 gdb_regs[BFIN_P2] = regs->p2;
72 gdb_regs[BFIN_P3] = regs->p3;
73 gdb_regs[BFIN_P4] = regs->p4;
74 gdb_regs[BFIN_P5] = regs->p5;
75 gdb_regs[BFIN_SP] = regs->reserved;
76 gdb_regs[BFIN_FP] = regs->fp;
77 gdb_regs[BFIN_I0] = regs->i0;
78 gdb_regs[BFIN_I1] = regs->i1;
79 gdb_regs[BFIN_I2] = regs->i2;
80 gdb_regs[BFIN_I3] = regs->i3;
81 gdb_regs[BFIN_M0] = regs->m0;
82 gdb_regs[BFIN_M1] = regs->m1;
83 gdb_regs[BFIN_M2] = regs->m2;
84 gdb_regs[BFIN_M3] = regs->m3;
85 gdb_regs[BFIN_B0] = regs->b0;
86 gdb_regs[BFIN_B1] = regs->b1;
87 gdb_regs[BFIN_B2] = regs->b2;
88 gdb_regs[BFIN_B3] = regs->b3;
89 gdb_regs[BFIN_L0] = regs->l0;
90 gdb_regs[BFIN_L1] = regs->l1;
91 gdb_regs[BFIN_L2] = regs->l2;
92 gdb_regs[BFIN_L3] = regs->l3;
93 gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
94 gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
95 gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
96 gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
97 gdb_regs[BFIN_ASTAT] = regs->astat;
98 gdb_regs[BFIN_RETS] = regs->rets;
99 gdb_regs[BFIN_LC0] = regs->lc0;
100 gdb_regs[BFIN_LT0] = regs->lt0;
101 gdb_regs[BFIN_LB0] = regs->lb0;
102 gdb_regs[BFIN_LC1] = regs->lc1;
103 gdb_regs[BFIN_LT1] = regs->lt1;
104 gdb_regs[BFIN_LB1] = regs->lb1;
105 gdb_regs[BFIN_CYCLES] = 0;
106 gdb_regs[BFIN_CYCLES2] = 0;
107 gdb_regs[BFIN_USP] = regs->usp;
108 gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
109 gdb_regs[BFIN_SYSCFG] = regs->syscfg;
110 gdb_regs[BFIN_RETI] = regs->pc;
111 gdb_regs[BFIN_RETX] = regs->retx;
112 gdb_regs[BFIN_RETN] = regs->retn;
113 gdb_regs[BFIN_RETE] = regs->rete;
114 gdb_regs[BFIN_PC] = regs->pc;
115 gdb_regs[BFIN_CC] = 0;
116 gdb_regs[BFIN_EXTRA1] = 0;
117 gdb_regs[BFIN_EXTRA2] = 0;
118 gdb_regs[BFIN_EXTRA3] = 0;
119 gdb_regs[BFIN_IPEND] = regs->ipend;
120}
121
122/*
123 * Extracts ebp, esp and eip values understandable by gdb from the values
124 * saved by switch_to.
125 * thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
126 * prior to entering switch_to is 8 greater then the value that is saved.
127 * If switch_to changes, change following code appropriately.
128 */
129void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
130{
131 gdb_regs[BFIN_SP] = p->thread.ksp;
132 gdb_regs[BFIN_PC] = p->thread.pc;
133 gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
134}
135
136void gdb_regs_to_regs(unsigned long *gdb_regs, struct pt_regs *regs)
137{
138 regs->r0 = gdb_regs[BFIN_R0];
139 regs->r1 = gdb_regs[BFIN_R1];
140 regs->r2 = gdb_regs[BFIN_R2];
141 regs->r3 = gdb_regs[BFIN_R3];
142 regs->r4 = gdb_regs[BFIN_R4];
143 regs->r5 = gdb_regs[BFIN_R5];
144 regs->r6 = gdb_regs[BFIN_R6];
145 regs->r7 = gdb_regs[BFIN_R7];
146 regs->p0 = gdb_regs[BFIN_P0];
147 regs->p1 = gdb_regs[BFIN_P1];
148 regs->p2 = gdb_regs[BFIN_P2];
149 regs->p3 = gdb_regs[BFIN_P3];
150 regs->p4 = gdb_regs[BFIN_P4];
151 regs->p5 = gdb_regs[BFIN_P5];
152 regs->fp = gdb_regs[BFIN_FP];
153 regs->i0 = gdb_regs[BFIN_I0];
154 regs->i1 = gdb_regs[BFIN_I1];
155 regs->i2 = gdb_regs[BFIN_I2];
156 regs->i3 = gdb_regs[BFIN_I3];
157 regs->m0 = gdb_regs[BFIN_M0];
158 regs->m1 = gdb_regs[BFIN_M1];
159 regs->m2 = gdb_regs[BFIN_M2];
160 regs->m3 = gdb_regs[BFIN_M3];
161 regs->b0 = gdb_regs[BFIN_B0];
162 regs->b1 = gdb_regs[BFIN_B1];
163 regs->b2 = gdb_regs[BFIN_B2];
164 regs->b3 = gdb_regs[BFIN_B3];
165 regs->l0 = gdb_regs[BFIN_L0];
166 regs->l1 = gdb_regs[BFIN_L1];
167 regs->l2 = gdb_regs[BFIN_L2];
168 regs->l3 = gdb_regs[BFIN_L3];
169 regs->a0x = gdb_regs[BFIN_A0_DOT_X];
170 regs->a0w = gdb_regs[BFIN_A0_DOT_W];
171 regs->a1x = gdb_regs[BFIN_A1_DOT_X];
172 regs->a1w = gdb_regs[BFIN_A1_DOT_W];
173 regs->rets = gdb_regs[BFIN_RETS];
174 regs->lc0 = gdb_regs[BFIN_LC0];
175 regs->lt0 = gdb_regs[BFIN_LT0];
176 regs->lb0 = gdb_regs[BFIN_LB0];
177 regs->lc1 = gdb_regs[BFIN_LC1];
178 regs->lt1 = gdb_regs[BFIN_LT1];
179 regs->lb1 = gdb_regs[BFIN_LB1];
180 regs->usp = gdb_regs[BFIN_USP];
181 regs->syscfg = gdb_regs[BFIN_SYSCFG];
182 regs->retx = gdb_regs[BFIN_PC];
183 regs->retn = gdb_regs[BFIN_RETN];
184 regs->rete = gdb_regs[BFIN_RETE];
185 regs->pc = gdb_regs[BFIN_PC];
186
187#if 0 /* can't change these */
188 regs->astat = gdb_regs[BFIN_ASTAT];
189 regs->seqstat = gdb_regs[BFIN_SEQSTAT];
190 regs->ipend = gdb_regs[BFIN_IPEND];
191#endif
192}
193
194struct hw_breakpoint {
195 unsigned int occupied:1;
196 unsigned int skip:1;
197 unsigned int enabled:1;
198 unsigned int type:1;
199 unsigned int dataacc:2;
200 unsigned short count;
201 unsigned int addr;
202} breakinfo[HW_BREAKPOINT_NUM];
203
204int kgdb_arch_init(void)
205{
206 kgdb_remove_all_hw_break();
207 return 0;
208}
209
210int kgdb_set_hw_break(unsigned long addr)
211{
212 int breakno;
213 for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++)
214 if (!breakinfo[breakno].occupied) {
215 breakinfo[breakno].occupied = 1;
216 breakinfo[breakno].enabled = 1;
217 breakinfo[breakno].type = 1;
218 breakinfo[breakno].addr = addr;
219 return 0;
220 }
221
222 return -ENOSPC;
223}
224
225int kgdb_remove_hw_break(unsigned long addr)
226{
227 int breakno;
228 for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++)
229 if (breakinfo[breakno].addr == addr)
230 memset(&(breakinfo[breakno]), 0, sizeof(struct hw_breakpoint));
231
232 return 0;
233}
234
235void kgdb_remove_all_hw_break(void)
236{
237 memset(breakinfo, 0, sizeof(struct hw_breakpoint)*8);
238}
239
240/*
241void kgdb_show_info(void)
242{
243 printk(KERN_DEBUG "hwd: wpia0=0x%x, wpiacnt0=%d, wpiactl=0x%x, wpstat=0x%x\n",
244 bfin_read_WPIA0(), bfin_read_WPIACNT0(),
245 bfin_read_WPIACTL(), bfin_read_WPSTAT());
246}
247*/
248
249void kgdb_correct_hw_break(void)
250{
251 int breakno;
252 int correctit;
253 uint32_t wpdactl = bfin_read_WPDACTL();
254
255 correctit = 0;
256 for (breakno = 0; breakno < HW_BREAKPOINT_NUM; breakno++) {
257 if (breakinfo[breakno].type == 1) {
258 switch (breakno) {
259 case 0:
260 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN0)) {
261 correctit = 1;
262 wpdactl &= ~(WPIREN01|EMUSW0);
263 wpdactl |= WPIAEN0|WPICNTEN0;
264 bfin_write_WPIA0(breakinfo[breakno].addr);
265 bfin_write_WPIACNT0(breakinfo[breakno].skip);
266 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN0)) {
267 correctit = 1;
268 wpdactl &= ~WPIAEN0;
269 }
270 break;
271
272 case 1:
273 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN1)) {
274 correctit = 1;
275 wpdactl &= ~(WPIREN01|EMUSW1);
276 wpdactl |= WPIAEN1|WPICNTEN1;
277 bfin_write_WPIA1(breakinfo[breakno].addr);
278 bfin_write_WPIACNT1(breakinfo[breakno].skip);
279 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN1)) {
280 correctit = 1;
281 wpdactl &= ~WPIAEN1;
282 }
283 break;
284
285 case 2:
286 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN2)) {
287 correctit = 1;
288 wpdactl &= ~(WPIREN23|EMUSW2);
289 wpdactl |= WPIAEN2|WPICNTEN2;
290 bfin_write_WPIA2(breakinfo[breakno].addr);
291 bfin_write_WPIACNT2(breakinfo[breakno].skip);
292 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN2)) {
293 correctit = 1;
294 wpdactl &= ~WPIAEN2;
295 }
296 break;
297
298 case 3:
299 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN3)) {
300 correctit = 1;
301 wpdactl &= ~(WPIREN23|EMUSW3);
302 wpdactl |= WPIAEN3|WPICNTEN3;
303 bfin_write_WPIA3(breakinfo[breakno].addr);
304 bfin_write_WPIACNT3(breakinfo[breakno].skip);
305 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN3)) {
306 correctit = 1;
307 wpdactl &= ~WPIAEN3;
308 }
309 break;
310 case 4:
311 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN4)) {
312 correctit = 1;
313 wpdactl &= ~(WPIREN45|EMUSW4);
314 wpdactl |= WPIAEN4|WPICNTEN4;
315 bfin_write_WPIA4(breakinfo[breakno].addr);
316 bfin_write_WPIACNT4(breakinfo[breakno].skip);
317 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN4)) {
318 correctit = 1;
319 wpdactl &= ~WPIAEN4;
320 }
321 break;
322 case 5:
323 if (breakinfo[breakno].enabled && !(wpdactl & WPIAEN5)) {
324 correctit = 1;
325 wpdactl &= ~(WPIREN45|EMUSW5);
326 wpdactl |= WPIAEN5|WPICNTEN5;
327 bfin_write_WPIA5(breakinfo[breakno].addr);
328 bfin_write_WPIACNT5(breakinfo[breakno].skip);
329 } else if (!breakinfo[breakno].enabled && (wpdactl & WPIAEN5)) {
330 correctit = 1;
331 wpdactl &= ~WPIAEN5;
332 }
333 break;
334 }
335 }
336 }
337 if (correctit) {
338 wpdactl &= ~WPAND;
339 wpdactl |= WPPWR;
340 /*printk("correct_hw_break: wpdactl=0x%x\n", wpdactl);*/
341 bfin_write_WPDACTL(wpdactl);
342 CSYNC();
343 /*kgdb_show_info();*/
344 }
345}
346
347void kgdb_disable_hw_debug(struct pt_regs *regs)
348{
349 /* Disable hardware debugging while we are in kgdb */
350 bfin_write_WPIACTL(bfin_read_WPIACTL() & ~0x1);
351 CSYNC();
352}
353
354void kgdb_post_master_code(struct pt_regs *regs, int eVector, int err_code)
355{
356 /* Master processor is completely in the debugger */
357 gdb_bf533vector = eVector;
358 gdb_bf533errcode = err_code;
359}
360
361int kgdb_arch_handle_exception(int exceptionVector, int signo,
362 int err_code, char *remcom_in_buffer,
363 char *remcom_out_buffer,
364 struct pt_regs *linux_regs)
365{
366 long addr;
367 long breakno;
368 char *ptr;
369 int newPC;
370 int wp_status;
371
372 switch (remcom_in_buffer[0]) {
373 case 'c':
374 case 's':
375 if (kgdb_contthread && kgdb_contthread != current) {
376 strcpy(remcom_out_buffer, "E00");
377 break;
378 }
379
380 kgdb_contthread = NULL;
381
382 /* try to read optional parameter, pc unchanged if no parm */
383 ptr = &remcom_in_buffer[1];
384 if (kgdb_hex2long(&ptr, &addr)) {
385 linux_regs->retx = addr;
386 }
387 newPC = linux_regs->retx;
388
389 /* clear the trace bit */
390 linux_regs->syscfg &= 0xfffffffe;
391
392 /* set the trace bit if we're stepping */
393 if (remcom_in_buffer[0] == 's') {
394 linux_regs->syscfg |= 0x1;
395 debugger_step = 1;
396 }
397
398 wp_status = bfin_read_WPSTAT();
399 CSYNC();
400
401 if (exceptionVector == VEC_WATCH) {
402 for (breakno = 0; breakno < 6; ++breakno) {
403 if (wp_status & (1 << breakno)) {
404 breakinfo->skip = 1;
405 break;
406 }
407 }
408 }
409 kgdb_correct_hw_break();
410
411 bfin_write_WPSTAT(0);
412
413 return 0;
414 } /* switch */
415 return -1; /* this means that we do not want to exit from the handler */
416}
417
418struct kgdb_arch arch_kgdb_ops = {
419 .gdb_bpt_instr = {0xa1},
420 .flags = KGDB_HW_BREAKPOINT,
421};
diff --git a/arch/blackfin/kernel/module.c b/arch/blackfin/kernel/module.c
index 372f756f1ad9..8b9fe29d03f4 100644
--- a/arch/blackfin/kernel/module.c
+++ b/arch/blackfin/kernel/module.c
@@ -165,8 +165,8 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs,
165 165
166 for (s = sechdrs; s < sechdrs_end; ++s) { 166 for (s = sechdrs; s < sechdrs_end; ++s) {
167 if ((strcmp(".l1.text", secstrings + s->sh_name) == 0) || 167 if ((strcmp(".l1.text", secstrings + s->sh_name) == 0) ||
168 ((strcmp(".text", secstrings + s->sh_name)==0) && 168 ((strcmp(".text", secstrings + s->sh_name) == 0) &&
169 (hdr->e_flags & FLG_CODE_IN_L1) && (s->sh_size > 0))) { 169 (hdr->e_flags & FLG_CODE_IN_L1) && (s->sh_size > 0))) {
170 mod->arch.text_l1 = s; 170 mod->arch.text_l1 = s;
171 dest = l1_inst_sram_alloc(s->sh_size); 171 dest = l1_inst_sram_alloc(s->sh_size);
172 if (dest == NULL) { 172 if (dest == NULL) {
@@ -179,9 +179,9 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs,
179 s->sh_flags &= ~SHF_ALLOC; 179 s->sh_flags &= ~SHF_ALLOC;
180 s->sh_addr = (unsigned long)dest; 180 s->sh_addr = (unsigned long)dest;
181 } 181 }
182 if ((strcmp(".l1.data", secstrings + s->sh_name) == 0)|| 182 if ((strcmp(".l1.data", secstrings + s->sh_name) == 0) ||
183 ((strcmp(".data", secstrings + s->sh_name)==0) && 183 ((strcmp(".data", secstrings + s->sh_name) == 0) &&
184 (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) { 184 (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) {
185 mod->arch.data_a_l1 = s; 185 mod->arch.data_a_l1 = s;
186 dest = l1_data_sram_alloc(s->sh_size); 186 dest = l1_data_sram_alloc(s->sh_size);
187 if (dest == NULL) { 187 if (dest == NULL) {
@@ -195,8 +195,8 @@ module_frob_arch_sections(Elf_Ehdr * hdr, Elf_Shdr * sechdrs,
195 s->sh_addr = (unsigned long)dest; 195 s->sh_addr = (unsigned long)dest;
196 } 196 }
197 if (strcmp(".l1.bss", secstrings + s->sh_name) == 0 || 197 if (strcmp(".l1.bss", secstrings + s->sh_name) == 0 ||
198 ((strcmp(".bss", secstrings + s->sh_name)==0) && 198 ((strcmp(".bss", secstrings + s->sh_name) == 0) &&
199 (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) { 199 (hdr->e_flags & FLG_DATA_IN_L1) && (s->sh_size > 0))) {
200 mod->arch.bss_a_l1 = s; 200 mod->arch.bss_a_l1 = s;
201 dest = l1_data_sram_alloc(s->sh_size); 201 dest = l1_data_sram_alloc(s->sh_size);
202 if (dest == NULL) { 202 if (dest == NULL) {
@@ -326,7 +326,7 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
326 pr_debug("before %x after %x\n", *location16, 326 pr_debug("before %x after %x\n", *location16,
327 (value & 0xffff)); 327 (value & 0xffff));
328 tmp = (value & 0xffff); 328 tmp = (value & 0xffff);
329 if((unsigned long)location16 >= L1_CODE_START) { 329 if ((unsigned long)location16 >= L1_CODE_START) {
330 dma_memcpy(location16, &tmp, 2); 330 dma_memcpy(location16, &tmp, 2);
331 } else 331 } else
332 *location16 = tmp; 332 *location16 = tmp;
@@ -335,7 +335,7 @@ apply_relocate_add(Elf_Shdr * sechdrs, const char *strtab,
335 pr_debug("before %x after %x\n", *location16, 335 pr_debug("before %x after %x\n", *location16,
336 ((value >> 16) & 0xffff)); 336 ((value >> 16) & 0xffff));
337 tmp = ((value >> 16) & 0xffff); 337 tmp = ((value >> 16) & 0xffff);
338 if((unsigned long)location16 >= L1_CODE_START) { 338 if ((unsigned long)location16 >= L1_CODE_START) {
339 dma_memcpy(location16, &tmp, 2); 339 dma_memcpy(location16, &tmp, 2);
340 } else 340 } else
341 *location16 = tmp; 341 *location16 = tmp;
@@ -404,8 +404,8 @@ module_finalize(const Elf_Ehdr * hdr,
404 continue; 404 continue;
405 405
406 if ((sechdrs[i].sh_type == SHT_RELA) && 406 if ((sechdrs[i].sh_type == SHT_RELA) &&
407 ((strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0)|| 407 ((strcmp(".rela.l1.text", secstrings + sechdrs[i].sh_name) == 0) ||
408 ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) && 408 ((strcmp(".rela.text", secstrings + sechdrs[i].sh_name) == 0) &&
409 (hdr->e_flags & FLG_CODE_IN_L1)))) { 409 (hdr->e_flags & FLG_CODE_IN_L1)))) {
410 apply_relocate_add((Elf_Shdr *) sechdrs, strtab, 410 apply_relocate_add((Elf_Shdr *) sechdrs, strtab,
411 symindex, i, mod); 411 symindex, i, mod);
@@ -417,13 +417,13 @@ module_finalize(const Elf_Ehdr * hdr,
417void module_arch_cleanup(struct module *mod) 417void module_arch_cleanup(struct module *mod)
418{ 418{
419 if ((mod->arch.text_l1) && (mod->arch.text_l1->sh_addr)) 419 if ((mod->arch.text_l1) && (mod->arch.text_l1->sh_addr))
420 l1_inst_sram_free((void*)mod->arch.text_l1->sh_addr); 420 l1_inst_sram_free((void *)mod->arch.text_l1->sh_addr);
421 if ((mod->arch.data_a_l1) && (mod->arch.data_a_l1->sh_addr)) 421 if ((mod->arch.data_a_l1) && (mod->arch.data_a_l1->sh_addr))
422 l1_data_sram_free((void*)mod->arch.data_a_l1->sh_addr); 422 l1_data_sram_free((void *)mod->arch.data_a_l1->sh_addr);
423 if ((mod->arch.bss_a_l1) && (mod->arch.bss_a_l1->sh_addr)) 423 if ((mod->arch.bss_a_l1) && (mod->arch.bss_a_l1->sh_addr))
424 l1_data_sram_free((void*)mod->arch.bss_a_l1->sh_addr); 424 l1_data_sram_free((void *)mod->arch.bss_a_l1->sh_addr);
425 if ((mod->arch.data_b_l1) && (mod->arch.data_b_l1->sh_addr)) 425 if ((mod->arch.data_b_l1) && (mod->arch.data_b_l1->sh_addr))
426 l1_data_B_sram_free((void*)mod->arch.data_b_l1->sh_addr); 426 l1_data_B_sram_free((void *)mod->arch.data_b_l1->sh_addr);
427 if ((mod->arch.bss_b_l1) && (mod->arch.bss_b_l1->sh_addr)) 427 if ((mod->arch.bss_b_l1) && (mod->arch.bss_b_l1->sh_addr))
428 l1_data_B_sram_free((void*)mod->arch.bss_b_l1->sh_addr); 428 l1_data_B_sram_free((void *)mod->arch.bss_b_l1->sh_addr);
429} 429}
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index 3eff7439d8d3..5a51dd6ab280 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -32,9 +32,10 @@
32#include <linux/unistd.h> 32#include <linux/unistd.h>
33#include <linux/user.h> 33#include <linux/user.h>
34#include <linux/a.out.h> 34#include <linux/a.out.h>
35#include <linux/uaccess.h>
35 36
36#include <asm/blackfin.h> 37#include <asm/blackfin.h>
37#include <asm/uaccess.h> 38#include <asm/fixed_code.h>
38 39
39#define LED_ON 0 40#define LED_ON 0
40#define LED_OFF 1 41#define LED_OFF 1
@@ -173,8 +174,8 @@ void show_regs(struct pt_regs *regs)
173 printk(KERN_NOTICE "R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n", 174 printk(KERN_NOTICE "R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
174 regs->r4, regs->r5, regs->r6, regs->r7); 175 regs->r4, regs->r5, regs->r6, regs->r7);
175 176
176 if (!(regs->ipend)) 177 if (!regs->ipend)
177 printk("USP: %08lx\n", rdusp()); 178 printk(KERN_NOTICE "USP: %08lx\n", rdusp());
178} 179}
179 180
180/* Fill in the fpu structure for a core dump. */ 181/* Fill in the fpu structure for a core dump. */
@@ -322,7 +323,7 @@ asmlinkage int sys_execve(char *name, char **argv, char **envp)
322 goto out; 323 goto out;
323 error = do_execve(filename, argv, envp, regs); 324 error = do_execve(filename, argv, envp, regs);
324 putname(filename); 325 putname(filename);
325 out: 326 out:
326 unlock_kernel(); 327 unlock_kernel();
327 return error; 328 return error;
328} 329}
@@ -350,13 +351,77 @@ unsigned long get_wchan(struct task_struct *p)
350 return 0; 351 return 0;
351} 352}
352 353
354void finish_atomic_sections (struct pt_regs *regs)
355{
356 if (regs->pc < ATOMIC_SEQS_START || regs->pc >= ATOMIC_SEQS_END)
357 return;
358
359 switch (regs->pc) {
360 case ATOMIC_XCHG32 + 2:
361 put_user(regs->r1, (int *)regs->p0);
362 regs->pc += 2;
363 break;
364
365 case ATOMIC_CAS32 + 2:
366 case ATOMIC_CAS32 + 4:
367 if (regs->r0 == regs->r1)
368 put_user(regs->r2, (int *)regs->p0);
369 regs->pc = ATOMIC_CAS32 + 8;
370 break;
371 case ATOMIC_CAS32 + 6:
372 put_user(regs->r2, (int *)regs->p0);
373 regs->pc += 2;
374 break;
375
376 case ATOMIC_ADD32 + 2:
377 regs->r0 = regs->r1 + regs->r0;
378 /* fall through */
379 case ATOMIC_ADD32 + 4:
380 put_user(regs->r0, (int *)regs->p0);
381 regs->pc = ATOMIC_ADD32 + 6;
382 break;
383
384 case ATOMIC_SUB32 + 2:
385 regs->r0 = regs->r1 - regs->r0;
386 /* fall through */
387 case ATOMIC_SUB32 + 4:
388 put_user(regs->r0, (int *)regs->p0);
389 regs->pc = ATOMIC_SUB32 + 6;
390 break;
391
392 case ATOMIC_IOR32 + 2:
393 regs->r0 = regs->r1 | regs->r0;
394 /* fall through */
395 case ATOMIC_IOR32 + 4:
396 put_user(regs->r0, (int *)regs->p0);
397 regs->pc = ATOMIC_IOR32 + 6;
398 break;
399
400 case ATOMIC_AND32 + 2:
401 regs->r0 = regs->r1 & regs->r0;
402 /* fall through */
403 case ATOMIC_AND32 + 4:
404 put_user(regs->r0, (int *)regs->p0);
405 regs->pc = ATOMIC_AND32 + 6;
406 break;
407
408 case ATOMIC_XOR32 + 2:
409 regs->r0 = regs->r1 ^ regs->r0;
410 /* fall through */
411 case ATOMIC_XOR32 + 4:
412 put_user(regs->r0, (int *)regs->p0);
413 regs->pc = ATOMIC_XOR32 + 6;
414 break;
415 }
416}
417
353#if defined(CONFIG_ACCESS_CHECK) 418#if defined(CONFIG_ACCESS_CHECK)
354int _access_ok(unsigned long addr, unsigned long size) 419int _access_ok(unsigned long addr, unsigned long size)
355{ 420{
356 421
357 if (addr > (addr + size)) 422 if (addr > (addr + size))
358 return 0; 423 return 0;
359 if (segment_eq(get_fs(),KERNEL_DS)) 424 if (segment_eq(get_fs(), KERNEL_DS))
360 return 1; 425 return 1;
361#ifdef CONFIG_MTD_UCLINUX 426#ifdef CONFIG_MTD_UCLINUX
362 if (addr >= memory_start && (addr + size) <= memory_end) 427 if (addr >= memory_start && (addr + size) <= memory_end)
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index e718bb4a1ef0..ed800c7456dd 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -36,8 +36,8 @@
36#include <linux/ptrace.h> 36#include <linux/ptrace.h>
37#include <linux/user.h> 37#include <linux/user.h>
38#include <linux/signal.h> 38#include <linux/signal.h>
39#include <linux/uaccess.h>
39 40
40#include <asm/uaccess.h>
41#include <asm/page.h> 41#include <asm/page.h>
42#include <asm/pgtable.h> 42#include <asm/pgtable.h>
43#include <asm/system.h> 43#include <asm/system.h>
@@ -122,7 +122,7 @@ static inline long get_reg(struct task_struct *task, int regno)
122static inline int 122static inline int
123put_reg(struct task_struct *task, int regno, unsigned long data) 123put_reg(struct task_struct *task, int regno, unsigned long data)
124{ 124{
125 char * reg_ptr; 125 char *reg_ptr;
126 126
127 struct pt_regs *regs = 127 struct pt_regs *regs =
128 (struct pt_regs *)((unsigned long)task_stack_page(task) + 128 (struct pt_regs *)((unsigned long)task_stack_page(task) +
@@ -146,7 +146,7 @@ put_reg(struct task_struct *task, int regno, unsigned long data)
146 break; 146 break;
147 default: 147 default:
148 if (regno <= 216) 148 if (regno <= 216)
149 *(long *)(reg_ptr + regno) = data; 149 *(long *)(reg_ptr + regno) = data;
150 } 150 }
151 return 0; 151 return 0;
152} 152}
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 83060f98d15d..f59dcee7bae3 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -42,6 +42,7 @@
42#include <asm/cacheflush.h> 42#include <asm/cacheflush.h>
43#include <asm/blackfin.h> 43#include <asm/blackfin.h>
44#include <asm/cplbinit.h> 44#include <asm/cplbinit.h>
45#include <asm/fixed_code.h>
45 46
46u16 _bfin_swrst; 47u16 _bfin_swrst;
47 48
@@ -63,10 +64,6 @@ EXPORT_SYMBOL(mtd_size);
63 64
64char __initdata command_line[COMMAND_LINE_SIZE]; 65char __initdata command_line[COMMAND_LINE_SIZE];
65 66
66#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
67static void generate_cpl_tables(void);
68#endif
69
70void __init bf53x_cache_init(void) 67void __init bf53x_cache_init(void)
71{ 68{
72#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) 69#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
@@ -197,6 +194,17 @@ void __init setup_arch(char **cmdline_p)
197 /* this give a chance to get printk() working before crash. */ 194 /* this give a chance to get printk() working before crash. */
198#endif 195#endif
199 196
197 printk(KERN_INFO "Hardware Trace ");
198 if (bfin_read_TBUFCTL() & 0x1 )
199 printk("Active ");
200 else
201 printk("Off ");
202 if (bfin_read_TBUFCTL() & 0x2)
203 printk("and Enabled\n");
204 else
205 printk("and Disabled\n");
206
207
200#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH) 208#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
201 /* we need to initialize the Flashrom device here since we might 209 /* we need to initialize the Flashrom device here since we might
202 * do things with flash early on in the boot 210 * do things with flash early on in the boot
@@ -354,15 +362,15 @@ void __init setup_arch(char **cmdline_p)
354 , _stext, _etext, 362 , _stext, _etext,
355 __start_rodata, __end_rodata, 363 __start_rodata, __end_rodata,
356 _sdata, _edata, 364 _sdata, _edata,
357 (void*)&init_thread_union, (void*)((int)(&init_thread_union) + 0x2000), 365 (void *)&init_thread_union, (void *)((int)(&init_thread_union) + 0x2000),
358 __init_begin, __init_end, 366 __init_begin, __init_end,
359 __bss_start, __bss_stop, 367 __bss_start, __bss_stop,
360 (void*)_ramstart, (void*)memory_end 368 (void *)_ramstart, (void *)memory_end
361#ifdef CONFIG_MTD_UCLINUX 369#ifdef CONFIG_MTD_UCLINUX
362 , (void*)memory_mtd_start, (void*)(memory_mtd_start + mtd_size) 370 , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
363#endif 371#endif
364#if DMA_UNCACHED_REGION > 0 372#if DMA_UNCACHED_REGION > 0
365 , (void*)(_ramend - DMA_UNCACHED_REGION), (void*)(_ramend) 373 , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
366#endif 374#endif
367 ); 375 );
368 376
@@ -388,11 +396,11 @@ void __init setup_arch(char **cmdline_p)
388 /* check the size of the l1 area */ 396 /* check the size of the l1 area */
389 l1_length = _etext_l1 - _stext_l1; 397 l1_length = _etext_l1 - _stext_l1;
390 if (l1_length > L1_CODE_LENGTH) 398 if (l1_length > L1_CODE_LENGTH)
391 panic("L1 memory overflow\n"); 399 panic("L1 code memory overflow\n");
392 400
393 l1_length = _ebss_l1 - _sdata_l1; 401 l1_length = _ebss_l1 - _sdata_l1;
394 if (l1_length > L1_DATA_A_LENGTH) 402 if (l1_length > L1_DATA_A_LENGTH)
395 panic("L1 memory overflow\n"); 403 panic("L1 data memory overflow\n");
396 404
397#ifdef BF561_FAMILY 405#ifdef BF561_FAMILY
398 _bfin_swrst = bfin_read_SICA_SWRST(); 406 _bfin_swrst = bfin_read_SICA_SWRST();
@@ -400,10 +408,28 @@ void __init setup_arch(char **cmdline_p)
400 _bfin_swrst = bfin_read_SWRST(); 408 _bfin_swrst = bfin_read_SWRST();
401#endif 409#endif
402 410
403 bf53x_cache_init(); 411 /* Copy atomic sequences to their fixed location, and sanity check that
412 these locations are the ones that we advertise to userspace. */
413 memcpy((void *)FIXED_CODE_START, &fixed_code_start,
414 FIXED_CODE_END - FIXED_CODE_START);
415 BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
416 != SIGRETURN_STUB - FIXED_CODE_START);
417 BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
418 != ATOMIC_XCHG32 - FIXED_CODE_START);
419 BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
420 != ATOMIC_CAS32 - FIXED_CODE_START);
421 BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
422 != ATOMIC_ADD32 - FIXED_CODE_START);
423 BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
424 != ATOMIC_SUB32 - FIXED_CODE_START);
425 BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
426 != ATOMIC_IOR32 - FIXED_CODE_START);
427 BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
428 != ATOMIC_AND32 - FIXED_CODE_START);
429 BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
430 != ATOMIC_XOR32 - FIXED_CODE_START);
404 431
405 printk(KERN_INFO "Hardware Trace Enabled\n"); 432 bf53x_cache_init();
406 bfin_write_TBUFCTL(0x03);
407} 433}
408 434
409static int __init topology_init(void) 435static int __init topology_init(void)
@@ -421,286 +447,6 @@ static int __init topology_init(void)
421 447
422subsys_initcall(topology_init); 448subsys_initcall(topology_init);
423 449
424#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
425static u16 __init lock_kernel_check(u32 start, u32 end)
426{
427 if ((start <= (u32) _stext && end >= (u32) _end)
428 || (start >= (u32) _stext && end <= (u32) _end))
429 return IN_KERNEL;
430 return 0;
431}
432
433static unsigned short __init
434fill_cplbtab(struct cplb_tab *table,
435 unsigned long start, unsigned long end,
436 unsigned long block_size, unsigned long cplb_data)
437{
438 int i;
439
440 switch (block_size) {
441 case SIZE_4M:
442 i = 3;
443 break;
444 case SIZE_1M:
445 i = 2;
446 break;
447 case SIZE_4K:
448 i = 1;
449 break;
450 case SIZE_1K:
451 default:
452 i = 0;
453 break;
454 }
455
456 cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
457
458 while ((start < end) && (table->pos < table->size)) {
459
460 table->tab[table->pos++] = start;
461
462 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
463 table->tab[table->pos++] =
464 cplb_data | CPLB_LOCK | CPLB_DIRTY;
465 else
466 table->tab[table->pos++] = cplb_data;
467
468 start += block_size;
469 }
470 return 0;
471}
472
473static unsigned short __init
474close_cplbtab(struct cplb_tab *table)
475{
476
477 while (table->pos < table->size) {
478
479 table->tab[table->pos++] = 0;
480 table->tab[table->pos++] = 0; /* !CPLB_VALID */
481 }
482 return 0;
483}
484
485/* helper function */
486static void __fill_code_cplbtab(struct cplb_tab *t, int i,
487 u32 a_start, u32 a_end)
488{
489 if (cplb_data[i].psize) {
490 fill_cplbtab(t,
491 cplb_data[i].start,
492 cplb_data[i].end,
493 cplb_data[i].psize,
494 cplb_data[i].i_conf);
495 } else {
496#if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
497 if (i == SDRAM_KERN) {
498 fill_cplbtab(t,
499 cplb_data[i].start,
500 cplb_data[i].end,
501 SIZE_4M,
502 cplb_data[i].i_conf);
503 } else {
504#endif
505 fill_cplbtab(t,
506 cplb_data[i].start,
507 a_start,
508 SIZE_1M,
509 cplb_data[i].i_conf);
510 fill_cplbtab(t,
511 a_start,
512 a_end,
513 SIZE_4M,
514 cplb_data[i].i_conf);
515 fill_cplbtab(t, a_end,
516 cplb_data[i].end,
517 SIZE_1M,
518 cplb_data[i].i_conf);
519 }
520 }
521}
522
523static void __fill_data_cplbtab(struct cplb_tab *t, int i,
524 u32 a_start, u32 a_end)
525{
526 if (cplb_data[i].psize) {
527 fill_cplbtab(t,
528 cplb_data[i].start,
529 cplb_data[i].end,
530 cplb_data[i].psize,
531 cplb_data[i].d_conf);
532 } else {
533 fill_cplbtab(t,
534 cplb_data[i].start,
535 a_start, SIZE_1M,
536 cplb_data[i].d_conf);
537 fill_cplbtab(t, a_start,
538 a_end, SIZE_4M,
539 cplb_data[i].d_conf);
540 fill_cplbtab(t, a_end,
541 cplb_data[i].end,
542 SIZE_1M,
543 cplb_data[i].d_conf);
544 }
545}
546static void __init generate_cpl_tables(void)
547{
548
549 u16 i, j, process;
550 u32 a_start, a_end, as, ae, as_1m;
551
552 struct cplb_tab *t_i = NULL;
553 struct cplb_tab *t_d = NULL;
554 struct s_cplb cplb;
555
556 cplb.init_i.size = MAX_CPLBS;
557 cplb.init_d.size = MAX_CPLBS;
558 cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
559 cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
560
561 cplb.init_i.pos = 0;
562 cplb.init_d.pos = 0;
563 cplb.switch_i.pos = 0;
564 cplb.switch_d.pos = 0;
565
566 cplb.init_i.tab = icplb_table;
567 cplb.init_d.tab = dcplb_table;
568 cplb.switch_i.tab = ipdt_table;
569 cplb.switch_d.tab = dpdt_table;
570
571 cplb_data[SDRAM_KERN].end = memory_end;
572
573#ifdef CONFIG_MTD_UCLINUX
574 cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
575 cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
576 cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
577# if defined(CONFIG_ROMFS_FS)
578 cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
579
580 /*
581 * The ROMFS_FS size is often not multiple of 1MB.
582 * This can cause multiple CPLB sets covering the same memory area.
583 * This will then cause multiple CPLB hit exceptions.
584 * Workaround: We ensure a contiguous memory area by extending the kernel
585 * memory section over the mtd section.
586 * For ROMFS_FS memory must be covered with ICPLBs anyways.
587 * So there is no difference between kernel and mtd memory setup.
588 */
589
590 cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
591 cplb_data[SDRAM_RAM_MTD].valid = 0;
592
593# endif
594#else
595 cplb_data[SDRAM_RAM_MTD].valid = 0;
596#endif
597
598 cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
599 cplb_data[SDRAM_DMAZ].end = _ramend;
600
601 cplb_data[RES_MEM].start = _ramend;
602 cplb_data[RES_MEM].end = physical_mem_end;
603
604 if (reserved_mem_dcache_on)
605 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
606 else
607 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
608
609 if (reserved_mem_icache_on)
610 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
611 else
612 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
613
614 for (i = ZERO_P; i <= L2_MEM; i++) {
615 if (!cplb_data[i].valid)
616 continue;
617
618 as_1m = cplb_data[i].start % SIZE_1M;
619
620 /*
621 * We need to make sure all sections are properly 1M aligned
622 * However between Kernel Memory and the Kernel mtd section,
623 * depending on the rootfs size, there can be overlapping
624 * memory areas.
625 */
626
627 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
628#ifdef CONFIG_MTD_UCLINUX
629 if (i == SDRAM_RAM_MTD) {
630 if ((cplb_data[SDRAM_KERN].end + 1) >
631 cplb_data[SDRAM_RAM_MTD].start)
632 cplb_data[SDRAM_RAM_MTD].start =
633 (cplb_data[i].start &
634 (-2*SIZE_1M)) + SIZE_1M;
635 else
636 cplb_data[SDRAM_RAM_MTD].start =
637 (cplb_data[i].start &
638 (-2*SIZE_1M));
639 } else
640#endif
641 printk(KERN_WARNING
642 "Unaligned Start of %s at 0x%X\n",
643 cplb_data[i].name, cplb_data[i].start);
644 }
645
646 as = cplb_data[i].start % SIZE_4M;
647 ae = cplb_data[i].end % SIZE_4M;
648
649 if (as)
650 a_start = cplb_data[i].start + (SIZE_4M - (as));
651 else
652 a_start = cplb_data[i].start;
653
654 a_end = cplb_data[i].end - ae;
655
656 for (j = INITIAL_T; j <= SWITCH_T; j++) {
657
658 switch (j) {
659 case INITIAL_T:
660 if (cplb_data[i].attr & INITIAL_T) {
661 t_i = &cplb.init_i;
662 t_d = &cplb.init_d;
663 process = 1;
664 } else
665 process = 0;
666 break;
667 case SWITCH_T:
668 if (cplb_data[i].attr & SWITCH_T) {
669 t_i = &cplb.switch_i;
670 t_d = &cplb.switch_d;
671 process = 1;
672 } else
673 process = 0;
674 break;
675 default:
676 process = 0;
677 break;
678 }
679
680 if (!process)
681 continue;
682 if (cplb_data[i].attr & I_CPLB)
683 __fill_code_cplbtab(t_i, i, a_start, a_end);
684
685 if (cplb_data[i].attr & D_CPLB)
686 __fill_data_cplbtab(t_d, i, a_start, a_end);
687 }
688 }
689
690/* close tables */
691
692 close_cplbtab(&cplb.init_i);
693 close_cplbtab(&cplb.init_d);
694
695 cplb.init_i.tab[cplb.init_i.pos] = -1;
696 cplb.init_d.tab[cplb.init_d.pos] = -1;
697 cplb.switch_i.tab[cplb.switch_i.pos] = -1;
698 cplb.switch_d.tab[cplb.switch_d.pos] = -1;
699
700}
701
702#endif
703
704static u_long get_vco(void) 450static u_long get_vco(void)
705{ 451{
706 u_long msel; 452 u_long msel;
@@ -730,7 +476,6 @@ u_long get_cclk(void)
730 return get_vco() / ssel; 476 return get_vco() / ssel;
731 return get_vco() >> csel; 477 return get_vco() >> csel;
732} 478}
733
734EXPORT_SYMBOL(get_cclk); 479EXPORT_SYMBOL(get_cclk);
735 480
736/* Get the System clock */ 481/* Get the System clock */
@@ -749,7 +494,6 @@ u_long get_sclk(void)
749 494
750 return get_vco() / ssel; 495 return get_vco() / ssel;
751} 496}
752
753EXPORT_SYMBOL(get_sclk); 497EXPORT_SYMBOL(get_sclk);
754 498
755/* 499/*
@@ -804,23 +548,23 @@ static int show_cpuinfo(struct seq_file *m, void *v)
804 seq_printf(m, "D-CACHE:\tOFF\n"); 548 seq_printf(m, "D-CACHE:\tOFF\n");
805 549
806 550
807 switch(bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) { 551 switch (bfin_read_DMEM_CONTROL() & (1 << DMC0_P | 1 << DMC1_P)) {
808 case ACACHE_BSRAM: 552 case ACACHE_BSRAM:
809 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n"); 553 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tSRAM\n");
810 dcache_size = 16; 554 dcache_size = 16;
811 dsup_banks = 1; 555 dsup_banks = 1;
812 break; 556 break;
813 case ACACHE_BCACHE: 557 case ACACHE_BCACHE:
814 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n"); 558 seq_printf(m, "DBANK-A:\tCACHE\n" "DBANK-B:\tCACHE\n");
815 dcache_size = 32; 559 dcache_size = 32;
816 dsup_banks = 2; 560 dsup_banks = 2;
817 break; 561 break;
818 case ASRAM_BSRAM: 562 case ASRAM_BSRAM:
819 seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n"); 563 seq_printf(m, "DBANK-A:\tSRAM\n" "DBANK-B:\tSRAM\n");
820 dcache_size = 0; 564 dcache_size = 0;
821 dsup_banks = 0; 565 dsup_banks = 0;
822 break; 566 break;
823 default: 567 default:
824 break; 568 break;
825 } 569 }
826 570
diff --git a/arch/blackfin/kernel/signal.c b/arch/blackfin/kernel/signal.c
index 316e65c3439d..5564c9588aa8 100644
--- a/arch/blackfin/kernel/signal.c
+++ b/arch/blackfin/kernel/signal.c
@@ -34,8 +34,8 @@
34#include <linux/personality.h> 34#include <linux/personality.h>
35#include <linux/binfmts.h> 35#include <linux/binfmts.h>
36#include <linux/freezer.h> 36#include <linux/freezer.h>
37#include <linux/uaccess.h>
37 38
38#include <asm/uaccess.h>
39#include <asm/cacheflush.h> 39#include <asm/cacheflush.h>
40#include <asm/ucontext.h> 40#include <asm/ucontext.h>
41 41
@@ -124,7 +124,7 @@ asmlinkage int do_rt_sigreturn(unsigned long __unused)
124 124
125 return r0; 125 return r0;
126 126
127 badframe: 127 badframe:
128 force_sig(SIGSEGV, current); 128 force_sig(SIGSEGV, current);
129 return 0; 129 return 0;
130} 130}
@@ -239,7 +239,7 @@ setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t * info,
239 239
240 return 0; 240 return 0;
241 241
242 give_sigsegv: 242 give_sigsegv:
243 if (sig == SIGSEGV) 243 if (sig == SIGSEGV)
244 ka->sa.sa_handler = SIG_DFL; 244 ka->sa.sa_handler = SIG_DFL;
245 force_sig(SIGSEGV, current); 245 force_sig(SIGSEGV, current);
@@ -263,7 +263,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
263 } 263 }
264 /* fallthrough */ 264 /* fallthrough */
265 case -ERESTARTNOINTR: 265 case -ERESTARTNOINTR:
266 do_restart: 266 do_restart:
267 regs->p0 = regs->orig_p0; 267 regs->p0 = regs->orig_p0;
268 regs->r0 = regs->orig_r0; 268 regs->r0 = regs->orig_r0;
269 regs->pc -= 2; 269 regs->pc -= 2;
@@ -341,7 +341,7 @@ asmlinkage void do_signal(struct pt_regs *regs)
341 return; 341 return;
342 } 342 }
343 343
344no_signal: 344 no_signal:
345 /* Did we come from a system call? */ 345 /* Did we come from a system call? */
346 if (regs->orig_p0 >= 0) 346 if (regs->orig_p0 >= 0)
347 /* Restart the system call - no handlers present */ 347 /* Restart the system call - no handlers present */
diff --git a/arch/blackfin/kernel/sys_bfin.c b/arch/blackfin/kernel/sys_bfin.c
index f436e6743f5a..f5e1ae3d1705 100644
--- a/arch/blackfin/kernel/sys_bfin.c
+++ b/arch/blackfin/kernel/sys_bfin.c
@@ -37,12 +37,12 @@
37#include <linux/syscalls.h> 37#include <linux/syscalls.h>
38#include <linux/mman.h> 38#include <linux/mman.h>
39#include <linux/file.h> 39#include <linux/file.h>
40#include <linux/uaccess.h>
41#include <linux/ipc.h>
42#include <linux/unistd.h>
40 43
41#include <asm/cacheflush.h> 44#include <asm/cacheflush.h>
42#include <asm/uaccess.h>
43#include <asm/ipc.h>
44#include <asm/dma.h> 45#include <asm/dma.h>
45#include <asm/unistd.h>
46 46
47/* 47/*
48 * sys_pipe() is the normal C calling standard for creating 48 * sys_pipe() is the normal C calling standard for creating
@@ -83,7 +83,7 @@ do_mmap2(unsigned long addr, unsigned long len,
83 83
84 if (file) 84 if (file)
85 fput(file); 85 fput(file);
86 out: 86 out:
87 return error; 87 return error;
88} 88}
89 89
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index f578176b6d92..beef057bd1dc 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -87,7 +87,7 @@ void __init init_leds(void)
87static inline void do_leds(void) 87static inline void do_leds(void)
88{ 88{
89 static unsigned int count = 50; 89 static unsigned int count = 50;
90 static int flag = 0; 90 static int flag;
91 unsigned short tmp = 0; 91 unsigned short tmp = 0;
92 92
93 if (--count == 0) { 93 if (--count == 0) {
@@ -200,7 +200,7 @@ irqreturn_t timer_interrupt(int irq, void *dummy)__attribute__((l1_text));
200irqreturn_t timer_interrupt(int irq, void *dummy) 200irqreturn_t timer_interrupt(int irq, void *dummy)
201{ 201{
202 /* last time the cmos clock got updated */ 202 /* last time the cmos clock got updated */
203 static long last_rtc_update = 0; 203 static long last_rtc_update;
204 204
205 write_seqlock(&xtime_lock); 205 write_seqlock(&xtime_lock);
206 206
diff --git a/arch/blackfin/kernel/traps.c b/arch/blackfin/kernel/traps.c
index 56058b0b6d4a..3909f5b35536 100644
--- a/arch/blackfin/kernel/traps.c
+++ b/arch/blackfin/kernel/traps.c
@@ -27,15 +27,15 @@
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 28 */
29 29
30#include <asm/uaccess.h> 30#include <linux/uaccess.h>
31#include <linux/interrupt.h>
32#include <linux/module.h>
33#include <linux/kallsyms.h>
31#include <asm/traps.h> 34#include <asm/traps.h>
32#include <asm/cacheflush.h> 35#include <asm/cacheflush.h>
33#include <asm/blackfin.h> 36#include <asm/blackfin.h>
34#include <asm/uaccess.h>
35#include <asm/irq_handler.h> 37#include <asm/irq_handler.h>
36#include <linux/interrupt.h> 38#include <asm/trace.h>
37#include <linux/module.h>
38#include <linux/kallsyms.h>
39 39
40#ifdef CONFIG_KGDB 40#ifdef CONFIG_KGDB
41# include <linux/debugger.h> 41# include <linux/debugger.h>
@@ -76,7 +76,7 @@ static int printk_address(unsigned long address)
76 if (!modname) 76 if (!modname)
77 modname = delim = ""; 77 modname = delim = "";
78 return printk("<0x%p> { %s%s%s%s + 0x%lx }", 78 return printk("<0x%p> { %s%s%s%s + 0x%lx }",
79 (void*)address, delim, modname, delim, symname, 79 (void *)address, delim, modname, delim, symname,
80 (unsigned long)offset); 80 (unsigned long)offset);
81 81
82 } 82 }
@@ -119,7 +119,7 @@ static int printk_address(unsigned long address)
119 119
120 write_unlock_irq(&tasklist_lock); 120 write_unlock_irq(&tasklist_lock);
121 return printk("<0x%p> [ %s + 0x%lx ]", 121 return printk("<0x%p> [ %s + 0x%lx ]",
122 (void*)address, name, offset); 122 (void *)address, name, offset);
123 } 123 }
124 124
125 vml = vml->next; 125 vml = vml->next;
@@ -128,19 +128,9 @@ static int printk_address(unsigned long address)
128 write_unlock_irq(&tasklist_lock); 128 write_unlock_irq(&tasklist_lock);
129 129
130 /* we were unable to find this address anywhere */ 130 /* we were unable to find this address anywhere */
131 return printk("[<0x%p>]", (void*)address); 131 return printk("[<0x%p>]", (void *)address);
132} 132}
133 133
134#define trace_buffer_save(x) \
135 do { \
136 (x) = bfin_read_TBUFCTL(); \
137 bfin_write_TBUFCTL((x) & ~TBUFEN); \
138 } while (0)
139#define trace_buffer_restore(x) \
140 do { \
141 bfin_write_TBUFCTL((x)); \
142 } while (0)
143
144asmlinkage void trap_c(struct pt_regs *fp) 134asmlinkage void trap_c(struct pt_regs *fp)
145{ 135{
146 int j, sig = 0; 136 int j, sig = 0;
@@ -203,15 +193,14 @@ asmlinkage void trap_c(struct pt_regs *fp)
203#else 193#else
204 /* 0x02 - User Defined, Caught by default */ 194 /* 0x02 - User Defined, Caught by default */
205#endif 195#endif
206 /* 0x03 - Atomic test and set */ 196 /* 0x03 - User Defined, userspace stack overflow */
207 case VEC_EXCPT03: 197 case VEC_EXCPT03:
208 info.si_code = SEGV_STACKFLOW; 198 info.si_code = SEGV_STACKFLOW;
209 sig = SIGSEGV; 199 sig = SIGSEGV;
210 printk(KERN_EMERG EXC_0x03); 200 printk(KERN_EMERG EXC_0x03);
211 CHK_DEBUGGER_TRAP(); 201 CHK_DEBUGGER_TRAP();
212 break; 202 break;
213 /* 0x04 - spinlock - handled by _ex_spinlock, 203 /* 0x04 - User Defined, Caught by default */
214 getting here is an error */
215 /* 0x05 - User Defined, Caught by default */ 204 /* 0x05 - User Defined, Caught by default */
216 /* 0x06 - User Defined, Caught by default */ 205 /* 0x06 - User Defined, Caught by default */
217 /* 0x07 - User Defined, Caught by default */ 206 /* 0x07 - User Defined, Caught by default */
@@ -547,29 +536,28 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
547 printk(KERN_EMERG "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n" 536 printk(KERN_EMERG "TEXT = 0x%p-0x%p DATA = 0x%p-0x%p\n"
548 KERN_EMERG "BSS = 0x%p-0x%p USER-STACK = 0x%p\n" 537 KERN_EMERG "BSS = 0x%p-0x%p USER-STACK = 0x%p\n"
549 KERN_EMERG "\n", 538 KERN_EMERG "\n",
550 (void*)current->mm->start_code, 539 (void *)current->mm->start_code,
551 (void*)current->mm->end_code, 540 (void *)current->mm->end_code,
552 (void*)current->mm->start_data, 541 (void *)current->mm->start_data,
553 (void*)current->mm->end_data, 542 (void *)current->mm->end_data,
554 (void*)current->mm->end_data, 543 (void *)current->mm->end_data,
555 (void*)current->mm->brk, 544 (void *)current->mm->brk,
556 (void*)current->mm->start_stack); 545 (void *)current->mm->start_stack);
557 } 546 }
558 547
559 printk(KERN_EMERG "return address: [0x%p]; contents of:", retaddr); 548 printk(KERN_EMERG "return address: [0x%p]; contents of:", retaddr);
560 if (retaddr != 0 && retaddr <= (void*)physical_mem_end 549 if (retaddr != 0 && retaddr <= (void *)physical_mem_end
561#if L1_CODE_LENGTH != 0 550#if L1_CODE_LENGTH != 0
562 /* FIXME: Copy the code out of L1 Instruction SRAM through dma 551 /* FIXME: Copy the code out of L1 Instruction SRAM through dma
563 memcpy. */ 552 memcpy. */
564 && !(retaddr >= (void*)L1_CODE_START 553 && !(retaddr >= (void *)L1_CODE_START
565 && retaddr < (void*)(L1_CODE_START + L1_CODE_LENGTH)) 554 && retaddr < (void *)(L1_CODE_START + L1_CODE_LENGTH))
566#endif 555#endif
567 ) { 556 ) {
568 int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32; 557 int i = ((unsigned int)retaddr & 0xFFFFFFF0) - 32;
569 unsigned short x = 0; 558 unsigned short x = 0;
570 for (; i < ((unsigned int)retaddr & 0xFFFFFFF0 ) + 32 ; 559 for (; i < ((unsigned int)retaddr & 0xFFFFFFF0) + 32; i += 2) {
571 i += 2) { 560 if (!(i & 0xF))
572 if ( !(i & 0xF) )
573 printk(KERN_EMERG "\n" KERN_EMERG 561 printk(KERN_EMERG "\n" KERN_EMERG
574 "0x%08x: ", i); 562 "0x%08x: ", i);
575 563
@@ -588,7 +576,7 @@ void dump_bfin_regs(struct pt_regs *fp, void *retaddr)
588 " The rest of this error" 576 " The rest of this error"
589 " is meanless\n"); 577 " is meanless\n");
590#endif 578#endif
591 if ( i == (unsigned int)retaddr ) 579 if (i == (unsigned int)retaddr)
592 printk("[%04x]", x); 580 printk("[%04x]", x);
593 else 581 else
594 printk(" %04x ", x); 582 printk(" %04x ", x);
@@ -681,8 +669,8 @@ void panic_cplb_error(int cplb_panic, struct pt_regs *fp)
681 break; 669 break;
682 } 670 }
683 671
684 printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void*)bfin_read_DCPLB_FAULT_ADDR()); 672 printk(KERN_EMERG "DCPLB_FAULT_ADDR=%p\n", (void *)bfin_read_DCPLB_FAULT_ADDR());
685 printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void*)bfin_read_ICPLB_FAULT_ADDR()); 673 printk(KERN_EMERG "ICPLB_FAULT_ADDR=%p\n", (void *)bfin_read_ICPLB_FAULT_ADDR());
686 dump_bfin_regs(fp, (void *)fp->retx); 674 dump_bfin_regs(fp, (void *)fp->retx);
687 dump_stack(); 675 dump_stack();
688 panic("Unrecoverable event\n"); 676 panic("Unrecoverable event\n");
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 1ef1e36b3957..d06f860f4790 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -31,6 +31,7 @@
31 31
32#include <asm-generic/vmlinux.lds.h> 32#include <asm-generic/vmlinux.lds.h>
33#include <asm/mem_map.h> 33#include <asm/mem_map.h>
34#include <asm/page.h>
34 35
35OUTPUT_FORMAT("elf32-bfin") 36OUTPUT_FORMAT("elf32-bfin")
36ENTRY(__start) 37ENTRY(__start)
@@ -63,8 +64,8 @@ SECTIONS
63 64
64 .data : 65 .data :
65 { 66 {
67 . = ALIGN(PAGE_SIZE);
66 __sdata = .; 68 __sdata = .;
67 . = ALIGN(0x2000);
68 *(.data.init_task) 69 *(.data.init_task)
69 DATA_DATA 70 DATA_DATA
70 CONSTRUCTORS 71 CONSTRUCTORS
@@ -72,14 +73,14 @@ SECTIONS
72 . = ALIGN(32); 73 . = ALIGN(32);
73 *(.data.cacheline_aligned) 74 *(.data.cacheline_aligned)
74 75
75 . = ALIGN(0x2000); 76 . = ALIGN(PAGE_SIZE);
76 __edata = .; 77 __edata = .;
77 } 78 }
78 79
80 . = ALIGN(PAGE_SIZE);
79 ___init_begin = .; 81 ___init_begin = .;
80 .init : 82 .init :
81 { 83 {
82 . = ALIGN(4096);
83 __sinittext = .; 84 __sinittext = .;
84 *(.init.text) 85 *(.init.text)
85 __einittext = .; 86 __einittext = .;
@@ -152,9 +153,10 @@ SECTIONS
152 __ebss_b_l1 = .; 153 __ebss_b_l1 = .;
153 } 154 }
154 155
155 ___init_end = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1); 156 . = LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1);
157 ___init_end = ALIGN(PAGE_SIZE);
156 158
157 .bss LOADADDR(.data_b_l1) + SIZEOF(.data_b_l1) : 159 .bss ___init_end :
158 { 160 {
159 . = ALIGN(4); 161 . = ALIGN(4);
160 ___bss_start = .; 162 ___bss_start = .;
diff --git a/arch/blackfin/lib/strcmp.c b/arch/blackfin/lib/strcmp.c
index 2ad47c4254ba..4eeefd86907f 100644
--- a/arch/blackfin/lib/strcmp.c
+++ b/arch/blackfin/lib/strcmp.c
@@ -6,6 +6,5 @@
6 6
7int strcmp(const char *dest, const char *src) 7int strcmp(const char *dest, const char *src)
8{ 8{
9 return __inline_strcmp(dest, src); 9 return __inline_strcmp(dest, src);
10} 10}
11
diff --git a/arch/blackfin/lib/strcpy.c b/arch/blackfin/lib/strcpy.c
index 4dc835a8a19b..534589db7256 100644
--- a/arch/blackfin/lib/strcpy.c
+++ b/arch/blackfin/lib/strcpy.c
@@ -6,6 +6,5 @@
6 6
7char *strcpy(char *dest, const char *src) 7char *strcpy(char *dest, const char *src)
8{ 8{
9 return __inline_strcpy(dest, src); 9 return __inline_strcpy(dest, src);
10} 10}
11
diff --git a/arch/blackfin/lib/strncmp.c b/arch/blackfin/lib/strncmp.c
index 947bcfe3f3bb..d791f120bff7 100644
--- a/arch/blackfin/lib/strncmp.c
+++ b/arch/blackfin/lib/strncmp.c
@@ -6,6 +6,5 @@
6 6
7int strncmp(const char *cs, const char *ct, size_t count) 7int strncmp(const char *cs, const char *ct, size_t count)
8{ 8{
9 return __inline_strncmp(cs, ct, count); 9 return __inline_strncmp(cs, ct, count);
10} 10}
11
diff --git a/arch/blackfin/lib/strncpy.c b/arch/blackfin/lib/strncpy.c
index 77a9b2e95097..1fecb5c71ffb 100644
--- a/arch/blackfin/lib/strncpy.c
+++ b/arch/blackfin/lib/strncpy.c
@@ -6,6 +6,5 @@
6 6
7char *strncpy(char *dest, const char *src, size_t n) 7char *strncpy(char *dest, const char *src, size_t n)
8{ 8{
9 return __inline_strncpy(dest, src, n); 9 return __inline_strncpy(dest, src, n);
10} 10}
11
diff --git a/arch/blackfin/mach-bf533/Makefile b/arch/blackfin/mach-bf533/Makefile
index 76d2c2b8579a..8cce1736360d 100644
--- a/arch/blackfin/mach-bf533/Makefile
+++ b/arch/blackfin/mach-bf533/Makefile
@@ -4,6 +4,6 @@
4 4
5extra-y := head.o 5extra-y := head.o
6 6
7obj-y := ints-priority.o 7obj-y := ints-priority.o dma.o
8 8
9obj-$(CONFIG_CPU_FREQ_BF533) += cpu.o 9obj-$(CONFIG_CPU_FREQ) += cpu.o
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index edd31ce4f8d2..4545f363e641 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -34,7 +34,7 @@
34#include <linux/spi/spi.h> 34#include <linux/spi/spi.h>
35#include <linux/spi/flash.h> 35#include <linux/spi/flash.h>
36#include <linux/usb_isp1362.h> 36#include <linux/usb_isp1362.h>
37#include <asm/irq.h> 37#include <linux/irq.h>
38#include <asm/bfin5xx_spi.h> 38#include <asm/bfin5xx_spi.h>
39 39
40/* 40/*
@@ -51,11 +51,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
51 .size = 0x00020000, 51 .size = 0x00020000,
52 .offset = 0, 52 .offset = 0,
53 .mask_flags = MTD_CAP_ROM 53 .mask_flags = MTD_CAP_ROM
54 },{ 54 }, {
55 .name = "kernel", 55 .name = "kernel",
56 .size = 0xe0000, 56 .size = 0xe0000,
57 .offset = 0x20000 57 .offset = 0x20000
58 },{ 58 }, {
59 .name = "file system", 59 .name = "file system",
60 .size = 0x700000, 60 .size = 0x700000,
61 .offset = 0x00100000, 61 .offset = 0x00100000,
@@ -98,7 +98,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
98 .platform_data = &bfin_spi_flash_data, 98 .platform_data = &bfin_spi_flash_data,
99 .controller_data = &spi_flash_chip_info, 99 .controller_data = &spi_flash_chip_info,
100 .mode = SPI_MODE_3, 100 .mode = SPI_MODE_3,
101 },{ 101 }, {
102 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ 102 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
103 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ 103 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
104 .bus_num = 1, /* Framework bus number */ 104 .bus_num = 1, /* Framework bus number */
@@ -145,7 +145,7 @@ static struct resource smc91x_resources[] = {
145 .start = 0x20200300, 145 .start = 0x20200300,
146 .end = 0x20200300 + 16, 146 .end = 0x20200300 + 16,
147 .flags = IORESOURCE_MEM, 147 .flags = IORESOURCE_MEM,
148 },{ 148 }, {
149 .start = IRQ_PF0, 149 .start = IRQ_PF0,
150 .end = IRQ_PF0, 150 .end = IRQ_PF0,
151 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 151 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -194,11 +194,11 @@ static struct resource isp1362_hcd_resources[] = {
194 .start = 0x20308000, 194 .start = 0x20308000,
195 .end = 0x20308000, 195 .end = 0x20308000,
196 .flags = IORESOURCE_MEM, 196 .flags = IORESOURCE_MEM,
197 },{ 197 }, {
198 .start = 0x20308004, 198 .start = 0x20308004,
199 .end = 0x20308004, 199 .end = 0x20308004,
200 .flags = IORESOURCE_MEM, 200 .flags = IORESOURCE_MEM,
201 },{ 201 }, {
202 .start = IRQ_PF4, 202 .start = IRQ_PF4,
203 .end = IRQ_PF4, 203 .end = IRQ_PF4,
204 .flags = IORESOURCE_IRQ, 204 .flags = IORESOURCE_IRQ,
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 0b522d95160d..0000b8f1239c 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -35,7 +35,7 @@
35#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 36#include <linux/spi/flash.h>
37#include <linux/usb_isp1362.h> 37#include <linux/usb_isp1362.h>
38#include <asm/irq.h> 38#include <linux/irq.h>
39#include <asm/bfin5xx_spi.h> 39#include <asm/bfin5xx_spi.h>
40 40
41/* 41/*
@@ -61,7 +61,7 @@ static struct resource smc91x_resources[] = {
61 .start = 0x20310300, 61 .start = 0x20310300,
62 .end = 0x20310300 + 16, 62 .end = 0x20310300 + 16,
63 .flags = IORESOURCE_MEM, 63 .flags = IORESOURCE_MEM,
64 },{ 64 }, {
65 .start = IRQ_PF9, 65 .start = IRQ_PF9,
66 .end = IRQ_PF9, 66 .end = IRQ_PF9,
67 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 67 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -85,11 +85,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
85 .size = 0x00020000, 85 .size = 0x00020000,
86 .offset = 0, 86 .offset = 0,
87 .mask_flags = MTD_CAP_ROM 87 .mask_flags = MTD_CAP_ROM
88 },{ 88 }, {
89 .name = "kernel", 89 .name = "kernel",
90 .size = 0xe0000, 90 .size = 0xe0000,
91 .offset = 0x20000 91 .offset = 0x20000
92 },{ 92 }, {
93 .name = "file system", 93 .name = "file system",
94 .size = 0x700000, 94 .size = 0x700000,
95 .offset = 0x00100000, 95 .offset = 0x00100000,
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c
index c0f43ccfbfb5..9bc1f0d0ab50 100644
--- a/arch/blackfin/mach-bf533/boards/generic_board.c
+++ b/arch/blackfin/mach-bf533/boards/generic_board.c
@@ -30,7 +30,7 @@
30 30
31#include <linux/device.h> 31#include <linux/device.h>
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <asm/irq.h> 33#include <linux/irq.h>
34 34
35/* 35/*
36 * Name the Board for the /proc/cpuinfo 36 * Name the Board for the /proc/cpuinfo
@@ -53,11 +53,11 @@ static struct resource smc91x_resources[] = {
53 .start = 0x20300300, 53 .start = 0x20300300,
54 .end = 0x20300300 + 16, 54 .end = 0x20300300 + 16,
55 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
56 },{ 56 }, {
57 .start = IRQ_PROG_INTB, 57 .start = IRQ_PROG_INTB,
58 .end = IRQ_PROG_INTB, 58 .end = IRQ_PROG_INTB,
59 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 59 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
60 },{ 60 }, {
61 /* 61 /*
62 * denotes the flag pin and is used directly if 62 * denotes the flag pin and is used directly if
63 * CONFIG_IRQCHIP_DEMUX_GPIO is defined. 63 * CONFIG_IRQCHIP_DEMUX_GPIO is defined.
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 9a472fe15833..a9143c4cbdcd 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -37,7 +37,7 @@
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h> 38#include <linux/usb_isp1362.h>
39#endif 39#endif
40#include <asm/irq.h> 40#include <linux/irq.h>
41#include <asm/bfin5xx_spi.h> 41#include <asm/bfin5xx_spi.h>
42 42
43/* 43/*
@@ -62,7 +62,7 @@ static struct resource smc91x_resources[] = {
62 .start = 0x20300300, 62 .start = 0x20300300,
63 .end = 0x20300300 + 16, 63 .end = 0x20300300 + 16,
64 .flags = IORESOURCE_MEM, 64 .flags = IORESOURCE_MEM,
65 },{ 65 }, {
66 .start = IRQ_PF7, 66 .start = IRQ_PF7,
67 .end = IRQ_PF7, 67 .end = IRQ_PF7,
68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -83,7 +83,7 @@ static struct resource net2272_bfin_resources[] = {
83 .start = 0x20300000, 83 .start = 0x20300000,
84 .end = 0x20300000 + 0x100, 84 .end = 0x20300000 + 0x100,
85 .flags = IORESOURCE_MEM, 85 .flags = IORESOURCE_MEM,
86 },{ 86 }, {
87 .start = IRQ_PF10, 87 .start = IRQ_PF10,
88 .end = IRQ_PF10, 88 .end = IRQ_PF10,
89 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 89 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -108,11 +108,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
108 .size = 0x00020000, 108 .size = 0x00020000,
109 .offset = 0, 109 .offset = 0,
110 .mask_flags = MTD_CAP_ROM 110 .mask_flags = MTD_CAP_ROM
111 },{ 111 }, {
112 .name = "kernel", 112 .name = "kernel",
113 .size = 0xe0000, 113 .size = 0xe0000,
114 .offset = 0x20000 114 .offset = 0x20000
115 },{ 115 }, {
116 .name = "file system", 116 .name = "file system",
117 .size = 0x700000, 117 .size = 0x700000,
118 .offset = 0x00100000, 118 .offset = 0x00100000,
@@ -229,19 +229,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
229 229
230#if defined(CONFIG_PBX) 230#if defined(CONFIG_PBX)
231 { 231 {
232 .modalias = "fxs-spi", 232 .modalias = "fxs-spi",
233 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 233 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
234 .bus_num = 1, 234 .bus_num = 1,
235 .chip_select = 3, 235 .chip_select = 3,
236 .controller_data= &spi_si3xxx_chip_info, 236 .controller_data = &spi_si3xxx_chip_info,
237 .mode = SPI_MODE_3, 237 .mode = SPI_MODE_3,
238 }, 238 },
239 { 239 {
240 .modalias = "fxo-spi", 240 .modalias = "fxo-spi",
241 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 241 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
242 .bus_num = 1, 242 .bus_num = 1,
243 .chip_select = 2, 243 .chip_select = 2,
244 .controller_data= &spi_si3xxx_chip_info, 244 .controller_data = &spi_si3xxx_chip_info,
245 .mode = SPI_MODE_3, 245 .mode = SPI_MODE_3,
246 }, 246 },
247#endif 247#endif
diff --git a/arch/blackfin/mach-bf533/cpu.c b/arch/blackfin/mach-bf533/cpu.c
index 99547c4c290e..6fd9cfd0a31b 100644
--- a/arch/blackfin/mach-bf533/cpu.c
+++ b/arch/blackfin/mach-bf533/cpu.c
@@ -79,8 +79,7 @@ static int bf533_target(struct cpufreq_policy *policy,
79 int i; 79 int i;
80 80
81 struct cpufreq_freqs freqs; 81 struct cpufreq_freqs freqs;
82 if (cpufreq_frequency_table_target 82 if (cpufreq_frequency_table_target(policy, bf533_freq_table, target_freq, relation, &index))
83 (policy, bf533_freq_table, target_freq, relation, &index))
84 return -EINVAL; 83 return -EINVAL;
85 cclk_mhz = bf533_freq_table[index].frequency; 84 cclk_mhz = bf533_freq_table[index].frequency;
86 vco_mhz = bf533_freq_table[index].index; 85 vco_mhz = bf533_freq_table[index].index;
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
new file mode 100644
index 000000000000..6c909cf4f7bf
--- /dev/null
+++ b/arch/blackfin/mach-bf533/dma.c
@@ -0,0 +1,95 @@
1/*
2 * File: arch/blackfin/mach-bf533/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#include <asm/blackfin.h>
30#include <asm/dma.h>
31
32struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
33 (struct dma_register *) DMA0_NEXT_DESC_PTR,
34 (struct dma_register *) DMA1_NEXT_DESC_PTR,
35 (struct dma_register *) DMA2_NEXT_DESC_PTR,
36 (struct dma_register *) DMA3_NEXT_DESC_PTR,
37 (struct dma_register *) DMA4_NEXT_DESC_PTR,
38 (struct dma_register *) DMA5_NEXT_DESC_PTR,
39 (struct dma_register *) DMA6_NEXT_DESC_PTR,
40 (struct dma_register *) DMA7_NEXT_DESC_PTR,
41 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
42 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
43 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
44 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
45};
46
47int channel2irq(unsigned int channel)
48{
49 int ret_irq = -1;
50
51 switch (channel) {
52 case CH_PPI:
53 ret_irq = IRQ_PPI;
54 break;
55
56 case CH_SPORT0_RX:
57 ret_irq = IRQ_SPORT0_RX;
58 break;
59
60 case CH_SPORT0_TX:
61 ret_irq = IRQ_SPORT0_TX;
62 break;
63
64 case CH_SPORT1_RX:
65 ret_irq = IRQ_SPORT1_RX;
66 break;
67
68 case CH_SPORT1_TX:
69 ret_irq = IRQ_SPORT1_TX;
70 break;
71
72 case CH_SPI:
73 ret_irq = IRQ_SPI;
74 break;
75
76 case CH_UART_RX:
77 ret_irq = IRQ_UART_RX;
78 break;
79
80 case CH_UART_TX:
81 ret_irq = IRQ_UART_TX;
82 break;
83
84 case CH_MEM_STREAM0_SRC:
85 case CH_MEM_STREAM0_DEST:
86 ret_irq = IRQ_MEM_DMA0;
87 break;
88
89 case CH_MEM_STREAM1_SRC:
90 case CH_MEM_STREAM1_DEST:
91 ret_irq = IRQ_MEM_DMA1;
92 break;
93 }
94 return ret_irq;
95}
diff --git a/arch/blackfin/mach-bf533/head.S b/arch/blackfin/mach-bf533/head.S
index 7e2aa8d0f44f..7dd0e9c3a936 100644
--- a/arch/blackfin/mach-bf533/head.S
+++ b/arch/blackfin/mach-bf533/head.S
@@ -30,6 +30,7 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
33#if CONFIG_BFIN_KERNEL_CLOCK 34#if CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach/mem_init.h> 35#include <asm/mach/mem_init.h>
35#endif 36#endif
@@ -96,6 +97,10 @@ ENTRY(__start)
96 M2 = r0; 97 M2 = r0;
97 M3 = r0; 98 M3 = r0;
98 99
100 trace_buffer_start(p0,r0);
101 P0 = R1;
102 R0 = R1;
103
99#if CONFIG_DEBUG_KERNEL_START 104#if CONFIG_DEBUG_KERNEL_START
100 105
101/* 106/*
diff --git a/arch/blackfin/mach-bf533/ints-priority.c b/arch/blackfin/mach-bf533/ints-priority.c
index a3e1789167be..7d79e0f9503d 100644
--- a/arch/blackfin/mach-bf533/ints-priority.c
+++ b/arch/blackfin/mach-bf533/ints-priority.c
@@ -28,8 +28,8 @@
28 */ 28 */
29 29
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/irq.h>
31#include <asm/blackfin.h> 32#include <asm/blackfin.h>
32#include <asm/irq.h>
33 33
34void program_IAR(void) 34void program_IAR(void)
35{ 35{
diff --git a/arch/blackfin/mach-bf537/Makefile b/arch/blackfin/mach-bf537/Makefile
index f32d44215bb7..7e7c9c8ac5b2 100644
--- a/arch/blackfin/mach-bf537/Makefile
+++ b/arch/blackfin/mach-bf537/Makefile
@@ -4,6 +4,6 @@
4 4
5extra-y := head.o 5extra-y := head.o
6 6
7obj-y := ints-priority.o 7obj-y := ints-priority.o dma.o
8 8
9obj-$(CONFIG_CPU_FREQ) += cpu.o 9obj-$(CONFIG_CPU_FREQ) += cpu.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index 6a60618a78ec..a8f947b72754 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -35,7 +35,7 @@
35#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 36#include <linux/spi/flash.h>
37#include <linux/usb_isp1362.h> 37#include <linux/usb_isp1362.h>
38#include <asm/irq.h> 38#include <linux/irq.h>
39#include <asm/bfin5xx_spi.h> 39#include <asm/bfin5xx_spi.h>
40 40
41/* 41/*
@@ -53,11 +53,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
53 .size = 0x00020000, 53 .size = 0x00020000,
54 .offset = 0, 54 .offset = 0,
55 .mask_flags = MTD_CAP_ROM 55 .mask_flags = MTD_CAP_ROM
56 },{ 56 }, {
57 .name = "kernel", 57 .name = "kernel",
58 .size = 0xe0000, 58 .size = 0xe0000,
59 .offset = 0x20000 59 .offset = 0x20000
60 },{ 60 }, {
61 .name = "file system", 61 .name = "file system",
62 .size = 0x700000, 62 .size = 0x700000,
63 .offset = 0x00100000, 63 .offset = 0x00100000,
@@ -202,7 +202,7 @@ static struct resource smc91x_resources[] = {
202 .start = 0x20200300, 202 .start = 0x20200300,
203 .end = 0x20200300 + 16, 203 .end = 0x20200300 + 16,
204 .flags = IORESOURCE_MEM, 204 .flags = IORESOURCE_MEM,
205 },{ 205 }, {
206 .start = IRQ_PF14, 206 .start = IRQ_PF14,
207 .end = IRQ_PF14, 207 .end = IRQ_PF14,
208 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 208 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -223,11 +223,11 @@ static struct resource isp1362_hcd_resources[] = {
223 .start = 0x20308000, 223 .start = 0x20308000,
224 .end = 0x20308000, 224 .end = 0x20308000,
225 .flags = IORESOURCE_MEM, 225 .flags = IORESOURCE_MEM,
226 },{ 226 }, {
227 .start = 0x20308004, 227 .start = 0x20308004,
228 .end = 0x20308004, 228 .end = 0x20308004,
229 .flags = IORESOURCE_MEM, 229 .flags = IORESOURCE_MEM,
230 },{ 230 }, {
231 .start = IRQ_PG15, 231 .start = IRQ_PG15,
232 .end = IRQ_PG15, 232 .end = IRQ_PG15,
233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 233 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -262,7 +262,7 @@ static struct resource net2272_bfin_resources[] = {
262 .start = 0x20200000, 262 .start = 0x20200000,
263 .end = 0x20200000 + 0x100, 263 .end = 0x20200000 + 0x100,
264 .flags = IORESOURCE_MEM, 264 .flags = IORESOURCE_MEM,
265 },{ 265 }, {
266 .start = IRQ_PF7, 266 .start = IRQ_PF7,
267 .end = IRQ_PF7, 267 .end = IRQ_PF7,
268 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 268 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -283,7 +283,7 @@ static struct resource bfin_uart_resources[] = {
283 .start = 0xFFC00400, 283 .start = 0xFFC00400,
284 .end = 0xFFC004FF, 284 .end = 0xFFC004FF,
285 .flags = IORESOURCE_MEM, 285 .flags = IORESOURCE_MEM,
286 },{ 286 }, {
287 .start = 0xFFC02000, 287 .start = 0xFFC02000,
288 .end = 0xFFC020FF, 288 .end = 0xFFC020FF,
289 .flags = IORESOURCE_MEM, 289 .flags = IORESOURCE_MEM,
diff --git a/arch/blackfin/mach-bf537/boards/eth_mac.c b/arch/blackfin/mach-bf537/boards/eth_mac.c
index e129a08d63de..a725cc8a9290 100644
--- a/arch/blackfin/mach-bf537/boards/eth_mac.c
+++ b/arch/blackfin/mach-bf537/boards/eth_mac.c
@@ -20,8 +20,7 @@
20#include <linux/module.h> 20#include <linux/module.h>
21#include <asm/blackfin.h> 21#include <asm/blackfin.h>
22 22
23#if defined(CONFIG_GENERIC_BOARD) \ 23#if defined(CONFIG_GENERIC_BOARD) || defined(CONFIG_BFIN537_STAMP)
24 || defined(CONFIG_BFIN537_STAMP)
25 24
26/* 25/*
27 * Currently the MAC address is saved in Flash by U-Boot 26 * Currently the MAC address is saved in Flash by U-Boot
@@ -43,7 +42,7 @@ void get_bf537_ether_addr(char *addr)
43 */ 42 */
44void get_bf537_ether_addr(char *addr) 43void get_bf537_ether_addr(char *addr)
45{ 44{
46 printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n",__FILE__); 45 printk(KERN_WARNING "%s: No valid Ethernet MAC address found\n", __FILE__);
47} 46}
48 47
49#endif 48#endif
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
index fd57e7439e0f..648d984e98d6 100644
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ b/arch/blackfin/mach-bf537/boards/generic_board.c
@@ -35,9 +35,9 @@
35#include <linux/spi/spi.h> 35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h> 36#include <linux/spi/flash.h>
37#include <linux/usb_isp1362.h> 37#include <linux/usb_isp1362.h>
38#include <asm/irq.h> 38#include <linux/irq.h>
39#include <asm/bfin5xx_spi.h>
40#include <linux/usb_sl811.h> 39#include <linux/usb_sl811.h>
40#include <asm/bfin5xx_spi.h>
41 41
42/* 42/*
43 * Name the Board for the /proc/cpuinfo 43 * Name the Board for the /proc/cpuinfo
@@ -54,19 +54,19 @@ static struct resource bfin_pcmcia_cf_resources[] = {
54 .start = 0x20310000, /* IO PORT */ 54 .start = 0x20310000, /* IO PORT */
55 .end = 0x20312000, 55 .end = 0x20312000,
56 .flags = IORESOURCE_MEM, 56 .flags = IORESOURCE_MEM,
57 },{ 57 }, {
58 .start = 0x20311000, /* Attribute Memory */ 58 .start = 0x20311000, /* Attribute Memory */
59 .end = 0x20311FFF, 59 .end = 0x20311FFF,
60 .flags = IORESOURCE_MEM, 60 .flags = IORESOURCE_MEM,
61 },{ 61 }, {
62 .start = IRQ_PROG_INTA, 62 .start = IRQ_PROG_INTA,
63 .end = IRQ_PROG_INTA, 63 .end = IRQ_PROG_INTA,
64 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 64 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
65 },{ 65 }, {
66 .start = IRQ_PF4, 66 .start = IRQ_PF4,
67 .end = IRQ_PF4, 67 .end = IRQ_PF4,
68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
69 },{ 69 }, {
70 .start = 6, /* Card Detect PF6 */ 70 .start = 6, /* Card Detect PF6 */
71 .end = 6, 71 .end = 6,
72 .flags = IORESOURCE_IRQ, 72 .flags = IORESOURCE_IRQ,
@@ -95,11 +95,11 @@ static struct resource smc91x_resources[] = {
95 .start = 0x20300300, 95 .start = 0x20300300,
96 .end = 0x20300300 + 16, 96 .end = 0x20300300 + 16,
97 .flags = IORESOURCE_MEM, 97 .flags = IORESOURCE_MEM,
98 },{ 98 }, {
99 .start = IRQ_PROG_INTB, 99 .start = IRQ_PROG_INTB,
100 .end = IRQ_PROG_INTB, 100 .end = IRQ_PROG_INTB,
101 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 101 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
102 },{ 102 }, {
103 /* 103 /*
104 * denotes the flag pin and is used directly if 104 * denotes the flag pin and is used directly if
105 * CONFIG_IRQCHIP_DEMUX_GPIO is defined. 105 * CONFIG_IRQCHIP_DEMUX_GPIO is defined.
@@ -123,15 +123,15 @@ static struct resource sl811_hcd_resources[] = {
123 .start = 0x20340000, 123 .start = 0x20340000,
124 .end = 0x20340000, 124 .end = 0x20340000,
125 .flags = IORESOURCE_MEM, 125 .flags = IORESOURCE_MEM,
126 },{ 126 }, {
127 .start = 0x20340004, 127 .start = 0x20340004,
128 .end = 0x20340004, 128 .end = 0x20340004,
129 .flags = IORESOURCE_MEM, 129 .flags = IORESOURCE_MEM,
130 },{ 130 }, {
131 .start = IRQ_PROG_INTA, 131 .start = IRQ_PROG_INTA,
132 .end = IRQ_PROG_INTA, 132 .end = IRQ_PROG_INTA,
133 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 133 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
134 },{ 134 }, {
135 .start = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO, 135 .start = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO,
136 .end = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO, 136 .end = IRQ_PF0 + CONFIG_USB_SL811_BFIN_GPIO,
137 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 137 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -179,15 +179,15 @@ static struct resource isp1362_hcd_resources[] = {
179 .start = 0x20360000, 179 .start = 0x20360000,
180 .end = 0x20360000, 180 .end = 0x20360000,
181 .flags = IORESOURCE_MEM, 181 .flags = IORESOURCE_MEM,
182 },{ 182 }, {
183 .start = 0x20360004, 183 .start = 0x20360004,
184 .end = 0x20360004, 184 .end = 0x20360004,
185 .flags = IORESOURCE_MEM, 185 .flags = IORESOURCE_MEM,
186 },{ 186 }, {
187 .start = IRQ_PROG_INTA, 187 .start = IRQ_PROG_INTA,
188 .end = IRQ_PROG_INTA, 188 .end = IRQ_PROG_INTA,
189 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 189 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
190 },{ 190 }, {
191 .start = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO, 191 .start = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO,
192 .end = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO, 192 .end = IRQ_PF0 + CONFIG_USB_ISP1362_BFIN_GPIO,
193 .flags = IORESOURCE_IRQ, 193 .flags = IORESOURCE_IRQ,
@@ -228,7 +228,7 @@ static struct resource net2272_bfin_resources[] = {
228 .start = 0x20300000, 228 .start = 0x20300000,
229 .end = 0x20300000 + 0x100, 229 .end = 0x20300000 + 0x100,
230 .flags = IORESOURCE_MEM, 230 .flags = IORESOURCE_MEM,
231 },{ 231 }, {
232 .start = IRQ_PF7, 232 .start = IRQ_PF7,
233 .end = IRQ_PF7, 233 .end = IRQ_PF7,
234 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 234 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -253,11 +253,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
253 .size = 0x00020000, 253 .size = 0x00020000,
254 .offset = 0, 254 .offset = 0,
255 .mask_flags = MTD_CAP_ROM 255 .mask_flags = MTD_CAP_ROM
256 },{ 256 }, {
257 .name = "kernel", 257 .name = "kernel",
258 .size = 0xe0000, 258 .size = 0xe0000,
259 .offset = 0x20000 259 .offset = 0x20000
260 },{ 260 }, {
261 .name = "file system", 261 .name = "file system",
262 .size = 0x700000, 262 .size = 0x700000,
263 .offset = 0x00100000, 263 .offset = 0x00100000,
@@ -375,7 +375,7 @@ static struct resource bfin_uart_resources[] = {
375 .start = 0xFFC00400, 375 .start = 0xFFC00400,
376 .end = 0xFFC004FF, 376 .end = 0xFFC004FF,
377 .flags = IORESOURCE_MEM, 377 .flags = IORESOURCE_MEM,
378 },{ 378 }, {
379 .start = 0xFFC02000, 379 .start = 0xFFC02000,
380 .end = 0xFFC020FF, 380 .end = 0xFFC020FF,
381 .flags = IORESOURCE_MEM, 381 .flags = IORESOURCE_MEM,
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 8aaf76dfce80..8806f1230f2d 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -37,7 +37,7 @@
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h> 38#include <linux/usb_isp1362.h>
39#endif 39#endif
40#include <asm/irq.h> 40#include <linux/irq.h>
41#include <asm/bfin5xx_spi.h> 41#include <asm/bfin5xx_spi.h>
42#include <linux/usb_sl811.h> 42#include <linux/usb_sl811.h>
43 43
@@ -58,15 +58,15 @@ static struct resource bfin_pcmcia_cf_resources[] = {
58 .start = 0x20310000, /* IO PORT */ 58 .start = 0x20310000, /* IO PORT */
59 .end = 0x20312000, 59 .end = 0x20312000,
60 .flags = IORESOURCE_MEM, 60 .flags = IORESOURCE_MEM,
61 },{ 61 }, {
62 .start = 0x20311000, /* Attribute Memory */ 62 .start = 0x20311000, /* Attribute Memory */
63 .end = 0x20311FFF, 63 .end = 0x20311FFF,
64 .flags = IORESOURCE_MEM, 64 .flags = IORESOURCE_MEM,
65 },{ 65 }, {
66 .start = IRQ_PF4, 66 .start = IRQ_PF4,
67 .end = IRQ_PF4, 67 .end = IRQ_PF4,
68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 68 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
69 },{ 69 }, {
70 .start = 6, /* Card Detect PF6 */ 70 .start = 6, /* Card Detect PF6 */
71 .end = 6, 71 .end = 6,
72 .flags = IORESOURCE_IRQ, 72 .flags = IORESOURCE_IRQ,
@@ -95,7 +95,7 @@ static struct resource smc91x_resources[] = {
95 .start = 0x20300300, 95 .start = 0x20300300,
96 .end = 0x20300300 + 16, 96 .end = 0x20300300 + 16,
97 .flags = IORESOURCE_MEM, 97 .flags = IORESOURCE_MEM,
98 },{ 98 }, {
99 99
100 .start = IRQ_PF7, 100 .start = IRQ_PF7,
101 .end = IRQ_PF7, 101 .end = IRQ_PF7,
@@ -116,11 +116,11 @@ static struct resource sl811_hcd_resources[] = {
116 .start = 0x20340000, 116 .start = 0x20340000,
117 .end = 0x20340000, 117 .end = 0x20340000,
118 .flags = IORESOURCE_MEM, 118 .flags = IORESOURCE_MEM,
119 },{ 119 }, {
120 .start = 0x20340004, 120 .start = 0x20340004,
121 .end = 0x20340004, 121 .end = 0x20340004,
122 .flags = IORESOURCE_MEM, 122 .flags = IORESOURCE_MEM,
123 },{ 123 }, {
124 .start = CONFIG_USB_SL811_BFIN_IRQ, 124 .start = CONFIG_USB_SL811_BFIN_IRQ,
125 .end = CONFIG_USB_SL811_BFIN_IRQ, 125 .end = CONFIG_USB_SL811_BFIN_IRQ,
126 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 126 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -167,11 +167,11 @@ static struct resource isp1362_hcd_resources[] = {
167 .start = 0x20360000, 167 .start = 0x20360000,
168 .end = 0x20360000, 168 .end = 0x20360000,
169 .flags = IORESOURCE_MEM, 169 .flags = IORESOURCE_MEM,
170 },{ 170 }, {
171 .start = 0x20360004, 171 .start = 0x20360004,
172 .end = 0x20360004, 172 .end = 0x20360004,
173 .flags = IORESOURCE_MEM, 173 .flags = IORESOURCE_MEM,
174 },{ 174 }, {
175 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, 175 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
176 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, 176 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
177 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 177 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -212,7 +212,7 @@ static struct resource net2272_bfin_resources[] = {
212 .start = 0x20300000, 212 .start = 0x20300000,
213 .end = 0x20300000 + 0x100, 213 .end = 0x20300000 + 0x100,
214 .flags = IORESOURCE_MEM, 214 .flags = IORESOURCE_MEM,
215 },{ 215 }, {
216 .start = IRQ_PF7, 216 .start = IRQ_PF7,
217 .end = IRQ_PF7, 217 .end = IRQ_PF7,
218 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 218 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -238,11 +238,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
238 .size = 0x00020000, 238 .size = 0x00020000,
239 .offset = 0, 239 .offset = 0,
240 .mask_flags = MTD_CAP_ROM 240 .mask_flags = MTD_CAP_ROM
241 },{ 241 }, {
242 .name = "kernel", 242 .name = "kernel",
243 .size = 0xe0000, 243 .size = 0xe0000,
244 .offset = 0x20000 244 .offset = 0x20000
245 },{ 245 }, {
246 .name = "file system", 246 .name = "file system",
247 .size = 0x700000, 247 .size = 0x700000,
248 .offset = 0x00100000, 248 .offset = 0x00100000,
@@ -294,16 +294,6 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
294}; 294};
295#endif 295#endif
296 296
297#if defined(CONFIG_PBX)
298static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
299 .ctl_reg = 0x4, /* send zero */
300 .enable_dma = 0,
301 .bits_per_word = 8,
302 .cs_change_per_word = 1,
303};
304#endif
305
306
307#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 297#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
308static struct bfin5xx_spi_chip spi_ad7877_chip_info = { 298static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
309 .cs_change_per_word = 1, 299 .cs_change_per_word = 1,
@@ -392,24 +382,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
392 .mode = SPI_MODE_3, 382 .mode = SPI_MODE_3,
393 }, 383 },
394#endif 384#endif
395#if defined(CONFIG_PBX)
396 {
397 .modalias = "fxs-spi",
398 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
399 .bus_num = 1,
400 .chip_select = 3,
401 .controller_data= &spi_si3xxx_chip_info,
402 .mode = SPI_MODE_3,
403 },
404 {
405 .modalias = "fxo-spi",
406 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
407 .bus_num = 1,
408 .chip_select = 2,
409 .controller_data= &spi_si3xxx_chip_info,
410 .mode = SPI_MODE_3,
411 },
412#endif
413#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 385#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
414{ 386{
415 .modalias = "ad7877", 387 .modalias = "ad7877",
@@ -451,7 +423,7 @@ static struct resource bfin_uart_resources[] = {
451 .start = 0xFFC00400, 423 .start = 0xFFC00400,
452 .end = 0xFFC004FF, 424 .end = 0xFFC004FF,
453 .flags = IORESOURCE_MEM, 425 .flags = IORESOURCE_MEM,
454 },{ 426 }, {
455 .start = 0xFFC02000, 427 .start = 0xFFC02000,
456 .end = 0xFFC020FF, 428 .end = 0xFFC020FF,
457 .flags = IORESOURCE_MEM, 429 .flags = IORESOURCE_MEM,
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 3a29b4d15f25..9c43d7756510 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -37,12 +37,10 @@
37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 37#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
38#include <linux/usb_isp1362.h> 38#include <linux/usb_isp1362.h>
39#endif 39#endif
40#include <asm/irq.h>
41#include <linux/irq.h> 40#include <linux/irq.h>
42#include <linux/interrupt.h> 41#include <linux/interrupt.h>
43#include <asm/bfin5xx_spi.h>
44#include <linux/usb_sl811.h> 42#include <linux/usb_sl811.h>
45 43#include <asm/bfin5xx_spi.h>
46#include <linux/spi/ad7877.h> 44#include <linux/spi/ad7877.h>
47 45
48/* 46/*
@@ -85,7 +83,7 @@ static struct platform_device *bfin_isp1761_devices[] = {
85 83
86int __init bfin_isp1761_init(void) 84int __init bfin_isp1761_init(void)
87{ 85{
88 unsigned int num_devices=ARRAY_SIZE(bfin_isp1761_devices); 86 unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
89 87
90 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); 88 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
91 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); 89 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
@@ -107,15 +105,15 @@ static struct resource bfin_pcmcia_cf_resources[] = {
107 .start = 0x20310000, /* IO PORT */ 105 .start = 0x20310000, /* IO PORT */
108 .end = 0x20312000, 106 .end = 0x20312000,
109 .flags = IORESOURCE_MEM, 107 .flags = IORESOURCE_MEM,
110 },{ 108 }, {
111 .start = 0x20311000, /* Attribute Memory */ 109 .start = 0x20311000, /* Attribute Memory */
112 .end = 0x20311FFF, 110 .end = 0x20311FFF,
113 .flags = IORESOURCE_MEM, 111 .flags = IORESOURCE_MEM,
114 },{ 112 }, {
115 .start = IRQ_PF4, 113 .start = IRQ_PF4,
116 .end = IRQ_PF4, 114 .end = IRQ_PF4,
117 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 115 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
118 },{ 116 }, {
119 .start = 6, /* Card Detect PF6 */ 117 .start = 6, /* Card Detect PF6 */
120 .end = 6, 118 .end = 6,
121 .flags = IORESOURCE_IRQ, 119 .flags = IORESOURCE_IRQ,
@@ -144,7 +142,7 @@ static struct resource smc91x_resources[] = {
144 .start = 0x20300300, 142 .start = 0x20300300,
145 .end = 0x20300300 + 16, 143 .end = 0x20300300 + 16,
146 .flags = IORESOURCE_MEM, 144 .flags = IORESOURCE_MEM,
147 },{ 145 }, {
148 146
149 .start = IRQ_PF7, 147 .start = IRQ_PF7,
150 .end = IRQ_PF7, 148 .end = IRQ_PF7,
@@ -159,17 +157,39 @@ static struct platform_device smc91x_device = {
159}; 157};
160#endif 158#endif
161 159
160#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
161static struct resource dm9000_resources[] = {
162 [0] = {
163 .start = 0x203FB800,
164 .end = 0x203FB800 + 8,
165 .flags = IORESOURCE_MEM,
166 },
167 [1] = {
168 .start = IRQ_PF9,
169 .end = IRQ_PF9,
170 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
171 },
172};
173
174static struct platform_device dm9000_device = {
175 .name = "dm9000",
176 .id = -1,
177 .num_resources = ARRAY_SIZE(dm9000_resources),
178 .resource = dm9000_resources,
179};
180#endif
181
162#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) 182#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
163static struct resource sl811_hcd_resources[] = { 183static struct resource sl811_hcd_resources[] = {
164 { 184 {
165 .start = 0x20340000, 185 .start = 0x20340000,
166 .end = 0x20340000, 186 .end = 0x20340000,
167 .flags = IORESOURCE_MEM, 187 .flags = IORESOURCE_MEM,
168 },{ 188 }, {
169 .start = 0x20340004, 189 .start = 0x20340004,
170 .end = 0x20340004, 190 .end = 0x20340004,
171 .flags = IORESOURCE_MEM, 191 .flags = IORESOURCE_MEM,
172 },{ 192 }, {
173 .start = CONFIG_USB_SL811_BFIN_IRQ, 193 .start = CONFIG_USB_SL811_BFIN_IRQ,
174 .end = CONFIG_USB_SL811_BFIN_IRQ, 194 .end = CONFIG_USB_SL811_BFIN_IRQ,
175 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 195 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -216,11 +236,11 @@ static struct resource isp1362_hcd_resources[] = {
216 .start = 0x20360000, 236 .start = 0x20360000,
217 .end = 0x20360000, 237 .end = 0x20360000,
218 .flags = IORESOURCE_MEM, 238 .flags = IORESOURCE_MEM,
219 },{ 239 }, {
220 .start = 0x20360004, 240 .start = 0x20360004,
221 .end = 0x20360004, 241 .end = 0x20360004,
222 .flags = IORESOURCE_MEM, 242 .flags = IORESOURCE_MEM,
223 },{ 243 }, {
224 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, 244 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
225 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, 245 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
226 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 246 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -261,7 +281,7 @@ static struct resource net2272_bfin_resources[] = {
261 .start = 0x20300000, 281 .start = 0x20300000,
262 .end = 0x20300000 + 0x100, 282 .end = 0x20300000 + 0x100,
263 .flags = IORESOURCE_MEM, 283 .flags = IORESOURCE_MEM,
264 },{ 284 }, {
265 .start = IRQ_PF7, 285 .start = IRQ_PF7,
266 .end = IRQ_PF7, 286 .end = IRQ_PF7,
267 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 287 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -287,11 +307,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
287 .size = 0x00020000, 307 .size = 0x00020000,
288 .offset = 0, 308 .offset = 0,
289 .mask_flags = MTD_CAP_ROM 309 .mask_flags = MTD_CAP_ROM
290 },{ 310 }, {
291 .name = "kernel", 311 .name = "kernel",
292 .size = 0xe0000, 312 .size = 0xe0000,
293 .offset = 0x20000 313 .offset = 0x20000
294 },{ 314 }, {
295 .name = "file system", 315 .name = "file system",
296 .size = 0x700000, 316 .size = 0x700000,
297 .offset = 0x00100000, 317 .offset = 0x00100000,
@@ -361,7 +381,6 @@ static struct bfin5xx_spi_chip ad5304_chip_info = {
361 381
362#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) 382#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
363static struct bfin5xx_spi_chip spi_ad7877_chip_info = { 383static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
364// .cs_change_per_word = 1,
365 .enable_dma = 0, 384 .enable_dma = 0,
366 .bits_per_word = 16, 385 .bits_per_word = 16,
367}; 386};
@@ -449,19 +468,19 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
449#endif 468#endif
450#if defined(CONFIG_PBX) 469#if defined(CONFIG_PBX)
451 { 470 {
452 .modalias = "fxs-spi", 471 .modalias = "fxs-spi",
453 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 472 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
454 .bus_num = 1, 473 .bus_num = 1,
455 .chip_select = 3, 474 .chip_select = 3,
456 .controller_data= &spi_si3xxx_chip_info, 475 .controller_data = &spi_si3xxx_chip_info,
457 .mode = SPI_MODE_3, 476 .mode = SPI_MODE_3,
458 }, 477 },
459 { 478 {
460 .modalias = "fxo-spi", 479 .modalias = "fxo-spi",
461 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 480 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
462 .bus_num = 1, 481 .bus_num = 1,
463 .chip_select = 2, 482 .chip_select = 2,
464 .controller_data= &spi_si3xxx_chip_info, 483 .controller_data = &spi_si3xxx_chip_info,
465 .mode = SPI_MODE_3, 484 .mode = SPI_MODE_3,
466 }, 485 },
467#endif 486#endif
@@ -516,7 +535,7 @@ static struct resource bfin_uart_resources[] = {
516 .start = 0xFFC00400, 535 .start = 0xFFC00400,
517 .end = 0xFFC004FF, 536 .end = 0xFFC004FF,
518 .flags = IORESOURCE_MEM, 537 .flags = IORESOURCE_MEM,
519 },{ 538 }, {
520 .start = 0xFFC02000, 539 .start = 0xFFC02000,
521 .end = 0xFFC020FF, 540 .end = 0xFFC020FF,
522 .flags = IORESOURCE_MEM, 541 .flags = IORESOURCE_MEM,
@@ -571,6 +590,10 @@ static struct platform_device *stamp_devices[] __initdata = {
571 &smc91x_device, 590 &smc91x_device,
572#endif 591#endif
573 592
593#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
594 &dm9000_device,
595#endif
596
574#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 597#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
575 &bfin_mac_device, 598 &bfin_mac_device,
576#endif 599#endif
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
new file mode 100644
index 000000000000..706cb97b0265
--- /dev/null
+++ b/arch/blackfin/mach-bf537/dma.c
@@ -0,0 +1,115 @@
1/*
2 * File: arch/blackfin/mach-bf537/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#include <asm/blackfin.h>
30#include <asm/dma.h>
31
32struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
33 (struct dma_register *) DMA0_NEXT_DESC_PTR,
34 (struct dma_register *) DMA1_NEXT_DESC_PTR,
35 (struct dma_register *) DMA2_NEXT_DESC_PTR,
36 (struct dma_register *) DMA3_NEXT_DESC_PTR,
37 (struct dma_register *) DMA4_NEXT_DESC_PTR,
38 (struct dma_register *) DMA5_NEXT_DESC_PTR,
39 (struct dma_register *) DMA6_NEXT_DESC_PTR,
40 (struct dma_register *) DMA7_NEXT_DESC_PTR,
41 (struct dma_register *) DMA8_NEXT_DESC_PTR,
42 (struct dma_register *) DMA9_NEXT_DESC_PTR,
43 (struct dma_register *) DMA10_NEXT_DESC_PTR,
44 (struct dma_register *) DMA11_NEXT_DESC_PTR,
45 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
46 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
47 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
48 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
49};
50
51int channel2irq(unsigned int channel)
52{
53 int ret_irq = -1;
54
55 switch (channel) {
56 case CH_PPI:
57 ret_irq = IRQ_PPI;
58 break;
59
60 case CH_EMAC_RX:
61 ret_irq = IRQ_MAC_RX;
62 break;
63
64 case CH_EMAC_TX:
65 ret_irq = IRQ_MAC_TX;
66 break;
67
68 case CH_UART1_RX:
69 ret_irq = IRQ_UART1_RX;
70 break;
71
72 case CH_UART1_TX:
73 ret_irq = IRQ_UART1_TX;
74 break;
75
76 case CH_SPORT0_RX:
77 ret_irq = IRQ_SPORT0_RX;
78 break;
79
80 case CH_SPORT0_TX:
81 ret_irq = IRQ_SPORT0_TX;
82 break;
83
84 case CH_SPORT1_RX:
85 ret_irq = IRQ_SPORT1_RX;
86 break;
87
88 case CH_SPORT1_TX:
89 ret_irq = IRQ_SPORT1_TX;
90 break;
91
92 case CH_SPI:
93 ret_irq = IRQ_SPI;
94 break;
95
96 case CH_UART_RX:
97 ret_irq = IRQ_UART_RX;
98 break;
99
100 case CH_UART_TX:
101 ret_irq = IRQ_UART_TX;
102 break;
103
104 case CH_MEM_STREAM0_SRC:
105 case CH_MEM_STREAM0_DEST:
106 ret_irq = IRQ_MEM_DMA0;
107 break;
108
109 case CH_MEM_STREAM1_SRC:
110 case CH_MEM_STREAM1_DEST:
111 ret_irq = IRQ_MEM_DMA1;
112 break;
113 }
114 return ret_irq;
115}
diff --git a/arch/blackfin/mach-bf537/head.S b/arch/blackfin/mach-bf537/head.S
index 7d902bbd860f..429c8a1019da 100644
--- a/arch/blackfin/mach-bf537/head.S
+++ b/arch/blackfin/mach-bf537/head.S
@@ -30,6 +30,8 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34
33#if CONFIG_BFIN_KERNEL_CLOCK 35#if CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach/mem_init.h> 36#include <asm/mach/mem_init.h>
35#endif 37#endif
@@ -93,6 +95,10 @@ ENTRY(__start)
93 M2 = r0; 95 M2 = r0;
94 M3 = r0; 96 M3 = r0;
95 97
98 trace_buffer_start(p0,r0);
99 P0 = R1;
100 R0 = R1;
101
96 /* Turn off the icache */ 102 /* Turn off the icache */
97 p0.l = (IMEM_CONTROL & 0xFFFF); 103 p0.l = (IMEM_CONTROL & 0xFFFF);
98 p0.h = (IMEM_CONTROL >> 16); 104 p0.h = (IMEM_CONTROL >> 16);
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
index 2dbf3df465d1..a8b915f202ec 100644
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -28,8 +28,8 @@
28 */ 28 */
29 29
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/irq.h>
31#include <asm/blackfin.h> 32#include <asm/blackfin.h>
32#include <asm/irq.h>
33 33
34void program_IAR(void) 34void program_IAR(void)
35{ 35{
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
new file mode 100644
index 000000000000..e78b03d56c7c
--- /dev/null
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -0,0 +1,316 @@
1if (BF54x)
2
3menu "BF548 Specific Configuration"
4
5comment "Interrupt Priority Assignment"
6menu "Priority"
7
8config IRQ_PLL_WAKEUP
9 int "IRQ_PLL_WAKEUP"
10 default 7
11config IRQ_DMAC0_ERR
12 int "IRQ_DMAC0_ERR"
13 default 7
14config IRQ_EPPI0_ERR
15 int "IRQ_EPPI0_ERR"
16 default 7
17config IRQ_SPORT0_ERR
18 int "IRQ_SPORT0_ERR"
19 default 7
20config IRQ_SPORT1_ERR
21 int "IRQ_SPORT1_ERR"
22 default 7
23config IRQ_SPI0_ERR
24 int "IRQ_SPI0_ERR"
25 default 7
26config IRQ_UART0_ERR
27 int "IRQ_UART0_ERR"
28 default 7
29config IRQ_RTC
30 int "IRQ_RTC"
31 default 8
32config IRQ_EPPI0
33 int "IRQ_EPPI0"
34 default 8
35config IRQ_SPORT0_RX
36 int "IRQ_SPORT0_RX"
37 default 9
38config IRQ_SPORT0_TX
39 int "IRQ_SPORT0_TX"
40 default 9
41config IRQ_SPORT1_RX
42 int "IRQ_SPORT1_RX"
43 default 9
44config IRQ_SPORT1_TX
45 int "IRQ_SPORT1_TX"
46 default 9
47config IRQ_SPI0
48 int "IRQ_SPI0"
49 default 10
50config IRQ_UART0_RX
51 int "IRQ_UART0_RX"
52 default 10
53config IRQ_UART0_TX
54 int "IRQ_UART0_TX"
55 default 10
56config IRQ_TIMER8
57 int "IRQ_TIMER8"
58 default 11
59config IRQ_TIMER9
60 int "IRQ_TIMER9"
61 default 11
62config IRQ_TIMER10
63 int "IRQ_TIMER10"
64 default 11
65config IRQ_PINT0
66 int "IRQ_PINT0"
67 default 12
68config IRQ_PINT1
69 int "IRQ_PINT0"
70 default 12
71config IRQ_MDMAS0
72 int "IRQ_MDMAS0"
73 default 13
74config IRQ_MDMAS1
75 int "IRQ_DMDMAS1"
76 default 13
77config IRQ_WATCHDOG
78 int "IRQ_WATCHDOG"
79 default 13
80config IRQ_DMAC1_ERR
81 int "IRQ_DMAC1_ERR"
82 default 7
83config IRQ_SPORT2_ERR
84 int "IRQ_SPORT2_ERR"
85 default 7
86config IRQ_SPORT3_ERR
87 int "IRQ_SPORT3_ERR"
88 default 7
89config IRQ_MXVR_DATA
90 int "IRQ MXVR Data"
91 default 7
92config IRQ_SPI1_ERR
93 int "IRQ_SPI1_ERR"
94 default 7
95config IRQ_SPI2_ERR
96 int "IRQ_SPI2_ERR"
97 default 7
98config IRQ_UART1_ERR
99 int "IRQ_UART1_ERR"
100 default 7
101config IRQ_UART2_ERR
102 int "IRQ_UART2_ERR"
103 default 7
104config IRQ_CAN0_ERR
105 int "IRQ_CAN0_ERR"
106 default 7
107config IRQ_SPORT2_RX
108 int "IRQ_SPORT2_RX"
109 default 9
110config IRQ_SPORT2_TX
111 int "IRQ_SPORT2_TX"
112 default 9
113config IRQ_SPORT3_RX
114 int "IRQ_SPORT3_RX"
115 default 9
116config IRQ_SPORT3_TX
117 int "IRQ_SPORT3_TX"
118 default 9
119config IRQ_EPPI1
120 int "IRQ_EPPI1"
121 default 9
122config IRQ_EPPI2
123 int "IRQ_EPPI2"
124 default 9
125config IRQ_SPI1
126 int "IRQ_SPI1"
127 default 10
128config IRQ_SPI2
129 int "IRQ_SPI2"
130 default 10
131config IRQ_UART1_RX
132 int "IRQ_UART1_RX"
133 default 10
134config IRQ_UART1_TX
135 int "IRQ_UART1_TX"
136 default 10
137config IRQ_ATAPI_RX
138 int "IRQ_ATAPI_RX"
139 default 10
140config IRQ_ATAPI_TX
141 int "IRQ_ATAPI_TX"
142 default 10
143config IRQ_TWI0
144 int "IRQ_TWI0"
145 default 11
146config IRQ_TWI1
147 int "IRQ_TWI1"
148 default 11
149config IRQ_CAN0_RX
150 int "IRQ_CAN_RX"
151 default 11
152config IRQ_CAN0_TX
153 int "IRQ_CAN_TX"
154 default 11
155config IRQ_MDMAS2
156 int "IRQ_MDMAS2"
157 default 13
158config IRQ_MDMAS3
159 int "IRQ_DMMAS3"
160 default 13
161config IRQ_MXVR_ERR
162 int "IRQ_MXVR_ERR"
163 default 11
164config IRQ_MXVR_MSG
165 int "IRQ_MXVR_MSG"
166 default 11
167config IRQ_MXVR_PKT
168 int "IRQ_MXVR_PKT"
169 default 11
170config IRQ_EPPI1_ERR
171 int "IRQ_EPPI1_ERR"
172 default 7
173config IRQ_EPPI2_ERR
174 int "IRQ_EPPI2_ERR"
175 default 7
176config IRQ_UART3_ERR
177 int "IRQ_UART3_ERR"
178 default 7
179config IRQ_HOST_ERR
180 int "IRQ_HOST_ERR"
181 default 7
182config IRQ_PIXC_ERR
183 int "IRQ_PIXC_ERR"
184 default 7
185config IRQ_NFC_ERR
186 int "IRQ_NFC_ERR"
187 default 7
188config IRQ_ATAPI_ERR
189 int "IRQ_ATAPI_ERR"
190 default 7
191config IRQ_CAN1_ERR
192 int "IRQ_CAN1_ERR"
193 default 7
194config IRQ_HS_DMA_ERR
195 int "IRQ Handshake DMA Status"
196 default 7
197config IRQ_PIXC_IN0
198 int "IRQ PIXC IN0"
199 default 8
200config IRQ_PIXC_IN1
201 int "IRQ PIXC IN1"
202 default 8
203config IRQ_PIXC_OUT
204 int "IRQ PIXC OUT"
205 default 8
206config IRQ_SDH
207 int "IRQ SDH"
208 default 8
209config IRQ_CNT
210 int "IRQ CNT"
211 default 8
212config IRQ_KEY
213 int "IRQ KEY"
214 default 8
215config IRQ_CAN1_RX
216 int "IRQ CAN1 RX"
217 default 11
218config IRQ_CAN1_TX
219 int "IRQ_CAN1_TX"
220 default 11
221config IRQ_SDH_MASK0
222 int "IRQ_SDH_MASK0"
223 default 11
224config IRQ_SDH_MASK1
225 int "IRQ_SDH_MASK1"
226 default 11
227config IRQ_USB_INT0
228 int "IRQ USB INT0"
229 default 11
230config IRQ_USB_INT1
231 int "IRQ USB INT1"
232 default 11
233config IRQ_USB_INT2
234 int "IRQ USB INT2"
235 default 11
236config IRQ_USB_DMA
237 int "IRQ USB DMA"
238 default 11
239config IRQ_OTPSEC
240 int "IRQ OPTSEC"
241 default 11
242config IRQ_TIMER0
243 int "IRQ_TIMER0"
244 default 11
245config IRQ_TIMER1
246 int "IRQ_TIMER1"
247 default 11
248config IRQ_TIMER2
249 int "IRQ_TIMER2"
250 default 11
251config IRQ_TIMER3
252 int "IRQ_TIMER3"
253 default 11
254config IRQ_TIMER4
255 int "IRQ_TIMER4"
256 default 11
257config IRQ_TIMER5
258 int "IRQ_TIMER5"
259 default 11
260config IRQ_TIMER6
261 int "IRQ_TIMER6"
262 default 11
263config IRQ_TIMER7
264 int "IRQ_TIMER7"
265 default 11
266config IRQ_PINT2
267 int "IRQ_PIN2"
268 default 11
269config IRQ_PINT3
270 int "IRQ_PIN3"
271 default 11
272
273 help
274 Enter the priority numbers between 7-13 ONLY. Others are Reserved.
275 This applies to all the above. It is not recommended to assign the
276 highest priority number 7 to UART or any other device.
277
278endmenu
279
280comment "Pin Interrupt to Port Assignment"
281menu "Assignment"
282
283config PINTx_REASSIGN
284 bool "Reprogram PINT Assignment"
285 default n
286 help
287 The interrupt assignment registers controls the pin-to-interrupt
288 assignment in a byte-wide manner. Each option allows you to select
289 a set of pins (High/Low Byte) of an specific Port being mapped
290 to one of the four PIN Interrupts IRQ_PINTx.
291
292 You shouldn't change any of these unless you know exactly what you're doing.
293 Please consult the Blackfin BF54x Processor Hardware Reference Manual.
294
295config PINT0_ASSIGN
296 hex "PINT0_ASSIGN"
297 depends on PINTx_REASSIGN
298 default 0x00000101
299config PINT1_ASSIGN
300 hex "PINT1_ASSIGN"
301 depends on PINTx_REASSIGN
302 default 0x01010000
303config PINT2_ASSIGN
304 hex "PINT2_ASSIGN"
305 depends on PINTx_REASSIGN
306 default 0x00000101
307config PINT3_ASSIGN
308 hex "PINT3_ASSIGN"
309 depends on PINTx_REASSIGN
310 default 0x02020303
311
312endmenu
313
314endmenu
315
316endif
diff --git a/arch/blackfin/mach-bf548/Makefile b/arch/blackfin/mach-bf548/Makefile
new file mode 100644
index 000000000000..060ad78ebf1d
--- /dev/null
+++ b/arch/blackfin/mach-bf548/Makefile
@@ -0,0 +1,9 @@
1#
2# arch/blackfin/mach-bf537/Makefile
3#
4
5extra-y := head.o
6
7obj-y := ints-priority.o dma.o gpio.o
8
9obj-$(CONFIG_CPU_FREQ) += cpu.o
diff --git a/arch/blackfin/mach-bf548/boards/Makefile b/arch/blackfin/mach-bf548/boards/Makefile
new file mode 100644
index 000000000000..486e07c99a51
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/Makefile
@@ -0,0 +1,5 @@
1#
2# arch/blackfin/mach-bf548/boards/Makefile
3#
4
5obj-$(CONFIG_BFIN548_EZKIT) += ezkit.o led.o
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
new file mode 100644
index 000000000000..96ad95fab1a8
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -0,0 +1,114 @@
1/*
2 * File: arch/blackfin/mach-bf548/boards/ezkit.c
3 * Based on: arch/blackfin/mach-bf537/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2007 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/mtd/mtd.h>
34#include <linux/mtd/partitions.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/flash.h>
37#include <linux/irq.h>
38#include <linux/irq.h>
39#include <linux/interrupt.h>
40#include <asm/bfin5xx_spi.h>
41
42/*
43 * Name the Board for the /proc/cpuinfo
44 */
45char *bfin_board_name = "ADSP-BF548-EZKIT";
46
47/*
48 * Driver needs to know address, irq and flag pin.
49 */
50
51#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
52static struct platform_device rtc_device = {
53 .name = "rtc-bfin",
54 .id = -1,
55};
56#endif
57
58#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
59static struct resource bfin_uart_resources[] = {
60#ifdef CONFIG_SERIAL_BFIN_UART0
61 {
62 .start = 0xFFC00400,
63 .end = 0xFFC004FF,
64 .flags = IORESOURCE_MEM,
65 },
66#endif
67#ifdef CONFIG_SERIAL_BFIN_UART1
68 {
69 .start = 0xFFC02000,
70 .end = 0xFFC020FF,
71 .flags = IORESOURCE_MEM,
72 },
73#endif
74#ifdef CONFIG_SERIAL_BFIN_UART2
75 {
76 .start = 0xFFC02100,
77 .end = 0xFFC021FF,
78 .flags = IORESOURCE_MEM,
79 },
80#endif
81#ifdef CONFIG_SERIAL_BFIN_UART3
82 {
83 .start = 0xFFC03100,
84 .end = 0xFFC031FF,
85 },
86#endif
87};
88
89static struct platform_device bfin_uart_device = {
90 .name = "bfin-uart",
91 .id = 1,
92 .num_resources = ARRAY_SIZE(bfin_uart_resources),
93 .resource = bfin_uart_resources,
94};
95#endif
96
97static struct platform_device *ezkit_devices[] __initdata = {
98#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
99 &rtc_device,
100#endif
101
102#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
103 &bfin_uart_device,
104#endif
105};
106
107static int __init stamp_init(void)
108{
109 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
110 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
111 return 0;
112}
113
114arch_initcall(stamp_init);
diff --git a/arch/blackfin/mach-bf548/boards/led.S b/arch/blackfin/mach-bf548/boards/led.S
new file mode 100644
index 000000000000..f47daf3770d0
--- /dev/null
+++ b/arch/blackfin/mach-bf548/boards/led.S
@@ -0,0 +1,172 @@
1/****************************************************
2 * LED1 ---- PG6 LED2 ---- PG7 *
3 * LED3 ---- PG8 LED4 ---- PG9 *
4 * LED5 ---- PG10 LED6 ---- PG11 *
5 ****************************************************/
6
7#include <linux/linkage.h>
8#include <asm/blackfin.h>
9
10/* All functions in this file save the registers they uses.
11 So there is no need to save any registers before calling them. */
12
13 .text;
14
15/* Initialize LEDs. */
16
17ENTRY(_led_init)
18 LINK 0;
19 [--SP] = P0;
20 [--SP] = R0;
21 [--SP] = R1;
22 [--SP] = R2;
23 R1 = (PG6|PG7|PG8|PG9|PG10|PG11)(Z);
24 R2 = ~R1;
25
26 P0.H = hi(PORTG_FER);
27 P0.L = lo(PORTG_FER);
28 R0 = W[P0](Z);
29 SSYNC;
30 R0 = R0 & R2;
31 W[P0] = R0.L;
32 SSYNC;
33
34 P0.H = hi(PORTG_DIR_SET);
35 P0.L = lo(PORTG_DIR_SET);
36 W[P0] = R1.L;
37 SSYNC;
38
39 P0.H = hi(PORTG_INEN);
40 P0.L = lo(PORTG_INEN);
41 R0 = W[P0](Z);
42 SSYNC;
43 R0 = R0 & R2;
44 W[P0] = R0.L;
45 SSYNC;
46
47 R2 = [SP++];
48 R1 = [SP++];
49 R0 = [SP++];
50 P0 = [SP++];
51 RTS;
52 .size _led_init, .-_led_init
53
54/* Set one LED on. Leave other LEDs unchanged.
55 It expects the LED number passed through R0. */
56
57ENTRY(_led_on)
58 LINK 0;
59 [--SP] = P0;
60 [--SP] = R1;
61 CALL _led_init;
62 R1 = 1;
63 R0 += 5;
64 R1 <<= R0;
65 P0.H = hi(PORTG_SET);
66 P0.L = lo(PORTG_SET);
67 W[P0] = R1.L;
68 SSYNC;
69 R1 = [SP++];
70 P0 = [SP++];
71 UNLINK;
72 RTS;
73 .size _led_on, .-_led_on
74
75/* Set one LED off. Leave other LEDs unchanged. */
76
77ENTRY(_led_off)
78 LINK 0;
79 [--SP] = P0;
80 [--SP] = R1;
81 CALL _led_init;
82 R1 = 1;
83 R0 += 5;
84 R1 <<= R0;
85 P0.H = hi(PORTG_CLEAR);
86 P0.L = lo(PORTG_CLEAR);
87 W[P0] = R1.L;
88 SSYNC;
89 R1 = [SP++];
90 P0 = [SP++];
91 UNLINK;
92 RTS;
93 .size _led_off, .-_led_off
94
95/* Toggle one LED. Leave other LEDs unchanged. */
96
97ENTRY(_led_toggle)
98 LINK 0;
99 [--SP] = P0;
100 [--SP] = R1;
101 CALL _led_init;
102 R1 = 1;
103 R0 += 5;
104 R1 <<= R0;
105 P0.H = hi(PORTG);
106 P0.L = lo(PORTG);
107 R0 = W[P0](Z);
108 SSYNC;
109 R0 = R0 ^ R1;
110 W[P0] = R0.L;
111 SSYNC;
112 R1 = [SP++];
113 P0 = [SP++];
114 UNLINK;
115 RTS;
116 .size _led_toggle, .-_led_toggle
117
118/* Display the number using LEDs in binary format. */
119
120ENTRY(_led_disp_num)
121 LINK 0;
122 [--SP] = P0;
123 [--SP] = R1;
124 [--SP] = R2;
125 CALL _led_init;
126 R1 = 0x3f(X);
127 R0 = R0 & R1;
128 R2 = 6(X);
129 R0 <<= R2;
130 R1 <<= R2;
131 P0.H = hi(PORTG);
132 P0.L = lo(PORTG);
133 R2 = W[P0](Z);
134 SSYNC;
135 R1 = ~R1;
136 R2 = R2 & R1;
137 R2 = R2 | R0;
138 W[P0] = R2.L;
139 SSYNC;
140 R2 = [SP++];
141 R1 = [SP++];
142 P0 = [SP++];
143 UNLINK;
144 RTS;
145 .size _led_disp_num, .-_led_disp_num
146
147/* Toggle the number using LEDs in binary format. */
148
149ENTRY(_led_toggle_num)
150 LINK 0;
151 [--SP] = P0;
152 [--SP] = R1;
153 [--SP] = R2;
154 CALL _led_init;
155 R1 = 0x3f(X);
156 R0 = R0 & R1;
157 R1 = 6(X);
158 R0 <<= R1;
159 P0.H = hi(PORTG);
160 P0.L = lo(PORTG);
161 R1 = W[P0](Z);
162 SSYNC;
163 R1 = R1 ^ R0;
164 W[P0] = R1.L;
165 SSYNC;
166 R2 = [SP++];
167 R1 = [SP++];
168 P0 = [SP++];
169 UNLINK;
170 RTS;
171 .size _led_toggle_num, .-_led_toggle_num
172
diff --git a/arch/blackfin/mach-bf548/cpu.c b/arch/blackfin/mach-bf548/cpu.c
new file mode 100644
index 000000000000..4298a3ccfbfc
--- /dev/null
+++ b/arch/blackfin/mach-bf548/cpu.c
@@ -0,0 +1,159 @@
1/*
2 * File: arch/blackfin/mach-bf548/cpu.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: clock scaling for the bf54x
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/init.h>
33#include <linux/cpufreq.h>
34#include <asm/dpmc.h>
35#include <linux/fs.h>
36#include <asm/bfin-global.h>
37
38/* CONFIG_CLKIN_HZ=25000000 */
39#define VCO5 (CONFIG_CLKIN_HZ*45)
40#define VCO4 (CONFIG_CLKIN_HZ*36)
41#define VCO3 (CONFIG_CLKIN_HZ*27)
42#define VCO2 (CONFIG_CLKIN_HZ*18)
43#define VCO1 (CONFIG_CLKIN_HZ*9)
44#define VCO(x) VCO##x
45
46#define MFREQ(x) {VCO(x),VCO(x)/4},{VCO(x),VCO(x)/2},{VCO(x),VCO(x)}
47/* frequency */
48static struct cpufreq_frequency_table bf548_freq_table[] = {
49 MFREQ(1),
50 MFREQ(3),
51 {VCO4, VCO4 / 2}, {VCO4, VCO4},
52 MFREQ(5),
53 {0, CPUFREQ_TABLE_END},
54};
55
56/*
57 * dpmc_fops->ioctl()
58 * static int dpmc_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
59 */
60static int bf548_getfreq(unsigned int cpu)
61{
62 unsigned long cclk_mhz;
63
64 /* The driver only support single cpu */
65 if (cpu == 0)
66 dpmc_fops.ioctl(NULL, NULL, IOCTL_GET_CORECLOCK, &cclk_mhz);
67 else
68 cclk_mhz = -1;
69
70 return cclk_mhz;
71}
72
73static int bf548_target(struct cpufreq_policy *policy,
74 unsigned int target_freq, unsigned int relation)
75{
76 unsigned long cclk_mhz;
77 unsigned long vco_mhz;
78 unsigned long flags;
79 unsigned int index;
80 struct cpufreq_freqs freqs;
81
82 if (cpufreq_frequency_table_target(policy, bf548_freq_table, target_freq, relation, &index))
83 return -EINVAL;
84
85 cclk_mhz = bf548_freq_table[index].frequency;
86 vco_mhz = bf548_freq_table[index].index;
87
88 dpmc_fops.ioctl(NULL, NULL, IOCTL_CHANGE_FREQUENCY, &vco_mhz);
89 freqs.old = bf548_getfreq(0);
90 freqs.new = cclk_mhz;
91 freqs.cpu = 0;
92
93 pr_debug("cclk begin change to cclk %d,vco=%d,index=%d,target=%d,oldfreq=%d\n",
94 cclk_mhz, vco_mhz, index, target_freq, freqs.old);
95
96 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
97 local_irq_save(flags);
98 dpmc_fops.ioctl(NULL, NULL, IOCTL_SET_CCLK, &cclk_mhz);
99 local_irq_restore(flags);
100 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
101
102 vco_mhz = get_vco();
103 cclk_mhz = get_cclk();
104 return 0;
105}
106
107/* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
108 * this platform, anyway.
109 */
110static int bf548_verify_speed(struct cpufreq_policy *policy)
111{
112 return cpufreq_frequency_table_verify(policy, &bf548_freq_table);
113}
114
115static int __init __bf548_cpu_init(struct cpufreq_policy *policy)
116{
117 if (policy->cpu != 0)
118 return -EINVAL;
119
120 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
121
122 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
123 /*Now ,only support one cpu */
124 policy->cur = bf548_getfreq(0);
125 cpufreq_frequency_table_get_attr(bf548_freq_table, policy->cpu);
126 return cpufreq_frequency_table_cpuinfo(policy, bf548_freq_table);
127}
128
129static struct freq_attr *bf548_freq_attr[] = {
130 &cpufreq_freq_attr_scaling_available_freqs,
131 NULL,
132};
133
134static struct cpufreq_driver bf548_driver = {
135 .verify = bf548_verify_speed,
136 .target = bf548_target,
137 .get = bf548_getfreq,
138 .init = __bf548_cpu_init,
139 .name = "bf548",
140 .owner = THIS_MODULE,
141 .attr = bf548_freq_attr,
142};
143
144static int __init bf548_cpu_init(void)
145{
146 return cpufreq_register_driver(&bf548_driver);
147}
148
149static void __exit bf548_cpu_exit(void)
150{
151 cpufreq_unregister_driver(&bf548_driver);
152}
153
154MODULE_AUTHOR("Mickael Kang");
155MODULE_DESCRIPTION("cpufreq driver for BF548 CPU");
156MODULE_LICENSE("GPL");
157
158module_init(bf548_cpu_init);
159module_exit(bf548_cpu_exit);
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
new file mode 100644
index 000000000000..a8184113be48
--- /dev/null
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -0,0 +1,156 @@
1/*
2 * File: arch/blackfin/mach-bf561/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <asm/blackfin.h>
31#include <asm/dma.h>
32
33 struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
34 (struct dma_register *) DMA0_NEXT_DESC_PTR,
35 (struct dma_register *) DMA1_NEXT_DESC_PTR,
36 (struct dma_register *) DMA2_NEXT_DESC_PTR,
37 (struct dma_register *) DMA3_NEXT_DESC_PTR,
38 (struct dma_register *) DMA4_NEXT_DESC_PTR,
39 (struct dma_register *) DMA5_NEXT_DESC_PTR,
40 (struct dma_register *) DMA6_NEXT_DESC_PTR,
41 (struct dma_register *) DMA7_NEXT_DESC_PTR,
42 (struct dma_register *) DMA8_NEXT_DESC_PTR,
43 (struct dma_register *) DMA9_NEXT_DESC_PTR,
44 (struct dma_register *) DMA10_NEXT_DESC_PTR,
45 (struct dma_register *) DMA11_NEXT_DESC_PTR,
46 (struct dma_register *) DMA12_NEXT_DESC_PTR,
47 (struct dma_register *) DMA13_NEXT_DESC_PTR,
48 (struct dma_register *) DMA14_NEXT_DESC_PTR,
49 (struct dma_register *) DMA15_NEXT_DESC_PTR,
50 (struct dma_register *) DMA16_NEXT_DESC_PTR,
51 (struct dma_register *) DMA17_NEXT_DESC_PTR,
52 (struct dma_register *) DMA18_NEXT_DESC_PTR,
53 (struct dma_register *) DMA19_NEXT_DESC_PTR,
54 (struct dma_register *) DMA20_NEXT_DESC_PTR,
55 (struct dma_register *) DMA21_NEXT_DESC_PTR,
56 (struct dma_register *) DMA22_NEXT_DESC_PTR,
57 (struct dma_register *) DMA23_NEXT_DESC_PTR,
58 (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
59 (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
60 (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
61 (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
62 (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
63 (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
64 (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
65 (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
66};
67
68int channel2irq(unsigned int channel)
69{
70 int ret_irq = -1;
71
72 switch (channel) {
73 case CH_SPORT0_RX:
74 ret_irq = IRQ_SPORT0_RX;
75 break;
76 case CH_SPORT0_TX:
77 ret_irq = IRQ_SPORT0_TX;
78 break;
79 case CH_SPORT1_RX:
80 ret_irq = IRQ_SPORT1_RX;
81 break;
82 case CH_SPORT1_TX:
83 ret_irq = IRQ_SPORT1_TX;
84 case CH_SPI0:
85 ret_irq = IRQ_SPI0;
86 break;
87 case CH_SPI1:
88 ret_irq = IRQ_SPI1;
89 break;
90 case CH_UART0_RX:
91 ret_irq = IRQ_UART_RX;
92 break;
93 case CH_UART0_TX:
94 ret_irq = IRQ_UART_TX;
95 break;
96 case CH_UART1_RX:
97 ret_irq = IRQ_UART_RX;
98 break;
99 case CH_UART1_TX:
100 ret_irq = IRQ_UART_TX;
101 break;
102 case CH_EPPI0:
103 ret_irq = IRQ_EPPI0;
104 break;
105 case CH_EPPI1:
106 ret_irq = IRQ_EPPI1;
107 break;
108 case CH_EPPI2:
109 ret_irq = IRQ_EPPI2;
110 break;
111 case CH_PIXC_IMAGE:
112 ret_irq = IRQ_PIXC_IN0;
113 break;
114 case CH_PIXC_OVERLAY:
115 ret_irq = IRQ_PIXC_IN1;
116 break;
117 case CH_PIXC_OUTPUT:
118 ret_irq = IRQ_PIXC_OUT;
119 break;
120 case CH_SPORT2_RX:
121 ret_irq = IRQ_SPORT2_RX;
122 break;
123 case CH_SPORT2_TX:
124 ret_irq = IRQ_SPORT2_TX;
125 break;
126 case CH_SPORT3_RX:
127 ret_irq = IRQ_SPORT3_RX;
128 break;
129 case CH_SPORT3_TX:
130 ret_irq = IRQ_SPORT3_TX;
131 break;
132 case CH_SDH:
133 ret_irq = IRQ_SDH;
134 break;
135 case CH_SPI2:
136 ret_irq = IRQ_SPI2;
137 break;
138 case CH_MEM_STREAM0_SRC:
139 case CH_MEM_STREAM0_DEST:
140 ret_irq = IRQ_MDMAS0;
141 break;
142 case CH_MEM_STREAM1_SRC:
143 case CH_MEM_STREAM1_DEST:
144 ret_irq = IRQ_MDMAS1;
145 break;
146 case CH_MEM_STREAM2_SRC:
147 case CH_MEM_STREAM2_DEST:
148 ret_irq = IRQ_MDMAS2;
149 break;
150 case CH_MEM_STREAM3_SRC:
151 case CH_MEM_STREAM3_DEST:
152 ret_irq = IRQ_MDMAS3;
153 break;
154 }
155 return ret_irq;
156}
diff --git a/arch/blackfin/mach-bf548/gpio.c b/arch/blackfin/mach-bf548/gpio.c
new file mode 100644
index 000000000000..0da5f0003b8c
--- /dev/null
+++ b/arch/blackfin/mach-bf548/gpio.c
@@ -0,0 +1,323 @@
1/*
2 * File: arch/blackfin/mach-bf548/gpio.c
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description: GPIO Abstraction Layer
8 *
9 * Modified:
10 * Copyright 2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/err.h>
32#include <asm/blackfin.h>
33#include <asm/gpio.h>
34#include <asm/portmux.h>
35#include <linux/irq.h>
36
37static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
38 (struct gpio_port_t *)PORTA_FER,
39 (struct gpio_port_t *)PORTB_FER,
40 (struct gpio_port_t *)PORTC_FER,
41 (struct gpio_port_t *)PORTD_FER,
42 (struct gpio_port_t *)PORTE_FER,
43 (struct gpio_port_t *)PORTF_FER,
44 (struct gpio_port_t *)PORTG_FER,
45 (struct gpio_port_t *)PORTH_FER,
46 (struct gpio_port_t *)PORTI_FER,
47 (struct gpio_port_t *)PORTJ_FER,
48};
49
50static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
51static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
52
53inline int check_gpio(unsigned short gpio)
54{
55 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
56 || gpio == GPIO_PH14 || gpio == GPIO_PH15
57 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
58 || gpio > MAX_BLACKFIN_GPIOS)
59 return -EINVAL;
60 return 0;
61}
62
63inline void portmux_setup(unsigned short portno, unsigned short function)
64{
65 u32 pmux;
66
67 pmux = gpio_array[gpio_bank(portno)]->port_mux;
68
69 pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
70 pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
71
72 gpio_array[gpio_bank(portno)]->port_mux = pmux;
73
74}
75
76inline u16 get_portmux(unsigned short portno)
77{
78 u32 pmux;
79
80 pmux = gpio_array[gpio_bank(portno)]->port_mux;
81
82 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
83
84}
85
86static void port_setup(unsigned short gpio, unsigned short usage)
87{
88 if (usage == GPIO_USAGE) {
89 if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio))
90 printk(KERN_WARNING
91 "bfin-gpio: Possible Conflict with Peripheral "
92 "usage and GPIO %d detected!\n", gpio);
93 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
94 } else
95 gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio);
96 SSYNC();
97}
98
99static int __init bfin_gpio_init(void)
100{
101 printk(KERN_INFO "Blackfin GPIO Controller\n");
102
103 return 0;
104}
105
106arch_initcall(bfin_gpio_init);
107
108int peripheral_request(unsigned short per, const char *label)
109{
110 unsigned long flags;
111 unsigned short ident = P_IDENT(per);
112
113 if (!(per & P_DEFINED))
114 return -ENODEV;
115
116 if (check_gpio(ident) < 0)
117 return -EINVAL;
118
119 local_irq_save(flags);
120
121 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
122 printk(KERN_ERR
123 "%s: Peripheral %d is already reserved as GPIO!\n",
124 __FUNCTION__, per);
125 dump_stack();
126 local_irq_restore(flags);
127 return -EBUSY;
128 }
129
130 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
131
132 u16 funct = get_portmux(ident);
133
134 if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
135 printk(KERN_ERR
136 "%s: Peripheral %d is already reserved!\n",
137 __FUNCTION__, per);
138 dump_stack();
139 local_irq_restore(flags);
140 return -EBUSY;
141 }
142 }
143
144 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
145
146 portmux_setup(ident, P_FUNCT2MUX(per));
147 port_setup(ident, PERIPHERAL_USAGE);
148
149 local_irq_restore(flags);
150
151 return 0;
152}
153EXPORT_SYMBOL(peripheral_request);
154
155int peripheral_request_list(unsigned short per[], const char *label)
156{
157
158 u16 cnt;
159 int ret;
160
161 for (cnt = 0; per[cnt] != 0; cnt++) {
162 ret = peripheral_request(per[cnt], label);
163 if (ret < 0)
164 return ret;
165 }
166
167 return 0;
168}
169EXPORT_SYMBOL(peripheral_request_list);
170
171void peripheral_free(unsigned short per)
172{
173 unsigned long flags;
174 unsigned short ident = P_IDENT(per);
175
176 if (!(per & P_DEFINED))
177 return;
178
179 if (check_gpio(ident) < 0)
180 return;
181
182 local_irq_save(flags);
183
184 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
185 printk(KERN_ERR "bfin-gpio: Peripheral %d wasn't reserved!\n", per);
186 dump_stack();
187 local_irq_restore(flags);
188 return;
189 }
190
191 if (!(per & P_MAYSHARE)) {
192 port_setup(ident, GPIO_USAGE);
193 }
194
195 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
196
197 local_irq_restore(flags);
198}
199EXPORT_SYMBOL(peripheral_free);
200
201void peripheral_free_list(unsigned short per[])
202{
203 u16 cnt;
204
205 for (cnt = 0; per[cnt] != 0; cnt++) {
206 peripheral_free(per[cnt]);
207 }
208
209}
210EXPORT_SYMBOL(peripheral_free_list);
211
212/***********************************************************
213*
214* FUNCTIONS: Blackfin GPIO Driver
215*
216* INPUTS/OUTPUTS:
217* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
218*
219*
220* DESCRIPTION: Blackfin GPIO Driver API
221*
222* CAUTION:
223*************************************************************
224* MODIFICATION HISTORY :
225**************************************************************/
226
227int gpio_request(unsigned short gpio, const char *label)
228{
229 unsigned long flags;
230
231 if (check_gpio(gpio) < 0)
232 return -EINVAL;
233
234 local_irq_save(flags);
235
236 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
237 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
238 dump_stack();
239 local_irq_restore(flags);
240 return -EBUSY;
241 }
242
243 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
244 printk(KERN_ERR
245 "bfin-gpio: GPIO %d is already reserved as Peripheral!\n", gpio);
246 dump_stack();
247 local_irq_restore(flags);
248 return -EBUSY;
249 }
250
251 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
252
253 local_irq_restore(flags);
254
255 port_setup(gpio, GPIO_USAGE);
256
257 return 0;
258}
259EXPORT_SYMBOL(gpio_request);
260
261void gpio_free(unsigned short gpio)
262{
263 unsigned long flags;
264
265 if (check_gpio(gpio) < 0)
266 return;
267
268 local_irq_save(flags);
269
270 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
271 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
272 dump_stack();
273 local_irq_restore(flags);
274 return;
275 }
276
277 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
278
279 local_irq_restore(flags);
280}
281EXPORT_SYMBOL(gpio_free);
282
283void gpio_direction_input(unsigned short gpio)
284{
285 unsigned long flags;
286
287 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
288
289 local_irq_save(flags);
290 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
291 gpio_array[gpio_bank(gpio)]->port_inen |= gpio_bit(gpio);
292 local_irq_restore(flags);
293}
294EXPORT_SYMBOL(gpio_direction_input);
295
296void gpio_direction_output(unsigned short gpio)
297{
298 unsigned long flags;
299
300 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
301
302 local_irq_save(flags);
303 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
304 gpio_array[gpio_bank(gpio)]->port_dir_set = gpio_bit(gpio);
305 local_irq_restore(flags);
306}
307EXPORT_SYMBOL(gpio_direction_output);
308
309void gpio_set_value(unsigned short gpio, unsigned short arg)
310{
311 if (arg)
312 gpio_array[gpio_bank(gpio)]->port_set = gpio_bit(gpio);
313 else
314 gpio_array[gpio_bank(gpio)]->port_clear = gpio_bit(gpio);
315
316}
317EXPORT_SYMBOL(gpio_set_value);
318
319unsigned short gpio_get_value(unsigned short gpio)
320{
321 return (1 & (gpio_array[gpio_bank(gpio)]->port_data >> gpio_sub_n(gpio)));
322}
323EXPORT_SYMBOL(gpio_get_value);
diff --git a/arch/blackfin/mach-bf548/head.S b/arch/blackfin/mach-bf548/head.S
new file mode 100644
index 000000000000..06751ae8b857
--- /dev/null
+++ b/arch/blackfin/mach-bf548/head.S
@@ -0,0 +1,512 @@
1/*
2 * File: arch/blackfin/mach-bf548/head.S
3 * Based on: arch/blackfin/mach-bf537/head.S
4 * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5 *
6 * Created: 1998
7 * Description: Startup code for Blackfin BF548
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/linkage.h>
31#include <asm/blackfin.h>
32#include <asm/trace.h>
33#if CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach/mem_init.h>
35#endif
36
37.global __rambase
38.global __ramstart
39.global __ramend
40.extern ___bss_stop
41.extern ___bss_start
42.extern _bf53x_relocate_l1_mem
43
44#define INITIAL_STACK 0xFFB01000
45
46.text
47
48ENTRY(__start)
49ENTRY(__stext)
50 /* R0: argument of command line string, passed from uboot, save it */
51 R7 = R0;
52 /* Set the SYSCFG register */
53 R0 = 0x36;
54 SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
55 R0 = 0;
56
57 /* Clear Out All the data and pointer Registers*/
58 R1 = R0;
59 R2 = R0;
60 R3 = R0;
61 R4 = R0;
62 R5 = R0;
63 R6 = R0;
64
65 P0 = R0;
66 P1 = R0;
67 P2 = R0;
68 P3 = R0;
69 P4 = R0;
70 P5 = R0;
71
72 LC0 = r0;
73 LC1 = r0;
74 L0 = r0;
75 L1 = r0;
76 L2 = r0;
77 L3 = r0;
78
79 /* Clear Out All the DAG Registers*/
80 B0 = r0;
81 B1 = r0;
82 B2 = r0;
83 B3 = r0;
84
85 I0 = r0;
86 I1 = r0;
87 I2 = r0;
88 I3 = r0;
89
90 M0 = r0;
91 M1 = r0;
92 M2 = r0;
93 M3 = r0;
94
95 trace_buffer_start(p0,r0);
96 P0 = R1;
97 R0 = R1;
98
99 /* Turn off the icache */
100 p0.l = (IMEM_CONTROL & 0xFFFF);
101 p0.h = (IMEM_CONTROL >> 16);
102 R1 = [p0];
103 R0 = ~ENICPLB;
104 R0 = R0 & R1;
105 [p0] = R0;
106 SSYNC;
107
108 /* Turn off the dcache */
109 p0.l = (DMEM_CONTROL & 0xFFFF);
110 p0.h = (DMEM_CONTROL >> 16);
111 R1 = [p0];
112 R0 = ~ENDCPLB;
113 R0 = R0 & R1;
114 [p0] = R0;
115 SSYNC;
116
117 /* Initialize stack pointer */
118 SP.L = LO(INITIAL_STACK);
119 SP.H = HI(INITIAL_STACK);
120 FP = SP;
121 USP = SP;
122
123 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
124 call _bf53x_relocate_l1_mem;
125#if CONFIG_BFIN_KERNEL_CLOCK
126 call _start_dma_code;
127#endif
128 /* Code for initializing Async memory banks */
129
130 p2.h = hi(EBIU_AMBCTL1);
131 p2.l = lo(EBIU_AMBCTL1);
132 r0.h = hi(AMBCTL1VAL);
133 r0.l = lo(AMBCTL1VAL);
134 [p2] = r0;
135 ssync;
136
137 p2.h = hi(EBIU_AMBCTL0);
138 p2.l = lo(EBIU_AMBCTL0);
139 r0.h = hi(AMBCTL0VAL);
140 r0.l = lo(AMBCTL0VAL);
141 [p2] = r0;
142 ssync;
143
144 p2.h = hi(EBIU_AMGCTL);
145 p2.l = lo(EBIU_AMGCTL);
146 r0 = AMGCTLVAL;
147 w[p2] = r0;
148 ssync;
149
150 /* This section keeps the processor in supervisor mode
151 * during kernel boot. Switches to user mode at end of boot.
152 * See page 3-9 of Hardware Reference manual for documentation.
153 */
154
155 /* EVT15 = _real_start */
156
157 p0.l = lo(EVT15);
158 p0.h = hi(EVT15);
159 p1.l = _real_start;
160 p1.h = _real_start;
161 [p0] = p1;
162 csync;
163
164 p0.l = lo(IMASK);
165 p0.h = hi(IMASK);
166 p1.l = IMASK_IVG15;
167 p1.h = 0x0;
168 [p0] = p1;
169 csync;
170
171 raise 15;
172 p0.l = .LWAIT_HERE;
173 p0.h = .LWAIT_HERE;
174 reti = p0;
175#if defined (ANOMALY_05000281)
176 nop;
177 nop;
178 nop;
179#endif
180 rti;
181
182.LWAIT_HERE:
183 jump .LWAIT_HERE;
184
185ENTRY(_real_start)
186 [ -- sp ] = reti;
187 p0.l = lo(WDOG_CTL);
188 p0.h = hi(WDOG_CTL);
189 r0 = 0xAD6(z);
190 w[p0] = r0; /* watchdog off for now */
191 ssync;
192
193 /* Code update for BSS size == 0
194 * Zero out the bss region.
195 */
196
197 p1.l = ___bss_start;
198 p1.h = ___bss_start;
199 p2.l = ___bss_stop;
200 p2.h = ___bss_stop;
201 r0 = 0;
202 p2 -= p1;
203 lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
204.L_clear_bss:
205 B[p1++] = r0;
206
207 /* In case there is a NULL pointer reference
208 * Zero out region before stext
209 */
210
211 p1.l = 0x0;
212 p1.h = 0x0;
213 r0.l = __stext;
214 r0.h = __stext;
215 r0 = r0 >> 1;
216 p2 = r0;
217 r0 = 0;
218 lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
219.L_clear_zero:
220 W[p1++] = r0;
221
222 /* pass the uboot arguments to the global value command line */
223 R0 = R7;
224 call _cmdline_init;
225
226 p1.l = __rambase;
227 p1.h = __rambase;
228 r0.l = __sdata;
229 r0.h = __sdata;
230 [p1] = r0;
231
232 p1.l = __ramstart;
233 p1.h = __ramstart;
234 p3.l = ___bss_stop;
235 p3.h = ___bss_stop;
236
237 r1 = p3;
238 [p1] = r1;
239
240
241 /*
242 * load the current thread pointer and stack
243 */
244 r1.l = _init_thread_union;
245 r1.h = _init_thread_union;
246
247 r2.l = 0x2000;
248 r2.h = 0x0000;
249 r1 = r1 + r2;
250 sp = r1;
251 usp = sp;
252 fp = sp;
253 call _start_kernel;
254.L_exit:
255 jump.s .L_exit;
256
257.section .l1.text
258#if CONFIG_BFIN_KERNEL_CLOCK
259ENTRY(_start_dma_code)
260
261 /* Enable PHY CLK buffer output */
262 p0.h = hi(VR_CTL);
263 p0.l = lo(VR_CTL);
264 r0.l = w[p0];
265 bitset(r0, 14);
266 w[p0] = r0.l;
267 ssync;
268
269 p0.h = hi(SIC_IWR);
270 p0.l = lo(SIC_IWR);
271 r0.l = 0x1;
272 r0.h = 0x0;
273 [p0] = r0;
274 SSYNC;
275
276 /*
277 * Set PLL_CTL
278 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
279 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
280 * - [7] = output delay (add 200ps of delay to mem signals)
281 * - [6] = input delay (add 200ps of input delay to mem signals)
282 * - [5] = PDWN : 1=All Clocks off
283 * - [3] = STOPCK : 1=Core Clock off
284 * - [1] = PLL_OFF : 1=Disable Power to PLL
285 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
286 * all other bits set to zero
287 */
288
289 p0.h = hi(PLL_LOCKCNT);
290 p0.l = lo(PLL_LOCKCNT);
291 r0 = 0x300(Z);
292 w[p0] = r0.l;
293 ssync;
294
295 P2.H = hi(EBIU_SDGCTL);
296 P2.L = lo(EBIU_SDGCTL);
297 R0 = [P2];
298 BITSET (R0, 24);
299 [P2] = R0;
300 SSYNC;
301
302 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
303 r0 = r0 << 9; /* Shift it over, */
304 r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
305 r0 = r1 | r0;
306 r1 = PLL_BYPASS; /* Bypass the PLL? */
307 r1 = r1 << 8; /* Shift it over */
308 r0 = r1 | r0; /* add them all together */
309
310 p0.h = hi(PLL_CTL);
311 p0.l = lo(PLL_CTL); /* Load the address */
312 cli r2; /* Disable interrupts */
313 ssync;
314 w[p0] = r0.l; /* Set the value */
315 idle; /* Wait for the PLL to stablize */
316 sti r2; /* Enable interrupts */
317
318.Lcheck_again:
319 p0.h = hi(PLL_STAT);
320 p0.l = lo(PLL_STAT);
321 R0 = W[P0](Z);
322 CC = BITTST(R0,5);
323 if ! CC jump .Lcheck_again;
324
325 /* Configure SCLK & CCLK Dividers */
326 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
327 p0.h = hi(PLL_DIV);
328 p0.l = lo(PLL_DIV);
329 w[p0] = r0.l;
330 ssync;
331
332 p0.l = lo(EBIU_SDRRC);
333 p0.h = hi(EBIU_SDRRC);
334 r0 = mem_SDRRC;
335 w[p0] = r0.l;
336 ssync;
337
338 p0.l = (EBIU_SDBCTL & 0xFFFF);
339 p0.h = (EBIU_SDBCTL >> 16); /* SDRAM Memory Bank Control Register */
340 r0 = mem_SDBCTL;
341 w[p0] = r0.l;
342 ssync;
343
344 P2.H = hi(EBIU_SDGCTL);
345 P2.L = lo(EBIU_SDGCTL);
346 R0 = [P2];
347 BITCLR (R0, 24);
348 p0.h = hi(EBIU_SDSTAT);
349 p0.l = lo(EBIU_SDSTAT);
350 r2.l = w[p0];
351 cc = bittst(r2,3);
352 if !cc jump .Lskip;
353 NOP;
354 BITSET (R0, 23);
355.Lskip:
356 [P2] = R0;
357 SSYNC;
358
359 R0.L = lo(mem_SDGCTL);
360 R0.H = hi(mem_SDGCTL);
361 R1 = [p2];
362 R1 = R1 | R0;
363 [P2] = R1;
364 SSYNC;
365
366 p0.h = hi(SIC_IWR);
367 p0.l = lo(SIC_IWR);
368 r0.l = lo(IWR_ENABLE_ALL);
369 r0.h = hi(IWR_ENABLE_ALL);
370 [p0] = r0;
371 SSYNC;
372
373 RTS;
374#endif /* CONFIG_BFIN_KERNEL_CLOCK */
375
376ENTRY(_bfin_reset)
377 /* No more interrupts to be handled*/
378 CLI R6;
379 SSYNC;
380
381#if defined(CONFIG_MTD_M25P80)
382/*
383 * The following code fix the SPI flash reboot issue,
384 * /CS signal of the chip which is using PF10 return to GPIO mode
385 */
386 p0.h = hi(PORTF_FER);
387 p0.l = lo(PORTF_FER);
388 r0.l = 0x0000;
389 w[p0] = r0.l;
390 SSYNC;
391
392/* /CS return to high */
393 p0.h = hi(PORTFIO);
394 p0.l = lo(PORTFIO);
395 r0.l = 0xFFFF;
396 w[p0] = r0.l;
397 SSYNC;
398
399/* Delay some time, This is necessary */
400 r1.h = 0;
401 r1.l = 0x400;
402 p1 = r1;
403 lsetup (_delay_lab1,_delay_lab1_end ) lc1 = p1;
404_delay_lab1:
405 r0.h = 0;
406 r0.l = 0x8000;
407 p0 = r0;
408 lsetup (_delay_lab0,_delay_lab0_end ) lc0 = p0;
409_delay_lab0:
410 nop;
411_delay_lab0_end:
412 nop;
413_delay_lab1_end:
414 nop;
415#endif
416
417 /* Clear the bits 13-15 in SWRST if they werent cleared */
418 p0.h = hi(SWRST);
419 p0.l = lo(SWRST);
420 csync;
421 r0.l = w[p0];
422
423 /* Clear the IMASK register */
424 p0.h = hi(IMASK);
425 p0.l = lo(IMASK);
426 r0 = 0x0;
427 [p0] = r0;
428
429 /* Clear the ILAT register */
430 p0.h = hi(ILAT);
431 p0.l = lo(ILAT);
432 r0 = [p0];
433 [p0] = r0;
434 SSYNC;
435
436 /* Disable the WDOG TIMER */
437 p0.h = hi(WDOG_CTL);
438 p0.l = lo(WDOG_CTL);
439 r0.l = 0xAD6;
440 w[p0] = r0.l;
441 SSYNC;
442
443 /* Clear the sticky bit incase it is already set */
444 p0.h = hi(WDOG_CTL);
445 p0.l = lo(WDOG_CTL);
446 r0.l = 0x8AD6;
447 w[p0] = r0.l;
448 SSYNC;
449
450 /* Program the count value */
451 R0.l = 0x100;
452 R0.h = 0x0;
453 P0.h = hi(WDOG_CNT);
454 P0.l = lo(WDOG_CNT);
455 [P0] = R0;
456 SSYNC;
457
458 /* Program WDOG_STAT if necessary */
459 P0.h = hi(WDOG_CTL);
460 P0.l = lo(WDOG_CTL);
461 R0 = W[P0](Z);
462 CC = BITTST(R0,1);
463 if !CC JUMP .LWRITESTAT;
464 CC = BITTST(R0,2);
465 if !CC JUMP .LWRITESTAT;
466 JUMP .LSKIP_WRITE;
467
468.LWRITESTAT:
469 /* When watch dog timer is enabled,
470 * a write to STAT will load the contents of CNT to STAT
471 */
472 R0 = 0x0000(z);
473 P0.h = hi(WDOG_STAT);
474 P0.l = lo(WDOG_STAT)
475 [P0] = R0;
476 SSYNC;
477
478.LSKIP_WRITE:
479 /* Enable the reset event */
480 P0.h = hi(WDOG_CTL);
481 P0.l = lo(WDOG_CTL);
482 R0 = W[P0](Z);
483 BITCLR(R0,1);
484 BITCLR(R0,2);
485 W[P0] = R0.L;
486 SSYNC;
487 NOP;
488
489 /* Enable the wdog counter */
490 R0 = W[P0](Z);
491 BITCLR(R0,4);
492 W[P0] = R0.L;
493 SSYNC;
494
495 IDLE;
496
497 RTS;
498
499.data
500
501/*
502 * Set up the usable of RAM stuff. Size of RAM is determined then
503 * an initial stack set up at the end.
504 */
505
506.align 4
507__rambase:
508.long 0
509__ramstart:
510.long 0
511__ramend:
512.long 0
diff --git a/arch/blackfin/mach-bf548/ints-priority.c b/arch/blackfin/mach-bf548/ints-priority.c
new file mode 100644
index 000000000000..cb0ebac53c79
--- /dev/null
+++ b/arch/blackfin/mach-bf548/ints-priority.c
@@ -0,0 +1,137 @@
1/*
2 * File: arch/blackfin/mach-bf537/ints-priority.c
3 * Based on: arch/blackfin/mach-bf533/ints-priority.c
4 * Author: Michael Hennerich
5 *
6 * Created:
7 * Description: Set up the interupt priorities
8 *
9 * Modified:
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#include <linux/module.h>
31#include <linux/irq.h>
32#include <asm/blackfin.h>
33
34void program_IAR(void)
35{
36 /* Program the IAR0 Register with the configured priority */
37 bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
38 ((CONFIG_IRQ_DMAC0_ERR - 7) << IRQ_DMAC0_ERR_POS) |
39 ((CONFIG_IRQ_EPPI0_ERR - 7) << IRQ_EPPI0_ERR_POS) |
40 ((CONFIG_IRQ_SPORT0_ERR - 7) << IRQ_SPORT0_ERR_POS) |
41 ((CONFIG_IRQ_SPORT1_ERR - 7) << IRQ_SPORT1_ERR_POS) |
42 ((CONFIG_IRQ_SPI0_ERR - 7) << IRQ_SPI0_ERR_POS) |
43 ((CONFIG_IRQ_UART0_ERR - 7) << IRQ_UART0_ERR_POS) |
44 ((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS));
45
46 bfin_write_SIC_IAR1(((CONFIG_IRQ_EPPI0 - 7) << IRQ_EPPI0_POS) |
47 ((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
48 ((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
49 ((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS) |
50 ((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
51 ((CONFIG_IRQ_SPI0 - 7) << IRQ_SPI0_POS) |
52 ((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
53 ((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS));
54
55 bfin_write_SIC_IAR2(((CONFIG_IRQ_TIMER8 - 7) << IRQ_TIMER8_POS) |
56 ((CONFIG_IRQ_TIMER9 - 7) << IRQ_TIMER9_POS) |
57 ((CONFIG_IRQ_PINT0 - 7) << IRQ_PINT0_POS) |
58 ((CONFIG_IRQ_PINT1 - 7) << IRQ_PINT1_POS) |
59 ((CONFIG_IRQ_MDMAS0 - 7) << IRQ_MDMAS0_POS) |
60 ((CONFIG_IRQ_MDMAS1 - 7) << IRQ_MDMAS1_POS) |
61 ((CONFIG_IRQ_WATCHDOG - 7) << IRQ_WATCHDOG_POS));
62
63 bfin_write_SIC_IAR3(((CONFIG_IRQ_DMAC1_ERR - 7) << IRQ_DMAC1_ERR_POS) |
64 ((CONFIG_IRQ_SPORT2_ERR - 7) << IRQ_SPORT2_ERR_POS) |
65 ((CONFIG_IRQ_SPORT3_ERR - 7) << IRQ_SPORT3_ERR_POS) |
66 ((CONFIG_IRQ_MXVR_DATA - 7) << IRQ_MXVR_DATA_POS) |
67 ((CONFIG_IRQ_SPI1_ERR - 7) << IRQ_SPI1_ERR_POS) |
68 ((CONFIG_IRQ_SPI2_ERR - 7) << IRQ_SPI2_ERR_POS) |
69 ((CONFIG_IRQ_UART1_ERR - 7) << IRQ_UART1_ERR_POS) |
70 ((CONFIG_IRQ_UART2_ERR - 7) << IRQ_UART2_ERR_POS));
71
72 bfin_write_SIC_IAR4(((CONFIG_IRQ_CAN0_ERR - 7) << IRQ_CAN0_ERR_POS) |
73 ((CONFIG_IRQ_SPORT2_RX - 7) << IRQ_SPORT2_RX_POS) |
74 ((CONFIG_IRQ_SPORT2_TX - 7) << IRQ_SPORT2_TX_POS) |
75 ((CONFIG_IRQ_SPORT3_RX - 7) << IRQ_SPORT3_RX_POS) |
76 ((CONFIG_IRQ_SPORT3_TX - 7) << IRQ_SPORT3_TX_POS) |
77 ((CONFIG_IRQ_EPPI1 - 7) << IRQ_EPPI1_POS) |
78 ((CONFIG_IRQ_EPPI2 - 7) << IRQ_EPPI2_POS) |
79 ((CONFIG_IRQ_SPI1 - 7) << IRQ_SPI1_POS));
80
81 bfin_write_SIC_IAR5(((CONFIG_IRQ_SPI2 - 7) << IRQ_SPI2_POS) |
82 ((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
83 ((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
84 ((CONFIG_IRQ_ATAPI_RX - 7) << IRQ_ATAPI_RX_POS) |
85 ((CONFIG_IRQ_ATAPI_TX - 7) << IRQ_ATAPI_TX_POS) |
86 ((CONFIG_IRQ_TWI0 - 7) << IRQ_TWI0_POS) |
87 ((CONFIG_IRQ_TWI1 - 7) << IRQ_TWI1_POS) |
88 ((CONFIG_IRQ_CAN0_RX - 7) << IRQ_CAN0_RX_POS));
89
90 bfin_write_SIC_IAR6(((CONFIG_IRQ_CAN0_TX - 7) << IRQ_CAN0_TX_POS) |
91 ((CONFIG_IRQ_MDMAS2 - 7) << IRQ_MDMAS2_POS) |
92 ((CONFIG_IRQ_MDMAS3 - 7) << IRQ_MDMAS3_POS) |
93 ((CONFIG_IRQ_MXVR_ERR - 7) << IRQ_MXVR_ERR_POS) |
94 ((CONFIG_IRQ_MXVR_MSG - 7) << IRQ_MXVR_MSG_POS) |
95 ((CONFIG_IRQ_MXVR_PKT - 7) << IRQ_MXVR_PKT_POS) |
96 ((CONFIG_IRQ_EPPI1_ERR - 7) << IRQ_EPPI1_ERR_POS) |
97 ((CONFIG_IRQ_EPPI2_ERR - 7) << IRQ_EPPI2_ERR_POS));
98
99 bfin_write_SIC_IAR7(((CONFIG_IRQ_UART3_ERR - 7) << IRQ_UART3_ERR_POS) |
100 ((CONFIG_IRQ_HOST_ERR - 7) << IRQ_HOST_ERR_POS) |
101 ((CONFIG_IRQ_PIXC_ERR - 7) << IRQ_PIXC_ERR_POS) |
102 ((CONFIG_IRQ_NFC_ERR - 7) << IRQ_NFC_ERR_POS) |
103 ((CONFIG_IRQ_ATAPI_ERR - 7) << IRQ_ATAPI_ERR_POS) |
104 ((CONFIG_IRQ_CAN1_ERR - 7) << IRQ_CAN1_ERR_POS) |
105 ((CONFIG_IRQ_HS_DMA_ERR - 7) << IRQ_HS_DMA_ERR_POS));
106
107 bfin_write_SIC_IAR8(((CONFIG_IRQ_PIXC_IN0 - 7) << IRQ_PIXC_IN1_POS) |
108 ((CONFIG_IRQ_PIXC_IN1 - 7) << IRQ_PIXC_IN1_POS) |
109 ((CONFIG_IRQ_PIXC_OUT - 7) << IRQ_PIXC_OUT_POS) |
110 ((CONFIG_IRQ_SDH - 7) << IRQ_SDH_POS) |
111 ((CONFIG_IRQ_CNT - 7) << IRQ_CNT_POS) |
112 ((CONFIG_IRQ_KEY - 7) << IRQ_KEY_POS) |
113 ((CONFIG_IRQ_CAN1_RX - 7) << IRQ_CAN1_RX_POS) |
114 ((CONFIG_IRQ_CAN1_TX - 7) << IRQ_CAN1_TX_POS));
115
116 bfin_write_SIC_IAR9(((CONFIG_IRQ_SDH_MASK0 - 7) << IRQ_SDH_MASK0_POS) |
117 ((CONFIG_IRQ_SDH_MASK1 - 7) << IRQ_SDH_MASK1_POS) |
118 ((CONFIG_IRQ_USB_INT0 - 7) << IRQ_USB_INT0_POS) |
119 ((CONFIG_IRQ_USB_INT1 - 7) << IRQ_USB_INT1_POS) |
120 ((CONFIG_IRQ_USB_INT2 - 7) << IRQ_USB_INT2_POS) |
121 ((CONFIG_IRQ_USB_DMA - 7) << IRQ_USB_DMA_POS) |
122 ((CONFIG_IRQ_OTPSEC - 7) << IRQ_OTPSEC_POS));
123
124 bfin_write_SIC_IAR10(((CONFIG_IRQ_TIMER0 - 7) << IRQ_TIMER0_POS) |
125 ((CONFIG_IRQ_TIMER1 - 7) << IRQ_TIMER1_POS));
126
127 bfin_write_SIC_IAR11(((CONFIG_IRQ_TIMER2 - 7) << IRQ_TIMER2_POS) |
128 ((CONFIG_IRQ_TIMER3 - 7) << IRQ_TIMER3_POS) |
129 ((CONFIG_IRQ_TIMER4 - 7) << IRQ_TIMER4_POS) |
130 ((CONFIG_IRQ_TIMER5 - 7) << IRQ_TIMER5_POS) |
131 ((CONFIG_IRQ_TIMER6 - 7) << IRQ_TIMER6_POS) |
132 ((CONFIG_IRQ_TIMER7 - 7) << IRQ_TIMER7_POS) |
133 ((CONFIG_IRQ_PINT2 - 7) << IRQ_PINT2_POS) |
134 ((CONFIG_IRQ_PINT3 - 7) << IRQ_PINT3_POS));
135
136 SSYNC();
137}
diff --git a/arch/blackfin/mach-bf561/Makefile b/arch/blackfin/mach-bf561/Makefile
index 57f475a55161..f39235a55783 100644
--- a/arch/blackfin/mach-bf561/Makefile
+++ b/arch/blackfin/mach-bf561/Makefile
@@ -4,6 +4,6 @@
4 4
5extra-y := head.o 5extra-y := head.o
6 6
7obj-y := ints-priority.o 7obj-y := ints-priority.o dma.o
8 8
9obj-$(CONFIG_BF561_COREB) += coreb.o 9obj-$(CONFIG_BF561_COREB) += coreb.o
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 3dc5c042048c..5b2b544529a1 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -34,7 +34,7 @@
34#include <linux/spi/spi.h> 34#include <linux/spi/spi.h>
35#include <linux/spi/flash.h> 35#include <linux/spi/flash.h>
36#include <linux/usb_isp1362.h> 36#include <linux/usb_isp1362.h>
37#include <asm/irq.h> 37#include <linux/irq.h>
38#include <asm/bfin5xx_spi.h> 38#include <asm/bfin5xx_spi.h>
39 39
40/* 40/*
@@ -52,11 +52,11 @@ static struct mtd_partition bfin_spi_flash_partitions[] = {
52 .size = 0x00020000, 52 .size = 0x00020000,
53 .offset = 0, 53 .offset = 0,
54 .mask_flags = MTD_CAP_ROM 54 .mask_flags = MTD_CAP_ROM
55 },{ 55 }, {
56 .name = "kernel", 56 .name = "kernel",
57 .size = 0xe0000, 57 .size = 0xe0000,
58 .offset = 0x20000 58 .offset = 0x20000
59 },{ 59 }, {
60 .name = "file system", 60 .name = "file system",
61 .size = 0x700000, 61 .size = 0x700000,
62 .offset = 0x00100000, 62 .offset = 0x00100000,
@@ -186,7 +186,7 @@ static struct resource smc91x_resources[] = {
186 .start = 0x28000300, 186 .start = 0x28000300,
187 .end = 0x28000300 + 16, 187 .end = 0x28000300 + 16,
188 .flags = IORESOURCE_MEM, 188 .flags = IORESOURCE_MEM,
189 },{ 189 }, {
190 .start = IRQ_PF0, 190 .start = IRQ_PF0,
191 .end = IRQ_PF0, 191 .end = IRQ_PF0,
192 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 192 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -206,11 +206,11 @@ static struct resource isp1362_hcd_resources[] = {
206 .start = 0x24008000, 206 .start = 0x24008000,
207 .end = 0x24008000, 207 .end = 0x24008000,
208 .flags = IORESOURCE_MEM, 208 .flags = IORESOURCE_MEM,
209 },{ 209 }, {
210 .start = 0x24008004, 210 .start = 0x24008004,
211 .end = 0x24008004, 211 .end = 0x24008004,
212 .flags = IORESOURCE_MEM, 212 .flags = IORESOURCE_MEM,
213 },{ 213 }, {
214 .start = IRQ_PF47, 214 .start = IRQ_PF47,
215 .end = IRQ_PF47, 215 .end = IRQ_PF47,
216 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 216 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
@@ -241,25 +241,25 @@ static struct platform_device isp1362_hcd_device = {
241 241
242#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 242#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
243static struct resource bfin_uart_resources[] = { 243static struct resource bfin_uart_resources[] = {
244 { 244 {
245 .start = 0xFFC00400, 245 .start = 0xFFC00400,
246 .end = 0xFFC004FF, 246 .end = 0xFFC004FF,
247 .flags = IORESOURCE_MEM, 247 .flags = IORESOURCE_MEM,
248 }, 248 },
249}; 249};
250 250
251static struct platform_device bfin_uart_device = { 251static struct platform_device bfin_uart_device = {
252 .name = "bfin-uart", 252 .name = "bfin-uart",
253 .id = 1, 253 .id = 1,
254 .num_resources = ARRAY_SIZE(bfin_uart_resources), 254 .num_resources = ARRAY_SIZE(bfin_uart_resources),
255 .resource = bfin_uart_resources, 255 .resource = bfin_uart_resources,
256}; 256};
257#endif 257#endif
258 258
259static struct platform_device *cm_bf561_devices[] __initdata = { 259static struct platform_device *cm_bf561_devices[] __initdata = {
260 260
261#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 261#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
262 &bfin_uart_device, 262 &bfin_uart_device,
263#endif 263#endif
264 264
265#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) 265#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 9720b5c307ab..724191da20a2 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -30,10 +30,9 @@
30#include <linux/device.h> 30#include <linux/device.h>
31#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/spi/spi.h> 32#include <linux/spi/spi.h>
33#include <asm/irq.h>
34#include <asm/bfin5xx_spi.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h> 33#include <linux/irq.h>
34#include <linux/interrupt.h>
35#include <asm/bfin5xx_spi.h>
37 36
38/* 37/*
39 * Name the Board for the /proc/cpuinfo 38 * Name the Board for the /proc/cpuinfo
@@ -45,13 +44,13 @@ char *bfin_board_name = "ADDS-BF561-EZKIT";
45 44
46#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) 45#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
47static struct resource bfin_isp1761_resources[] = { 46static struct resource bfin_isp1761_resources[] = {
48 [0] = { 47 {
49 .name = "isp1761-regs", 48 .name = "isp1761-regs",
50 .start = ISP1761_BASE + 0x00000000, 49 .start = ISP1761_BASE + 0x00000000,
51 .end = ISP1761_BASE + 0x000fffff, 50 .end = ISP1761_BASE + 0x000fffff,
52 .flags = IORESOURCE_MEM, 51 .flags = IORESOURCE_MEM,
53 }, 52 },
54 [1] = { 53 {
55 .start = ISP1761_IRQ, 54 .start = ISP1761_IRQ,
56 .end = ISP1761_IRQ, 55 .end = ISP1761_IRQ,
57 .flags = IORESOURCE_IRQ, 56 .flags = IORESOURCE_IRQ,
@@ -71,7 +70,7 @@ static struct platform_device *bfin_isp1761_devices[] = {
71 70
72int __init bfin_isp1761_init(void) 71int __init bfin_isp1761_init(void)
73{ 72{
74 unsigned int num_devices=ARRAY_SIZE(bfin_isp1761_devices); 73 unsigned int num_devices = ARRAY_SIZE(bfin_isp1761_devices);
75 74
76 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__); 75 printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
77 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING); 76 set_irq_type(ISP1761_IRQ, IRQF_TRIGGER_FALLING);
@@ -98,7 +97,7 @@ static struct resource smc91x_resources[] = {
98 .start = 0x2C010300, 97 .start = 0x2C010300,
99 .end = 0x2C010300 + 16, 98 .end = 0x2C010300 + 16,
100 .flags = IORESOURCE_MEM, 99 .flags = IORESOURCE_MEM,
101 },{ 100 }, {
102 101
103 .start = IRQ_PF9, 102 .start = IRQ_PF9,
104 .end = IRQ_PF9, 103 .end = IRQ_PF9,
@@ -116,18 +115,18 @@ static struct platform_device smc91x_device = {
116 115
117#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 116#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
118static struct resource bfin_uart_resources[] = { 117static struct resource bfin_uart_resources[] = {
119 { 118 {
120 .start = 0xFFC00400, 119 .start = 0xFFC00400,
121 .end = 0xFFC004FF, 120 .end = 0xFFC004FF,
122 .flags = IORESOURCE_MEM, 121 .flags = IORESOURCE_MEM,
123 }, 122 },
124}; 123};
125 124
126static struct platform_device bfin_uart_device = { 125static struct platform_device bfin_uart_device = {
127 .name = "bfin-uart", 126 .name = "bfin-uart",
128 .id = 1, 127 .id = 1,
129 .num_resources = ARRAY_SIZE(bfin_uart_resources), 128 .num_resources = ARRAY_SIZE(bfin_uart_resources),
130 .resource = bfin_uart_resources, 129 .resource = bfin_uart_resources,
131}; 130};
132#endif 131#endif
133 132
@@ -176,7 +175,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
176 &spi_bfin_master_device, 175 &spi_bfin_master_device,
177#endif 176#endif
178#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) 177#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
179 &bfin_uart_device, 178 &bfin_uart_device,
180#endif 179#endif
181}; 180};
182 181
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c
index 585ecdd2f6a5..4dfea5da674c 100644
--- a/arch/blackfin/mach-bf561/boards/generic_board.c
+++ b/arch/blackfin/mach-bf561/boards/generic_board.c
@@ -30,7 +30,7 @@
30 30
31#include <linux/device.h> 31#include <linux/device.h>
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33#include <asm/irq.h> 33#include <linux/irq.h>
34 34
35char *bfin_board_name = "UNKNOWN BOARD"; 35char *bfin_board_name = "UNKNOWN BOARD";
36 36
@@ -43,11 +43,11 @@ static struct resource smc91x_resources[] = {
43 .start = 0x2C010300, 43 .start = 0x2C010300,
44 .end = 0x2C010300 + 16, 44 .end = 0x2C010300 + 16,
45 .flags = IORESOURCE_MEM, 45 .flags = IORESOURCE_MEM,
46 },{ 46 }, {
47 .start = IRQ_PROG_INTB, 47 .start = IRQ_PROG_INTB,
48 .end = IRQ_PROG_INTB, 48 .end = IRQ_PROG_INTB,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 },{ 50 }, {
51 /* 51 /*
52 * denotes the flag pin and is used directly if 52 * denotes the flag pin and is used directly if
53 * CONFIG_IRQCHIP_DEMUX_GPIO is defined. 53 * CONFIG_IRQCHIP_DEMUX_GPIO is defined.
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index db308c7ccabb..c442eb23db5e 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -14,7 +14,7 @@
14 14
15#include <linux/device.h> 15#include <linux/device.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <asm/irq.h> 17#include <linux/irq.h>
18 18
19char *bfin_board_name = "Tepla-BF561"; 19char *bfin_board_name = "Tepla-BF561";
20 20
@@ -26,11 +26,11 @@ static struct resource smc91x_resources[] = {
26 .start = 0x2C000300, 26 .start = 0x2C000300,
27 .end = 0x2C000320, 27 .end = 0x2C000320,
28 .flags = IORESOURCE_MEM, 28 .flags = IORESOURCE_MEM,
29 },{ 29 }, {
30 .start = IRQ_PROG_INTB, 30 .start = IRQ_PROG_INTB,
31 .end = IRQ_PROG_INTB, 31 .end = IRQ_PROG_INTB,
32 .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL, 32 .flags = IORESOURCE_IRQ|IORESOURCE_IRQ_HIGHLEVEL,
33 },{ 33 }, {
34 /* 34 /*
35 * denotes the flag pin and is used directly if 35 * denotes the flag pin and is used directly if
36 * CONFIG_IRQCHIP_DEMUX_GPIO is defined. 36 * CONFIG_IRQCHIP_DEMUX_GPIO is defined.
diff --git a/arch/blackfin/mach-bf561/coreb.c b/arch/blackfin/mach-bf561/coreb.c
index b28582fe083c..5d1d21b4c2a7 100644
--- a/arch/blackfin/mach-bf561/coreb.c
+++ b/arch/blackfin/mach-bf561/coreb.c
@@ -32,8 +32,8 @@
32#include <linux/device.h> 32#include <linux/device.h>
33#include <linux/ioport.h> 33#include <linux/ioport.h>
34#include <linux/module.h> 34#include <linux/module.h>
35#include <linux/uaccess.h>
35#include <asm/dma.h> 36#include <asm/dma.h>
36#include <asm/uaccess.h>
37 37
38#define MODULE_VER "v0.1" 38#define MODULE_VER "v0.1"
39 39
@@ -202,7 +202,7 @@ static int coreb_open(struct inode *inode, struct file *file)
202 spin_unlock_irq(&coreb_lock); 202 spin_unlock_irq(&coreb_lock);
203 return 0; 203 return 0;
204 204
205 out_busy: 205 out_busy:
206 spin_unlock_irq(&coreb_lock); 206 spin_unlock_irq(&coreb_lock);
207 return -EBUSY; 207 return -EBUSY;
208} 208}
@@ -365,19 +365,19 @@ int __init bf561_coreb_init(void)
365 printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER); 365 printk(KERN_INFO "BF561 Core B driver %s initialized.\n", MODULE_VER);
366 return 0; 366 return 0;
367 367
368 release_dma_src: 368 release_dma_src:
369 free_dma(CH_MEM_STREAM2_SRC); 369 free_dma(CH_MEM_STREAM2_SRC);
370 release_dma_dest: 370 release_dma_dest:
371 free_dma(CH_MEM_STREAM2_DEST); 371 free_dma(CH_MEM_STREAM2_DEST);
372 release_data_a_sram: 372 release_data_a_sram:
373 release_mem_region(0xff400000, 0x8000); 373 release_mem_region(0xff400000, 0x8000);
374 release_data_b_sram: 374 release_data_b_sram:
375 release_mem_region(0xff500000, 0x8000); 375 release_mem_region(0xff500000, 0x8000);
376 release_instruction_b_sram: 376 release_instruction_b_sram:
377 release_mem_region(0xff610000, 0x4000); 377 release_mem_region(0xff610000, 0x4000);
378 release_instruction_a_sram: 378 release_instruction_a_sram:
379 release_mem_region(0xff600000, 0x4000); 379 release_mem_region(0xff600000, 0x4000);
380 exit: 380 exit:
381 return -ENOMEM; 381 return -ENOMEM;
382} 382}
383 383
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
new file mode 100644
index 000000000000..89c65bb0bed3
--- /dev/null
+++ b/arch/blackfin/mach-bf561/dma.c
@@ -0,0 +1,131 @@
1/*
2 * File: arch/blackfin/mach-bf561/dma.c
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: This file contains the simple DMA Implementation for Blackfin
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29#include <asm/blackfin.h>
30#include <asm/dma.h>
31
32struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = {
33 (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
34 (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
35 (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
36 (struct dma_register *) DMA1_3_NEXT_DESC_PTR,
37 (struct dma_register *) DMA1_4_NEXT_DESC_PTR,
38 (struct dma_register *) DMA1_5_NEXT_DESC_PTR,
39 (struct dma_register *) DMA1_6_NEXT_DESC_PTR,
40 (struct dma_register *) DMA1_7_NEXT_DESC_PTR,
41 (struct dma_register *) DMA1_8_NEXT_DESC_PTR,
42 (struct dma_register *) DMA1_9_NEXT_DESC_PTR,
43 (struct dma_register *) DMA1_10_NEXT_DESC_PTR,
44 (struct dma_register *) DMA1_11_NEXT_DESC_PTR,
45 (struct dma_register *) DMA2_0_NEXT_DESC_PTR,
46 (struct dma_register *) DMA2_1_NEXT_DESC_PTR,
47 (struct dma_register *) DMA2_2_NEXT_DESC_PTR,
48 (struct dma_register *) DMA2_3_NEXT_DESC_PTR,
49 (struct dma_register *) DMA2_4_NEXT_DESC_PTR,
50 (struct dma_register *) DMA2_5_NEXT_DESC_PTR,
51 (struct dma_register *) DMA2_6_NEXT_DESC_PTR,
52 (struct dma_register *) DMA2_7_NEXT_DESC_PTR,
53 (struct dma_register *) DMA2_8_NEXT_DESC_PTR,
54 (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
55 (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
56 (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
57 (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
58 (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
59 (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
60 (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
61 (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
62 (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
63 (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
64 (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
65 (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
66 (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
67 (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
68 (struct dma_register *) IMDMA_S1_NEXT_DESC_PTR,
69};
70
71int channel2irq(unsigned int channel)
72{
73 int ret_irq = -1;
74
75 switch (channel) {
76 case CH_PPI0:
77 ret_irq = IRQ_PPI0;
78 break;
79 case CH_PPI1:
80 ret_irq = IRQ_PPI1;
81 break;
82 case CH_SPORT0_RX:
83 ret_irq = IRQ_SPORT0_RX;
84 break;
85 case CH_SPORT0_TX:
86 ret_irq = IRQ_SPORT0_TX;
87 break;
88 case CH_SPORT1_RX:
89 ret_irq = IRQ_SPORT1_RX;
90 break;
91 case CH_SPORT1_TX:
92 ret_irq = IRQ_SPORT1_TX;
93 break;
94 case CH_SPI:
95 ret_irq = IRQ_SPI;
96 break;
97 case CH_UART_RX:
98 ret_irq = IRQ_UART_RX;
99 break;
100 case CH_UART_TX:
101 ret_irq = IRQ_UART_TX;
102 break;
103
104 case CH_MEM_STREAM0_SRC:
105 case CH_MEM_STREAM0_DEST:
106 ret_irq = IRQ_MEM_DMA0;
107 break;
108 case CH_MEM_STREAM1_SRC:
109 case CH_MEM_STREAM1_DEST:
110 ret_irq = IRQ_MEM_DMA1;
111 break;
112 case CH_MEM_STREAM2_SRC:
113 case CH_MEM_STREAM2_DEST:
114 ret_irq = IRQ_MEM_DMA2;
115 break;
116 case CH_MEM_STREAM3_SRC:
117 case CH_MEM_STREAM3_DEST:
118 ret_irq = IRQ_MEM_DMA3;
119 break;
120
121 case CH_IMEM_STREAM0_SRC:
122 case CH_IMEM_STREAM0_DEST:
123 ret_irq = IRQ_IMEM_DMA0;
124 break;
125 case CH_IMEM_STREAM1_SRC:
126 case CH_IMEM_STREAM1_DEST:
127 ret_irq = IRQ_IMEM_DMA1;
128 break;
129 }
130 return ret_irq;
131}
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 31cbc75c85cf..2f08bcb2dded 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -30,6 +30,8 @@
30#include <linux/linkage.h> 30#include <linux/linkage.h>
31#include <linux/init.h> 31#include <linux/init.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/trace.h>
34
33#if CONFIG_BFIN_KERNEL_CLOCK 35#if CONFIG_BFIN_KERNEL_CLOCK
34#include <asm/mach/mem_init.h> 36#include <asm/mach/mem_init.h>
35#endif 37#endif
@@ -93,6 +95,10 @@ ENTRY(__start)
93 M2 = r0; 95 M2 = r0;
94 M3 = r0; 96 M3 = r0;
95 97
98 trace_buffer_start(p0,r0);
99 P0 = R1;
100 R0 = R1;
101
96 /* Turn off the icache */ 102 /* Turn off the icache */
97 p0.l = (IMEM_CONTROL & 0xFFFF); 103 p0.l = (IMEM_CONTROL & 0xFFFF);
98 p0.h = (IMEM_CONTROL >> 16); 104 p0.h = (IMEM_CONTROL >> 16);
diff --git a/arch/blackfin/mach-bf561/ints-priority.c b/arch/blackfin/mach-bf561/ints-priority.c
index 86e3b0ee93f4..09b541b0f7c2 100644
--- a/arch/blackfin/mach-bf561/ints-priority.c
+++ b/arch/blackfin/mach-bf561/ints-priority.c
@@ -28,8 +28,8 @@
28 */ 28 */
29 29
30#include <linux/module.h> 30#include <linux/module.h>
31#include <linux/irq.h>
31#include <asm/blackfin.h> 32#include <asm/blackfin.h>
32#include <asm/irq.h>
33 33
34void program_IAR(void) 34void program_IAR(void)
35{ 35{
diff --git a/arch/blackfin/mach-common/Makefile b/arch/blackfin/mach-common/Makefile
index d3a49073d196..0279ede70392 100644
--- a/arch/blackfin/mach-common/Makefile
+++ b/arch/blackfin/mach-common/Makefile
@@ -4,9 +4,9 @@
4 4
5obj-y := \ 5obj-y := \
6 cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \ 6 cache.o cacheinit.o cplbhdlr.o cplbmgr.o entry.o \
7 interrupt.o lock.o dpmc.o irqpanic.o 7 interrupt.o lock.o irqpanic.o
8 8
9obj-$(CONFIG_CPLB_INFO) += cplbinfo.o 9obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
10obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o 10obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
11obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o 11obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
12obj-$(CONFIG_PM) += pm.o 12obj-$(CONFIG_PM) += pm.o dpmc.o
diff --git a/arch/blackfin/mach-common/cacheinit.S b/arch/blackfin/mach-common/cacheinit.S
index 7924a90d9658..9d475623b724 100644
--- a/arch/blackfin/mach-common/cacheinit.S
+++ b/arch/blackfin/mach-common/cacheinit.S
@@ -38,104 +38,37 @@
38 38
39.text 39.text
40 40
41#ifdef ANOMALY_05000125
41#if defined(CONFIG_BLKFIN_CACHE) 42#if defined(CONFIG_BLKFIN_CACHE)
42ENTRY(_bfin_icache_init) 43ENTRY(_bfin_write_IMEM_CONTROL)
43 44
44 /* Initialize Instruction CPLBS */
45
46 I0.L = (ICPLB_ADDR0 & 0xFFFF);
47 I0.H = (ICPLB_ADDR0 >> 16);
48
49 I1.L = (ICPLB_DATA0 & 0xFFFF);
50 I1.H = (ICPLB_DATA0 >> 16);
51
52 I2.L = _icplb_table;
53 I2.H = _icplb_table;
54
55 r1 = -1; /* end point comparison */
56 r3 = 15; /* max counter */
57
58/* read entries from table */
59
60.Lread_iaddr:
61 R0 = [I2++];
62 CC = R0 == R1;
63 IF CC JUMP .Lidone;
64 [I0++] = R0;
65
66.Lread_idata:
67 R2 = [I2++];
68 [I1++] = R2;
69 R3 = R3 + R1;
70 CC = R3 == R1;
71 IF !CC JUMP .Lread_iaddr;
72
73.Lidone:
74 /* Enable Instruction Cache */ 45 /* Enable Instruction Cache */
75 P0.l = (IMEM_CONTROL & 0xFFFF); 46 P0.l = (IMEM_CONTROL & 0xFFFF);
76 P0.h = (IMEM_CONTROL >> 16); 47 P0.h = (IMEM_CONTROL >> 16);
77 R1 = [P0];
78 R0 = (IMC | ENICPLB);
79 R0 = R0 | R1;
80 48
81 /* Anomaly 05000125 */ 49 /* Anomaly 05000125 */
82 CLI R2; 50 CLI R1;
83 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */ 51 SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
84 .align 8; 52 .align 8;
85 [P0] = R0; 53 [P0] = R0;
86 SSYNC; 54 SSYNC;
87 STI R2; 55 STI R1;
88 RTS; 56 RTS;
89 57
90ENDPROC(_bfin_icache_init) 58ENDPROC(_bfin_write_IMEM_CONTROL)
91#endif 59#endif
92 60
93#if defined(CONFIG_BLKFIN_DCACHE) 61#if defined(CONFIG_BLKFIN_DCACHE)
94ENTRY(_bfin_dcache_init) 62ENTRY(_bfin_write_DMEM_CONTROL)
95 63 CLI R1;
96 /* Initialize Data CPLBS */
97
98 I0.L = (DCPLB_ADDR0 & 0xFFFF);
99 I0.H = (DCPLB_ADDR0 >> 16);
100
101 I1.L = (DCPLB_DATA0 & 0xFFFF);
102 I1.H = (DCPLB_DATA0 >> 16);
103
104 I2.L = _dcplb_table;
105 I2.H = _dcplb_table;
106
107 R1 = -1; /* end point comparison */
108 R3 = 15; /* max counter */
109
110 /* read entries from table */
111.Lread_daddr:
112 R0 = [I2++];
113 cc = R0 == R1;
114 IF CC JUMP .Lddone;
115 [I0++] = R0;
116
117.Lread_ddata:
118 R2 = [I2++];
119 [I1++] = R2;
120 R3 = R3 + R1;
121 CC = R3 == R1;
122 IF !CC JUMP .Lread_daddr;
123.Lddone:
124 P0.L = (DMEM_CONTROL & 0xFFFF);
125 P0.H = (DMEM_CONTROL >> 16);
126 R1 = [P0];
127
128 R0 = DMEM_CNTR;
129
130 R0 = R0 | R1;
131 /* Anomaly 05000125 */
132 CLI R2;
133 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */ 64 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
134 .align 8; 65 .align 8;
135 [P0] = R0; 66 [P0] = R0;
136 SSYNC; 67 SSYNC;
137 STI R2; 68 STI R1;
138 RTS; 69 RTS;
139 70
140ENDPROC(_bfin_dcache_init) 71ENDPROC(_bfin_write_DMEM_CONTROL)
72#endif
73
141#endif 74#endif
diff --git a/arch/blackfin/mach-common/cplbinfo.c b/arch/blackfin/mach-common/cplbinfo.c
index caa9623e6bd6..785ca9816971 100644
--- a/arch/blackfin/mach-common/cplbinfo.c
+++ b/arch/blackfin/mach-common/cplbinfo.c
@@ -31,11 +31,10 @@
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/proc_fs.h> 33#include <linux/proc_fs.h>
34#include <linux/uaccess.h>
34 35
35#include <asm/current.h> 36#include <asm/current.h>
36#include <asm/uaccess.h>
37#include <asm/system.h> 37#include <asm/system.h>
38
39#include <asm/cplb.h> 38#include <asm/cplb.h>
40#include <asm/blackfin.h> 39#include <asm/blackfin.h>
41 40
@@ -92,8 +91,7 @@ static char *cplb_print_entry(char *buf, int type)
92 } else 91 } else
93 buf += sprintf(buf, "Data CPLB entry:\n"); 92 buf += sprintf(buf, "Data CPLB entry:\n");
94 93
95 buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\ 94 buf += sprintf(buf, "Address\t\tData\tSize\tValid\tLocked\tSwapin\n\tiCount\toCount\n");
96\tiCount\toCount\n");
97 95
98 while (*p_addr != 0xffffffff) { 96 while (*p_addr != 0xffffffff) {
99 entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data); 97 entry = cplb_find_entry(cplb_addr, cplb_data, *p_addr, *p_data);
@@ -144,8 +142,7 @@ static int cplbinfo_proc_output(char *buf)
144 142
145 p = buf; 143 p = buf;
146 144
147 p += sprintf(p, 145 p += sprintf(p, "------------------ CPLB Information ------------------\n\n");
148 "------------------ CPLB Information ------------------\n\n");
149 146
150 if (bfin_read_IMEM_CONTROL() & ENICPLB) 147 if (bfin_read_IMEM_CONTROL() & ENICPLB)
151 p = cplb_print_entry(p, CPLB_I); 148 p = cplb_print_entry(p, CPLB_I);
@@ -191,9 +188,9 @@ static int __init cplbinfo_init(void)
191{ 188{
192 struct proc_dir_entry *entry; 189 struct proc_dir_entry *entry;
193 190
194 if ((entry = create_proc_entry("cplbinfo", 0, NULL)) == NULL) { 191 entry = create_proc_entry("cplbinfo", 0, NULL);
192 if (!entry)
195 return -ENOMEM; 193 return -ENOMEM;
196 }
197 194
198 entry->read_proc = cplbinfo_read_proc; 195 entry->read_proc = cplbinfo_read_proc;
199 entry->write_proc = cplbinfo_write_proc; 196 entry->write_proc = cplbinfo_write_proc;
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 40045b1386ad..d61bba98fb54 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -49,34 +49,15 @@
49 49
50 50
51#include <linux/linkage.h> 51#include <linux/linkage.h>
52#include <linux/unistd.h>
52#include <asm/blackfin.h> 53#include <asm/blackfin.h>
53#include <asm/unistd.h>
54#include <asm/errno.h> 54#include <asm/errno.h>
55#include <asm/thread_info.h> /* TIF_NEED_RESCHED */ 55#include <asm/thread_info.h> /* TIF_NEED_RESCHED */
56#include <asm/asm-offsets.h> 56#include <asm/asm-offsets.h>
57#include <asm/trace.h>
57 58
58#include <asm/mach-common/context.S> 59#include <asm/mach-common/context.S>
59 60
60#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
61 /*
62 * TODO: this should be proper save/restore, but for now
63 * we'll just cheat and use 0x1/0x13
64 */
65# define DEBUG_START_HWTRACE \
66 P5.l = LO(TBUFCTL); \
67 P5.h = HI(TBUFCTL); \
68 R7 = 0x13; \
69 [P5] = R7;
70# define DEBUG_STOP_HWTRACE \
71 P5.l = LO(TBUFCTL); \
72 P5.h = HI(TBUFCTL); \
73 R7 = 0x01; \
74 [P5] = R7;
75#else
76# define DEBUG_START_HWTRACE
77# define DEBUG_STOP_HWTRACE
78#endif
79
80#ifdef CONFIG_EXCPT_IRQ_SYSC_L1 61#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
81.section .l1.text 62.section .l1.text
82#else 63#else
@@ -110,25 +91,14 @@ ENTRY(_ex_icplb)
110 ASTAT = [sp++]; 91 ASTAT = [sp++];
111 SAVE_ALL_SYS 92 SAVE_ALL_SYS
112 call __cplb_hdr; 93 call __cplb_hdr;
113 DEBUG_START_HWTRACE 94 DEBUG_START_HWTRACE(p5, r7)
114 RESTORE_ALL_SYS 95 RESTORE_ALL_SYS
115 SP = RETN; 96 SP = RETN;
116 rtx; 97 rtx;
117ENDPROC(_ex_icplb) 98ENDPROC(_ex_icplb)
118 99
119ENTRY(_ex_spinlock)
120 /* Transform this into a syscall - twiddle the syscall vector. */
121 p5.l = lo(EVT15);
122 p5.h = hi(EVT15);
123 r7.l = _spinlock_bh;
124 r7.h = _spinlock_bh;
125 [p5] = r7;
126 csync;
127 /* Fall through. */
128ENDPROC(_ex_spinlock)
129
130ENTRY(_ex_syscall) 100ENTRY(_ex_syscall)
131 DEBUG_START_HWTRACE 101 DEBUG_START_HWTRACE(p5, r7)
132 (R7:6,P5:4) = [sp++]; 102 (R7:6,P5:4) = [sp++];
133 ASTAT = [sp++]; 103 ASTAT = [sp++];
134 raise 15; /* invoked by TRAP #0, for sys call */ 104 raise 15; /* invoked by TRAP #0, for sys call */
@@ -136,26 +106,6 @@ ENTRY(_ex_syscall)
136 rtx 106 rtx
137ENDPROC(_ex_syscall) 107ENDPROC(_ex_syscall)
138 108
139ENTRY(_spinlock_bh)
140 SAVE_ALL_SYS
141 /* To end up here, vector 15 was changed - so we have to change it
142 * back.
143 */
144 p0.l = lo(EVT15);
145 p0.h = hi(EVT15);
146 p1.l = _evt_system_call;
147 p1.h = _evt_system_call;
148 [p0] = p1;
149 csync;
150 r0 = [sp + PT_R0];
151 sp += -12;
152 call _sys_bfin_spinlock;
153 sp += 12;
154 [SP + PT_R0] = R0;
155 RESTORE_ALL_SYS
156 rti;
157ENDPROC(_spinlock_bh)
158
159ENTRY(_ex_soft_bp) 109ENTRY(_ex_soft_bp)
160 r7 = retx; 110 r7 = retx;
161 r7 += -2; 111 r7 += -2;
@@ -186,7 +136,7 @@ ENTRY(_ex_single_step)
186 if !cc jump _ex_trap_c; 136 if !cc jump _ex_trap_c;
187 137
188_return_from_exception: 138_return_from_exception:
189 DEBUG_START_HWTRACE 139 DEBUG_START_HWTRACE(p5, r7)
190#ifdef ANOMALY_05000257 140#ifdef ANOMALY_05000257
191 R7=LC0; 141 R7=LC0;
192 LC0=R7; 142 LC0=R7;
@@ -208,7 +158,7 @@ ENTRY(_handle_bad_cplb)
208 * need to make a CPLB exception look like a normal exception 158 * need to make a CPLB exception look like a normal exception
209 */ 159 */
210 160
211 DEBUG_START_HWTRACE 161 DEBUG_START_HWTRACE(p5, r7)
212 RESTORE_ALL_SYS 162 RESTORE_ALL_SYS
213 [--sp] = ASTAT; 163 [--sp] = ASTAT;
214 [--sp] = (R7:6, P5:4); 164 [--sp] = (R7:6, P5:4);
@@ -251,7 +201,7 @@ ENTRY(_ex_trap_c)
251 R6 = SEQSTAT; 201 R6 = SEQSTAT;
252 [P5] = R6; 202 [P5] = R6;
253 203
254 DEBUG_START_HWTRACE 204 DEBUG_START_HWTRACE(p5, r7)
255 (R7:6,P5:4) = [sp++]; 205 (R7:6,P5:4) = [sp++];
256 ASTAT = [sp++]; 206 ASTAT = [sp++];
257 SP = RETN; 207 SP = RETN;
@@ -335,7 +285,7 @@ ENTRY(_trap) /* Exception: 4th entry into system event table(supervisor mode)*/
335 /* Try to deal with syscalls quickly. */ 285 /* Try to deal with syscalls quickly. */
336 [--sp] = ASTAT; 286 [--sp] = ASTAT;
337 [--sp] = (R7:6, P5:4); 287 [--sp] = (R7:6, P5:4);
338 DEBUG_STOP_HWTRACE 288 DEBUG_STOP_HWTRACE(p5, r7)
339 r7 = SEQSTAT; /* reason code is in bit 5:0 */ 289 r7 = SEQSTAT; /* reason code is in bit 5:0 */
340 r6.l = lo(SEQSTAT_EXCAUSE); 290 r6.l = lo(SEQSTAT_EXCAUSE);
341 r6.h = hi(SEQSTAT_EXCAUSE); 291 r6.h = hi(SEQSTAT_EXCAUSE);
@@ -741,6 +691,10 @@ _schedule_and_signal_from_int:
741 r0 = [p0]; 691 r0 = [p0];
742 sti r0; 692 sti r0;
743 693
694 r0 = sp;
695 sp += -12;
696 call _finish_atomic_sections;
697 sp += 12;
744 jump.s .Lresume_userspace; 698 jump.s .Lresume_userspace;
745 699
746_schedule_and_signal: 700_schedule_and_signal:
@@ -790,14 +744,14 @@ ENDPROC(_init_exception_buff)
790ALIGN 744ALIGN
791_extable: 745_extable:
792 /* entry for each EXCAUSE[5:0] 746 /* entry for each EXCAUSE[5:0]
793 * This table bmust be in sync with the table in ./kernel/traps.c 747 * This table must be in sync with the table in ./kernel/traps.c
794 * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined 748 * EXCPT instruction can provide 4 bits of EXCAUSE, allowing 16 to be user defined
795 */ 749 */
796 .long _ex_syscall; /* 0x00 - User Defined - Linux Syscall */ 750 .long _ex_syscall; /* 0x00 - User Defined - Linux Syscall */
797 .long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */ 751 .long _ex_soft_bp /* 0x01 - User Defined - Software breakpoint */
798 .long _ex_trap_c /* 0x02 - User Defined */ 752 .long _ex_trap_c /* 0x02 - User Defined */
799 .long _ex_trap_c /* 0x03 - User Defined - Atomic test and set service */ 753 .long _ex_trap_c /* 0x03 - User Defined - userspace stack overflow */
800 .long _ex_spinlock /* 0x04 - User Defined */ 754 .long _ex_trap_c /* 0x04 - User Defined */
801 .long _ex_trap_c /* 0x05 - User Defined */ 755 .long _ex_trap_c /* 0x05 - User Defined */
802 .long _ex_trap_c /* 0x06 - User Defined */ 756 .long _ex_trap_c /* 0x06 - User Defined */
803 .long _ex_trap_c /* 0x07 - User Defined */ 757 .long _ex_trap_c /* 0x07 - User Defined */
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 8be548e061bf..203e20709163 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -34,6 +34,7 @@
34#include <linux/linkage.h> 34#include <linux/linkage.h>
35#include <asm/entry.h> 35#include <asm/entry.h>
36#include <asm/asm-offsets.h> 36#include <asm/asm-offsets.h>
37#include <asm/trace.h>
37 38
38#include <asm/mach-common/context.S> 39#include <asm/mach-common/context.S>
39 40
@@ -170,10 +171,9 @@ ENTRY(_evt_ivhw)
170 r7.l = W[p5]; 171 r7.l = W[p5];
1711: 1721:
172#endif 173#endif
173 p0.l = lo(TBUFCTL); 174
174 p0.h = hi(TBUFCTL); 175 trace_buffer_stop(p0, r0);
175 r0 = 1; 176
176 [p0] = r0;
177 r0 = IRQ_HWERR; 177 r0 = IRQ_HWERR;
178 r1 = sp; 178 r1 = sp;
179 179
diff --git a/arch/blackfin/mach-common/ints-priority-dc.c b/arch/blackfin/mach-common/ints-priority-dc.c
index 80943bbd37c2..6b9fd03ce835 100644
--- a/arch/blackfin/mach-common/ints-priority-dc.c
+++ b/arch/blackfin/mach-common/ints-priority-dc.c
@@ -183,7 +183,7 @@ static void bf561_gpio_ack_irq(unsigned int irq)
183{ 183{
184 u16 gpionr = irq - IRQ_PF0; 184 u16 gpionr = irq - IRQ_PF0;
185 185
186 if(gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { 186 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
187 set_gpio_data(gpionr, 0); 187 set_gpio_data(gpionr, 0);
188 SSYNC(); 188 SSYNC();
189 } 189 }
@@ -193,7 +193,7 @@ static void bf561_gpio_mask_ack_irq(unsigned int irq)
193{ 193{
194 u16 gpionr = irq - IRQ_PF0; 194 u16 gpionr = irq - IRQ_PF0;
195 195
196 if(gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { 196 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
197 set_gpio_data(gpionr, 0); 197 set_gpio_data(gpionr, 0);
198 SSYNC(); 198 SSYNC();
199 } 199 }
@@ -222,7 +222,7 @@ static unsigned int bf561_gpio_irq_startup(unsigned int irq)
222 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 222 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
223 223
224 ret = gpio_request(gpionr, NULL); 224 ret = gpio_request(gpionr, NULL);
225 if(ret) 225 if (ret)
226 return ret; 226 return ret;
227 227
228 } 228 }
@@ -262,7 +262,7 @@ static int bf561_gpio_irq_type(unsigned int irq, unsigned int type)
262 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 262 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
263 263
264 ret = gpio_request(gpionr, NULL); 264 ret = gpio_request(gpionr, NULL);
265 if(ret) 265 if (ret)
266 return ret; 266 return ret;
267 267
268 } 268 }
@@ -371,6 +371,9 @@ int __init init_arch_irq(void)
371 bfin_write_SICA_IMASK1(SIC_UNMASK_ALL); 371 bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
372 SSYNC(); 372 SSYNC();
373 373
374 bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
375 bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
376
374 local_irq_disable(); 377 local_irq_disable();
375 378
376 init_exception_buff(); 379 init_exception_buff();
@@ -393,7 +396,7 @@ int __init init_arch_irq(void)
393 bfin_write_EVT15(evt_system_call); 396 bfin_write_EVT15(evt_system_call);
394 CSYNC(); 397 CSYNC();
395 398
396 for (irq = 0; irq < SYS_IRQS; irq++) { 399 for (irq = 0; irq <= SYS_IRQS; irq++) {
397 if (irq <= IRQ_CORETMR) 400 if (irq <= IRQ_CORETMR)
398 set_irq_chip(irq, &bf561_core_irqchip); 401 set_irq_chip(irq, &bf561_core_irqchip);
399 else 402 else
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c
index 2cfc7d5aec5c..28a878c3577a 100644
--- a/arch/blackfin/mach-common/ints-priority-sc.c
+++ b/arch/blackfin/mach-common/ints-priority-sc.c
@@ -13,7 +13,7 @@
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> 13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola 14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl> 15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2006 Analog Devices Inc. 16 * Copyright 2004-2007 Analog Devices Inc.
17 * 17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 * 19 *
@@ -65,9 +65,9 @@ atomic_t num_spurious;
65 65
66struct ivgx { 66struct ivgx {
67 /* irq number for request_irq, available in mach-bf533/irq.h */ 67 /* irq number for request_irq, available in mach-bf533/irq.h */
68 int irqno; 68 unsigned int irqno;
69 /* corresponding bit in the SIC_ISR register */ 69 /* corresponding bit in the SIC_ISR register */
70 int isrflag; 70 unsigned int isrflag;
71} ivg_table[NR_PERI_INTS]; 71} ivg_table[NR_PERI_INTS];
72 72
73struct ivg_slice { 73struct ivg_slice {
@@ -88,17 +88,16 @@ static void __init search_IAR(void)
88 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { 88 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
89 int irqn; 89 int irqn;
90 90
91 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = 91 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
92 &ivg_table[irq_pos];
93 92
94 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { 93 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
95 int iar_shift = (irqn & 7) * 4; 94 int iar_shift = (irqn & 7) * 4;
96 if (ivg == 95 if (ivg ==
97 (0xf & 96 (0xf &
98 bfin_read32((unsigned long *) SIC_IAR0 + 97 bfin_read32((unsigned long *)SIC_IAR0 +
99 (irqn >> 3)) >> iar_shift)) { 98 (irqn >> 3)) >> iar_shift)) {
100 ivg_table[irq_pos].irqno = IVG7 + irqn; 99 ivg_table[irq_pos].irqno = IVG7 + irqn;
101 ivg_table[irq_pos].isrflag = 1 << irqn; 100 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
102 ivg7_13[ivg].istop++; 101 ivg7_13[ivg].istop++;
103 irq_pos++; 102 irq_pos++;
104 } 103 }
@@ -141,15 +140,31 @@ static void bfin_core_unmask_irq(unsigned int irq)
141 140
142static void bfin_internal_mask_irq(unsigned int irq) 141static void bfin_internal_mask_irq(unsigned int irq)
143{ 142{
143#ifndef CONFIG_BF54x
144 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 144 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
145 ~(1 << (irq - (IRQ_CORETMR + 1)))); 145 ~(1 << (irq - (IRQ_CORETMR + 1))));
146#else
147 unsigned mask_bank, mask_bit;
148 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
149 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
150 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
151 ~(1 << mask_bit));
152#endif
146 SSYNC(); 153 SSYNC();
147} 154}
148 155
149static void bfin_internal_unmask_irq(unsigned int irq) 156static void bfin_internal_unmask_irq(unsigned int irq)
150{ 157{
158#ifndef CONFIG_BF54x
151 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 159 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
152 (1 << (irq - (IRQ_CORETMR + 1)))); 160 (1 << (irq - (IRQ_CORETMR + 1))));
161#else
162 unsigned mask_bank, mask_bit;
163 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
164 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
165 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
166 (1 << mask_bit));
167#endif
153 SSYNC(); 168 SSYNC();
154} 169}
155 170
@@ -206,7 +221,7 @@ static struct irq_chip bfin_generic_error_irqchip = {
206}; 221};
207 222
208static void bfin_demux_error_irq(unsigned int int_err_irq, 223static void bfin_demux_error_irq(unsigned int int_err_irq,
209 struct irq_desc *intb_desc) 224 struct irq_desc *intb_desc)
210{ 225{
211 int irq = 0; 226 int irq = 0;
212 227
@@ -270,8 +285,8 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
270 } 285 }
271 286
272 pr_debug("IRQ %d:" 287 pr_debug("IRQ %d:"
273 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", 288 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
274 irq); 289 irq);
275 } 290 }
276 } else 291 } else
277 printk(KERN_ERR 292 printk(KERN_ERR
@@ -279,11 +294,10 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
279 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", 294 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
280 __FUNCTION__, __FILE__, __LINE__); 295 __FUNCTION__, __FILE__, __LINE__);
281 296
282
283} 297}
284#endif /* BF537_GENERIC_ERROR_INT_DEMUX */ 298#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
285 299
286#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 300#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x)
287 301
288static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; 302static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
289static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; 303static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
@@ -361,8 +375,7 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
361 } 375 }
362 376
363 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | 377 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
364 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 378 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
365 {
366 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { 379 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
367 ret = gpio_request(gpionr, NULL); 380 ret = gpio_request(gpionr, NULL);
368 if (ret) 381 if (ret)
@@ -407,7 +420,6 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
407 return 0; 420 return 0;
408} 421}
409 422
410
411static struct irq_chip bfin_gpio_irqchip = { 423static struct irq_chip bfin_gpio_irqchip = {
412 .ack = bfin_gpio_ack_irq, 424 .ack = bfin_gpio_ack_irq,
413 .mask = bfin_gpio_mask_irq, 425 .mask = bfin_gpio_mask_irq,
@@ -419,20 +431,20 @@ static struct irq_chip bfin_gpio_irqchip = {
419}; 431};
420 432
421static void bfin_demux_gpio_irq(unsigned int intb_irq, 433static void bfin_demux_gpio_irq(unsigned int intb_irq,
422 struct irq_desc *intb_desc) 434 struct irq_desc *intb_desc)
423{ 435{
424 u16 i; 436 u16 i;
437 struct irq_desc *desc;
425 438
426 for (i = 0; i < MAX_BLACKFIN_GPIOS; i+=16) { 439 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
427 int irq = IRQ_PF0 + i; 440 int irq = IRQ_PF0 + i;
428 int flag_d = get_gpiop_data(i); 441 int flag_d = get_gpiop_data(i);
429 int mask = 442 int mask =
430 flag_d & (gpio_enabled[gpio_bank(i)] & 443 flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
431 get_gpiop_maska(i));
432 444
433 while (mask) { 445 while (mask) {
434 if (mask & 1) { 446 if (mask & 1) {
435 struct irq_desc *desc = irq_desc + irq; 447 desc = irq_desc + irq;
436 desc->handle_irq(irq, desc); 448 desc->handle_irq(irq, desc);
437 } 449 }
438 irq++; 450 irq++;
@@ -441,6 +453,264 @@ static void bfin_demux_gpio_irq(unsigned int intb_irq,
441 } 453 }
442} 454}
443 455
456#else /* CONFIG_IRQCHIP_DEMUX_GPIO */
457
458#define NR_PINT_SYS_IRQS 4
459#define NR_PINT_BITS 32
460#define NR_PINTS 160
461#define IRQ_NOT_AVAIL 0xFF
462
463#define PINT_2_BANK(x) ((x) >> 5)
464#define PINT_2_BIT(x) ((x) & 0x1F)
465#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
466
467static unsigned char irq2pint_lut[NR_PINTS];
468static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
469
470struct pin_int_t {
471 unsigned int mask_set;
472 unsigned int mask_clear;
473 unsigned int request;
474 unsigned int assign;
475 unsigned int edge_set;
476 unsigned int edge_clear;
477 unsigned int invert_set;
478 unsigned int invert_clear;
479 unsigned int pinstate;
480 unsigned int latch;
481};
482
483static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
484 (struct pin_int_t *)PINT0_MASK_SET,
485 (struct pin_int_t *)PINT1_MASK_SET,
486 (struct pin_int_t *)PINT2_MASK_SET,
487 (struct pin_int_t *)PINT3_MASK_SET,
488};
489
490unsigned short get_irq_base(u8 bank, u8 bmap)
491{
492
493 u16 irq_base;
494
495 if (bank < 2) { /*PA-PB */
496 irq_base = IRQ_PA0 + bmap * 16;
497 } else { /*PC-PJ */
498 irq_base = IRQ_PC0 + bmap * 16;
499 }
500
501 return irq_base;
502
503}
504
505 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
506void init_pint_lut(void)
507{
508 u16 bank, bit, irq_base, bit_pos;
509 u32 pint_assign;
510 u8 bmap;
511
512 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
513
514 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
515
516 pint_assign = pint[bank]->assign;
517
518 for (bit = 0; bit < NR_PINT_BITS; bit++) {
519
520 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
521
522 irq_base = get_irq_base(bank, bmap);
523
524 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
525 bit_pos = bit + bank * NR_PINT_BITS;
526
527 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
528 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
529
530 }
531
532 }
533
534}
535
536static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
537
538static void bfin_gpio_ack_irq(unsigned int irq)
539{
540 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
541
542 pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val);
543 SSYNC();
544}
545
546static void bfin_gpio_mask_ack_irq(unsigned int irq)
547{
548 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
549 u32 pintbit = PINT_BIT(pint_val);
550 u8 bank = PINT_2_BANK(pint_val);
551
552 pint[bank]->request = pintbit;
553 pint[bank]->mask_clear = pintbit;
554 SSYNC();
555}
556
557static void bfin_gpio_mask_irq(unsigned int irq)
558{
559 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
560
561 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
562 SSYNC();
563}
564
565static void bfin_gpio_unmask_irq(unsigned int irq)
566{
567 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
568 u32 pintbit = PINT_BIT(pint_val);
569 u8 bank = PINT_2_BANK(pint_val);
570
571 pint[bank]->request = pintbit;
572 pint[bank]->mask_set = pintbit;
573 SSYNC();
574}
575
576static unsigned int bfin_gpio_irq_startup(unsigned int irq)
577{
578 unsigned int ret;
579 u16 gpionr = irq - IRQ_PA0;
580 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
581
582 if (pint_val == IRQ_NOT_AVAIL)
583 return -ENODEV;
584
585 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
586 ret = gpio_request(gpionr, NULL);
587 if (ret)
588 return ret;
589 }
590
591 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
592 bfin_gpio_unmask_irq(irq);
593
594 return ret;
595}
596
597static void bfin_gpio_irq_shutdown(unsigned int irq)
598{
599 bfin_gpio_mask_irq(irq);
600 gpio_free(irq - IRQ_PA0);
601 gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0);
602}
603
604static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
605{
606
607 unsigned int ret;
608 u16 gpionr = irq - IRQ_PA0;
609 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
610 u32 pintbit = PINT_BIT(pint_val);
611 u8 bank = PINT_2_BANK(pint_val);
612
613 if (pint_val == IRQ_NOT_AVAIL)
614 return -ENODEV;
615
616 if (type == IRQ_TYPE_PROBE) {
617 /* only probe unenabled GPIO interrupt lines */
618 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
619 return 0;
620 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
621 }
622
623 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
624 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
625 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
626 ret = gpio_request(gpionr, NULL);
627 if (ret)
628 return ret;
629 }
630
631 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
632 } else {
633 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
634 return 0;
635 }
636
637 gpio_direction_input(gpionr);
638
639 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
640 pint[bank]->edge_set = pintbit;
641 } else {
642 pint[bank]->edge_clear = pintbit;
643 }
644
645 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
646 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
647 else
648 pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */
649
650 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
651 pint[bank]->invert_set = pintbit;
652 else
653 pint[bank]->invert_set = pintbit;
654
655 SSYNC();
656
657 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
658 set_irq_handler(irq, handle_edge_irq);
659 else
660 set_irq_handler(irq, handle_level_irq);
661
662 return 0;
663}
664
665static struct irq_chip bfin_gpio_irqchip = {
666 .ack = bfin_gpio_ack_irq,
667 .mask = bfin_gpio_mask_irq,
668 .mask_ack = bfin_gpio_mask_ack_irq,
669 .unmask = bfin_gpio_unmask_irq,
670 .set_type = bfin_gpio_irq_type,
671 .startup = bfin_gpio_irq_startup,
672 .shutdown = bfin_gpio_irq_shutdown
673};
674
675static void bfin_demux_gpio_irq(unsigned int intb_irq,
676 struct irq_desc *intb_desc)
677{
678 u8 bank, pint_val;
679 u32 request, irq;
680 struct irq_desc *desc;
681
682 switch (intb_irq) {
683 case IRQ_PINT0:
684 bank = 0;
685 break;
686 case IRQ_PINT2:
687 bank = 2;
688 break;
689 case IRQ_PINT3:
690 bank = 3;
691 break;
692 case IRQ_PINT1:
693 bank = 1;
694 break;
695 default:
696 return;
697 }
698
699 pint_val = bank * NR_PINT_BITS;
700
701 request = pint[bank]->request;
702
703 while (request) {
704 if (request & 1) {
705 irq = pint2irq_lut[pint_val] + SYS_IRQS;
706 desc = irq_desc + irq;
707 desc->handle_irq(irq, desc);
708 }
709 pint_val++;
710 request >>= 1;
711 }
712
713}
444#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */ 714#endif /* CONFIG_IRQCHIP_DEMUX_GPIO */
445 715
446/* 716/*
@@ -452,7 +722,18 @@ int __init init_arch_irq(void)
452 int irq; 722 int irq;
453 unsigned long ilat = 0; 723 unsigned long ilat = 0;
454 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ 724 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
725#ifdef CONFIG_BF54x
726 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
727 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
728 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
729 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
730 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
731 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
732#else
455 bfin_write_SIC_IMASK(SIC_UNMASK_ALL); 733 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
734 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
735#endif
736
456 SSYNC(); 737 SSYNC();
457 738
458 local_irq_disable(); 739 local_irq_disable();
@@ -475,7 +756,18 @@ int __init init_arch_irq(void)
475 bfin_write_EVT15(evt_system_call); 756 bfin_write_EVT15(evt_system_call);
476 CSYNC(); 757 CSYNC();
477 758
478 for (irq = 0; irq < SYS_IRQS; irq++) { 759#if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x)
760#ifdef CONFIG_PINTx_REASSIGN
761 pint[0]->assign = CONFIG_PINT0_ASSIGN;
762 pint[1]->assign = CONFIG_PINT1_ASSIGN;
763 pint[2]->assign = CONFIG_PINT2_ASSIGN;
764 pint[3]->assign = CONFIG_PINT3_ASSIGN;
765#endif
766 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
767 init_pint_lut();
768#endif
769
770 for (irq = 0; irq <= SYS_IRQS; irq++) {
479 if (irq <= IRQ_CORETMR) 771 if (irq <= IRQ_CORETMR)
480 set_irq_chip(irq, &bfin_core_irqchip); 772 set_irq_chip(irq, &bfin_core_irqchip);
481 else 773 else
@@ -484,20 +776,42 @@ int __init init_arch_irq(void)
484 if (irq != IRQ_GENERIC_ERROR) { 776 if (irq != IRQ_GENERIC_ERROR) {
485#endif 777#endif
486 778
779 switch (irq) {
487#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 780#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
488 if ((irq != IRQ_PROG_INTA) /*PORT F & G MASK_A Interrupt*/ 781#ifndef CONFIG_BF54x
489# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) 782 case IRQ_PROG_INTA:
490 && (irq != IRQ_MAC_RX) /*PORT H MASK_A Interrupt*/ 783 set_irq_chained_handler(irq,
491# endif 784 bfin_demux_gpio_irq);
492 ) { 785 break;
786#if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
787 case IRQ_MAC_RX:
788 set_irq_chained_handler(irq,
789 bfin_demux_gpio_irq);
790 break;
493#endif 791#endif
494 set_irq_handler(irq, handle_simple_irq); 792#else
495#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 793 case IRQ_PINT0:
496 } else {
497 set_irq_chained_handler(irq, 794 set_irq_chained_handler(irq,
498 bfin_demux_gpio_irq); 795 bfin_demux_gpio_irq);
499 } 796 break;
797 case IRQ_PINT1:
798 set_irq_chained_handler(irq,
799 bfin_demux_gpio_irq);
800 break;
801 case IRQ_PINT2:
802 set_irq_chained_handler(irq,
803 bfin_demux_gpio_irq);
804 break;
805 case IRQ_PINT3:
806 set_irq_chained_handler(irq,
807 bfin_demux_gpio_irq);
808 break;
809#endif /*CONFIG_BF54x */
500#endif 810#endif
811 default:
812 set_irq_handler(irq, handle_simple_irq);
813 break;
814 }
501 815
502#ifdef BF537_GENERIC_ERROR_INT_DEMUX 816#ifdef BF537_GENERIC_ERROR_INT_DEMUX
503 } else { 817 } else {
@@ -513,7 +827,11 @@ int __init init_arch_irq(void)
513#endif 827#endif
514 828
515#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 829#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
830#ifndef CONFIG_BF54x
516 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) { 831 for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
832#else
833 for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
834#endif
517 set_irq_chip(irq, &bfin_gpio_irqchip); 835 set_irq_chip(irq, &bfin_gpio_irqchip);
518 /* if configured as edge, then will be changed to do_edge_IRQ */ 836 /* if configured as edge, then will be changed to do_edge_IRQ */
519 set_irq_handler(irq, handle_level_irq); 837 set_irq_handler(irq, handle_level_irq);
@@ -526,8 +844,7 @@ int __init init_arch_irq(void)
526 bfin_write_ILAT(ilat); 844 bfin_write_ILAT(ilat);
527 CSYNC(); 845 CSYNC();
528 846
529 printk(KERN_INFO 847 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
530 "Configuring Blackfin Priority Driven Interrupts\n");
531 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx, 848 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
532 * local_irq_enable() 849 * local_irq_enable()
533 */ 850 */
@@ -538,14 +855,13 @@ int __init init_arch_irq(void)
538 /* Enable interrupts IVG7-15 */ 855 /* Enable interrupts IVG7-15 */
539 irq_flags = irq_flags | IMASK_IVG15 | 856 irq_flags = irq_flags | IMASK_IVG15 |
540 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | 857 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
541 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | 858 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
542 IMASK_IVGHW;
543 859
544 return 0; 860 return 0;
545} 861}
546 862
547#ifdef CONFIG_DO_IRQ_L1 863#ifdef CONFIG_DO_IRQ_L1
548void do_irq(int vec, struct pt_regs *fp)__attribute__((l1_text)); 864void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text));
549#endif 865#endif
550 866
551void do_irq(int vec, struct pt_regs *fp) 867void do_irq(int vec, struct pt_regs *fp)
@@ -555,9 +871,25 @@ void do_irq(int vec, struct pt_regs *fp)
555 } else { 871 } else {
556 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; 872 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
557 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; 873 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
558 unsigned long sic_status; 874#ifdef CONFIG_BF54x
875 unsigned long sic_status[3];
559 876
560 SSYNC(); 877 SSYNC();
878 sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0);
879 sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1);
880 sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2);
881
882 for (;; ivg++) {
883 if (ivg >= ivg_stop) {
884 atomic_inc(&num_spurious);
885 return;
886 }
887 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
888 break;
889 }
890#else
891 unsigned long sic_status;
892 SSYNC();
561 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); 893 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
562 894
563 for (;; ivg++) { 895 for (;; ivg++) {
@@ -567,6 +899,7 @@ void do_irq(int vec, struct pt_regs *fp)
567 } else if (sic_status & ivg->isrflag) 899 } else if (sic_status & ivg->isrflag)
568 break; 900 break;
569 } 901 }
902#endif
570 vec = ivg->irqno; 903 vec = ivg->irqno;
571 } 904 }
572 asm_do_IRQ(vec, fp); 905 asm_do_IRQ(vec, fp);
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 150ef5d088dc..1772d8d2c1a7 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -35,10 +35,10 @@
35#include <linux/pm.h> 35#include <linux/pm.h>
36#include <linux/sched.h> 36#include <linux/sched.h>
37#include <linux/proc_fs.h> 37#include <linux/proc_fs.h>
38#include <linux/io.h>
39#include <linux/irq.h>
38 40
39#include <asm/io.h>
40#include <asm/dpmc.h> 41#include <asm/dpmc.h>
41#include <asm/irq.h>
42#include <asm/gpio.h> 42#include <asm/gpio.h>
43 43
44#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H 44#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
diff --git a/arch/blackfin/mm/blackfin_sram.c b/arch/blackfin/mm/blackfin_sram.c
index 68107924639e..16c6169ed01b 100644
--- a/arch/blackfin/mm/blackfin_sram.c
+++ b/arch/blackfin/mm/blackfin_sram.c
@@ -87,7 +87,7 @@ void __init l1sram_init(void)
87 L1_SCRATCH_LENGTH >> 10); 87 L1_SCRATCH_LENGTH >> 10);
88 88
89 memset(&l1_ssram, 0x00, sizeof(l1_ssram)); 89 memset(&l1_ssram, 0x00, sizeof(l1_ssram));
90 l1_ssram[0].paddr = (void*)L1_SCRATCH_START; 90 l1_ssram[0].paddr = (void *)L1_SCRATCH_START;
91 l1_ssram[0].size = L1_SCRATCH_LENGTH; 91 l1_ssram[0].size = L1_SCRATCH_LENGTH;
92 l1_ssram[0].flag = SRAM_SLT_FREE; 92 l1_ssram[0].flag = SRAM_SLT_FREE;
93 93
@@ -126,7 +126,7 @@ void __init l1_inst_sram_init(void)
126{ 126{
127#if L1_CODE_LENGTH != 0 127#if L1_CODE_LENGTH != 0
128 memset(&l1_inst_sram, 0x00, sizeof(l1_inst_sram)); 128 memset(&l1_inst_sram, 0x00, sizeof(l1_inst_sram));
129 l1_inst_sram[0].paddr = (void*)L1_CODE_START + (_etext_l1 - _stext_l1); 129 l1_inst_sram[0].paddr = (void *)L1_CODE_START + (_etext_l1 - _stext_l1);
130 l1_inst_sram[0].size = L1_CODE_LENGTH - (_etext_l1 - _stext_l1); 130 l1_inst_sram[0].size = L1_CODE_LENGTH - (_etext_l1 - _stext_l1);
131 l1_inst_sram[0].flag = SRAM_SLT_FREE; 131 l1_inst_sram[0].flag = SRAM_SLT_FREE;
132 132
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 570356dbe028..68459cc052a1 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -29,8 +29,8 @@
29 29
30#include <linux/swap.h> 30#include <linux/swap.h>
31#include <linux/bootmem.h> 31#include <linux/bootmem.h>
32#include <linux/uaccess.h>
32#include <asm/bfin-global.h> 33#include <asm/bfin-global.h>
33#include <asm/uaccess.h>
34#include <asm/l1layout.h> 34#include <asm/l1layout.h>
35#include "blackfin_sram.h" 35#include "blackfin_sram.h"
36 36
@@ -168,42 +168,31 @@ void __init mem_init(void)
168 } 168 }
169} 169}
170 170
171#ifdef CONFIG_BLK_DEV_INITRD 171static __init void free_init_pages(const char *what, unsigned long begin, unsigned long end)
172void __init free_initrd_mem(unsigned long start, unsigned long end)
173{ 172{
174 int pages = 0; 173 unsigned long addr;
175 for (; start < end; start += PAGE_SIZE) { 174 /* next to check that the page we free is not a partial page */
176 ClearPageReserved(virt_to_page(start)); 175 for (addr = begin; addr + PAGE_SIZE <= end; addr += PAGE_SIZE) {
177 init_page_count(virt_to_page(start)); 176 ClearPageReserved(virt_to_page(addr));
178 free_page(start); 177 init_page_count(virt_to_page(addr));
178 free_page(addr);
179 totalram_pages++; 179 totalram_pages++;
180 pages++;
181 } 180 }
182 printk(KERN_NOTICE "Freeing initrd memory: %dk freed\n", pages); 181 printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
182}
183
184#ifdef CONFIG_BLK_DEV_INITRD
185void __init free_initrd_mem(unsigned long start, unsigned long end)
186{
187 free_init_pages("initrd memory", start, end);
183} 188}
184#endif 189#endif
185 190
186void __init free_initmem(void) 191void __init free_initmem(void)
187{ 192{
188#ifdef CONFIG_RAMKERNEL 193#ifdef CONFIG_RAMKERNEL
189 unsigned long addr; 194 free_init_pages("unused kernel memory",
190 /* 195 (unsigned long)(&__init_begin),
191 * the following code should be cool even if these sections 196 (unsigned long)(&__init_end));
192 * are not page aligned.
193 */
194 addr = PAGE_ALIGN((unsigned long)(__init_begin));
195 /* next to check that the page we free is not a partial page */
196 for (; addr + PAGE_SIZE < (unsigned long)(__init_end);
197 addr += PAGE_SIZE) {
198 ClearPageReserved(virt_to_page(addr));
199 init_page_count(virt_to_page(addr));
200 free_page(addr);
201 totalram_pages++;
202 }
203 printk(KERN_NOTICE
204 "Freeing unused kernel memory: %ldk freed (0x%x - 0x%x)\n",
205 (addr - PAGE_ALIGN((long)__init_begin)) >> 10,
206 (int)(PAGE_ALIGN((unsigned long)(__init_begin))),
207 (int)(addr - PAGE_SIZE));
208#endif 197#endif
209} 198}
diff --git a/arch/blackfin/oprofile/common.c b/arch/blackfin/oprofile/common.c
index 009a1700c854..cb8b8d5af34f 100644
--- a/arch/blackfin/oprofile/common.c
+++ b/arch/blackfin/oprofile/common.c
@@ -33,12 +33,12 @@
33#include <linux/smp.h> 33#include <linux/smp.h>
34#include <linux/errno.h> 34#include <linux/errno.h>
35#include <linux/mutex.h> 35#include <linux/mutex.h>
36#include <linux/ptrace.h>
37#include <linux/irq.h>
38#include <linux/io.h>
36 39
37#include <asm/ptrace.h>
38#include <asm/system.h> 40#include <asm/system.h>
39#include <asm/blackfin.h> 41#include <asm/blackfin.h>
40#include <asm/irq.h>
41#include <asm/io.h>
42 42
43#include "op_blackfin.h" 43#include "op_blackfin.h"
44 44
diff --git a/arch/blackfin/oprofile/op_model_bf533.c b/arch/blackfin/oprofile/op_model_bf533.c
index b7a20a006b49..872dffe33623 100644
--- a/arch/blackfin/oprofile/op_model_bf533.c
+++ b/arch/blackfin/oprofile/op_model_bf533.c
@@ -32,12 +32,12 @@
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/smp.h> 33#include <linux/smp.h>
34#include <linux/interrupt.h> 34#include <linux/interrupt.h>
35#include <asm/ptrace.h> 35#include <linux/ptrace.h>
36#include <linux/irq.h>
37#include <linux/io.h>
36#include <asm/system.h> 38#include <asm/system.h>
37#include <asm/processor.h> 39#include <asm/processor.h>
38#include <asm/blackfin.h> 40#include <asm/blackfin.h>
39#include <asm/irq.h>
40#include <asm/io.h>
41 41
42#include "op_blackfin.h" 42#include "op_blackfin.h"
43 43
diff --git a/arch/blackfin/oprofile/timer_int.c b/arch/blackfin/oprofile/timer_int.c
index 8fba16c846c9..6c6f8606af4c 100644
--- a/arch/blackfin/oprofile/timer_int.c
+++ b/arch/blackfin/oprofile/timer_int.c
@@ -31,8 +31,7 @@
31#include <linux/smp.h> 31#include <linux/smp.h>
32#include <linux/irq.h> 32#include <linux/irq.h>
33#include <linux/oprofile.h> 33#include <linux/oprofile.h>
34 34#include <linux/ptrace.h>
35#include <asm/ptrace.h>
36 35
37static void enable_sys_timer0() 36static void enable_sys_timer0()
38{ 37{
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index b941c74a06c4..80572e2c9dab 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -877,7 +877,7 @@ config NET_NETX
877 877
878config DM9000 878config DM9000
879 tristate "DM9000 support" 879 tristate "DM9000 support"
880 depends on ARM || MIPS 880 depends on ARM || BLACKFIN || MIPS
881 select CRC32 881 select CRC32
882 select MII 882 select MII
883 ---help--- 883 ---help---
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 264fa0e2e075..c3de81bf090a 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c
@@ -104,6 +104,18 @@
104#define PRINTK(args...) printk(KERN_DEBUG args) 104#define PRINTK(args...) printk(KERN_DEBUG args)
105#endif 105#endif
106 106
107#ifdef CONFIG_BLACKFIN
108#define readsb insb
109#define readsw insw
110#define readsl insl
111#define writesb outsb
112#define writesw outsw
113#define writesl outsl
114#define DM9000_IRQ_FLAGS (IRQF_SHARED | IRQF_TRIGGER_HIGH)
115#else
116#define DM9000_IRQ_FLAGS IRQF_SHARED
117#endif
118
107/* 119/*
108 * Transmit timeout, default 5 seconds. 120 * Transmit timeout, default 5 seconds.
109 */ 121 */
@@ -431,6 +443,9 @@ dm9000_probe(struct platform_device *pdev)
431 db->io_addr = (void __iomem *)base; 443 db->io_addr = (void __iomem *)base;
432 db->io_data = (void __iomem *)(base + 4); 444 db->io_data = (void __iomem *)(base + 4);
433 445
446 /* ensure at least we have a default set of IO routines */
447 dm9000_set_io(db, 2);
448
434 } else { 449 } else {
435 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 450 db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
436 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 451 db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
@@ -614,7 +629,7 @@ dm9000_open(struct net_device *dev)
614 629
615 PRINTK2("entering dm9000_open\n"); 630 PRINTK2("entering dm9000_open\n");
616 631
617 if (request_irq(dev->irq, &dm9000_interrupt, IRQF_SHARED, dev->name, dev)) 632 if (request_irq(dev->irq, &dm9000_interrupt, DM9000_IRQ_FLAGS, dev->name, dev))
618 return -EAGAIN; 633 return -EAGAIN;
619 634
620 /* Initialize DM9000 board */ 635 /* Initialize DM9000 board */
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 315ea9916456..2adbed4e10f3 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -556,7 +556,7 @@ choice
556 556
557config SERIAL_BFIN_DMA 557config SERIAL_BFIN_DMA
558 bool "DMA mode" 558 bool "DMA mode"
559 depends on DMA_UNCACHED_1M 559 depends on DMA_UNCACHED_1M && !KGDB_UART
560 help 560 help
561 This driver works under DMA mode. If this option is selected, the 561 This driver works under DMA mode. If this option is selected, the
562 blackfin simple dma driver is also enabled. 562 blackfin simple dma driver is also enabled.
@@ -599,7 +599,7 @@ config UART0_RTS_PIN
599 599
600config SERIAL_BFIN_UART1 600config SERIAL_BFIN_UART1
601 bool "Enable UART1" 601 bool "Enable UART1"
602 depends on SERIAL_BFIN && (BF534 || BF536 || BF537) 602 depends on SERIAL_BFIN && (BF534 || BF536 || BF537 || BF54x)
603 help 603 help
604 Enable UART1 604 Enable UART1
605 605
@@ -612,18 +612,58 @@ config BFIN_UART1_CTSRTS
612 612
613config UART1_CTS_PIN 613config UART1_CTS_PIN
614 int "UART1 CTS pin" 614 int "UART1 CTS pin"
615 depends on BFIN_UART1_CTSRTS 615 depends on BFIN_UART1_CTSRTS && (BF53x || BF561)
616 default -1 616 default -1
617 help 617 help
618 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. 618 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
619 619
620config UART1_RTS_PIN 620config UART1_RTS_PIN
621 int "UART1 RTS pin" 621 int "UART1 RTS pin"
622 depends on BFIN_UART1_CTSRTS 622 depends on BFIN_UART1_CTSRTS && (BF53x || BF561)
623 default -1 623 default -1
624 help 624 help
625 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map. 625 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
626 626
627config SERIAL_BFIN_UART2
628 bool "Enable UART2"
629 depends on SERIAL_BFIN && (BF54x)
630 help
631 Enable UART2
632
633config BFIN_UART2_CTSRTS
634 bool "Enable UART2 hardware flow control"
635 depends on SERIAL_BFIN_UART2
636 help
637 Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
638 signal.
639
640config UART2_CTS_PIN
641 int "UART2 CTS pin"
642 depends on BFIN_UART2_CTSRTS
643 default -1
644 help
645 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
646
647config UART2_RTS_PIN
648 int "UART2 RTS pin"
649 depends on BFIN_UART2_CTSRTS
650 default -1
651 help
652 Refer to ./include/asm-blackfin/gpio.h to see the GPIO map.
653
654config SERIAL_BFIN_UART3
655 bool "Enable UART3"
656 depends on SERIAL_BFIN && (BF54x)
657 help
658 Enable UART3
659
660config BFIN_UART3_CTSRTS
661 bool "Enable UART3 hardware flow control"
662 depends on SERIAL_BFIN_UART3
663 help
664 Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
665 signal.
666
627config SERIAL_IMX 667config SERIAL_IMX
628 bool "IMX serial port support" 668 bool "IMX serial port support"
629 depends on ARM && ARCH_IMX 669 depends on ARM && ARCH_IMX
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index 22569bd5d821..66c92bc36f3d 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -41,6 +41,11 @@
41#include <linux/tty_flip.h> 41#include <linux/tty_flip.h>
42#include <linux/serial_core.h> 42#include <linux/serial_core.h>
43 43
44#ifdef CONFIG_KGDB_UART
45#include <linux/kgdb.h>
46#include <asm/irq_regs.h>
47#endif
48
44#include <asm/gpio.h> 49#include <asm/gpio.h>
45#include <asm/mach/bfin_serial_5xx.h> 50#include <asm/mach/bfin_serial_5xx.h>
46 51
@@ -81,15 +86,29 @@ static void bfin_serial_stop_tx(struct uart_port *port)
81{ 86{
82 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; 87 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
83 88
89#ifdef CONFIG_BF54x
90 while (!(UART_GET_LSR(uart) & TEMT))
91 continue;
92#endif
93
84#ifdef CONFIG_SERIAL_BFIN_DMA 94#ifdef CONFIG_SERIAL_BFIN_DMA
85 disable_dma(uart->tx_dma_channel); 95 disable_dma(uart->tx_dma_channel);
86#else 96#else
97#ifdef CONFIG_BF54x
98 /* Waiting for Transmission Finished */
99 while (!(UART_GET_LSR(uart) & TFI))
100 continue;
101 /* Clear TFI bit */
102 UART_PUT_LSR(uart, TFI);
103 UART_CLEAR_IER(uart, ETBEI);
104#else
87 unsigned short ier; 105 unsigned short ier;
88 106
89 ier = UART_GET_IER(uart); 107 ier = UART_GET_IER(uart);
90 ier &= ~ETBEI; 108 ier &= ~ETBEI;
91 UART_PUT_IER(uart, ier); 109 UART_PUT_IER(uart, ier);
92#endif 110#endif
111#endif
93} 112}
94 113
95/* 114/*
@@ -102,12 +121,16 @@ static void bfin_serial_start_tx(struct uart_port *port)
102#ifdef CONFIG_SERIAL_BFIN_DMA 121#ifdef CONFIG_SERIAL_BFIN_DMA
103 bfin_serial_dma_tx_chars(uart); 122 bfin_serial_dma_tx_chars(uart);
104#else 123#else
124#ifdef CONFIG_BF54x
125 UART_SET_IER(uart, ETBEI);
126#else
105 unsigned short ier; 127 unsigned short ier;
106 ier = UART_GET_IER(uart); 128 ier = UART_GET_IER(uart);
107 ier |= ETBEI; 129 ier |= ETBEI;
108 UART_PUT_IER(uart, ier); 130 UART_PUT_IER(uart, ier);
109 bfin_serial_tx_chars(uart); 131 bfin_serial_tx_chars(uart);
110#endif 132#endif
133#endif
111} 134}
112 135
113/* 136/*
@@ -116,11 +139,18 @@ static void bfin_serial_start_tx(struct uart_port *port)
116static void bfin_serial_stop_rx(struct uart_port *port) 139static void bfin_serial_stop_rx(struct uart_port *port)
117{ 140{
118 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; 141 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
142#ifdef CONFIG_BF54x
143 UART_CLEAR_IER(uart, ERBFI);
144#else
119 unsigned short ier; 145 unsigned short ier;
120 146
121 ier = UART_GET_IER(uart); 147 ier = UART_GET_IER(uart);
148#ifdef CONFIG_KGDB_UART
149 if (uart->port.line != CONFIG_KGDB_UART_PORT)
150#endif
122 ier &= ~ERBFI; 151 ier &= ~ERBFI;
123 UART_PUT_IER(uart, ier); 152 UART_PUT_IER(uart, ier);
153#endif
124} 154}
125 155
126/* 156/*
@@ -130,6 +160,49 @@ static void bfin_serial_enable_ms(struct uart_port *port)
130{ 160{
131} 161}
132 162
163#ifdef CONFIG_KGDB_UART
164static int kgdb_entry_state;
165
166void kgdb_put_debug_char(int chr)
167{
168 struct bfin_serial_port *uart;
169
170 if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
171 uart = &bfin_serial_ports[0];
172 else
173 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
174
175 while (!(UART_GET_LSR(uart) & THRE)) {
176 __builtin_bfin_ssync();
177 }
178 UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
179 __builtin_bfin_ssync();
180 UART_PUT_CHAR(uart, (unsigned char)chr);
181 __builtin_bfin_ssync();
182}
183
184int kgdb_get_debug_char(void)
185{
186 struct bfin_serial_port *uart;
187 unsigned char chr;
188
189 if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
190 uart = &bfin_serial_ports[0];
191 else
192 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
193
194 while(!(UART_GET_LSR(uart) & DR)) {
195 __builtin_bfin_ssync();
196 }
197 UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
198 __builtin_bfin_ssync();
199 chr = UART_GET_CHAR(uart);
200 __builtin_bfin_ssync();
201
202 return chr;
203}
204#endif
205
133#ifdef CONFIG_SERIAL_BFIN_PIO 206#ifdef CONFIG_SERIAL_BFIN_PIO
134static void local_put_char(struct bfin_serial_port *uart, char ch) 207static void local_put_char(struct bfin_serial_port *uart, char ch)
135{ 208{
@@ -152,6 +225,9 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
152{ 225{
153 struct tty_struct *tty = uart->port.info->tty; 226 struct tty_struct *tty = uart->port.info->tty;
154 unsigned int status, ch, flg; 227 unsigned int status, ch, flg;
228#ifdef CONFIG_KGDB_UART
229 struct pt_regs *regs = get_irq_regs();
230#endif
155#ifdef BF533_FAMILY 231#ifdef BF533_FAMILY
156 static int in_break = 0; 232 static int in_break = 0;
157#endif 233#endif
@@ -160,6 +236,27 @@ static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
160 ch = UART_GET_CHAR(uart); 236 ch = UART_GET_CHAR(uart);
161 uart->port.icount.rx++; 237 uart->port.icount.rx++;
162 238
239#ifdef CONFIG_KGDB_UART
240 if (uart->port.line == CONFIG_KGDB_UART_PORT) {
241 if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */
242 kgdb_breakkey_pressed(regs);
243 return;
244 } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */
245 kgdb_entry_state = 1;
246 } else if (kgdb_entry_state == 1 && ch == 'q') {
247 kgdb_entry_state = 0;
248 kgdb_breakkey_pressed(regs);
249 return;
250 } else if (ch == 0x3) {/* Ctrl + C */
251 kgdb_entry_state = 0;
252 kgdb_breakkey_pressed(regs);
253 return;
254 } else {
255 kgdb_entry_state = 0;
256 }
257 }
258#endif
259
163#ifdef BF533_FAMILY 260#ifdef BF533_FAMILY
164 /* The BF533 family of processors have a nice misbehavior where 261 /* The BF533 family of processors have a nice misbehavior where
165 * they continuously generate characters for a "single" break. 262 * they continuously generate characters for a "single" break.
@@ -250,10 +347,21 @@ static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
250{ 347{
251 struct bfin_serial_port *uart = dev_id; 348 struct bfin_serial_port *uart = dev_id;
252 349
350#ifdef CONFIG_BF54x
351 unsigned short status;
352 spin_lock(&uart->port.lock);
353 status = UART_GET_LSR(uart);
354 while ((UART_GET_IER(uart) & ERBFI) && (status & DR)) {
355 bfin_serial_rx_chars(uart);
356 status = UART_GET_LSR(uart);
357 }
358 spin_unlock(&uart->port.lock);
359#else
253 spin_lock(&uart->port.lock); 360 spin_lock(&uart->port.lock);
254 while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_RX_READY) 361 while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_RX_READY)
255 bfin_serial_rx_chars(uart); 362 bfin_serial_rx_chars(uart);
256 spin_unlock(&uart->port.lock); 363 spin_unlock(&uart->port.lock);
364#endif
257 return IRQ_HANDLED; 365 return IRQ_HANDLED;
258} 366}
259 367
@@ -261,10 +369,21 @@ static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
261{ 369{
262 struct bfin_serial_port *uart = dev_id; 370 struct bfin_serial_port *uart = dev_id;
263 371
372#ifdef CONFIG_BF54x
373 unsigned short status;
374 spin_lock(&uart->port.lock);
375 status = UART_GET_LSR(uart);
376 while ((UART_GET_IER(uart) & ETBEI) && (status & THRE)) {
377 bfin_serial_tx_chars(uart);
378 status = UART_GET_LSR(uart);
379 }
380 spin_unlock(&uart->port.lock);
381#else
264 spin_lock(&uart->port.lock); 382 spin_lock(&uart->port.lock);
265 while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_TX_READY) 383 while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_TX_READY)
266 bfin_serial_tx_chars(uart); 384 bfin_serial_tx_chars(uart);
267 spin_unlock(&uart->port.lock); 385 spin_unlock(&uart->port.lock);
386#endif
268 return IRQ_HANDLED; 387 return IRQ_HANDLED;
269} 388}
270 389
@@ -275,7 +394,6 @@ static void bfin_serial_do_work(struct work_struct *work)
275 394
276 bfin_serial_mctrl_check(uart); 395 bfin_serial_mctrl_check(uart);
277} 396}
278
279#endif 397#endif
280 398
281#ifdef CONFIG_SERIAL_BFIN_DMA 399#ifdef CONFIG_SERIAL_BFIN_DMA
@@ -324,9 +442,13 @@ static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
324 set_dma_x_count(uart->tx_dma_channel, uart->tx_count); 442 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
325 set_dma_x_modify(uart->tx_dma_channel, 1); 443 set_dma_x_modify(uart->tx_dma_channel, 1);
326 enable_dma(uart->tx_dma_channel); 444 enable_dma(uart->tx_dma_channel);
445#ifdef CONFIG_BF54x
446 UART_SET_IER(uart, ETBEI);
447#else
327 ier = UART_GET_IER(uart); 448 ier = UART_GET_IER(uart);
328 ier |= ETBEI; 449 ier |= ETBEI;
329 UART_PUT_IER(uart, ier); 450 UART_PUT_IER(uart, ier);
451#endif
330 spin_unlock_irqrestore(&uart->port.lock, flags); 452 spin_unlock_irqrestore(&uart->port.lock, flags);
331} 453}
332 454
@@ -406,9 +528,13 @@ static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
406 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { 528 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
407 clear_dma_irqstat(uart->tx_dma_channel); 529 clear_dma_irqstat(uart->tx_dma_channel);
408 disable_dma(uart->tx_dma_channel); 530 disable_dma(uart->tx_dma_channel);
531#ifdef CONFIG_BF54x
532 UART_CLEAR_IER(uart, ETBEI);
533#else
409 ier = UART_GET_IER(uart); 534 ier = UART_GET_IER(uart);
410 ier &= ~ETBEI; 535 ier &= ~ETBEI;
411 UART_PUT_IER(uart, ier); 536 UART_PUT_IER(uart, ier);
537#endif
412 xmit->tail = (xmit->tail+uart->tx_count) &(UART_XMIT_SIZE -1); 538 xmit->tail = (xmit->tail+uart->tx_count) &(UART_XMIT_SIZE -1);
413 uart->port.icount.tx+=uart->tx_count; 539 uart->port.icount.tx+=uart->tx_count;
414 540
@@ -571,7 +697,11 @@ static int bfin_serial_startup(struct uart_port *port)
571 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; 697 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
572 add_timer(&(uart->rx_dma_timer)); 698 add_timer(&(uart->rx_dma_timer));
573#else 699#else
700# ifdef CONFIG_KGDB_UART
701 if (uart->port.line != CONFIG_KGDB_UART_PORT && request_irq
702# else
574 if (request_irq 703 if (request_irq
704# endif
575 (uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, 705 (uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
576 "BFIN_UART_RX", uart)) { 706 "BFIN_UART_RX", uart)) {
577 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); 707 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
@@ -586,7 +716,11 @@ static int bfin_serial_startup(struct uart_port *port)
586 return -EBUSY; 716 return -EBUSY;
587 } 717 }
588#endif 718#endif
719#ifdef CONFIG_BF54x
720 UART_SET_IER(uart, ERBFI);
721#else
589 UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI); 722 UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
723#endif
590 return 0; 724 return 0;
591} 725}
592 726
@@ -601,6 +735,9 @@ static void bfin_serial_shutdown(struct uart_port *port)
601 free_dma(uart->rx_dma_channel); 735 free_dma(uart->rx_dma_channel);
602 del_timer(&(uart->rx_dma_timer)); 736 del_timer(&(uart->rx_dma_timer));
603#else 737#else
738#ifdef CONFIG_KGDB_UART
739 if (uart->port.line != CONFIG_KGDB_UART_PORT)
740#endif
604 free_irq(uart->port.irq, uart); 741 free_irq(uart->port.irq, uart);
605 free_irq(uart->port.irq+1, uart); 742 free_irq(uart->port.irq+1, uart);
606#endif 743#endif
@@ -674,29 +811,41 @@ bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
674 811
675 /* Disable UART */ 812 /* Disable UART */
676 ier = UART_GET_IER(uart); 813 ier = UART_GET_IER(uart);
814#ifdef CONFIG_BF54x
815 UART_CLEAR_IER(uart, 0xF);
816#else
677 UART_PUT_IER(uart, 0); 817 UART_PUT_IER(uart, 0);
818#endif
678 819
820#ifndef CONFIG_BF54x
679 /* Set DLAB in LCR to Access DLL and DLH */ 821 /* Set DLAB in LCR to Access DLL and DLH */
680 val = UART_GET_LCR(uart); 822 val = UART_GET_LCR(uart);
681 val |= DLAB; 823 val |= DLAB;
682 UART_PUT_LCR(uart, val); 824 UART_PUT_LCR(uart, val);
683 SSYNC(); 825 SSYNC();
826#endif
684 827
685 UART_PUT_DLL(uart, quot & 0xFF); 828 UART_PUT_DLL(uart, quot & 0xFF);
686 SSYNC(); 829 SSYNC();
687 UART_PUT_DLH(uart, (quot >> 8) & 0xFF); 830 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
688 SSYNC(); 831 SSYNC();
689 832
833#ifndef CONFIG_BF54x
690 /* Clear DLAB in LCR to Access THR RBR IER */ 834 /* Clear DLAB in LCR to Access THR RBR IER */
691 val = UART_GET_LCR(uart); 835 val = UART_GET_LCR(uart);
692 val &= ~DLAB; 836 val &= ~DLAB;
693 UART_PUT_LCR(uart, val); 837 UART_PUT_LCR(uart, val);
694 SSYNC(); 838 SSYNC();
839#endif
695 840
696 UART_PUT_LCR(uart, lcr); 841 UART_PUT_LCR(uart, lcr);
697 842
698 /* Enable UART */ 843 /* Enable UART */
844#ifdef CONFIG_BF54x
845 UART_SET_IER(uart, ier);
846#else
699 UART_PUT_IER(uart, ier); 847 UART_PUT_IER(uart, ier);
848#endif
700 849
701 val = UART_GET_GCTL(uart); 850 val = UART_GET_GCTL(uart);
702 val |= UCEN; 851 val |= UCEN;
@@ -808,15 +957,15 @@ static void __init bfin_serial_init_ports(void)
808 bfin_serial_resource[i].uart_rts_pin; 957 bfin_serial_resource[i].uart_rts_pin;
809#endif 958#endif
810 bfin_serial_hw_init(&bfin_serial_ports[i]); 959 bfin_serial_hw_init(&bfin_serial_ports[i]);
811
812 } 960 }
961
813} 962}
814 963
815#ifdef CONFIG_SERIAL_BFIN_CONSOLE 964#ifdef CONFIG_SERIAL_BFIN_CONSOLE
816static void bfin_serial_console_putchar(struct uart_port *port, int ch) 965static void bfin_serial_console_putchar(struct uart_port *port, int ch)
817{ 966{
818 struct bfin_serial_port *uart = (struct bfin_serial_port *)port; 967 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
819 while (!(UART_GET_LSR(uart))) 968 while (!(UART_GET_LSR(uart) & THRE))
820 barrier(); 969 barrier();
821 UART_PUT_CHAR(uart, ch); 970 UART_PUT_CHAR(uart, ch);
822 SSYNC(); 971 SSYNC();
@@ -868,18 +1017,22 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
868 case 2: *bits = 7; break; 1017 case 2: *bits = 7; break;
869 case 3: *bits = 8; break; 1018 case 3: *bits = 8; break;
870 } 1019 }
1020#ifndef CONFIG_BF54x
871 /* Set DLAB in LCR to Access DLL and DLH */ 1021 /* Set DLAB in LCR to Access DLL and DLH */
872 val = UART_GET_LCR(uart); 1022 val = UART_GET_LCR(uart);
873 val |= DLAB; 1023 val |= DLAB;
874 UART_PUT_LCR(uart, val); 1024 UART_PUT_LCR(uart, val);
1025#endif
875 1026
876 dll = UART_GET_DLL(uart); 1027 dll = UART_GET_DLL(uart);
877 dlh = UART_GET_DLH(uart); 1028 dlh = UART_GET_DLH(uart);
878 1029
1030#ifndef CONFIG_BF54x
879 /* Clear DLAB in LCR to Access THR RBR IER */ 1031 /* Clear DLAB in LCR to Access THR RBR IER */
880 val = UART_GET_LCR(uart); 1032 val = UART_GET_LCR(uart);
881 val &= ~DLAB; 1033 val &= ~DLAB;
882 UART_PUT_LCR(uart, val); 1034 UART_PUT_LCR(uart, val);
1035#endif
883 1036
884 *baud = get_sclk() / (16*(dll | dlh << 8)); 1037 *baud = get_sclk() / (16*(dll | dlh << 8));
885 } 1038 }
@@ -931,6 +1084,10 @@ static int __init bfin_serial_rs_console_init(void)
931{ 1084{
932 bfin_serial_init_ports(); 1085 bfin_serial_init_ports();
933 register_console(&bfin_serial_console); 1086 register_console(&bfin_serial_console);
1087#ifdef CONFIG_KGDB_UART
1088 kgdb_entry_state = 0;
1089 init_kgdb_uart();
1090#endif
934 return 0; 1091 return 0;
935} 1092}
936console_initcall(bfin_serial_rs_console_init); 1093console_initcall(bfin_serial_rs_console_init);
@@ -1023,6 +1180,10 @@ static struct platform_driver bfin_serial_driver = {
1023static int __init bfin_serial_init(void) 1180static int __init bfin_serial_init(void)
1024{ 1181{
1025 int ret; 1182 int ret;
1183#ifdef CONFIG_KGDB_UART
1184 struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
1185 struct termios t;
1186#endif
1026 1187
1027 pr_info("Serial: Blackfin serial driver\n"); 1188 pr_info("Serial: Blackfin serial driver\n");
1028 1189
@@ -1036,6 +1197,21 @@ static int __init bfin_serial_init(void)
1036 uart_unregister_driver(&bfin_serial_reg); 1197 uart_unregister_driver(&bfin_serial_reg);
1037 } 1198 }
1038 } 1199 }
1200#ifdef CONFIG_KGDB_UART
1201 if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
1202 request_irq(uart->port.irq, bfin_serial_int,
1203 IRQF_DISABLED, "BFIN_UART_RX", uart);
1204 pr_info("Request irq for kgdb uart port\n");
1205 UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
1206 __builtin_bfin_ssync();
1207 t.c_cflag = CS8|B57600;
1208 t.c_iflag = 0;
1209 t.c_oflag = 0;
1210 t.c_lflag = ICANON;
1211 t.c_line = CONFIG_KGDB_UART_PORT;
1212 bfin_serial_set_termios(&uart->port, &t, &t);
1213 }
1214#endif
1039 return ret; 1215 return ret;
1040} 1216}
1041 1217
diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 63b85bf81a65..d3b8a6be2916 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -6,7 +6,7 @@ menu "Console display driver support"
6 6
7config VGA_CONSOLE 7config VGA_CONSOLE
8 bool "VGA text console" if EMBEDDED || !X86 8 bool "VGA text console" if EMBEDDED || !X86
9 depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH 9 depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BFIN
10 default y 10 default y
11 help 11 help
12 Saying Y here will allow you to use Linux in text mode through a 12 Saying Y here will allow you to use Linux in text mode through a
diff --git a/include/asm-blackfin/Kbuild b/include/asm-blackfin/Kbuild
index c68e1680da01..71f8fe783258 100644
--- a/include/asm-blackfin/Kbuild
+++ b/include/asm-blackfin/Kbuild
@@ -1 +1,3 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2
3header-y += fixed_code.h
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 57f37ccdcdf1..c4d6cbbf96d4 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -67,6 +67,18 @@ extern void evt14_softirq(void);
67extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); 67extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
68extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type); 68extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type);
69 69
70extern asmlinkage void finish_atomic_sections (struct pt_regs *regs);
71extern char fixed_code_start;
72extern char fixed_code_end;
73extern int atomic_xchg32(void);
74extern int atomic_cas32(void);
75extern int atomic_add32(void);
76extern int atomic_sub32(void);
77extern int atomic_ior32(void);
78extern int atomic_and32(void);
79extern int atomic_xor32(void);
80extern void sigreturn_stub(void);
81
70extern void *l1_data_A_sram_alloc(size_t); 82extern void *l1_data_A_sram_alloc(size_t);
71extern void *l1_data_B_sram_alloc(size_t); 83extern void *l1_data_B_sram_alloc(size_t);
72extern void *l1_inst_sram_alloc(size_t); 84extern void *l1_inst_sram_alloc(size_t);
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index 3bad2d1e6a8c..bec6ecdf1bdb 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -57,8 +57,8 @@ struct cplb_tab {
57 u16 size; 57 u16 size;
58}; 58};
59 59
60u_long icplb_table[MAX_CPLBS+1]; 60extern u_long icplb_table[MAX_CPLBS+1];
61u_long dcplb_table[MAX_CPLBS+1]; 61extern u_long dcplb_table[MAX_CPLBS+1];
62 62
63/* Till here we are discussing about the static memory management model. 63/* Till here we are discussing about the static memory management model.
64 * However, the operating envoronments commonly define more CPLB 64 * However, the operating envoronments commonly define more CPLB
@@ -70,134 +70,27 @@ u_long dcplb_table[MAX_CPLBS+1];
70 */ 70 */
71 71
72#ifdef CONFIG_CPLB_SWITCH_TAB_L1 72#ifdef CONFIG_CPLB_SWITCH_TAB_L1
73u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); 73extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
74u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data)); 74extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
75 75
76#ifdef CONFIG_CPLB_INFO 76#ifdef CONFIG_CPLB_INFO
77u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data)); 77extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
78u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data)); 78extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
79#endif /* CONFIG_CPLB_INFO */ 79#endif /* CONFIG_CPLB_INFO */
80 80
81#else 81#else
82 82
83u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; 83extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
84u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; 84extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
85 85
86#ifdef CONFIG_CPLB_INFO 86#ifdef CONFIG_CPLB_INFO
87u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; 87extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
88u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; 88extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
89#endif /* CONFIG_CPLB_INFO */ 89#endif /* CONFIG_CPLB_INFO */
90 90
91#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/ 91#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
92 92
93struct s_cplb { 93extern unsigned long reserved_mem_dcache_on;
94 struct cplb_tab init_i; 94extern unsigned long reserved_mem_icache_on;
95 struct cplb_tab init_d;
96 struct cplb_tab switch_i;
97 struct cplb_tab switch_d;
98};
99 95
100#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE) 96extern void generate_cpl_tables(void);
101static struct cplb_desc cplb_data[] = {
102 {
103 .start = 0,
104 .end = SIZE_4K,
105 .psize = SIZE_4K,
106 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
107 .i_conf = SDRAM_OOPS,
108 .d_conf = SDRAM_OOPS,
109#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
110 .valid = 1,
111#else
112 .valid = 0,
113#endif
114 .name = "ZERO Pointer Saveguard",
115 },
116 {
117 .start = L1_CODE_START,
118 .end = L1_CODE_START + L1_CODE_LENGTH,
119 .psize = SIZE_4M,
120 .attr = INITIAL_T | SWITCH_T | I_CPLB,
121 .i_conf = L1_IMEMORY,
122 .d_conf = 0,
123 .valid = 1,
124 .name = "L1 I-Memory",
125 },
126 {
127 .start = L1_DATA_A_START,
128 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
129 .psize = SIZE_4M,
130 .attr = INITIAL_T | SWITCH_T | D_CPLB,
131 .i_conf = 0,
132 .d_conf = L1_DMEMORY,
133#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
134 .valid = 1,
135#else
136 .valid = 0,
137#endif
138 .name = "L1 D-Memory",
139 },
140 {
141 .start = 0,
142 .end = 0, /* dynamic */
143 .psize = 0,
144 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
145 .i_conf = SDRAM_IGENERIC,
146 .d_conf = SDRAM_DGENERIC,
147 .valid = 1,
148 .name = "SDRAM Kernel",
149 },
150 {
151 .start = 0, /* dynamic */
152 .end = 0, /* dynamic */
153 .psize = 0,
154 .attr = INITIAL_T | SWITCH_T | D_CPLB,
155 .i_conf = SDRAM_IGENERIC,
156 .d_conf = SDRAM_DNON_CHBL,
157 .valid = 1,
158 .name = "SDRAM RAM MTD",
159 },
160 {
161 .start = 0, /* dynamic */
162 .end = 0, /* dynamic */
163 .psize = SIZE_1M,
164 .attr = INITIAL_T | SWITCH_T | D_CPLB,
165 .d_conf = SDRAM_DNON_CHBL,
166 .valid = 1,//(DMA_UNCACHED_REGION > 0),
167 .name = "SDRAM Uncached DMA ZONE",
168 },
169 {
170 .start = 0, /* dynamic */
171 .end = 0, /* dynamic */
172 .psize = 0,
173 .attr = SWITCH_T | D_CPLB,
174 .i_conf = 0, /* dynamic */
175 .d_conf = 0, /* dynamic */
176 .valid = 1,
177 .name = "SDRAM Reserved Memory",
178 },
179 {
180 .start = ASYNC_BANK0_BASE,
181 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
182 .psize = 0,
183 .attr = SWITCH_T | D_CPLB,
184 .d_conf = SDRAM_EBIU,
185 .valid = 1,
186 .name = "ASYNC Memory",
187 },
188 {
189#if defined(CONFIG_BF561)
190 .start = L2_SRAM,
191 .end = L2_SRAM_END,
192 .psize = SIZE_1M,
193 .attr = SWITCH_T | D_CPLB,
194 .i_conf = L2_MEMORY,
195 .d_conf = L2_MEMORY,
196 .valid = 1,
197#else
198 .valid = 0,
199#endif
200 .name = "L2 Memory",
201 }
202};
203#endif
diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h
new file mode 100644
index 000000000000..e6df84ee1557
--- /dev/null
+++ b/include/asm-blackfin/fixed_code.h
@@ -0,0 +1,20 @@
1/* This file defines the fixed addresses where userspace programs can find
2 atomic code sequences. */
3
4#define FIXED_CODE_START 0x400
5
6#define SIGRETURN_STUB 0x400
7
8#define ATOMIC_SEQS_START 0x410
9
10#define ATOMIC_XCHG32 0x410
11#define ATOMIC_CAS32 0x420
12#define ATOMIC_ADD32 0x430
13#define ATOMIC_SUB32 0x440
14#define ATOMIC_IOR32 0x450
15#define ATOMIC_AND32 0x460
16#define ATOMIC_XOR32 0x470
17
18#define ATOMIC_SEQS_END 0x480
19
20#define FIXED_CODE_END 0x480
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index d98d77ad71f7..7480cfa7e2d6 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -204,8 +204,62 @@
204 204
205#endif 205#endif
206 206
207#ifdef BF548_FAMILY
208#include <asm-blackfin/mach-bf548/gpio.h>
209#endif
210
207#ifdef BF561_FAMILY 211#ifdef BF561_FAMILY
208#define MAX_BLACKFIN_GPIOS 48 212#define MAX_BLACKFIN_GPIOS 48
213
214#define GPIO_PF0 0
215#define GPIO_PF1 1
216#define GPIO_PF2 2
217#define GPIO_PF3 3
218#define GPIO_PF4 4
219#define GPIO_PF5 5
220#define GPIO_PF6 6
221#define GPIO_PF7 7
222#define GPIO_PF8 8
223#define GPIO_PF9 9
224#define GPIO_PF10 10
225#define GPIO_PF11 11
226#define GPIO_PF12 12
227#define GPIO_PF13 13
228#define GPIO_PF14 14
229#define GPIO_PF15 15
230#define GPIO_PF16 16
231#define GPIO_PF17 17
232#define GPIO_PF18 18
233#define GPIO_PF19 19
234#define GPIO_PF20 20
235#define GPIO_PF21 21
236#define GPIO_PF22 22
237#define GPIO_PF23 23
238#define GPIO_PF24 24
239#define GPIO_PF25 25
240#define GPIO_PF26 26
241#define GPIO_PF27 27
242#define GPIO_PF28 28
243#define GPIO_PF29 29
244#define GPIO_PF30 30
245#define GPIO_PF31 31
246#define GPIO_PF32 32
247#define GPIO_PF33 33
248#define GPIO_PF34 34
249#define GPIO_PF35 35
250#define GPIO_PF36 36
251#define GPIO_PF37 37
252#define GPIO_PF38 38
253#define GPIO_PF39 39
254#define GPIO_PF40 40
255#define GPIO_PF41 41
256#define GPIO_PF42 42
257#define GPIO_PF43 43
258#define GPIO_PF44 44
259#define GPIO_PF45 45
260#define GPIO_PF46 46
261#define GPIO_PF47 47
262
209#define PORT_FIO0 GPIO_0 263#define PORT_FIO0 GPIO_0
210#define PORT_FIO1 GPIO_16 264#define PORT_FIO1 GPIO_16
211#define PORT_FIO2 GPIO_32 265#define PORT_FIO2 GPIO_32
@@ -230,6 +284,7 @@
230* MODIFICATION HISTORY : 284* MODIFICATION HISTORY :
231**************************************************************/ 285**************************************************************/
232 286
287#ifndef BF548_FAMILY
233void set_gpio_dir(unsigned short, unsigned short); 288void set_gpio_dir(unsigned short, unsigned short);
234void set_gpio_inen(unsigned short, unsigned short); 289void set_gpio_inen(unsigned short, unsigned short);
235void set_gpio_polar(unsigned short, unsigned short); 290void set_gpio_polar(unsigned short, unsigned short);
@@ -299,6 +354,7 @@ struct gpio_port_t {
299 unsigned short dummy16; 354 unsigned short dummy16;
300 unsigned short inen; 355 unsigned short inen;
301}; 356};
357#endif
302 358
303#ifdef CONFIG_PM 359#ifdef CONFIG_PM
304#define PM_WAKE_RISING 0x1 360#define PM_WAKE_RISING 0x1
@@ -357,8 +413,10 @@ void gpio_free(unsigned short);
357void gpio_set_value(unsigned short gpio, unsigned short arg); 413void gpio_set_value(unsigned short gpio, unsigned short arg);
358unsigned short gpio_get_value(unsigned short gpio); 414unsigned short gpio_get_value(unsigned short gpio);
359 415
416#ifndef BF548_FAMILY
360#define gpio_get_value(gpio) get_gpio_data(gpio) 417#define gpio_get_value(gpio) get_gpio_data(gpio)
361#define gpio_set_value(gpio, value) set_gpio_data(gpio, value) 418#define gpio_set_value(gpio, value) set_gpio_data(gpio, value)
419#endif
362 420
363void gpio_direction_input(unsigned short gpio); 421void gpio_direction_input(unsigned short gpio);
364void gpio_direction_output(unsigned short gpio); 422void gpio_direction_output(unsigned short gpio);
diff --git a/include/asm-blackfin/hardirq.h b/include/asm-blackfin/hardirq.h
index 0cab0d35badc..b6b19f1b9dab 100644
--- a/include/asm-blackfin/hardirq.h
+++ b/include/asm-blackfin/hardirq.h
@@ -28,7 +28,11 @@ typedef struct {
28 * SOFTIRQ_MASK: 0x00ff0000 28 * SOFTIRQ_MASK: 0x00ff0000
29 */ 29 */
30 30
31#if NR_IRQS > 256
32#define HARDIRQ_BITS 9
33#else
31#define HARDIRQ_BITS 8 34#define HARDIRQ_BITS 8
35#endif
32 36
33#ifdef NR_IRQS 37#ifdef NR_IRQS
34# if (1 << HARDIRQ_BITS) < NR_IRQS 38# if (1 << HARDIRQ_BITS) < NR_IRQS
diff --git a/include/asm-blackfin/kgdb.h b/include/asm-blackfin/kgdb.h
new file mode 100644
index 000000000000..532bd9052004
--- /dev/null
+++ b/include/asm-blackfin/kgdb.h
@@ -0,0 +1,183 @@
1/*
2 * File: include/asm-blackfin/kgdb.h
3 * Based on:
4 * Author: Sonic Zhang
5 *
6 * Created:
7 * Description:
8 *
9 * Rev: $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
10 *
11 * Modified:
12 * Copyright 2005-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see the file COPYING, or write
28 * to the Free Software Foundation, Inc.,
29 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 */
31
32#ifndef __ASM_BLACKFIN_KGDB_H__
33#define __ASM_BLACKFIN_KGDB_H__
34
35#include <linux/ptrace.h>
36
37/* gdb locks */
38#define KGDB_MAX_NO_CPUS 8
39
40/************************************************************************/
41/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
42/* at least NUMREGBYTES*2 are needed for register packets */
43/* Longer buffer is needed to list all threads */
44#define BUFMAX 2048
45
46/*
47 * Note that this register image is different from
48 * the register image that Linux produces at interrupt time.
49 *
50 * Linux's register image is defined by struct pt_regs in ptrace.h.
51 */
52enum regnames {
53 /* Core Registers */
54 BFIN_R0 = 0,
55 BFIN_R1,
56 BFIN_R2,
57 BFIN_R3,
58 BFIN_R4,
59 BFIN_R5,
60 BFIN_R6,
61 BFIN_R7,
62 BFIN_P0,
63 BFIN_P1,
64 BFIN_P2,
65 BFIN_P3,
66 BFIN_P4,
67 BFIN_P5,
68 BFIN_SP,
69 BFIN_FP,
70 BFIN_I0,
71 BFIN_I1,
72 BFIN_I2,
73 BFIN_I3,
74 BFIN_M0,
75 BFIN_M1,
76 BFIN_M2,
77 BFIN_M3,
78 BFIN_B0,
79 BFIN_B1,
80 BFIN_B2,
81 BFIN_B3,
82 BFIN_L0,
83 BFIN_L1,
84 BFIN_L2,
85 BFIN_L3,
86 BFIN_A0_DOT_X,
87 BFIN_A0_DOT_W,
88 BFIN_A1_DOT_X,
89 BFIN_A1_DOT_W,
90 BFIN_ASTAT,
91 BFIN_RETS,
92 BFIN_LC0,
93 BFIN_LT0,
94 BFIN_LB0,
95 BFIN_LC1,
96 BFIN_LT1,
97 BFIN_LB1,
98 BFIN_CYCLES,
99 BFIN_CYCLES2,
100 BFIN_USP,
101 BFIN_SEQSTAT,
102 BFIN_SYSCFG,
103 BFIN_RETI,
104 BFIN_RETX,
105 BFIN_RETN,
106 BFIN_RETE,
107
108 /* Pseudo Registers */
109 BFIN_PC,
110 BFIN_CC,
111 BFIN_EXTRA1, /* Address of .text section. */
112 BFIN_EXTRA2, /* Address of .data section. */
113 BFIN_EXTRA3, /* Address of .bss section. */
114 BFIN_FDPIC_EXEC,
115 BFIN_FDPIC_INTERP,
116
117 /* MMRs */
118 BFIN_IPEND,
119
120 /* LAST ENTRY SHOULD NOT BE CHANGED. */
121 BFIN_NUM_REGS /* The number of all registers. */
122};
123
124/* Number of bytes of registers. */
125#define NUMREGBYTES BFIN_NUM_REGS*4
126
127#define BREAKPOINT() asm(" EXCPT 2;");
128#define BREAK_INSTR_SIZE 2
129#define HW_BREAKPOINT_NUM 6
130
131/* Instruction watchpoint address control register bits mask */
132#define WPPWR 0x1
133#define WPIREN01 0x2
134#define WPIRINV01 0x4
135#define WPIAEN0 0x8
136#define WPIAEN1 0x10
137#define WPICNTEN0 0x20
138#define WPICNTEN1 0x40
139#define EMUSW0 0x80
140#define EMUSW1 0x100
141#define WPIREN23 0x200
142#define WPIRINV23 0x400
143#define WPIAEN2 0x800
144#define WPIAEN3 0x1000
145#define WPICNTEN2 0x2000
146#define WPICNTEN3 0x4000
147#define EMUSW2 0x8000
148#define EMUSW3 0x10000
149#define WPIREN45 0x20000
150#define WPIRINV45 0x40000
151#define WPIAEN4 0x80000
152#define WPIAEN5 0x100000
153#define WPICNTEN4 0x200000
154#define WPICNTEN5 0x400000
155#define EMUSW4 0x800000
156#define EMUSW5 0x1000000
157#define WPAND 0x2000000
158
159/* Data watchpoint address control register bits mask */
160#define WPDREN01 0x1
161#define WPDRINV01 0x2
162#define WPDAEN0 0x4
163#define WPDAEN1 0x8
164#define WPDCNTEN0 0x10
165#define WPDCNTEN1 0x20
166#define WPDSRC0 0xc0
167#define WPDACC0 0x300
168#define WPDSRC1 0xc00
169#define WPDACC1 0x3000
170
171/* Watchpoint status register bits mask */
172#define STATIA0 0x1
173#define STATIA1 0x2
174#define STATIA2 0x4
175#define STATIA3 0x8
176#define STATIA4 0x10
177#define STATIA5 0x20
178#define STATDA0 0x40
179#define STATDA1 0x80
180
181extern void kgdb_print(const char *fmt, ...);
182
183#endif
diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h
index bd9d5e94307d..16c672c01d80 100644
--- a/include/asm-blackfin/mach-bf533/dma.h
+++ b/include/asm-blackfin/mach-bf533/dma.h
@@ -51,4 +51,7 @@
51#define CH_MEM_STREAM1_DEST 10 /* TX */ 51#define CH_MEM_STREAM1_DEST 10 /* TX */
52#define CH_MEM_STREAM1_SRC 11 /* RX */ 52#define CH_MEM_STREAM1_SRC 11 /* RX */
53 53
54extern int channel2irq(unsigned int channel);
55extern struct dma_register *base_addr[];
56
54#endif 57#endif
diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h
new file mode 100644
index 000000000000..b88d7a03ee3e
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/portmux.h
@@ -0,0 +1,65 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define P_PPI0_CLK (P_DONTCARE)
5#define P_PPI0_FS1 (P_DONTCARE)
6#define P_PPI0_FS2 (P_DONTCARE)
7#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
8#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
9#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
10#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
11#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
12#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
13#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
14#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
15#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
16#define P_PPI0_D0 (P_DONTCARE)
17#define P_PPI0_D1 (P_DONTCARE)
18#define P_PPI0_D2 (P_DONTCARE)
19#define P_PPI0_D3 (P_DONTCARE)
20#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
21#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
22#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
23#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
24
25#define P_SPORT1_TSCLK (P_DONTCARE)
26#define P_SPORT1_RSCLK (P_DONTCARE)
27#define P_SPORT0_TSCLK (P_DONTCARE)
28#define P_SPORT0_RSCLK (P_DONTCARE)
29#define P_UART0_RX (P_DONTCARE)
30#define P_UART0_TX (P_DONTCARE)
31#define P_SPORT1_DRSEC (P_DONTCARE)
32#define P_SPORT1_RFS (P_DONTCARE)
33#define P_SPORT1_DTPRI (P_DONTCARE)
34#define P_SPORT1_DTSEC (P_DONTCARE)
35#define P_SPORT1_TFS (P_DONTCARE)
36#define P_SPORT1_DRPRI (P_DONTCARE)
37#define P_SPORT0_DRSEC (P_DONTCARE)
38#define P_SPORT0_RFS (P_DONTCARE)
39#define P_SPORT0_DTPRI (P_DONTCARE)
40#define P_SPORT0_DTSEC (P_DONTCARE)
41#define P_SPORT0_TFS (P_DONTCARE)
42#define P_SPORT0_DRPRI (P_DONTCARE)
43
44#define P_SPI0_MOSI (P_DONTCARE)
45#define P_SPI0_MIS0 (P_DONTCARE)
46#define P_SPI0_SCK (P_DONTCARE)
47#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
48#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
49#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
50#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
51#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
52#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
53#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
54#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
55
56#define P_TMR2 (P_DONTCARE)
57#define P_TMR1 (P_DONTCARE)
58#define P_TMR0 (P_DONTCARE)
59#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
60
61
62
63
64
65#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h
index 7a964040870a..021991984e6e 100644
--- a/include/asm-blackfin/mach-bf537/dma.h
+++ b/include/asm-blackfin/mach-bf537/dma.h
@@ -52,4 +52,7 @@
52#define CH_MEM_STREAM1_DEST 14 /* TX */ 52#define CH_MEM_STREAM1_DEST 14 /* TX */
53#define CH_MEM_STREAM1_SRC 15 /* RX */ 53#define CH_MEM_STREAM1_SRC 15 /* RX */
54 54
55extern int channel2irq(unsigned int channel);
56extern struct dma_register *base_addr[];
57
55#endif 58#endif
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
new file mode 100644
index 000000000000..23e13c5abc4d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/portmux.h
@@ -0,0 +1,109 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
5#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
6#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
7#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
8#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
9#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
10#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
11#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
12#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
13#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
14#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
15#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
16#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
17#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
18#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
19#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
20#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
21#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
22#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
23#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
24#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
25#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
26#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
27#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
28#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
29#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
30#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
31#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
32
33#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
34#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
35#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
36#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
37#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
38#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
39#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
40#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
41#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
42#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
43#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
44#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
45#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
46#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
47#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
48#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
49#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
50#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
51#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
52#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
53#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
54#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
55#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
56#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
57
58#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
59#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
60#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
61#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
62#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
63#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
64#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
65#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
66#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
67#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
68#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
69#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
70#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
71#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
72#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
73#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
74#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
75#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
76#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
77
78#define PORT_PJ0 (GPIO_PH15 + 1)
79#define PORT_PJ1 (GPIO_PH15 + 2)
80#define PORT_PJ2 (GPIO_PH15 + 3)
81#define PORT_PJ3 (GPIO_PH15 + 4)
82#define PORT_PJ4 (GPIO_PH15 + 5)
83#define PORT_PJ5 (GPIO_PH15 + 6)
84#define PORT_PJ6 (GPIO_PH15 + 7)
85#define PORT_PJ7 (GPIO_PH15 + 8)
86#define PORT_PJ8 (GPIO_PH15 + 9)
87#define PORT_PJ9 (GPIO_PH15 + 10)
88#define PORT_PJ10 (GPIO_PH15 + 11)
89#define PORT_PJ11 (GPIO_PH15 + 12)
90
91#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
92#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
93#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
94#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
95#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
96#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
97#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
98#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
99#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
100#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
101#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
102#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
103#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
104#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
105#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
106#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
107#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
108
109#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
new file mode 100644
index 000000000000..aca1d4ba145c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/anomaly.h
@@ -0,0 +1,74 @@
1
2/*
3 * File: include/asm-blackfin/mach-bf548/anomaly.h
4 * Based on:
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 *
15 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING.
29 * If not, write to the Free Software Foundation,
30 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 */
32
33#ifndef _MACH_ANOMALY_H_
34#define _MACH_ANOMALY_H_
35#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
36 slot1 and store of a P register in slot 2 is not
37 supported */
38#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
39 Channel DMA stops */
40#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
41 registers. */
42#define ANOMALY_05000245 /* Spurious Hardware Error from an Access in the
43 Shadow of a Conditional Branch */
44#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
45 interrupt not functional */
46#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
47 SPORT external receive and transmit clocks. */
48#define ANOMALY_05000272 /* Certain data cache write through modes fail for
49 VDDint <=0.9V */
50#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
51 not restored */
52#define ANOMALY_05000310 /* False Hardware Errors Caused by Fetches at the
53 Boundary of Reserved Memory */
54#define ANOMALY_05000312 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and
55 LC Registers Are Interrupted */
56#define ANOMALY_05000324 /* TWI Slave Boot Mode Is Not Functional */
57#define ANOMALY_05000325 /* External FIFO Boot Mode Is Not Functional */
58#define ANOMALY_05000327 /* Data Lost When Core and DMA Accesses Are Made to
59 the USB FIFO Simultaneously */
60#define ANOMALY_05000328 /* Incorrect Access of OTP_STATUS During otp_write()
61 function */
62#define ANOMALY_05000329 /* Synchronous Burst Flash Boot Mode Is Not Functional
63 */
64#define ANOMALY_05000330 /* Host DMA Boot Mode Is Not Functional */
65#define ANOMALY_05000334 /* Inadequate Timing Margins on DDR DQS to DQ and DQM
66 Skew */
67#define ANOMALY_05000335 /* Inadequate Rotary Debounce Logic Duration */
68#define ANOMALY_05000336 /* Phantom Interrupt Occurs After First Configuration
69 of Host DMA Port */
70#define ANOMALY_05000337 /* Disallowed Configuration Prevents Subsequent
71 Allowed Configuration on Host DMA Port */
72#define ANOMALY_05000338 /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
73
74#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
new file mode 100644
index 000000000000..9498313a2cb7
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -0,0 +1,271 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/bf548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: System MMR register and memory map for ADSP-BF548
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#ifndef __MACH_BF548_H__
31#define __MACH_BF548_H__
32
33#define SUPPORTED_REVID 0
34
35#define OFFSET_(x) ((x) & 0x0000FFFF)
36
37/*some misc defines*/
38#define IMASK_IVG15 0x8000
39#define IMASK_IVG14 0x4000
40#define IMASK_IVG13 0x2000
41#define IMASK_IVG12 0x1000
42
43#define IMASK_IVG11 0x0800
44#define IMASK_IVG10 0x0400
45#define IMASK_IVG9 0x0200
46#define IMASK_IVG8 0x0100
47
48#define IMASK_IVG7 0x0080
49#define IMASK_IVGTMR 0x0040
50#define IMASK_IVGHW 0x0020
51
52/***************************/
53
54
55#define BLKFIN_DSUBBANKS 4
56#define BLKFIN_DWAYS 2
57#define BLKFIN_DLINES 64
58#define BLKFIN_ISUBBANKS 4
59#define BLKFIN_IWAYS 4
60#define BLKFIN_ILINES 32
61
62#define WAY0_L 0x1
63#define WAY1_L 0x2
64#define WAY01_L 0x3
65#define WAY2_L 0x4
66#define WAY02_L 0x5
67#define WAY12_L 0x6
68#define WAY012_L 0x7
69
70#define WAY3_L 0x8
71#define WAY03_L 0x9
72#define WAY13_L 0xA
73#define WAY013_L 0xB
74
75#define WAY32_L 0xC
76#define WAY320_L 0xD
77#define WAY321_L 0xE
78#define WAYALL_L 0xF
79
80#define DMC_ENABLE (2<<2) /*yes, 2, not 1 */
81
82/********************************* EBIU Settings ************************************/
83#define AMBCTL0VAL ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
84#define AMBCTL1VAL ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
85
86#ifdef CONFIG_C_AMBEN_ALL
87#define V_AMBEN AMBEN_ALL
88#endif
89#ifdef CONFIG_C_AMBEN
90#define V_AMBEN 0x0
91#endif
92#ifdef CONFIG_C_AMBEN_B0
93#define V_AMBEN AMBEN_B0
94#endif
95#ifdef CONFIG_C_AMBEN_B0_B1
96#define V_AMBEN AMBEN_B0_B1
97#endif
98#ifdef CONFIG_C_AMBEN_B0_B1_B2
99#define V_AMBEN AMBEN_B0_B1_B2
100#endif
101#ifdef CONFIG_C_AMCKEN
102#define V_AMCKEN AMCKEN
103#else
104#define V_AMCKEN 0x0
105#endif
106
107#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
108
109#define MAX_VC 650000000
110#define MIN_VC 50000000
111
112/********************************PLL Settings **************************************/
113#ifdef CONFIG_BFIN_KERNEL_CLOCK
114#if (CONFIG_VCO_MULT < 0)
115#error "VCO Multiplier is less than 0. Please select a different value"
116#endif
117
118#if (CONFIG_VCO_MULT == 0)
119#error "VCO Multiplier should be greater than 0. Please select a different value"
120#endif
121
122#if (CONFIG_VCO_MULT > 64)
123#error "VCO Multiplier is more than 64. Please select a different value"
124#endif
125
126#ifndef CONFIG_CLKIN_HALF
127#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
128#else
129#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
130#endif
131
132#ifndef CONFIG_PLL_BYPASS
133#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
134#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
135#else
136#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
137#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
138#endif
139
140#if (CONFIG_SCLK_DIV < 1)
141#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
142#endif
143
144#if (CONFIG_SCLK_DIV > 15)
145#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
146#endif
147
148#if (CONFIG_CCLK_DIV != 1)
149#if (CONFIG_CCLK_DIV != 2)
150#if (CONFIG_CCLK_DIV != 4)
151#if (CONFIG_CCLK_DIV != 8)
152#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
153#endif
154#endif
155#endif
156#endif
157
158#if (CONFIG_VCO_HZ > MAX_VC)
159#error "VCO selected is more than maximum value. Please change the VCO multipler"
160#endif
161
162#if (CONFIG_SCLK_HZ > 133000000)
163#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
164#endif
165
166#if (CONFIG_SCLK_HZ < 27000000)
167#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
168#endif
169
170#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
171#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
172#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
173#error "Please select sclk less than cclk"
174#endif
175#endif
176#endif
177
178#if (CONFIG_CCLK_DIV == 1)
179#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
180#endif
181#if (CONFIG_CCLK_DIV == 2)
182#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
183#endif
184#if (CONFIG_CCLK_DIV == 4)
185#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
186#endif
187#if (CONFIG_CCLK_DIV == 8)
188#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
189#endif
190#ifndef CONFIG_CCLK_ACT_DIV
191#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
192#endif
193
194#endif /* CONFIG_BFIN_KERNEL_CLOCK */
195
196#ifdef CONFIG_BF542
197#define CPU "BF542"
198#define CPUID 0x027c8000
199#endif
200#ifdef CONFIG_BF544
201#define CPU "BF544"
202#define CPUID 0x027c8000
203#endif
204#ifdef CONFIG_BF548
205#define CPU "BF548"
206#define CPUID 0x027c6000
207#endif
208#ifdef CONFIG_BF549
209#define CPU "BF549"
210#endif
211#ifndef CPU
212#define CPU "UNKNOWN"
213#define CPUID 0x0
214#endif
215
216#if (CONFIG_MEM_SIZE % 4)
217#error "SDRAM mem size must be multible of 4MB"
218#endif
219
220#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
221#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
222#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
223#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
224
225/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
226
227#define ANOMALY_05000158_WORKAROUND 0x200
228#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
229#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
230 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
231#else /*Write Through */
232#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
233 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
234#endif
235
236
237#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
238#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
239#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
240#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
241
242#define SIZE_1K 0x00000400 /* 1K */
243#define SIZE_4K 0x00001000 /* 4K */
244#define SIZE_1M 0x00100000 /* 1M */
245#define SIZE_4M 0x00400000 /* 4M */
246
247#define MAX_CPLBS (16 * 2)
248
249/*
250* Number of required data CPLB switchtable entries
251* MEMSIZE / 4 (we mostly install 4M page size CPLBs
252* approx 16 for smaller 1MB page size CPLBs for allignment purposes
253* 1 for L1 Data Memory
254* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
255* 1 for ASYNC Memory
256*/
257
258
259#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
260
261/*
262* Number of required instruction CPLB switchtable entries
263* MEMSIZE / 4 (we mostly install 4M page size CPLBs
264* approx 12 for smaller 1MB page size CPLBs for allignment purposes
265* 1 for L1 Instruction Memory
266* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
267*/
268
269#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
270
271#endif /* __MACH_BF48_H__ */
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
new file mode 100644
index 000000000000..2f4afc90db11
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -0,0 +1,193 @@
1#include <linux/serial.h>
2#include <asm/dma.h>
3
4#define NR_PORTS 4
5
6#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
7#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
8#define OFFSET_GCTL 0x08 /* Global Control Register */
9#define OFFSET_LCR 0x0C /* Line Control Register */
10#define OFFSET_MCR 0x10 /* Modem Control Register */
11#define OFFSET_LSR 0x14 /* Line Status Register */
12#define OFFSET_MSR 0x18 /* Modem Status Register */
13#define OFFSET_SCR 0x1C /* SCR Scratch Register */
14#define OFFSET_IER_SET 0x20 /* Set Interrupt Enable Register */
15#define OFFSET_IER_CLEAR 0x24 /* Clear Interrupt Enable Register */
16#define OFFSET_THR 0x28 /* Transmit Holding register */
17#define OFFSET_RBR 0x2C /* Receive Buffer register */
18
19#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
20#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
21#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
22#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
23#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
24#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
25#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
26
27#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
28#define UART_PUT_DLL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
29#define UART_SET_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
30#define UART_CLEAR_IER(uart,v) bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
31#define UART_PUT_DLH(uart,v) bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
32#define UART_PUT_LSR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
33#define UART_PUT_LCR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
34#define UART_PUT_GCTL(uart,v) bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
35
36#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
37# define CONFIG_SERIAL_BFIN_CTSRTS
38
39# ifndef CONFIG_UART0_CTS_PIN
40# define CONFIG_UART0_CTS_PIN -1
41# endif
42
43# ifndef CONFIG_UART0_RTS_PIN
44# define CONFIG_UART0_RTS_PIN -1
45# endif
46
47# ifndef CONFIG_UART1_CTS_PIN
48# define CONFIG_UART1_CTS_PIN -1
49# endif
50
51# ifndef CONFIG_UART1_RTS_PIN
52# define CONFIG_UART1_RTS_PIN -1
53# endif
54#endif
55/*
56 * The pin configuration is different from schematic
57 */
58struct bfin_serial_port {
59 struct uart_port port;
60 unsigned int old_status;
61#ifdef CONFIG_SERIAL_BFIN_DMA
62 int tx_done;
63 int tx_count;
64 struct circ_buf rx_dma_buf;
65 struct timer_list rx_dma_timer;
66 int rx_dma_nrows;
67 unsigned int tx_dma_channel;
68 unsigned int rx_dma_channel;
69 struct work_struct tx_dma_workqueue;
70#else
71 struct work_struct cts_workqueue;
72#endif
73#ifdef CONFIG_SERIAL_BFIN_CTSRTS
74 int cts_pin;
75 int rts_pin;
76#endif
77};
78
79struct bfin_serial_port bfin_serial_ports[NR_PORTS];
80struct bfin_serial_res {
81 unsigned long uart_base_addr;
82 int uart_irq;
83#ifdef CONFIG_SERIAL_BFIN_DMA
84 unsigned int uart_tx_dma_channel;
85 unsigned int uart_rx_dma_channel;
86#endif
87#ifdef CONFIG_SERIAL_BFIN_CTSRTS
88 int uart_cts_pin;
89 int uart_rts_pin;
90#endif
91};
92
93struct bfin_serial_res bfin_serial_resource[] = {
94#ifdef CONFIG_SERIAL_BFIN_UART0
95 {
96 0xFFC00400,
97 IRQ_UART0_RX,
98#ifdef CONFIG_SERIAL_BFIN_DMA
99 CH_UART0_TX,
100 CH_UART0_RX,
101#endif
102#ifdef CONFIG_BFIN_UART0_CTSRTS
103 CONFIG_UART0_CTS_PIN,
104 CONFIG_UART0_RTS_PIN,
105#endif
106 },
107#endif
108#ifdef CONFIG_SERIAL_BFIN_UART1
109 {
110 0xFFC02000,
111 IRQ_UART1_RX,
112#ifdef CONFIG_SERIAL_BFIN_DMA
113 CH_UART1_TX,
114 CH_UART1_RX,
115#endif
116 },
117#endif
118#ifdef CONFIG_SERIAL_BFIN_UART2
119 {
120 0xFFC02100,
121 IRQ_UART2_RX,
122#ifdef CONFIG_SERIAL_BFIN_DMA
123 CH_UART2_TX,
124 CH_UART2_RX,
125#endif
126#ifdef CONFIG_BFIN_UART2_CTSRTS
127 CONFIG_UART2_CTS_PIN,
128 CONFIG_UART2_RTS_PIN,
129#endif
130 },
131#endif
132#ifdef CONFIG_SERIAL_BFIN_UART3
133 {
134 0xFFC03100,
135 IRQ_UART3_RX,
136#ifdef CONFIG_SERIAL_BFIN_DMA
137 CH_UART3_TX,
138 CH_UART3_RX,
139#endif
140 },
141#endif
142};
143
144int nr_ports = ARRAY_SIZE(bfin_serial_resource);
145
146static void bfin_serial_hw_init(struct bfin_serial_port *uart)
147{
148#ifdef CONFIG_SERIAL_BFIN_UART0
149 /* Enable UART0 RX and TX on pin 7 & 8 of PORT E */
150 bfin_write_PORTE_FER(0x180 | bfin_read_PORTE_FER());
151 bfin_write_PORTE_MUX(0x3C000 | bfin_read_PORTE_MUX());
152#endif
153
154#ifdef CONFIG_SERIAL_BFIN_UART1
155 /* Enable UART1 RX and TX on pin 0 & 1 of PORT H */
156 bfin_write_PORTH_FER(0x3 | bfin_read_PORTH_FER());
157 bfin_write_PORTH_MUX(~0xF & bfin_read_PORTH_MUX());
158#ifdef CONFIG_BFIN_UART1_CTSRTS
159 /* Enable UART1 RTS and CTS on pin 9 & 10 of PORT E */
160 bfin_write_PORTE_FER(0x600 | bfin_read_PORTE_FER());
161 bfin_write_PORTE_MUX(~0x3C0000 & bfin_read_PORTE_MUX());
162#endif
163#endif
164
165#ifdef CONFIG_SERIAL_BFIN_UART2
166 /* Enable UART2 RX and TX on pin 4 & 5 of PORT B */
167 bfin_write_PORTB_FER(0x30 | bfin_read_PORTB_FER());
168 bfin_write_PORTB_MUX(~0xF00 & bfin_read_PORTB_MUX());
169#endif
170
171#ifdef CONFIG_SERIAL_BFIN_UART3
172 /* Enable UART3 RX and TX on pin 6 & 7 of PORT B */
173 bfin_write_PORTB_FER(0xC0 | bfin_read_PORTB_FER());
174 bfin_write_PORTB_MUX(~0xF000 | bfin_read_PORTB_MUX());
175#ifdef CONFIG_BFIN_UART3_CTSRTS
176 /* Enable UART3 RTS and CTS on pin 2 & 3 of PORT B */
177 bfin_write_PORTB_FER(0xC | bfin_read_PORTB_FER());
178 bfin_write_PORTB_MUX(~0xF0 | bfin_read_PORTB_MUX());
179#endif
180#endif
181 SSYNC();
182#ifdef CONFIG_SERIAL_BFIN_CTSRTS
183 if (uart->cts_pin >= 0) {
184 gpio_request(uart->cts_pin, NULL);
185 gpio_direction_input(uart->cts_pin);
186 }
187
188 if (uart->rts_pin >= 0) {
189 gpio_request(uart->rts_pin, NULL);
190 gpio_direction_output(uart->rts_pin);
191 }
192#endif
193}
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
new file mode 100644
index 000000000000..791218fe7d94
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/blackfin.h
@@ -0,0 +1,168 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/blackfin.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _MACH_BLACKFIN_H_
33#define _MACH_BLACKFIN_H_
34
35#define BF548_FAMILY
36
37#include "bf548.h"
38#include "mem_map.h"
39#include "anomaly.h"
40
41#ifdef CONFIG_BF542
42#include "defBF542.h"
43#endif
44
45#ifdef CONFIG_BF544
46#include "defBF544.h"
47#endif
48
49#ifdef CONFIG_BF548
50#include "defBF548.h"
51#endif
52
53#ifdef CONFIG_BF549
54#include "defBF549.h"
55#endif
56
57#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
58#ifdef CONFIG_BF542
59#include "cdefBF542.h"
60#endif
61
62#ifdef CONFIG_BF544
63#include "cdefBF544.h"
64#endif
65#ifdef CONFIG_BF548
66#include "cdefBF548.h"
67#endif
68#ifdef CONFIG_BF549
69#include "cdefBF549.h"
70#endif
71
72/* UART 1*/
73#define bfin_read_UART_THR() bfin_read_UART1_THR()
74#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
75#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
76#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
77#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
78#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
79#define bfin_read_UART_IER() bfin_read_UART1_IER()
80#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
81#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
82#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
83#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
84#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
85#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
86#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
87#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
88#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
89#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
90#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
91#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
92#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
93#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
94#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
95
96#endif
97
98/* MAP used DEFINES from BF533 to BF54x - so we don't need to change
99 * them in the driver, kernel, etc. */
100
101/* UART_IIR Register */
102#define STATUS(x) ((x << 1) & 0x06)
103#define STATUS_P1 0x02
104#define STATUS_P0 0x01
105
106/* UART 0*/
107
108/* DMA Channnel */
109#define bfin_read_CH_UART_RX() bfin_read_CH_UART1_RX()
110#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART1_RX(val)
111#define bfin_read_CH_UART_TX() bfin_read_CH_UART1_TX()
112#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART1_TX(val)
113#define CH_UART_RX CH_UART1_RX
114#define CH_UART_TX CH_UART1_TX
115
116/* System Interrupt Controller */
117#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART1_RX()
118#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART1_RX(val)
119#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART1_TX()
120#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART1_TX(val)
121#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART1_ERROR()
122#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART1_ERROR(val)
123#define IRQ_UART_RX IRQ_UART1_RX
124#define IRQ_UART_TX IRQ_UART1_TX
125#define IRQ_UART_ERROR IRQ_UART1_ERROR
126
127/* MMR Registers*/
128#define bfin_read_UART_THR() bfin_read_UART1_THR()
129#define bfin_write_UART_THR(val) bfin_write_UART1_THR(val)
130#define bfin_read_UART_RBR() bfin_read_UART1_RBR()
131#define bfin_write_UART_RBR(val) bfin_write_UART1_RBR(val)
132#define bfin_read_UART_DLL() bfin_read_UART1_DLL()
133#define bfin_write_UART_DLL(val) bfin_write_UART1_DLL(val)
134#define bfin_read_UART_IER() bfin_read_UART1_IER()
135#define bfin_write_UART_IER(val) bfin_write_UART1_IER(val)
136#define bfin_read_UART_DLH() bfin_read_UART1_DLH()
137#define bfin_write_UART_DLH(val) bfin_write_UART1_DLH(val)
138#define bfin_read_UART_IIR() bfin_read_UART1_IIR()
139#define bfin_write_UART_IIR(val) bfin_write_UART1_IIR(val)
140#define bfin_read_UART_LCR() bfin_read_UART1_LCR()
141#define bfin_write_UART_LCR(val) bfin_write_UART1_LCR(val)
142#define bfin_read_UART_MCR() bfin_read_UART1_MCR()
143#define bfin_write_UART_MCR(val) bfin_write_UART1_MCR(val)
144#define bfin_read_UART_LSR() bfin_read_UART1_LSR()
145#define bfin_write_UART_LSR(val) bfin_write_UART1_LSR(val)
146#define bfin_read_UART_SCR() bfin_read_UART1_SCR()
147#define bfin_write_UART_SCR(val) bfin_write_UART1_SCR(val)
148#define bfin_read_UART_GCTL() bfin_read_UART1_GCTL()
149#define bfin_write_UART_GCTL(val) bfin_write_UART1_GCTL(val)
150#define UART_THR UART1_THR
151#define UART_RBR UART1_RBR
152#define UART_DLL UART1_DLL
153#define UART_IER UART1_IER
154#define UART_DLH UART1_DLH
155#define UART_IIR UART1_IIR
156#define UART_LCR UART1_LCR
157#define UART_MCR UART1_MCR
158#define UART_LSR UART1_LSR
159#define UART_SCR UART1_SCR
160#define UART_GCTL UART1_GCTL
161
162/* PLL_DIV Masks */
163#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
164#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
165#define CCLK_DIV4 CSEL_DIV4 /* CCLK = VCO / 4 */
166#define CCLK_DIV8 CSEL_DIV8 /* CCLK = VCO / 8 */
167
168#endif
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
index 6bbcefeb3627..98d35a929116 100644
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -31,7 +31,8 @@
31#ifndef _CDEF_BF54X_H 31#ifndef _CDEF_BF54X_H
32#define _CDEF_BF54X_H 32#define _CDEF_BF54X_H
33 33
34#include <defBF54x_base.h> 34#include "defBF54x_base.h"
35#include <asm/system.h>
35 36
36/* ************************************************************** */ 37/* ************************************************************** */
37/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */ 38/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
@@ -44,7 +45,30 @@
44#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 45#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
45#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val) 46#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
46#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 47#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
47#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val) 48/* Writing to VR_CTL initiates a PLL relock sequence. */
49static __inline__ void bfin_write_VR_CTL(unsigned int val)
50{
51 unsigned long flags, iwr0, iwr1, iwr2;
52
53 /* Enable the PLL Wakeup bit in SIC IWR */
54 iwr0 = bfin_read32(SIC_IWR0);
55 iwr1 = bfin_read32(SIC_IWR1);
56 iwr2 = bfin_read32(SIC_IWR2);
57 /* Only allow PPL Wakeup) */
58 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
59 bfin_write32(SIC_IWR1, 0);
60 bfin_write32(SIC_IWR2, 0);
61
62 bfin_write16(VR_CTL, val);
63 __builtin_bfin_ssync();
64
65 local_irq_save(flags);
66 asm("IDLE;");
67 local_irq_restore(flags);
68 bfin_write32(SIC_IWR0, iwr0);
69 bfin_write32(SIC_IWR1, iwr1);
70 bfin_write32(SIC_IWR2, iwr2);
71}
48#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 72#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
49#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val) 73#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
50#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 74#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
@@ -70,12 +94,18 @@
70#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val) 94#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
71#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2) 95#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
72#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val) 96#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
97#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
98#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
99
73#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0) 100#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
74#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val) 101#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
75#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1) 102#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
76#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val) 103#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
77#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2) 104#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
78#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val) 105#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
106#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
107#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
108
79#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0) 109#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
80#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val) 110#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
81#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1) 111#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
@@ -710,21 +740,21 @@
710#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR) 740#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
711#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR) 741#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR)
712#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR) 742#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
713#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR) 743#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
714#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG) 744#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
715#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val) 745#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
716#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT) 746#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
717#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val) 747#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
718#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY) 748#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
719#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY) 749#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
720#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT) 750#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
721#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val) 751#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
722#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY) 752#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
723#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY) 753#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
724#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR) 754#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
725#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR) 755#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
726#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR) 756#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
727#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR) 757#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
728#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS) 758#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
729#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val) 759#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
730#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP) 760#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
@@ -734,23 +764,23 @@
734#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT) 764#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
735#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val) 765#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
736#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR) 766#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
737#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR) 767#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
738#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR) 768#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
739#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR) 769#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
740#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG) 770#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
741#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val) 771#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
742#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT) 772#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
743#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val) 773#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
744#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY) 774#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
745#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY) 775#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
746#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT) 776#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
747#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val) 777#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
748#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY) 778#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
749#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY) 779#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
750#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR) 780#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
751#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR) 781#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
752#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR) 782#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
753#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR) 783#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
754#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS) 784#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
755#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val) 785#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
756#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP) 786#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
@@ -763,9 +793,9 @@
763/* MDMA Stream 1 Registers */ 793/* MDMA Stream 1 Registers */
764 794
765#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR) 795#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
766#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR) 796#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
767#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR) 797#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
768#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR) 798#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
769#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG) 799#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
770#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val) 800#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
771#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT) 801#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
@@ -777,9 +807,9 @@
777#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY) 807#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
778#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY) 808#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY)
779#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR) 809#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
780#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR) 810#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
781#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR) 811#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
782#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR) 812#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
783#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS) 813#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
784#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val) 814#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
785#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP) 815#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
@@ -789,9 +819,9 @@
789#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT) 819#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
790#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val) 820#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
791#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR) 821#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
792#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR) 822#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
793#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR) 823#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
794#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR) 824#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
795#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG) 825#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
796#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val) 826#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
797#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT) 827#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
@@ -803,9 +833,9 @@
803#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY) 833#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
804#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY) 834#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY)
805#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR) 835#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
806#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR) 836#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
807#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR) 837#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
808#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR) 838#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
809#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS) 839#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
810#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val) 840#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
811#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP) 841#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
index ac968fca5cc5..32d07130200c 100644
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ b/include/asm-blackfin/mach-bf548/defBF542.h
@@ -362,7 +362,6 @@
362/* Bit masks for KPAD_CTL */ 362/* Bit masks for KPAD_CTL */
363 363
364#define KPAD_EN 0x1 /* Keypad Enable */ 364#define KPAD_EN 0x1 /* Keypad Enable */
365#define nKPAD_EN 0x0
366#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ 365#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
367#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ 366#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
368#define KPAD_COLEN 0xe000 /* Column Enable Width */ 367#define KPAD_COLEN 0xe000 /* Column Enable Width */
@@ -384,29 +383,21 @@
384/* Bit masks for KPAD_STAT */ 383/* Bit masks for KPAD_STAT */
385 384
386#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ 385#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
387#define nKPAD_IRQ 0x0
388#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ 386#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
389#define KPAD_PRESSED 0x8 /* Key press current status */ 387#define KPAD_PRESSED 0x8 /* Key press current status */
390#define nKPAD_PRESSED 0x0
391 388
392/* Bit masks for KPAD_SOFTEVAL */ 389/* Bit masks for KPAD_SOFTEVAL */
393 390
394#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 391#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
395#define nKPAD_SOFTEVAL_E 0x0
396 392
397/* Bit masks for SDH_COMMAND */ 393/* Bit masks for SDH_COMMAND */
398 394
399#define CMD_IDX 0x3f /* Command Index */ 395#define CMD_IDX 0x3f /* Command Index */
400#define CMD_RSP 0x40 /* Response */ 396#define CMD_RSP 0x40 /* Response */
401#define nCMD_RSP 0x0
402#define CMD_L_RSP 0x80 /* Long Response */ 397#define CMD_L_RSP 0x80 /* Long Response */
403#define nCMD_L_RSP 0x0
404#define CMD_INT_E 0x100 /* Command Interrupt */ 398#define CMD_INT_E 0x100 /* Command Interrupt */
405#define nCMD_INT_E 0x0
406#define CMD_PEND_E 0x200 /* Command Pending */ 399#define CMD_PEND_E 0x200 /* Command Pending */
407#define nCMD_PEND_E 0x0
408#define CMD_E 0x400 /* Command Enable */ 400#define CMD_E 0x400 /* Command Enable */
409#define nCMD_E 0x0
410 401
411/* Bit masks for SDH_PWR_CTL */ 402/* Bit masks for SDH_PWR_CTL */
412 403
@@ -415,21 +406,15 @@
415#define TBD 0x3c /* TBD */ 406#define TBD 0x3c /* TBD */
416#endif 407#endif
417#define SD_CMD_OD 0x40 /* Open Drain Output */ 408#define SD_CMD_OD 0x40 /* Open Drain Output */
418#define nSD_CMD_OD 0x0
419#define ROD_CTL 0x80 /* Rod Control */ 409#define ROD_CTL 0x80 /* Rod Control */
420#define nROD_CTL 0x0
421 410
422/* Bit masks for SDH_CLK_CTL */ 411/* Bit masks for SDH_CLK_CTL */
423 412
424#define CLKDIV 0xff /* MC_CLK Divisor */ 413#define CLKDIV 0xff /* MC_CLK Divisor */
425#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ 414#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
426#define nCLK_E 0x0
427#define PWR_SV_E 0x200 /* Power Save Enable */ 415#define PWR_SV_E 0x200 /* Power Save Enable */
428#define nPWR_SV_E 0x0
429#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ 416#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
430#define nCLKDIV_BYPASS 0x0
431#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ 417#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
432#define nWIDE_BUS 0x0
433 418
434/* Bit masks for SDH_RESP_CMD */ 419/* Bit masks for SDH_RESP_CMD */
435 420
@@ -438,133 +423,74 @@
438/* Bit masks for SDH_DATA_CTL */ 423/* Bit masks for SDH_DATA_CTL */
439 424
440#define DTX_E 0x1 /* Data Transfer Enable */ 425#define DTX_E 0x1 /* Data Transfer Enable */
441#define nDTX_E 0x0
442#define DTX_DIR 0x2 /* Data Transfer Direction */ 426#define DTX_DIR 0x2 /* Data Transfer Direction */
443#define nDTX_DIR 0x0
444#define DTX_MODE 0x4 /* Data Transfer Mode */ 427#define DTX_MODE 0x4 /* Data Transfer Mode */
445#define nDTX_MODE 0x0
446#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ 428#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
447#define nDTX_DMA_E 0x0
448#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 429#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
449 430
450/* Bit masks for SDH_STATUS */ 431/* Bit masks for SDH_STATUS */
451 432
452#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 433#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
453#define nCMD_CRC_FAIL 0x0
454#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 434#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
455#define nDAT_CRC_FAIL 0x0
456#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 435#define CMD_TIMEOUT 0x4 /* CMD Time Out */
457#define nCMD_TIMEOUT 0x0
458#define DAT_TIMEOUT 0x8 /* Data Time Out */ 436#define DAT_TIMEOUT 0x8 /* Data Time Out */
459#define nDAT_TIMEOUT 0x0
460#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 437#define TX_UNDERRUN 0x10 /* Transmit Underrun */
461#define nTX_UNDERRUN 0x0
462#define RX_OVERRUN 0x20 /* Receive Overrun */ 438#define RX_OVERRUN 0x20 /* Receive Overrun */
463#define nRX_OVERRUN 0x0
464#define CMD_RESP_END 0x40 /* CMD Response End */ 439#define CMD_RESP_END 0x40 /* CMD Response End */
465#define nCMD_RESP_END 0x0
466#define CMD_SENT 0x80 /* CMD Sent */ 440#define CMD_SENT 0x80 /* CMD Sent */
467#define nCMD_SENT 0x0
468#define DAT_END 0x100 /* Data End */ 441#define DAT_END 0x100 /* Data End */
469#define nDAT_END 0x0
470#define START_BIT_ERR 0x200 /* Start Bit Error */ 442#define START_BIT_ERR 0x200 /* Start Bit Error */
471#define nSTART_BIT_ERR 0x0
472#define DAT_BLK_END 0x400 /* Data Block End */ 443#define DAT_BLK_END 0x400 /* Data Block End */
473#define nDAT_BLK_END 0x0
474#define CMD_ACT 0x800 /* CMD Active */ 444#define CMD_ACT 0x800 /* CMD Active */
475#define nCMD_ACT 0x0
476#define TX_ACT 0x1000 /* Transmit Active */ 445#define TX_ACT 0x1000 /* Transmit Active */
477#define nTX_ACT 0x0
478#define RX_ACT 0x2000 /* Receive Active */ 446#define RX_ACT 0x2000 /* Receive Active */
479#define nRX_ACT 0x0
480#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ 447#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
481#define nTX_FIFO_STAT 0x0
482#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ 448#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
483#define nRX_FIFO_STAT 0x0
484#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ 449#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
485#define nTX_FIFO_FULL 0x0
486#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ 450#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
487#define nRX_FIFO_FULL 0x0
488#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ 451#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
489#define nTX_FIFO_ZERO 0x0
490#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ 452#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
491#define nRX_DAT_ZERO 0x0
492#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ 453#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
493#define nTX_DAT_RDY 0x0
494#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ 454#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
495#define nRX_FIFO_RDY 0x0
496 455
497/* Bit masks for SDH_STATUS_CLR */ 456/* Bit masks for SDH_STATUS_CLR */
498 457
499#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ 458#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
500#define nCMD_CRC_FAIL_STAT 0x0
501#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ 459#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
502#define nDAT_CRC_FAIL_STAT 0x0
503#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ 460#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
504#define nCMD_TIMEOUT_STAT 0x0
505#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ 461#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
506#define nDAT_TIMEOUT_STAT 0x0
507#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ 462#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
508#define nTX_UNDERRUN_STAT 0x0
509#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ 463#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
510#define nRX_OVERRUN_STAT 0x0
511#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ 464#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
512#define nCMD_RESP_END_STAT 0x0
513#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ 465#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
514#define nCMD_SENT_STAT 0x0
515#define DAT_END_STAT 0x100 /* Data End Status */ 466#define DAT_END_STAT 0x100 /* Data End Status */
516#define nDAT_END_STAT 0x0
517#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ 467#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
518#define nSTART_BIT_ERR_STAT 0x0
519#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ 468#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
520#define nDAT_BLK_END_STAT 0x0
521 469
522/* Bit masks for SDH_MASK0 */ 470/* Bit masks for SDH_MASK0 */
523 471
524#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ 472#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
525#define nCMD_CRC_FAIL_MASK 0x0
526#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ 473#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
527#define nDAT_CRC_FAIL_MASK 0x0
528#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ 474#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
529#define nCMD_TIMEOUT_MASK 0x0
530#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ 475#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
531#define nDAT_TIMEOUT_MASK 0x0
532#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ 476#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
533#define nTX_UNDERRUN_MASK 0x0
534#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ 477#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
535#define nRX_OVERRUN_MASK 0x0
536#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ 478#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
537#define nCMD_RESP_END_MASK 0x0
538#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ 479#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
539#define nCMD_SENT_MASK 0x0
540#define DAT_END_MASK 0x100 /* Data End Mask */ 480#define DAT_END_MASK 0x100 /* Data End Mask */
541#define nDAT_END_MASK 0x0
542#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ 481#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
543#define nSTART_BIT_ERR_MASK 0x0
544#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ 482#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
545#define nDAT_BLK_END_MASK 0x0
546#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ 483#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
547#define nCMD_ACT_MASK 0x0
548#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ 484#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
549#define nTX_ACT_MASK 0x0
550#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ 485#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
551#define nRX_ACT_MASK 0x0
552#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ 486#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
553#define nTX_FIFO_STAT_MASK 0x0
554#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ 487#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
555#define nRX_FIFO_STAT_MASK 0x0
556#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ 488#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
557#define nTX_FIFO_FULL_MASK 0x0
558#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ 489#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
559#define nRX_FIFO_FULL_MASK 0x0
560#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ 490#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
561#define nTX_FIFO_ZERO_MASK 0x0
562#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ 491#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
563#define nRX_DAT_ZERO_MASK 0x0
564#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ 492#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
565#define nTX_DAT_RDY_MASK 0x0
566#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ 493#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
567#define nRX_FIFO_RDY_MASK 0x0
568 494
569/* Bit masks for SDH_FIFO_CNT */ 495/* Bit masks for SDH_FIFO_CNT */
570 496
@@ -573,73 +499,47 @@
573/* Bit masks for SDH_E_STATUS */ 499/* Bit masks for SDH_E_STATUS */
574 500
575#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ 501#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
576#define nSDIO_INT_DET 0x0
577#define SD_CARD_DET 0x10 /* SD Card Detect */ 502#define SD_CARD_DET 0x10 /* SD Card Detect */
578#define nSD_CARD_DET 0x0
579 503
580/* Bit masks for SDH_E_MASK */ 504/* Bit masks for SDH_E_MASK */
581 505
582#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ 506#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
583#define nSDIO_MSK 0x0
584#define SCD_MSK 0x40 /* Mask Card Detect */ 507#define SCD_MSK 0x40 /* Mask Card Detect */
585#define nSCD_MSK 0x0
586 508
587/* Bit masks for SDH_CFG */ 509/* Bit masks for SDH_CFG */
588 510
589#define CLKS_EN 0x1 /* Clocks Enable */ 511#define CLKS_EN 0x1 /* Clocks Enable */
590#define nCLKS_EN 0x0
591#define SD4E 0x4 /* SDIO 4-Bit Enable */ 512#define SD4E 0x4 /* SDIO 4-Bit Enable */
592#define nSD4E 0x0
593#define MWE 0x8 /* Moving Window Enable */ 513#define MWE 0x8 /* Moving Window Enable */
594#define nMWE 0x0
595#define SD_RST 0x10 /* SDMMC Reset */ 514#define SD_RST 0x10 /* SDMMC Reset */
596#define nSD_RST 0x0
597#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ 515#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
598#define nPUP_SDDAT 0x0
599#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ 516#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
600#define nPUP_SDDAT3 0x0
601#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ 517#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
602#define nPD_SDDAT3 0x0
603 518
604/* Bit masks for SDH_RD_WAIT_EN */ 519/* Bit masks for SDH_RD_WAIT_EN */
605 520
606#define RWR 0x1 /* Read Wait Request */ 521#define RWR 0x1 /* Read Wait Request */
607#define nRWR 0x0
608 522
609/* Bit masks for ATAPI_CONTROL */ 523/* Bit masks for ATAPI_CONTROL */
610 524
611#define PIO_START 0x1 /* Start PIO/Reg Op */ 525#define PIO_START 0x1 /* Start PIO/Reg Op */
612#define nPIO_START 0x0
613#define MULTI_START 0x2 /* Start Multi-DMA Op */ 526#define MULTI_START 0x2 /* Start Multi-DMA Op */
614#define nMULTI_START 0x0
615#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ 527#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
616#define nULTRA_START 0x0
617#define XFER_DIR 0x8 /* Transfer Direction */ 528#define XFER_DIR 0x8 /* Transfer Direction */
618#define nXFER_DIR 0x0
619#define IORDY_EN 0x10 /* IORDY Enable */ 529#define IORDY_EN 0x10 /* IORDY Enable */
620#define nIORDY_EN 0x0
621#define FIFO_FLUSH 0x20 /* Flush FIFOs */ 530#define FIFO_FLUSH 0x20 /* Flush FIFOs */
622#define nFIFO_FLUSH 0x0
623#define SOFT_RST 0x40 /* Soft Reset */ 531#define SOFT_RST 0x40 /* Soft Reset */
624#define nSOFT_RST 0x0
625#define DEV_RST 0x80 /* Device Reset */ 532#define DEV_RST 0x80 /* Device Reset */
626#define nDEV_RST 0x0
627#define TFRCNT_RST 0x100 /* Trans Count Reset */ 533#define TFRCNT_RST 0x100 /* Trans Count Reset */
628#define nTFRCNT_RST 0x0
629#define END_ON_TERM 0x200 /* End/Terminate Select */ 534#define END_ON_TERM 0x200 /* End/Terminate Select */
630#define nEND_ON_TERM 0x0
631#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ 535#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
632#define nPIO_USE_DMA 0x0
633#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ 536#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
634 537
635/* Bit masks for ATAPI_STATUS */ 538/* Bit masks for ATAPI_STATUS */
636 539
637#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ 540#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
638#define nPIO_XFER_ON 0x0
639#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ 541#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
640#define nMULTI_XFER_ON 0x0
641#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ 542#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
642#define nULTRA_XFER_ON 0x0
643#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ 543#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
644 544
645/* Bit masks for ATAPI_DEV_ADDR */ 545/* Bit masks for ATAPI_DEV_ADDR */
@@ -649,66 +549,39 @@
649/* Bit masks for ATAPI_INT_MASK */ 549/* Bit masks for ATAPI_INT_MASK */
650 550
651#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ 551#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
652#define nATAPI_DEV_INT_MASK 0x0
653#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ 552#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
654#define nPIO_DONE_MASK 0x0
655#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ 553#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
656#define nMULTI_DONE_MASK 0x0
657#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ 554#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
658#define nUDMAIN_DONE_MASK 0x0
659#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ 555#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
660#define nUDMAOUT_DONE_MASK 0x0
661#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ 556#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
662#define nHOST_TERM_XFER_MASK 0x0
663#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ 557#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
664#define nMULTI_TERM_MASK 0x0
665#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ 558#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
666#define nUDMAIN_TERM_MASK 0x0
667#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ 559#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
668#define nUDMAOUT_TERM_MASK 0x0
669 560
670/* Bit masks for ATAPI_INT_STATUS */ 561/* Bit masks for ATAPI_INT_STATUS */
671 562
672#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ 563#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
673#define nATAPI_DEV_INT 0x0
674#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ 564#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
675#define nPIO_DONE_INT 0x0
676#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ 565#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
677#define nMULTI_DONE_INT 0x0
678#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ 566#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
679#define nUDMAIN_DONE_INT 0x0
680#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ 567#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
681#define nUDMAOUT_DONE_INT 0x0
682#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ 568#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
683#define nHOST_TERM_XFER_INT 0x0
684#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ 569#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
685#define nMULTI_TERM_INT 0x0
686#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ 570#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
687#define nUDMAIN_TERM_INT 0x0
688#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ 571#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
689#define nUDMAOUT_TERM_INT 0x0
690 572
691/* Bit masks for ATAPI_LINE_STATUS */ 573/* Bit masks for ATAPI_LINE_STATUS */
692 574
693#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ 575#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
694#define nATAPI_INTR 0x0
695#define ATAPI_DASP 0x2 /* Device dasp to host line status */ 576#define ATAPI_DASP 0x2 /* Device dasp to host line status */
696#define nATAPI_DASP 0x0
697#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ 577#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
698#define nATAPI_CS0N 0x0
699#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ 578#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
700#define nATAPI_CS1N 0x0
701#define ATAPI_ADDR 0x70 /* ATAPI address line status */ 579#define ATAPI_ADDR 0x70 /* ATAPI address line status */
702#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ 580#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
703#define nATAPI_DMAREQ 0x0
704#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ 581#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
705#define nATAPI_DMAACKN 0x0
706#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ 582#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
707#define nATAPI_DIOWN 0x0
708#define ATAPI_DIORN 0x400 /* ATAPI read line status */ 583#define ATAPI_DIORN 0x400 /* ATAPI read line status */
709#define nATAPI_DIORN 0x0
710#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ 584#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
711#define nATAPI_IORDY 0x0
712 585
713/* Bit masks for ATAPI_SM_STATE */ 586/* Bit masks for ATAPI_SM_STATE */
714 587
@@ -720,7 +593,6 @@
720/* Bit masks for ATAPI_TERMINATE */ 593/* Bit masks for ATAPI_TERMINATE */
721 594
722#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ 595#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
723#define nATAPI_HOST_TERM 0x0
724 596
725/* Bit masks for ATAPI_REG_TIM_0 */ 597/* Bit masks for ATAPI_REG_TIM_0 */
726 598
@@ -779,131 +651,77 @@
779/* Bit masks for USB_POWER */ 651/* Bit masks for USB_POWER */
780 652
781#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ 653#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
782#define nENABLE_SUSPENDM 0x0
783#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ 654#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
784#define nSUSPEND_MODE 0x0
785#define RESUME_MODE 0x4 /* DMA Mode */ 655#define RESUME_MODE 0x4 /* DMA Mode */
786#define nRESUME_MODE 0x0
787#define RESET 0x8 /* Reset indicator */ 656#define RESET 0x8 /* Reset indicator */
788#define nRESET 0x0
789#define HS_MODE 0x10 /* High Speed mode indicator */ 657#define HS_MODE 0x10 /* High Speed mode indicator */
790#define nHS_MODE 0x0
791#define HS_ENABLE 0x20 /* high Speed Enable */ 658#define HS_ENABLE 0x20 /* high Speed Enable */
792#define nHS_ENABLE 0x0
793#define SOFT_CONN 0x40 /* Soft connect */ 659#define SOFT_CONN 0x40 /* Soft connect */
794#define nSOFT_CONN 0x0
795#define ISO_UPDATE 0x80 /* Isochronous update */ 660#define ISO_UPDATE 0x80 /* Isochronous update */
796#define nISO_UPDATE 0x0
797 661
798/* Bit masks for USB_INTRTX */ 662/* Bit masks for USB_INTRTX */
799 663
800#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ 664#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
801#define nEP0_TX 0x0
802#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ 665#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
803#define nEP1_TX 0x0
804#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ 666#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
805#define nEP2_TX 0x0
806#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ 667#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
807#define nEP3_TX 0x0
808#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ 668#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
809#define nEP4_TX 0x0
810#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ 669#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
811#define nEP5_TX 0x0
812#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ 670#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
813#define nEP6_TX 0x0
814#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ 671#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
815#define nEP7_TX 0x0
816 672
817/* Bit masks for USB_INTRRX */ 673/* Bit masks for USB_INTRRX */
818 674
819#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ 675#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
820#define nEP1_RX 0x0
821#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ 676#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
822#define nEP2_RX 0x0
823#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ 677#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
824#define nEP3_RX 0x0
825#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ 678#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
826#define nEP4_RX 0x0
827#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ 679#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
828#define nEP5_RX 0x0
829#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ 680#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
830#define nEP6_RX 0x0
831#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ 681#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
832#define nEP7_RX 0x0
833 682
834/* Bit masks for USB_INTRTXE */ 683/* Bit masks for USB_INTRTXE */
835 684
836#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ 685#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
837#define nEP0_TX_E 0x0
838#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ 686#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
839#define nEP1_TX_E 0x0
840#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ 687#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
841#define nEP2_TX_E 0x0
842#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ 688#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
843#define nEP3_TX_E 0x0
844#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ 689#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
845#define nEP4_TX_E 0x0
846#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ 690#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
847#define nEP5_TX_E 0x0
848#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ 691#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
849#define nEP6_TX_E 0x0
850#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ 692#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
851#define nEP7_TX_E 0x0
852 693
853/* Bit masks for USB_INTRRXE */ 694/* Bit masks for USB_INTRRXE */
854 695
855#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ 696#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
856#define nEP1_RX_E 0x0
857#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ 697#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
858#define nEP2_RX_E 0x0
859#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ 698#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
860#define nEP3_RX_E 0x0
861#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ 699#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
862#define nEP4_RX_E 0x0
863#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ 700#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
864#define nEP5_RX_E 0x0
865#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ 701#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
866#define nEP6_RX_E 0x0
867#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ 702#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
868#define nEP7_RX_E 0x0
869 703
870/* Bit masks for USB_INTRUSB */ 704/* Bit masks for USB_INTRUSB */
871 705
872#define SUSPEND_B 0x1 /* Suspend indicator */ 706#define SUSPEND_B 0x1 /* Suspend indicator */
873#define nSUSPEND_B 0x0
874#define RESUME_B 0x2 /* Resume indicator */ 707#define RESUME_B 0x2 /* Resume indicator */
875#define nRESUME_B 0x0
876#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ 708#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
877#define nRESET_OR_BABLE_B 0x0
878#define SOF_B 0x8 /* Start of frame */ 709#define SOF_B 0x8 /* Start of frame */
879#define nSOF_B 0x0
880#define CONN_B 0x10 /* Connection indicator */ 710#define CONN_B 0x10 /* Connection indicator */
881#define nCONN_B 0x0
882#define DISCON_B 0x20 /* Disconnect indicator */ 711#define DISCON_B 0x20 /* Disconnect indicator */
883#define nDISCON_B 0x0
884#define SESSION_REQ_B 0x40 /* Session Request */ 712#define SESSION_REQ_B 0x40 /* Session Request */
885#define nSESSION_REQ_B 0x0
886#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ 713#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
887#define nVBUS_ERROR_B 0x0
888 714
889/* Bit masks for USB_INTRUSBE */ 715/* Bit masks for USB_INTRUSBE */
890 716
891#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ 717#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
892#define nSUSPEND_BE 0x0
893#define RESUME_BE 0x2 /* Resume indicator int enable */ 718#define RESUME_BE 0x2 /* Resume indicator int enable */
894#define nRESUME_BE 0x0
895#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ 719#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
896#define nRESET_OR_BABLE_BE 0x0
897#define SOF_BE 0x8 /* Start of frame int enable */ 720#define SOF_BE 0x8 /* Start of frame int enable */
898#define nSOF_BE 0x0
899#define CONN_BE 0x10 /* Connection indicator int enable */ 721#define CONN_BE 0x10 /* Connection indicator int enable */
900#define nCONN_BE 0x0
901#define DISCON_BE 0x20 /* Disconnect indicator int enable */ 722#define DISCON_BE 0x20 /* Disconnect indicator int enable */
902#define nDISCON_BE 0x0
903#define SESSION_REQ_BE 0x40 /* Session Request int enable */ 723#define SESSION_REQ_BE 0x40 /* Session Request int enable */
904#define nSESSION_REQ_BE 0x0
905#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ 724#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
906#define nVBUS_ERROR_BE 0x0
907 725
908/* Bit masks for USB_FRAME */ 726/* Bit masks for USB_FRAME */
909 727
@@ -916,117 +734,67 @@
916/* Bit masks for USB_GLOBAL_CTL */ 734/* Bit masks for USB_GLOBAL_CTL */
917 735
918#define GLOBAL_ENA 0x1 /* enables USB module */ 736#define GLOBAL_ENA 0x1 /* enables USB module */
919#define nGLOBAL_ENA 0x0
920#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ 737#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
921#define nEP1_TX_ENA 0x0
922#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ 738#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
923#define nEP2_TX_ENA 0x0
924#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ 739#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
925#define nEP3_TX_ENA 0x0
926#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ 740#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
927#define nEP4_TX_ENA 0x0
928#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ 741#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
929#define nEP5_TX_ENA 0x0
930#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ 742#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
931#define nEP6_TX_ENA 0x0
932#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ 743#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
933#define nEP7_TX_ENA 0x0
934#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ 744#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
935#define nEP1_RX_ENA 0x0
936#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ 745#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
937#define nEP2_RX_ENA 0x0
938#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ 746#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
939#define nEP3_RX_ENA 0x0
940#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ 747#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
941#define nEP4_RX_ENA 0x0
942#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ 748#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
943#define nEP5_RX_ENA 0x0
944#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ 749#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
945#define nEP6_RX_ENA 0x0
946#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ 750#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
947#define nEP7_RX_ENA 0x0
948 751
949/* Bit masks for USB_OTG_DEV_CTL */ 752/* Bit masks for USB_OTG_DEV_CTL */
950 753
951#define SESSION 0x1 /* session indicator */ 754#define SESSION 0x1 /* session indicator */
952#define nSESSION 0x0
953#define HOST_REQ 0x2 /* Host negotiation request */ 755#define HOST_REQ 0x2 /* Host negotiation request */
954#define nHOST_REQ 0x0
955#define HOST_MODE 0x4 /* indicates USBDRC is a host */ 756#define HOST_MODE 0x4 /* indicates USBDRC is a host */
956#define nHOST_MODE 0x0
957#define VBUS0 0x8 /* Vbus level indicator[0] */ 757#define VBUS0 0x8 /* Vbus level indicator[0] */
958#define nVBUS0 0x0
959#define VBUS1 0x10 /* Vbus level indicator[1] */ 758#define VBUS1 0x10 /* Vbus level indicator[1] */
960#define nVBUS1 0x0
961#define LSDEV 0x20 /* Low-speed indicator */ 759#define LSDEV 0x20 /* Low-speed indicator */
962#define nLSDEV 0x0
963#define FSDEV 0x40 /* Full or High-speed indicator */ 760#define FSDEV 0x40 /* Full or High-speed indicator */
964#define nFSDEV 0x0
965#define B_DEVICE 0x80 /* A' or 'B' device indicator */ 761#define B_DEVICE 0x80 /* A' or 'B' device indicator */
966#define nB_DEVICE 0x0
967 762
968/* Bit masks for USB_OTG_VBUS_IRQ */ 763/* Bit masks for USB_OTG_VBUS_IRQ */
969 764
970#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ 765#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
971#define nDRIVE_VBUS_ON 0x0
972#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ 766#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
973#define nDRIVE_VBUS_OFF 0x0
974#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ 767#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
975#define nCHRG_VBUS_START 0x0
976#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ 768#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
977#define nCHRG_VBUS_END 0x0
978#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ 769#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
979#define nDISCHRG_VBUS_START 0x0
980#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ 770#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
981#define nDISCHRG_VBUS_END 0x0
982 771
983/* Bit masks for USB_OTG_VBUS_MASK */ 772/* Bit masks for USB_OTG_VBUS_MASK */
984 773
985#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ 774#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
986#define nDRIVE_VBUS_ON_ENA 0x0
987#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ 775#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
988#define nDRIVE_VBUS_OFF_ENA 0x0
989#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ 776#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
990#define nCHRG_VBUS_START_ENA 0x0
991#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ 777#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
992#define nCHRG_VBUS_END_ENA 0x0
993#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ 778#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
994#define nDISCHRG_VBUS_START_ENA 0x0
995#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ 779#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
996#define nDISCHRG_VBUS_END_ENA 0x0
997 780
998/* Bit masks for USB_CSR0 */ 781/* Bit masks for USB_CSR0 */
999 782
1000#define RXPKTRDY 0x1 /* data packet receive indicator */ 783#define RXPKTRDY 0x1 /* data packet receive indicator */
1001#define nRXPKTRDY 0x0
1002#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ 784#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1003#define nTXPKTRDY 0x0
1004#define STALL_SENT 0x4 /* STALL handshake sent */ 785#define STALL_SENT 0x4 /* STALL handshake sent */
1005#define nSTALL_SENT 0x0
1006#define DATAEND 0x8 /* Data end indicator */ 786#define DATAEND 0x8 /* Data end indicator */
1007#define nDATAEND 0x0
1008#define SETUPEND 0x10 /* Setup end */ 787#define SETUPEND 0x10 /* Setup end */
1009#define nSETUPEND 0x0
1010#define SENDSTALL 0x20 /* Send STALL handshake */ 788#define SENDSTALL 0x20 /* Send STALL handshake */
1011#define nSENDSTALL 0x0
1012#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ 789#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1013#define nSERVICED_RXPKTRDY 0x0
1014#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ 790#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1015#define nSERVICED_SETUPEND 0x0
1016#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ 791#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1017#define nFLUSHFIFO 0x0
1018#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ 792#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1019#define nSTALL_RECEIVED_H 0x0
1020#define SETUPPKT_H 0x8 /* send Setup token host mode */ 793#define SETUPPKT_H 0x8 /* send Setup token host mode */
1021#define nSETUPPKT_H 0x0
1022#define ERROR_H 0x10 /* timeout error indicator host mode */ 794#define ERROR_H 0x10 /* timeout error indicator host mode */
1023#define nERROR_H 0x0
1024#define REQPKT_H 0x20 /* Request an IN transaction host mode */ 795#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1025#define nREQPKT_H 0x0
1026#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ 796#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1027#define nSTATUSPKT_H 0x0
1028#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ 797#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1029#define nNAK_TIMEOUT_H 0x0
1030 798
1031/* Bit masks for USB_COUNT0 */ 799/* Bit masks for USB_COUNT0 */
1032 800
@@ -1047,37 +815,21 @@
1047/* Bit masks for USB_TXCSR */ 815/* Bit masks for USB_TXCSR */
1048 816
1049#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ 817#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1050#define nTXPKTRDY_T 0x0
1051#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ 818#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1052#define nFIFO_NOT_EMPTY_T 0x0
1053#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ 819#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1054#define nUNDERRUN_T 0x0
1055#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ 820#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1056#define nFLUSHFIFO_T 0x0
1057#define STALL_SEND_T 0x10 /* issue a Stall handshake */ 821#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1058#define nSTALL_SEND_T 0x0
1059#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ 822#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1060#define nSTALL_SENT_T 0x0
1061#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ 823#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1062#define nCLEAR_DATATOGGLE_T 0x0
1063#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ 824#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1064#define nINCOMPTX_T 0x0
1065#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ 825#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1066#define nDMAREQMODE_T 0x0
1067#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ 826#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1068#define nFORCE_DATATOGGLE_T 0x0
1069#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ 827#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1070#define nDMAREQ_ENA_T 0x0
1071#define ISO_T 0x4000 /* enable Isochronous transfers */ 828#define ISO_T 0x4000 /* enable Isochronous transfers */
1072#define nISO_T 0x0
1073#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ 829#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1074#define nAUTOSET_T 0x0
1075#define ERROR_TH 0x4 /* error condition host mode */ 830#define ERROR_TH 0x4 /* error condition host mode */
1076#define nERROR_TH 0x0
1077#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ 831#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1078#define nSTALL_RECEIVED_TH 0x0
1079#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ 832#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1080#define nNAK_TIMEOUT_TH 0x0
1081 833
1082/* Bit masks for USB_TXCOUNT */ 834/* Bit masks for USB_TXCOUNT */
1083 835
@@ -1086,45 +838,25 @@
1086/* Bit masks for USB_RXCSR */ 838/* Bit masks for USB_RXCSR */
1087 839
1088#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ 840#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1089#define nRXPKTRDY_R 0x0
1090#define FIFO_FULL_R 0x2 /* FIFO not empty */ 841#define FIFO_FULL_R 0x2 /* FIFO not empty */
1091#define nFIFO_FULL_R 0x0
1092#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ 842#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1093#define nOVERRUN_R 0x0
1094#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ 843#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1095#define nDATAERROR_R 0x0
1096#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ 844#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1097#define nFLUSHFIFO_R 0x0
1098#define STALL_SEND_R 0x20 /* issue a Stall handshake */ 845#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1099#define nSTALL_SEND_R 0x0
1100#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ 846#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1101#define nSTALL_SENT_R 0x0
1102#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ 847#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1103#define nCLEAR_DATATOGGLE_R 0x0
1104#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ 848#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1105#define nINCOMPRX_R 0x0
1106#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ 849#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1107#define nDMAREQMODE_R 0x0
1108#define DISNYET_R 0x1000 /* disable Nyet handshakes */ 850#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1109#define nDISNYET_R 0x0
1110#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ 851#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1111#define nDMAREQ_ENA_R 0x0
1112#define ISO_R 0x4000 /* enable Isochronous transfers */ 852#define ISO_R 0x4000 /* enable Isochronous transfers */
1113#define nISO_R 0x0
1114#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ 853#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1115#define nAUTOCLEAR_R 0x0
1116#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ 854#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1117#define nERROR_RH 0x0
1118#define REQPKT_RH 0x20 /* request an IN transaction host mode */ 855#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1119#define nREQPKT_RH 0x0
1120#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ 856#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1121#define nSTALL_RECEIVED_RH 0x0
1122#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ 857#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1123#define nINCOMPRX_RH 0x0
1124#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ 858#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1125#define nDMAREQMODE_RH 0x0
1126#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ 859#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1127#define nAUTOREQ_RH 0x0
1128 860
1129/* Bit masks for USB_RXCOUNT */ 861/* Bit masks for USB_RXCOUNT */
1130 862
@@ -1151,35 +883,22 @@
1151/* Bit masks for USB_DMA_INTERRUPT */ 883/* Bit masks for USB_DMA_INTERRUPT */
1152 884
1153#define DMA0_INT 0x1 /* DMA0 pending interrupt */ 885#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1154#define nDMA0_INT 0x0
1155#define DMA1_INT 0x2 /* DMA1 pending interrupt */ 886#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1156#define nDMA1_INT 0x0
1157#define DMA2_INT 0x4 /* DMA2 pending interrupt */ 887#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1158#define nDMA2_INT 0x0
1159#define DMA3_INT 0x8 /* DMA3 pending interrupt */ 888#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1160#define nDMA3_INT 0x0
1161#define DMA4_INT 0x10 /* DMA4 pending interrupt */ 889#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1162#define nDMA4_INT 0x0
1163#define DMA5_INT 0x20 /* DMA5 pending interrupt */ 890#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1164#define nDMA5_INT 0x0
1165#define DMA6_INT 0x40 /* DMA6 pending interrupt */ 891#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1166#define nDMA6_INT 0x0
1167#define DMA7_INT 0x80 /* DMA7 pending interrupt */ 892#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1168#define nDMA7_INT 0x0
1169 893
1170/* Bit masks for USB_DMAxCONTROL */ 894/* Bit masks for USB_DMAxCONTROL */
1171 895
1172#define DMA_ENA 0x1 /* DMA enable */ 896#define DMA_ENA 0x1 /* DMA enable */
1173#define nDMA_ENA 0x0
1174#define DIRECTION 0x2 /* direction of DMA transfer */ 897#define DIRECTION 0x2 /* direction of DMA transfer */
1175#define nDIRECTION 0x0
1176#define MODE 0x4 /* DMA Bus error */ 898#define MODE 0x4 /* DMA Bus error */
1177#define nMODE 0x0
1178#define INT_ENA 0x8 /* Interrupt enable */ 899#define INT_ENA 0x8 /* Interrupt enable */
1179#define nINT_ENA 0x0
1180#define EPNUM 0xf0 /* EP number */ 900#define EPNUM 0xf0 /* EP number */
1181#define BUSERROR 0x100 /* DMA Bus error */ 901#define BUSERROR 0x100 /* DMA Bus error */
1182#define nBUSERROR 0x0
1183 902
1184/* Bit masks for USB_DMAxADDRHIGH */ 903/* Bit masks for USB_DMAxADDRHIGH */
1185 904
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
index 8fc77ea12aa9..dd955dcd39b8 100644
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -538,21 +538,13 @@
538/* Bit masks for PIXC_CTL */ 538/* Bit masks for PIXC_CTL */
539 539
540#define PIXC_EN 0x1 /* Pixel Compositor Enable */ 540#define PIXC_EN 0x1 /* Pixel Compositor Enable */
541#define nPIXC_EN 0x0
542#define OVR_A_EN 0x2 /* Overlay A Enable */ 541#define OVR_A_EN 0x2 /* Overlay A Enable */
543#define nOVR_A_EN 0x0
544#define OVR_B_EN 0x4 /* Overlay B Enable */ 542#define OVR_B_EN 0x4 /* Overlay B Enable */
545#define nOVR_B_EN 0x0
546#define IMG_FORM 0x8 /* Image Data Format */ 543#define IMG_FORM 0x8 /* Image Data Format */
547#define nIMG_FORM 0x0
548#define OVR_FORM 0x10 /* Overlay Data Format */ 544#define OVR_FORM 0x10 /* Overlay Data Format */
549#define nOVR_FORM 0x0
550#define OUT_FORM 0x20 /* Output Data Format */ 545#define OUT_FORM 0x20 /* Output Data Format */
551#define nOUT_FORM 0x0
552#define UDS_MOD 0x40 /* Resampling Mode */ 546#define UDS_MOD 0x40 /* Resampling Mode */
553#define nUDS_MOD 0x0
554#define TC_EN 0x80 /* Transparent Color Enable */ 547#define TC_EN 0x80 /* Transparent Color Enable */
555#define nTC_EN 0x0
556#define IMG_STAT 0x300 /* Image FIFO Status */ 548#define IMG_STAT 0x300 /* Image FIFO Status */
557#define OVR_STAT 0xc00 /* Overlay FIFO Status */ 549#define OVR_STAT 0xc00 /* Overlay FIFO Status */
558#define WM_LVL 0x3000 /* FIFO Watermark Level */ 550#define WM_LVL 0x3000 /* FIFO Watermark Level */
@@ -600,13 +592,9 @@
600/* Bit masks for PIXC_INTRSTAT */ 592/* Bit masks for PIXC_INTRSTAT */
601 593
602#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ 594#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
603#define nOVR_INT_EN 0x0
604#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ 595#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
605#define nFRM_INT_EN 0x0
606#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ 596#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
607#define nOVR_INT_STAT 0x0
608#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ 597#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
609#define nFRM_INT_STAT 0x0
610 598
611/* Bit masks for PIXC_RYCON */ 599/* Bit masks for PIXC_RYCON */
612 600
@@ -614,7 +602,6 @@
614#define A12 0xffc00 /* A12 in the Coefficient Matrix */ 602#define A12 0xffc00 /* A12 in the Coefficient Matrix */
615#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ 603#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
616#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ 604#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
617#define nRY_MULT4 0x0
618 605
619/* Bit masks for PIXC_GUCON */ 606/* Bit masks for PIXC_GUCON */
620 607
@@ -622,7 +609,6 @@
622#define A22 0xffc00 /* A22 in the Coefficient Matrix */ 609#define A22 0xffc00 /* A22 in the Coefficient Matrix */
623#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ 610#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
624#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ 611#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
625#define nGU_MULT4 0x0
626 612
627/* Bit masks for PIXC_BVCON */ 613/* Bit masks for PIXC_BVCON */
628 614
@@ -630,7 +616,6 @@
630#define A32 0xffc00 /* A32 in the Coefficient Matrix */ 616#define A32 0xffc00 /* A32 in the Coefficient Matrix */
631#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ 617#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
632#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ 618#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
633#define nBV_MULT4 0x0
634 619
635/* Bit masks for PIXC_CCBIAS */ 620/* Bit masks for PIXC_CCBIAS */
636 621
@@ -647,48 +632,28 @@
647/* Bit masks for HOST_CONTROL */ 632/* Bit masks for HOST_CONTROL */
648 633
649#define HOST_EN 0x1 /* Host Enable */ 634#define HOST_EN 0x1 /* Host Enable */
650#define nHOST_EN 0x0
651#define HOST_END 0x2 /* Host Endianess */ 635#define HOST_END 0x2 /* Host Endianess */
652#define nHOST_END 0x0
653#define DATA_SIZE 0x4 /* Data Size */ 636#define DATA_SIZE 0x4 /* Data Size */
654#define nDATA_SIZE 0x0
655#define HOST_RST 0x8 /* Host Reset */ 637#define HOST_RST 0x8 /* Host Reset */
656#define nHOST_RST 0x0
657#define HRDY_OVR 0x20 /* Host Ready Override */ 638#define HRDY_OVR 0x20 /* Host Ready Override */
658#define nHRDY_OVR 0x0
659#define INT_MODE 0x40 /* Interrupt Mode */ 639#define INT_MODE 0x40 /* Interrupt Mode */
660#define nINT_MODE 0x0
661#define BT_EN 0x80 /* Bus Timeout Enable */ 640#define BT_EN 0x80 /* Bus Timeout Enable */
662#define nBT_EN 0x0
663#define EHW 0x100 /* Enable Host Write */ 641#define EHW 0x100 /* Enable Host Write */
664#define nEHW 0x0
665#define EHR 0x200 /* Enable Host Read */ 642#define EHR 0x200 /* Enable Host Read */
666#define nEHR 0x0
667#define BDR 0x400 /* Burst DMA Requests */ 643#define BDR 0x400 /* Burst DMA Requests */
668#define nBDR 0x0
669 644
670/* Bit masks for HOST_STATUS */ 645/* Bit masks for HOST_STATUS */
671 646
672#define READY 0x1 /* DMA Ready */ 647#define READY 0x1 /* DMA Ready */
673#define nREADY 0x0
674#define FIFOFULL 0x2 /* FIFO Full */ 648#define FIFOFULL 0x2 /* FIFO Full */
675#define nFIFOFULL 0x0
676#define FIFOEMPTY 0x4 /* FIFO Empty */ 649#define FIFOEMPTY 0x4 /* FIFO Empty */
677#define nFIFOEMPTY 0x0
678#define COMPLETE 0x8 /* DMA Complete */ 650#define COMPLETE 0x8 /* DMA Complete */
679#define nCOMPLETE 0x0
680#define HSHK 0x10 /* Host Handshake */ 651#define HSHK 0x10 /* Host Handshake */
681#define nHSHK 0x0
682#define TIMEOUT 0x20 /* Host Timeout */ 652#define TIMEOUT 0x20 /* Host Timeout */
683#define nTIMEOUT 0x0
684#define HIRQ 0x40 /* Host Interrupt Request */ 653#define HIRQ 0x40 /* Host Interrupt Request */
685#define nHIRQ 0x0
686#define ALLOW_CNFG 0x80 /* Allow New Configuration */ 654#define ALLOW_CNFG 0x80 /* Allow New Configuration */
687#define nALLOW_CNFG 0x0
688#define DMA_DIR 0x100 /* DMA Direction */ 655#define DMA_DIR 0x100 /* DMA Direction */
689#define nDMA_DIR 0x0
690#define BTE 0x200 /* Bus Timeout Enabled */ 656#define BTE 0x200 /* Bus Timeout Enabled */
691#define nBTE 0x0
692 657
693/* Bit masks for HOST_TIMEOUT */ 658/* Bit masks for HOST_TIMEOUT */
694 659
@@ -697,67 +662,42 @@
697/* Bit masks for TIMER_ENABLE1 */ 662/* Bit masks for TIMER_ENABLE1 */
698 663
699#define TIMEN8 0x1 /* Timer 8 Enable */ 664#define TIMEN8 0x1 /* Timer 8 Enable */
700#define nTIMEN8 0x0
701#define TIMEN9 0x2 /* Timer 9 Enable */ 665#define TIMEN9 0x2 /* Timer 9 Enable */
702#define nTIMEN9 0x0
703#define TIMEN10 0x4 /* Timer 10 Enable */ 666#define TIMEN10 0x4 /* Timer 10 Enable */
704#define nTIMEN10 0x0
705 667
706/* Bit masks for TIMER_DISABLE1 */ 668/* Bit masks for TIMER_DISABLE1 */
707 669
708#define TIMDIS8 0x1 /* Timer 8 Disable */ 670#define TIMDIS8 0x1 /* Timer 8 Disable */
709#define nTIMDIS8 0x0
710#define TIMDIS9 0x2 /* Timer 9 Disable */ 671#define TIMDIS9 0x2 /* Timer 9 Disable */
711#define nTIMDIS9 0x0
712#define TIMDIS10 0x4 /* Timer 10 Disable */ 672#define TIMDIS10 0x4 /* Timer 10 Disable */
713#define nTIMDIS10 0x0
714 673
715/* Bit masks for TIMER_STATUS1 */ 674/* Bit masks for TIMER_STATUS1 */
716 675
717#define TIMIL8 0x1 /* Timer 8 Interrupt */ 676#define TIMIL8 0x1 /* Timer 8 Interrupt */
718#define nTIMIL8 0x0
719#define TIMIL9 0x2 /* Timer 9 Interrupt */ 677#define TIMIL9 0x2 /* Timer 9 Interrupt */
720#define nTIMIL9 0x0
721#define TIMIL10 0x4 /* Timer 10 Interrupt */ 678#define TIMIL10 0x4 /* Timer 10 Interrupt */
722#define nTIMIL10 0x0
723#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ 679#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
724#define nTOVF_ERR8 0x0
725#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ 680#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
726#define nTOVF_ERR9 0x0
727#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ 681#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
728#define nTOVF_ERR10 0x0
729#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ 682#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
730#define nTRUN8 0x0
731#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ 683#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
732#define nTRUN9 0x0
733#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ 684#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
734#define nTRUN10 0x0
735 685
736/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ 686/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
737 687
738/* Bit masks for HMDMAx_CONTROL */ 688/* Bit masks for HMDMAx_CONTROL */
739 689
740#define HMDMAEN 0x1 /* Handshake MDMA Enable */ 690#define HMDMAEN 0x1 /* Handshake MDMA Enable */
741#define nHMDMAEN 0x0
742#define REP 0x2 /* Handshake MDMA Request Polarity */ 691#define REP 0x2 /* Handshake MDMA Request Polarity */
743#define nREP 0x0
744#define UTE 0x8 /* Urgency Threshold Enable */ 692#define UTE 0x8 /* Urgency Threshold Enable */
745#define nUTE 0x0
746#define OIE 0x10 /* Overflow Interrupt Enable */ 693#define OIE 0x10 /* Overflow Interrupt Enable */
747#define nOIE 0x0
748#define BDIE 0x20 /* Block Done Interrupt Enable */ 694#define BDIE 0x20 /* Block Done Interrupt Enable */
749#define nBDIE 0x0
750#define MBDI 0x40 /* Mask Block Done Interrupt */ 695#define MBDI 0x40 /* Mask Block Done Interrupt */
751#define nMBDI 0x0
752#define DRQ 0x300 /* Handshake MDMA Request Type */ 696#define DRQ 0x300 /* Handshake MDMA Request Type */
753#define RBC 0x1000 /* Force Reload of BCOUNT */ 697#define RBC 0x1000 /* Force Reload of BCOUNT */
754#define nRBC 0x0
755#define PS 0x2000 /* Pin Status */ 698#define PS 0x2000 /* Pin Status */
756#define nPS 0x0
757#define OI 0x4000 /* Overflow Interrupt Generated */ 699#define OI 0x4000 /* Overflow Interrupt Generated */
758#define nOI 0x0
759#define BDI 0x8000 /* Block Done Interrupt Generated */ 700#define BDI 0x8000 /* Block Done Interrupt Generated */
760#define nBDI 0x0
761 701
762/* ******************************************* */ 702/* ******************************************* */
763/* MULTI BIT MACRO ENUMERATIONS */ 703/* MULTI BIT MACRO ENUMERATIONS */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index d9e3062a9117..8d4214e0807c 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -899,21 +899,13 @@
899/* Bit masks for PIXC_CTL */ 899/* Bit masks for PIXC_CTL */
900 900
901#define PIXC_EN 0x1 /* Pixel Compositor Enable */ 901#define PIXC_EN 0x1 /* Pixel Compositor Enable */
902#define nPIXC_EN 0x0
903#define OVR_A_EN 0x2 /* Overlay A Enable */ 902#define OVR_A_EN 0x2 /* Overlay A Enable */
904#define nOVR_A_EN 0x0
905#define OVR_B_EN 0x4 /* Overlay B Enable */ 903#define OVR_B_EN 0x4 /* Overlay B Enable */
906#define nOVR_B_EN 0x0
907#define IMG_FORM 0x8 /* Image Data Format */ 904#define IMG_FORM 0x8 /* Image Data Format */
908#define nIMG_FORM 0x0
909#define OVR_FORM 0x10 /* Overlay Data Format */ 905#define OVR_FORM 0x10 /* Overlay Data Format */
910#define nOVR_FORM 0x0
911#define OUT_FORM 0x20 /* Output Data Format */ 906#define OUT_FORM 0x20 /* Output Data Format */
912#define nOUT_FORM 0x0
913#define UDS_MOD 0x40 /* Resampling Mode */ 907#define UDS_MOD 0x40 /* Resampling Mode */
914#define nUDS_MOD 0x0
915#define TC_EN 0x80 /* Transparent Color Enable */ 908#define TC_EN 0x80 /* Transparent Color Enable */
916#define nTC_EN 0x0
917#define IMG_STAT 0x300 /* Image FIFO Status */ 909#define IMG_STAT 0x300 /* Image FIFO Status */
918#define OVR_STAT 0xc00 /* Overlay FIFO Status */ 910#define OVR_STAT 0xc00 /* Overlay FIFO Status */
919#define WM_LVL 0x3000 /* FIFO Watermark Level */ 911#define WM_LVL 0x3000 /* FIFO Watermark Level */
@@ -961,13 +953,9 @@
961/* Bit masks for PIXC_INTRSTAT */ 953/* Bit masks for PIXC_INTRSTAT */
962 954
963#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ 955#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
964#define nOVR_INT_EN 0x0
965#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ 956#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
966#define nFRM_INT_EN 0x0
967#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ 957#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
968#define nOVR_INT_STAT 0x0
969#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ 958#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
970#define nFRM_INT_STAT 0x0
971 959
972/* Bit masks for PIXC_RYCON */ 960/* Bit masks for PIXC_RYCON */
973 961
@@ -975,7 +963,6 @@
975#define A12 0xffc00 /* A12 in the Coefficient Matrix */ 963#define A12 0xffc00 /* A12 in the Coefficient Matrix */
976#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ 964#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
977#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ 965#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
978#define nRY_MULT4 0x0
979 966
980/* Bit masks for PIXC_GUCON */ 967/* Bit masks for PIXC_GUCON */
981 968
@@ -983,7 +970,6 @@
983#define A22 0xffc00 /* A22 in the Coefficient Matrix */ 970#define A22 0xffc00 /* A22 in the Coefficient Matrix */
984#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ 971#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
985#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ 972#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
986#define nGU_MULT4 0x0
987 973
988/* Bit masks for PIXC_BVCON */ 974/* Bit masks for PIXC_BVCON */
989 975
@@ -991,7 +977,6 @@
991#define A32 0xffc00 /* A32 in the Coefficient Matrix */ 977#define A32 0xffc00 /* A32 in the Coefficient Matrix */
992#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ 978#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
993#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ 979#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
994#define nBV_MULT4 0x0
995 980
996/* Bit masks for PIXC_CCBIAS */ 981/* Bit masks for PIXC_CCBIAS */
997 982
@@ -1008,48 +993,28 @@
1008/* Bit masks for HOST_CONTROL */ 993/* Bit masks for HOST_CONTROL */
1009 994
1010#define HOST_EN 0x1 /* Host Enable */ 995#define HOST_EN 0x1 /* Host Enable */
1011#define nHOST_EN 0x0
1012#define HOST_END 0x2 /* Host Endianess */ 996#define HOST_END 0x2 /* Host Endianess */
1013#define nHOST_END 0x0
1014#define DATA_SIZE 0x4 /* Data Size */ 997#define DATA_SIZE 0x4 /* Data Size */
1015#define nDATA_SIZE 0x0
1016#define HOST_RST 0x8 /* Host Reset */ 998#define HOST_RST 0x8 /* Host Reset */
1017#define nHOST_RST 0x0
1018#define HRDY_OVR 0x20 /* Host Ready Override */ 999#define HRDY_OVR 0x20 /* Host Ready Override */
1019#define nHRDY_OVR 0x0
1020#define INT_MODE 0x40 /* Interrupt Mode */ 1000#define INT_MODE 0x40 /* Interrupt Mode */
1021#define nINT_MODE 0x0
1022#define BT_EN 0x80 /* Bus Timeout Enable */ 1001#define BT_EN 0x80 /* Bus Timeout Enable */
1023#define nBT_EN 0x0
1024#define EHW 0x100 /* Enable Host Write */ 1002#define EHW 0x100 /* Enable Host Write */
1025#define nEHW 0x0
1026#define EHR 0x200 /* Enable Host Read */ 1003#define EHR 0x200 /* Enable Host Read */
1027#define nEHR 0x0
1028#define BDR 0x400 /* Burst DMA Requests */ 1004#define BDR 0x400 /* Burst DMA Requests */
1029#define nBDR 0x0
1030 1005
1031/* Bit masks for HOST_STATUS */ 1006/* Bit masks for HOST_STATUS */
1032 1007
1033#define READY 0x1 /* DMA Ready */ 1008#define READY 0x1 /* DMA Ready */
1034#define nREADY 0x0
1035#define FIFOFULL 0x2 /* FIFO Full */ 1009#define FIFOFULL 0x2 /* FIFO Full */
1036#define nFIFOFULL 0x0
1037#define FIFOEMPTY 0x4 /* FIFO Empty */ 1010#define FIFOEMPTY 0x4 /* FIFO Empty */
1038#define nFIFOEMPTY 0x0
1039#define COMPLETE 0x8 /* DMA Complete */ 1011#define COMPLETE 0x8 /* DMA Complete */
1040#define nCOMPLETE 0x0
1041#define HSHK 0x10 /* Host Handshake */ 1012#define HSHK 0x10 /* Host Handshake */
1042#define nHSHK 0x0
1043#define TIMEOUT 0x20 /* Host Timeout */ 1013#define TIMEOUT 0x20 /* Host Timeout */
1044#define nTIMEOUT 0x0
1045#define HIRQ 0x40 /* Host Interrupt Request */ 1014#define HIRQ 0x40 /* Host Interrupt Request */
1046#define nHIRQ 0x0
1047#define ALLOW_CNFG 0x80 /* Allow New Configuration */ 1015#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1048#define nALLOW_CNFG 0x0
1049#define DMA_DIR 0x100 /* DMA Direction */ 1016#define DMA_DIR 0x100 /* DMA Direction */
1050#define nDMA_DIR 0x0
1051#define BTE 0x200 /* Bus Timeout Enabled */ 1017#define BTE 0x200 /* Bus Timeout Enabled */
1052#define nBTE 0x0
1053 1018
1054/* Bit masks for HOST_TIMEOUT */ 1019/* Bit masks for HOST_TIMEOUT */
1055 1020
@@ -1058,7 +1023,6 @@
1058/* Bit masks for KPAD_CTL */ 1023/* Bit masks for KPAD_CTL */
1059 1024
1060#define KPAD_EN 0x1 /* Keypad Enable */ 1025#define KPAD_EN 0x1 /* Keypad Enable */
1061#define nKPAD_EN 0x0
1062#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ 1026#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
1063#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ 1027#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
1064#define KPAD_COLEN 0xe000 /* Column Enable Width */ 1028#define KPAD_COLEN 0xe000 /* Column Enable Width */
@@ -1080,29 +1044,21 @@
1080/* Bit masks for KPAD_STAT */ 1044/* Bit masks for KPAD_STAT */
1081 1045
1082#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ 1046#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
1083#define nKPAD_IRQ 0x0
1084#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ 1047#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
1085#define KPAD_PRESSED 0x8 /* Key press current status */ 1048#define KPAD_PRESSED 0x8 /* Key press current status */
1086#define nKPAD_PRESSED 0x0
1087 1049
1088/* Bit masks for KPAD_SOFTEVAL */ 1050/* Bit masks for KPAD_SOFTEVAL */
1089 1051
1090#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 1052#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
1091#define nKPAD_SOFTEVAL_E 0x0
1092 1053
1093/* Bit masks for SDH_COMMAND */ 1054/* Bit masks for SDH_COMMAND */
1094 1055
1095#define CMD_IDX 0x3f /* Command Index */ 1056#define CMD_IDX 0x3f /* Command Index */
1096#define CMD_RSP 0x40 /* Response */ 1057#define CMD_RSP 0x40 /* Response */
1097#define nCMD_RSP 0x0
1098#define CMD_L_RSP 0x80 /* Long Response */ 1058#define CMD_L_RSP 0x80 /* Long Response */
1099#define nCMD_L_RSP 0x0
1100#define CMD_INT_E 0x100 /* Command Interrupt */ 1059#define CMD_INT_E 0x100 /* Command Interrupt */
1101#define nCMD_INT_E 0x0
1102#define CMD_PEND_E 0x200 /* Command Pending */ 1060#define CMD_PEND_E 0x200 /* Command Pending */
1103#define nCMD_PEND_E 0x0
1104#define CMD_E 0x400 /* Command Enable */ 1061#define CMD_E 0x400 /* Command Enable */
1105#define nCMD_E 0x0
1106 1062
1107/* Bit masks for SDH_PWR_CTL */ 1063/* Bit masks for SDH_PWR_CTL */
1108 1064
@@ -1111,21 +1067,15 @@
1111#define TBD 0x3c /* TBD */ 1067#define TBD 0x3c /* TBD */
1112#endif 1068#endif
1113#define SD_CMD_OD 0x40 /* Open Drain Output */ 1069#define SD_CMD_OD 0x40 /* Open Drain Output */
1114#define nSD_CMD_OD 0x0
1115#define ROD_CTL 0x80 /* Rod Control */ 1070#define ROD_CTL 0x80 /* Rod Control */
1116#define nROD_CTL 0x0
1117 1071
1118/* Bit masks for SDH_CLK_CTL */ 1072/* Bit masks for SDH_CLK_CTL */
1119 1073
1120#define CLKDIV 0xff /* MC_CLK Divisor */ 1074#define CLKDIV 0xff /* MC_CLK Divisor */
1121#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ 1075#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
1122#define nCLK_E 0x0
1123#define PWR_SV_E 0x200 /* Power Save Enable */ 1076#define PWR_SV_E 0x200 /* Power Save Enable */
1124#define nPWR_SV_E 0x0
1125#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ 1077#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
1126#define nCLKDIV_BYPASS 0x0
1127#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ 1078#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
1128#define nWIDE_BUS 0x0
1129 1079
1130/* Bit masks for SDH_RESP_CMD */ 1080/* Bit masks for SDH_RESP_CMD */
1131 1081
@@ -1134,133 +1084,74 @@
1134/* Bit masks for SDH_DATA_CTL */ 1084/* Bit masks for SDH_DATA_CTL */
1135 1085
1136#define DTX_E 0x1 /* Data Transfer Enable */ 1086#define DTX_E 0x1 /* Data Transfer Enable */
1137#define nDTX_E 0x0
1138#define DTX_DIR 0x2 /* Data Transfer Direction */ 1087#define DTX_DIR 0x2 /* Data Transfer Direction */
1139#define nDTX_DIR 0x0
1140#define DTX_MODE 0x4 /* Data Transfer Mode */ 1088#define DTX_MODE 0x4 /* Data Transfer Mode */
1141#define nDTX_MODE 0x0
1142#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ 1089#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
1143#define nDTX_DMA_E 0x0
1144#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 1090#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
1145 1091
1146/* Bit masks for SDH_STATUS */ 1092/* Bit masks for SDH_STATUS */
1147 1093
1148#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 1094#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
1149#define nCMD_CRC_FAIL 0x0
1150#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 1095#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
1151#define nDAT_CRC_FAIL 0x0
1152#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 1096#define CMD_TIMEOUT 0x4 /* CMD Time Out */
1153#define nCMD_TIMEOUT 0x0
1154#define DAT_TIMEOUT 0x8 /* Data Time Out */ 1097#define DAT_TIMEOUT 0x8 /* Data Time Out */
1155#define nDAT_TIMEOUT 0x0
1156#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 1098#define TX_UNDERRUN 0x10 /* Transmit Underrun */
1157#define nTX_UNDERRUN 0x0
1158#define RX_OVERRUN 0x20 /* Receive Overrun */ 1099#define RX_OVERRUN 0x20 /* Receive Overrun */
1159#define nRX_OVERRUN 0x0
1160#define CMD_RESP_END 0x40 /* CMD Response End */ 1100#define CMD_RESP_END 0x40 /* CMD Response End */
1161#define nCMD_RESP_END 0x0
1162#define CMD_SENT 0x80 /* CMD Sent */ 1101#define CMD_SENT 0x80 /* CMD Sent */
1163#define nCMD_SENT 0x0
1164#define DAT_END 0x100 /* Data End */ 1102#define DAT_END 0x100 /* Data End */
1165#define nDAT_END 0x0
1166#define START_BIT_ERR 0x200 /* Start Bit Error */ 1103#define START_BIT_ERR 0x200 /* Start Bit Error */
1167#define nSTART_BIT_ERR 0x0
1168#define DAT_BLK_END 0x400 /* Data Block End */ 1104#define DAT_BLK_END 0x400 /* Data Block End */
1169#define nDAT_BLK_END 0x0
1170#define CMD_ACT 0x800 /* CMD Active */ 1105#define CMD_ACT 0x800 /* CMD Active */
1171#define nCMD_ACT 0x0
1172#define TX_ACT 0x1000 /* Transmit Active */ 1106#define TX_ACT 0x1000 /* Transmit Active */
1173#define nTX_ACT 0x0
1174#define RX_ACT 0x2000 /* Receive Active */ 1107#define RX_ACT 0x2000 /* Receive Active */
1175#define nRX_ACT 0x0
1176#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ 1108#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
1177#define nTX_FIFO_STAT 0x0
1178#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ 1109#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
1179#define nRX_FIFO_STAT 0x0
1180#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ 1110#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
1181#define nTX_FIFO_FULL 0x0
1182#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ 1111#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
1183#define nRX_FIFO_FULL 0x0
1184#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ 1112#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
1185#define nTX_FIFO_ZERO 0x0
1186#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ 1113#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
1187#define nRX_DAT_ZERO 0x0
1188#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ 1114#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
1189#define nTX_DAT_RDY 0x0
1190#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ 1115#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
1191#define nRX_FIFO_RDY 0x0
1192 1116
1193/* Bit masks for SDH_STATUS_CLR */ 1117/* Bit masks for SDH_STATUS_CLR */
1194 1118
1195#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ 1119#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
1196#define nCMD_CRC_FAIL_STAT 0x0
1197#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ 1120#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
1198#define nDAT_CRC_FAIL_STAT 0x0
1199#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ 1121#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
1200#define nCMD_TIMEOUT_STAT 0x0
1201#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ 1122#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
1202#define nDAT_TIMEOUT_STAT 0x0
1203#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ 1123#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
1204#define nTX_UNDERRUN_STAT 0x0
1205#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ 1124#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
1206#define nRX_OVERRUN_STAT 0x0
1207#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ 1125#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
1208#define nCMD_RESP_END_STAT 0x0
1209#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ 1126#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
1210#define nCMD_SENT_STAT 0x0
1211#define DAT_END_STAT 0x100 /* Data End Status */ 1127#define DAT_END_STAT 0x100 /* Data End Status */
1212#define nDAT_END_STAT 0x0
1213#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ 1128#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
1214#define nSTART_BIT_ERR_STAT 0x0
1215#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ 1129#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
1216#define nDAT_BLK_END_STAT 0x0
1217 1130
1218/* Bit masks for SDH_MASK0 */ 1131/* Bit masks for SDH_MASK0 */
1219 1132
1220#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ 1133#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
1221#define nCMD_CRC_FAIL_MASK 0x0
1222#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ 1134#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
1223#define nDAT_CRC_FAIL_MASK 0x0
1224#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ 1135#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
1225#define nCMD_TIMEOUT_MASK 0x0
1226#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ 1136#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
1227#define nDAT_TIMEOUT_MASK 0x0
1228#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ 1137#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
1229#define nTX_UNDERRUN_MASK 0x0
1230#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ 1138#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
1231#define nRX_OVERRUN_MASK 0x0
1232#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ 1139#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
1233#define nCMD_RESP_END_MASK 0x0
1234#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ 1140#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
1235#define nCMD_SENT_MASK 0x0
1236#define DAT_END_MASK 0x100 /* Data End Mask */ 1141#define DAT_END_MASK 0x100 /* Data End Mask */
1237#define nDAT_END_MASK 0x0
1238#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ 1142#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
1239#define nSTART_BIT_ERR_MASK 0x0
1240#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ 1143#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
1241#define nDAT_BLK_END_MASK 0x0
1242#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ 1144#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
1243#define nCMD_ACT_MASK 0x0
1244#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ 1145#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
1245#define nTX_ACT_MASK 0x0
1246#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ 1146#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
1247#define nRX_ACT_MASK 0x0
1248#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ 1147#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
1249#define nTX_FIFO_STAT_MASK 0x0
1250#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ 1148#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
1251#define nRX_FIFO_STAT_MASK 0x0
1252#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ 1149#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
1253#define nTX_FIFO_FULL_MASK 0x0
1254#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ 1150#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
1255#define nRX_FIFO_FULL_MASK 0x0
1256#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ 1151#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
1257#define nTX_FIFO_ZERO_MASK 0x0
1258#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ 1152#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
1259#define nRX_DAT_ZERO_MASK 0x0
1260#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ 1153#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
1261#define nTX_DAT_RDY_MASK 0x0
1262#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ 1154#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
1263#define nRX_FIFO_RDY_MASK 0x0
1264 1155
1265/* Bit masks for SDH_FIFO_CNT */ 1156/* Bit masks for SDH_FIFO_CNT */
1266 1157
@@ -1269,73 +1160,47 @@
1269/* Bit masks for SDH_E_STATUS */ 1160/* Bit masks for SDH_E_STATUS */
1270 1161
1271#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ 1162#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
1272#define nSDIO_INT_DET 0x0
1273#define SD_CARD_DET 0x10 /* SD Card Detect */ 1163#define SD_CARD_DET 0x10 /* SD Card Detect */
1274#define nSD_CARD_DET 0x0
1275 1164
1276/* Bit masks for SDH_E_MASK */ 1165/* Bit masks for SDH_E_MASK */
1277 1166
1278#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ 1167#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
1279#define nSDIO_MSK 0x0
1280#define SCD_MSK 0x40 /* Mask Card Detect */ 1168#define SCD_MSK 0x40 /* Mask Card Detect */
1281#define nSCD_MSK 0x0
1282 1169
1283/* Bit masks for SDH_CFG */ 1170/* Bit masks for SDH_CFG */
1284 1171
1285#define CLKS_EN 0x1 /* Clocks Enable */ 1172#define CLKS_EN 0x1 /* Clocks Enable */
1286#define nCLKS_EN 0x0
1287#define SD4E 0x4 /* SDIO 4-Bit Enable */ 1173#define SD4E 0x4 /* SDIO 4-Bit Enable */
1288#define nSD4E 0x0
1289#define MWE 0x8 /* Moving Window Enable */ 1174#define MWE 0x8 /* Moving Window Enable */
1290#define nMWE 0x0
1291#define SD_RST 0x10 /* SDMMC Reset */ 1175#define SD_RST 0x10 /* SDMMC Reset */
1292#define nSD_RST 0x0
1293#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ 1176#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
1294#define nPUP_SDDAT 0x0
1295#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ 1177#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
1296#define nPUP_SDDAT3 0x0
1297#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ 1178#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
1298#define nPD_SDDAT3 0x0
1299 1179
1300/* Bit masks for SDH_RD_WAIT_EN */ 1180/* Bit masks for SDH_RD_WAIT_EN */
1301 1181
1302#define RWR 0x1 /* Read Wait Request */ 1182#define RWR 0x1 /* Read Wait Request */
1303#define nRWR 0x0
1304 1183
1305/* Bit masks for ATAPI_CONTROL */ 1184/* Bit masks for ATAPI_CONTROL */
1306 1185
1307#define PIO_START 0x1 /* Start PIO/Reg Op */ 1186#define PIO_START 0x1 /* Start PIO/Reg Op */
1308#define nPIO_START 0x0
1309#define MULTI_START 0x2 /* Start Multi-DMA Op */ 1187#define MULTI_START 0x2 /* Start Multi-DMA Op */
1310#define nMULTI_START 0x0
1311#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ 1188#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
1312#define nULTRA_START 0x0
1313#define XFER_DIR 0x8 /* Transfer Direction */ 1189#define XFER_DIR 0x8 /* Transfer Direction */
1314#define nXFER_DIR 0x0
1315#define IORDY_EN 0x10 /* IORDY Enable */ 1190#define IORDY_EN 0x10 /* IORDY Enable */
1316#define nIORDY_EN 0x0
1317#define FIFO_FLUSH 0x20 /* Flush FIFOs */ 1191#define FIFO_FLUSH 0x20 /* Flush FIFOs */
1318#define nFIFO_FLUSH 0x0
1319#define SOFT_RST 0x40 /* Soft Reset */ 1192#define SOFT_RST 0x40 /* Soft Reset */
1320#define nSOFT_RST 0x0
1321#define DEV_RST 0x80 /* Device Reset */ 1193#define DEV_RST 0x80 /* Device Reset */
1322#define nDEV_RST 0x0
1323#define TFRCNT_RST 0x100 /* Trans Count Reset */ 1194#define TFRCNT_RST 0x100 /* Trans Count Reset */
1324#define nTFRCNT_RST 0x0
1325#define END_ON_TERM 0x200 /* End/Terminate Select */ 1195#define END_ON_TERM 0x200 /* End/Terminate Select */
1326#define nEND_ON_TERM 0x0
1327#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ 1196#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
1328#define nPIO_USE_DMA 0x0
1329#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ 1197#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
1330 1198
1331/* Bit masks for ATAPI_STATUS */ 1199/* Bit masks for ATAPI_STATUS */
1332 1200
1333#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ 1201#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
1334#define nPIO_XFER_ON 0x0
1335#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ 1202#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
1336#define nMULTI_XFER_ON 0x0
1337#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ 1203#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
1338#define nULTRA_XFER_ON 0x0
1339#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ 1204#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
1340 1205
1341/* Bit masks for ATAPI_DEV_ADDR */ 1206/* Bit masks for ATAPI_DEV_ADDR */
@@ -1345,66 +1210,39 @@
1345/* Bit masks for ATAPI_INT_MASK */ 1210/* Bit masks for ATAPI_INT_MASK */
1346 1211
1347#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ 1212#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
1348#define nATAPI_DEV_INT_MASK 0x0
1349#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ 1213#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
1350#define nPIO_DONE_MASK 0x0
1351#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ 1214#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
1352#define nMULTI_DONE_MASK 0x0
1353#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ 1215#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
1354#define nUDMAIN_DONE_MASK 0x0
1355#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ 1216#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
1356#define nUDMAOUT_DONE_MASK 0x0
1357#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ 1217#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
1358#define nHOST_TERM_XFER_MASK 0x0
1359#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ 1218#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
1360#define nMULTI_TERM_MASK 0x0
1361#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ 1219#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
1362#define nUDMAIN_TERM_MASK 0x0
1363#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ 1220#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
1364#define nUDMAOUT_TERM_MASK 0x0
1365 1221
1366/* Bit masks for ATAPI_INT_STATUS */ 1222/* Bit masks for ATAPI_INT_STATUS */
1367 1223
1368#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ 1224#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
1369#define nATAPI_DEV_INT 0x0
1370#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ 1225#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
1371#define nPIO_DONE_INT 0x0
1372#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ 1226#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
1373#define nMULTI_DONE_INT 0x0
1374#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ 1227#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
1375#define nUDMAIN_DONE_INT 0x0
1376#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ 1228#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
1377#define nUDMAOUT_DONE_INT 0x0
1378#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ 1229#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
1379#define nHOST_TERM_XFER_INT 0x0
1380#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ 1230#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
1381#define nMULTI_TERM_INT 0x0
1382#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ 1231#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
1383#define nUDMAIN_TERM_INT 0x0
1384#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ 1232#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
1385#define nUDMAOUT_TERM_INT 0x0
1386 1233
1387/* Bit masks for ATAPI_LINE_STATUS */ 1234/* Bit masks for ATAPI_LINE_STATUS */
1388 1235
1389#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ 1236#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
1390#define nATAPI_INTR 0x0
1391#define ATAPI_DASP 0x2 /* Device dasp to host line status */ 1237#define ATAPI_DASP 0x2 /* Device dasp to host line status */
1392#define nATAPI_DASP 0x0
1393#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ 1238#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
1394#define nATAPI_CS0N 0x0
1395#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ 1239#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
1396#define nATAPI_CS1N 0x0
1397#define ATAPI_ADDR 0x70 /* ATAPI address line status */ 1240#define ATAPI_ADDR 0x70 /* ATAPI address line status */
1398#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ 1241#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
1399#define nATAPI_DMAREQ 0x0
1400#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ 1242#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
1401#define nATAPI_DMAACKN 0x0
1402#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ 1243#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
1403#define nATAPI_DIOWN 0x0
1404#define ATAPI_DIORN 0x400 /* ATAPI read line status */ 1244#define ATAPI_DIORN 0x400 /* ATAPI read line status */
1405#define nATAPI_DIORN 0x0
1406#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ 1245#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
1407#define nATAPI_IORDY 0x0
1408 1246
1409/* Bit masks for ATAPI_SM_STATE */ 1247/* Bit masks for ATAPI_SM_STATE */
1410 1248
@@ -1416,7 +1254,6 @@
1416/* Bit masks for ATAPI_TERMINATE */ 1254/* Bit masks for ATAPI_TERMINATE */
1417 1255
1418#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ 1256#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
1419#define nATAPI_HOST_TERM 0x0
1420 1257
1421/* Bit masks for ATAPI_REG_TIM_0 */ 1258/* Bit masks for ATAPI_REG_TIM_0 */
1422 1259
@@ -1471,41 +1308,26 @@
1471/* Bit masks for TIMER_ENABLE1 */ 1308/* Bit masks for TIMER_ENABLE1 */
1472 1309
1473#define TIMEN8 0x1 /* Timer 8 Enable */ 1310#define TIMEN8 0x1 /* Timer 8 Enable */
1474#define nTIMEN8 0x0
1475#define TIMEN9 0x2 /* Timer 9 Enable */ 1311#define TIMEN9 0x2 /* Timer 9 Enable */
1476#define nTIMEN9 0x0
1477#define TIMEN10 0x4 /* Timer 10 Enable */ 1312#define TIMEN10 0x4 /* Timer 10 Enable */
1478#define nTIMEN10 0x0
1479 1313
1480/* Bit masks for TIMER_DISABLE1 */ 1314/* Bit masks for TIMER_DISABLE1 */
1481 1315
1482#define TIMDIS8 0x1 /* Timer 8 Disable */ 1316#define TIMDIS8 0x1 /* Timer 8 Disable */
1483#define nTIMDIS8 0x0
1484#define TIMDIS9 0x2 /* Timer 9 Disable */ 1317#define TIMDIS9 0x2 /* Timer 9 Disable */
1485#define nTIMDIS9 0x0
1486#define TIMDIS10 0x4 /* Timer 10 Disable */ 1318#define TIMDIS10 0x4 /* Timer 10 Disable */
1487#define nTIMDIS10 0x0
1488 1319
1489/* Bit masks for TIMER_STATUS1 */ 1320/* Bit masks for TIMER_STATUS1 */
1490 1321
1491#define TIMIL8 0x1 /* Timer 8 Interrupt */ 1322#define TIMIL8 0x1 /* Timer 8 Interrupt */
1492#define nTIMIL8 0x0
1493#define TIMIL9 0x2 /* Timer 9 Interrupt */ 1323#define TIMIL9 0x2 /* Timer 9 Interrupt */
1494#define nTIMIL9 0x0
1495#define TIMIL10 0x4 /* Timer 10 Interrupt */ 1324#define TIMIL10 0x4 /* Timer 10 Interrupt */
1496#define nTIMIL10 0x0
1497#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ 1325#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
1498#define nTOVF_ERR8 0x0
1499#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ 1326#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
1500#define nTOVF_ERR9 0x0
1501#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ 1327#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
1502#define nTOVF_ERR10 0x0
1503#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ 1328#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
1504#define nTRUN8 0x0
1505#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ 1329#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
1506#define nTRUN9 0x0
1507#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ 1330#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
1508#define nTRUN10 0x0
1509 1331
1510/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ 1332/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
1511 1333
@@ -1516,131 +1338,77 @@
1516/* Bit masks for USB_POWER */ 1338/* Bit masks for USB_POWER */
1517 1339
1518#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ 1340#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
1519#define nENABLE_SUSPENDM 0x0
1520#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ 1341#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
1521#define nSUSPEND_MODE 0x0
1522#define RESUME_MODE 0x4 /* DMA Mode */ 1342#define RESUME_MODE 0x4 /* DMA Mode */
1523#define nRESUME_MODE 0x0
1524#define RESET 0x8 /* Reset indicator */ 1343#define RESET 0x8 /* Reset indicator */
1525#define nRESET 0x0
1526#define HS_MODE 0x10 /* High Speed mode indicator */ 1344#define HS_MODE 0x10 /* High Speed mode indicator */
1527#define nHS_MODE 0x0
1528#define HS_ENABLE 0x20 /* high Speed Enable */ 1345#define HS_ENABLE 0x20 /* high Speed Enable */
1529#define nHS_ENABLE 0x0
1530#define SOFT_CONN 0x40 /* Soft connect */ 1346#define SOFT_CONN 0x40 /* Soft connect */
1531#define nSOFT_CONN 0x0
1532#define ISO_UPDATE 0x80 /* Isochronous update */ 1347#define ISO_UPDATE 0x80 /* Isochronous update */
1533#define nISO_UPDATE 0x0
1534 1348
1535/* Bit masks for USB_INTRTX */ 1349/* Bit masks for USB_INTRTX */
1536 1350
1537#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ 1351#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
1538#define nEP0_TX 0x0
1539#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ 1352#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
1540#define nEP1_TX 0x0
1541#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ 1353#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
1542#define nEP2_TX 0x0
1543#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ 1354#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
1544#define nEP3_TX 0x0
1545#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ 1355#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
1546#define nEP4_TX 0x0
1547#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ 1356#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
1548#define nEP5_TX 0x0
1549#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ 1357#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
1550#define nEP6_TX 0x0
1551#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ 1358#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
1552#define nEP7_TX 0x0
1553 1359
1554/* Bit masks for USB_INTRRX */ 1360/* Bit masks for USB_INTRRX */
1555 1361
1556#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ 1362#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
1557#define nEP1_RX 0x0
1558#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ 1363#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
1559#define nEP2_RX 0x0
1560#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ 1364#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
1561#define nEP3_RX 0x0
1562#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ 1365#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
1563#define nEP4_RX 0x0
1564#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ 1366#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
1565#define nEP5_RX 0x0
1566#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ 1367#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
1567#define nEP6_RX 0x0
1568#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ 1368#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
1569#define nEP7_RX 0x0
1570 1369
1571/* Bit masks for USB_INTRTXE */ 1370/* Bit masks for USB_INTRTXE */
1572 1371
1573#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ 1372#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
1574#define nEP0_TX_E 0x0
1575#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ 1373#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
1576#define nEP1_TX_E 0x0
1577#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ 1374#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
1578#define nEP2_TX_E 0x0
1579#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ 1375#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
1580#define nEP3_TX_E 0x0
1581#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ 1376#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
1582#define nEP4_TX_E 0x0
1583#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ 1377#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
1584#define nEP5_TX_E 0x0
1585#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ 1378#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
1586#define nEP6_TX_E 0x0
1587#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ 1379#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
1588#define nEP7_TX_E 0x0
1589 1380
1590/* Bit masks for USB_INTRRXE */ 1381/* Bit masks for USB_INTRRXE */
1591 1382
1592#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ 1383#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1593#define nEP1_RX_E 0x0
1594#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ 1384#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1595#define nEP2_RX_E 0x0
1596#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ 1385#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1597#define nEP3_RX_E 0x0
1598#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ 1386#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1599#define nEP4_RX_E 0x0
1600#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ 1387#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1601#define nEP5_RX_E 0x0
1602#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ 1388#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1603#define nEP6_RX_E 0x0
1604#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ 1389#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1605#define nEP7_RX_E 0x0
1606 1390
1607/* Bit masks for USB_INTRUSB */ 1391/* Bit masks for USB_INTRUSB */
1608 1392
1609#define SUSPEND_B 0x1 /* Suspend indicator */ 1393#define SUSPEND_B 0x1 /* Suspend indicator */
1610#define nSUSPEND_B 0x0
1611#define RESUME_B 0x2 /* Resume indicator */ 1394#define RESUME_B 0x2 /* Resume indicator */
1612#define nRESUME_B 0x0
1613#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ 1395#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1614#define nRESET_OR_BABLE_B 0x0
1615#define SOF_B 0x8 /* Start of frame */ 1396#define SOF_B 0x8 /* Start of frame */
1616#define nSOF_B 0x0
1617#define CONN_B 0x10 /* Connection indicator */ 1397#define CONN_B 0x10 /* Connection indicator */
1618#define nCONN_B 0x0
1619#define DISCON_B 0x20 /* Disconnect indicator */ 1398#define DISCON_B 0x20 /* Disconnect indicator */
1620#define nDISCON_B 0x0
1621#define SESSION_REQ_B 0x40 /* Session Request */ 1399#define SESSION_REQ_B 0x40 /* Session Request */
1622#define nSESSION_REQ_B 0x0
1623#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ 1400#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1624#define nVBUS_ERROR_B 0x0
1625 1401
1626/* Bit masks for USB_INTRUSBE */ 1402/* Bit masks for USB_INTRUSBE */
1627 1403
1628#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ 1404#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1629#define nSUSPEND_BE 0x0
1630#define RESUME_BE 0x2 /* Resume indicator int enable */ 1405#define RESUME_BE 0x2 /* Resume indicator int enable */
1631#define nRESUME_BE 0x0
1632#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ 1406#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1633#define nRESET_OR_BABLE_BE 0x0
1634#define SOF_BE 0x8 /* Start of frame int enable */ 1407#define SOF_BE 0x8 /* Start of frame int enable */
1635#define nSOF_BE 0x0
1636#define CONN_BE 0x10 /* Connection indicator int enable */ 1408#define CONN_BE 0x10 /* Connection indicator int enable */
1637#define nCONN_BE 0x0
1638#define DISCON_BE 0x20 /* Disconnect indicator int enable */ 1409#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1639#define nDISCON_BE 0x0
1640#define SESSION_REQ_BE 0x40 /* Session Request int enable */ 1410#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1641#define nSESSION_REQ_BE 0x0
1642#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ 1411#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1643#define nVBUS_ERROR_BE 0x0
1644 1412
1645/* Bit masks for USB_FRAME */ 1413/* Bit masks for USB_FRAME */
1646 1414
@@ -1653,117 +1421,67 @@
1653/* Bit masks for USB_GLOBAL_CTL */ 1421/* Bit masks for USB_GLOBAL_CTL */
1654 1422
1655#define GLOBAL_ENA 0x1 /* enables USB module */ 1423#define GLOBAL_ENA 0x1 /* enables USB module */
1656#define nGLOBAL_ENA 0x0
1657#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ 1424#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1658#define nEP1_TX_ENA 0x0
1659#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ 1425#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1660#define nEP2_TX_ENA 0x0
1661#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ 1426#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1662#define nEP3_TX_ENA 0x0
1663#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ 1427#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1664#define nEP4_TX_ENA 0x0
1665#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ 1428#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1666#define nEP5_TX_ENA 0x0
1667#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ 1429#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1668#define nEP6_TX_ENA 0x0
1669#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ 1430#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1670#define nEP7_TX_ENA 0x0
1671#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ 1431#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1672#define nEP1_RX_ENA 0x0
1673#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ 1432#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1674#define nEP2_RX_ENA 0x0
1675#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ 1433#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1676#define nEP3_RX_ENA 0x0
1677#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ 1434#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1678#define nEP4_RX_ENA 0x0
1679#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ 1435#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1680#define nEP5_RX_ENA 0x0
1681#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ 1436#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1682#define nEP6_RX_ENA 0x0
1683#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ 1437#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1684#define nEP7_RX_ENA 0x0
1685 1438
1686/* Bit masks for USB_OTG_DEV_CTL */ 1439/* Bit masks for USB_OTG_DEV_CTL */
1687 1440
1688#define SESSION 0x1 /* session indicator */ 1441#define SESSION 0x1 /* session indicator */
1689#define nSESSION 0x0
1690#define HOST_REQ 0x2 /* Host negotiation request */ 1442#define HOST_REQ 0x2 /* Host negotiation request */
1691#define nHOST_REQ 0x0
1692#define HOST_MODE 0x4 /* indicates USBDRC is a host */ 1443#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1693#define nHOST_MODE 0x0
1694#define VBUS0 0x8 /* Vbus level indicator[0] */ 1444#define VBUS0 0x8 /* Vbus level indicator[0] */
1695#define nVBUS0 0x0
1696#define VBUS1 0x10 /* Vbus level indicator[1] */ 1445#define VBUS1 0x10 /* Vbus level indicator[1] */
1697#define nVBUS1 0x0
1698#define LSDEV 0x20 /* Low-speed indicator */ 1446#define LSDEV 0x20 /* Low-speed indicator */
1699#define nLSDEV 0x0
1700#define FSDEV 0x40 /* Full or High-speed indicator */ 1447#define FSDEV 0x40 /* Full or High-speed indicator */
1701#define nFSDEV 0x0
1702#define B_DEVICE 0x80 /* A' or 'B' device indicator */ 1448#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1703#define nB_DEVICE 0x0
1704 1449
1705/* Bit masks for USB_OTG_VBUS_IRQ */ 1450/* Bit masks for USB_OTG_VBUS_IRQ */
1706 1451
1707#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ 1452#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1708#define nDRIVE_VBUS_ON 0x0
1709#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ 1453#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1710#define nDRIVE_VBUS_OFF 0x0
1711#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ 1454#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1712#define nCHRG_VBUS_START 0x0
1713#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ 1455#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1714#define nCHRG_VBUS_END 0x0
1715#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ 1456#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1716#define nDISCHRG_VBUS_START 0x0
1717#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ 1457#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1718#define nDISCHRG_VBUS_END 0x0
1719 1458
1720/* Bit masks for USB_OTG_VBUS_MASK */ 1459/* Bit masks for USB_OTG_VBUS_MASK */
1721 1460
1722#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ 1461#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1723#define nDRIVE_VBUS_ON_ENA 0x0
1724#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ 1462#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1725#define nDRIVE_VBUS_OFF_ENA 0x0
1726#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ 1463#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1727#define nCHRG_VBUS_START_ENA 0x0
1728#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ 1464#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1729#define nCHRG_VBUS_END_ENA 0x0
1730#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ 1465#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1731#define nDISCHRG_VBUS_START_ENA 0x0
1732#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ 1466#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1733#define nDISCHRG_VBUS_END_ENA 0x0
1734 1467
1735/* Bit masks for USB_CSR0 */ 1468/* Bit masks for USB_CSR0 */
1736 1469
1737#define RXPKTRDY 0x1 /* data packet receive indicator */ 1470#define RXPKTRDY 0x1 /* data packet receive indicator */
1738#define nRXPKTRDY 0x0
1739#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ 1471#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1740#define nTXPKTRDY 0x0
1741#define STALL_SENT 0x4 /* STALL handshake sent */ 1472#define STALL_SENT 0x4 /* STALL handshake sent */
1742#define nSTALL_SENT 0x0
1743#define DATAEND 0x8 /* Data end indicator */ 1473#define DATAEND 0x8 /* Data end indicator */
1744#define nDATAEND 0x0
1745#define SETUPEND 0x10 /* Setup end */ 1474#define SETUPEND 0x10 /* Setup end */
1746#define nSETUPEND 0x0
1747#define SENDSTALL 0x20 /* Send STALL handshake */ 1475#define SENDSTALL 0x20 /* Send STALL handshake */
1748#define nSENDSTALL 0x0
1749#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ 1476#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1750#define nSERVICED_RXPKTRDY 0x0
1751#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ 1477#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1752#define nSERVICED_SETUPEND 0x0
1753#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ 1478#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1754#define nFLUSHFIFO 0x0
1755#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ 1479#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1756#define nSTALL_RECEIVED_H 0x0
1757#define SETUPPKT_H 0x8 /* send Setup token host mode */ 1480#define SETUPPKT_H 0x8 /* send Setup token host mode */
1758#define nSETUPPKT_H 0x0
1759#define ERROR_H 0x10 /* timeout error indicator host mode */ 1481#define ERROR_H 0x10 /* timeout error indicator host mode */
1760#define nERROR_H 0x0
1761#define REQPKT_H 0x20 /* Request an IN transaction host mode */ 1482#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1762#define nREQPKT_H 0x0
1763#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ 1483#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1764#define nSTATUSPKT_H 0x0
1765#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ 1484#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1766#define nNAK_TIMEOUT_H 0x0
1767 1485
1768/* Bit masks for USB_COUNT0 */ 1486/* Bit masks for USB_COUNT0 */
1769 1487
@@ -1784,37 +1502,21 @@
1784/* Bit masks for USB_TXCSR */ 1502/* Bit masks for USB_TXCSR */
1785 1503
1786#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ 1504#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1787#define nTXPKTRDY_T 0x0
1788#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ 1505#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1789#define nFIFO_NOT_EMPTY_T 0x0
1790#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ 1506#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1791#define nUNDERRUN_T 0x0
1792#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ 1507#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1793#define nFLUSHFIFO_T 0x0
1794#define STALL_SEND_T 0x10 /* issue a Stall handshake */ 1508#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1795#define nSTALL_SEND_T 0x0
1796#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ 1509#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1797#define nSTALL_SENT_T 0x0
1798#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ 1510#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1799#define nCLEAR_DATATOGGLE_T 0x0
1800#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ 1511#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1801#define nINCOMPTX_T 0x0
1802#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ 1512#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1803#define nDMAREQMODE_T 0x0
1804#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ 1513#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1805#define nFORCE_DATATOGGLE_T 0x0
1806#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ 1514#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1807#define nDMAREQ_ENA_T 0x0
1808#define ISO_T 0x4000 /* enable Isochronous transfers */ 1515#define ISO_T 0x4000 /* enable Isochronous transfers */
1809#define nISO_T 0x0
1810#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ 1516#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1811#define nAUTOSET_T 0x0
1812#define ERROR_TH 0x4 /* error condition host mode */ 1517#define ERROR_TH 0x4 /* error condition host mode */
1813#define nERROR_TH 0x0
1814#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ 1518#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1815#define nSTALL_RECEIVED_TH 0x0
1816#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ 1519#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1817#define nNAK_TIMEOUT_TH 0x0
1818 1520
1819/* Bit masks for USB_TXCOUNT */ 1521/* Bit masks for USB_TXCOUNT */
1820 1522
@@ -1823,45 +1525,25 @@
1823/* Bit masks for USB_RXCSR */ 1525/* Bit masks for USB_RXCSR */
1824 1526
1825#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ 1527#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1826#define nRXPKTRDY_R 0x0
1827#define FIFO_FULL_R 0x2 /* FIFO not empty */ 1528#define FIFO_FULL_R 0x2 /* FIFO not empty */
1828#define nFIFO_FULL_R 0x0
1829#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ 1529#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1830#define nOVERRUN_R 0x0
1831#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ 1530#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1832#define nDATAERROR_R 0x0
1833#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ 1531#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1834#define nFLUSHFIFO_R 0x0
1835#define STALL_SEND_R 0x20 /* issue a Stall handshake */ 1532#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1836#define nSTALL_SEND_R 0x0
1837#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ 1533#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1838#define nSTALL_SENT_R 0x0
1839#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ 1534#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1840#define nCLEAR_DATATOGGLE_R 0x0
1841#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ 1535#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1842#define nINCOMPRX_R 0x0
1843#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ 1536#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1844#define nDMAREQMODE_R 0x0
1845#define DISNYET_R 0x1000 /* disable Nyet handshakes */ 1537#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1846#define nDISNYET_R 0x0
1847#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ 1538#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1848#define nDMAREQ_ENA_R 0x0
1849#define ISO_R 0x4000 /* enable Isochronous transfers */ 1539#define ISO_R 0x4000 /* enable Isochronous transfers */
1850#define nISO_R 0x0
1851#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ 1540#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1852#define nAUTOCLEAR_R 0x0
1853#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ 1541#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1854#define nERROR_RH 0x0
1855#define REQPKT_RH 0x20 /* request an IN transaction host mode */ 1542#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1856#define nREQPKT_RH 0x0
1857#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ 1543#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1858#define nSTALL_RECEIVED_RH 0x0
1859#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ 1544#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1860#define nINCOMPRX_RH 0x0
1861#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ 1545#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1862#define nDMAREQMODE_RH 0x0
1863#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ 1546#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1864#define nAUTOREQ_RH 0x0
1865 1547
1866/* Bit masks for USB_RXCOUNT */ 1548/* Bit masks for USB_RXCOUNT */
1867 1549
@@ -1888,35 +1570,22 @@
1888/* Bit masks for USB_DMA_INTERRUPT */ 1570/* Bit masks for USB_DMA_INTERRUPT */
1889 1571
1890#define DMA0_INT 0x1 /* DMA0 pending interrupt */ 1572#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1891#define nDMA0_INT 0x0
1892#define DMA1_INT 0x2 /* DMA1 pending interrupt */ 1573#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1893#define nDMA1_INT 0x0
1894#define DMA2_INT 0x4 /* DMA2 pending interrupt */ 1574#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1895#define nDMA2_INT 0x0
1896#define DMA3_INT 0x8 /* DMA3 pending interrupt */ 1575#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1897#define nDMA3_INT 0x0
1898#define DMA4_INT 0x10 /* DMA4 pending interrupt */ 1576#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1899#define nDMA4_INT 0x0
1900#define DMA5_INT 0x20 /* DMA5 pending interrupt */ 1577#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1901#define nDMA5_INT 0x0
1902#define DMA6_INT 0x40 /* DMA6 pending interrupt */ 1578#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1903#define nDMA6_INT 0x0
1904#define DMA7_INT 0x80 /* DMA7 pending interrupt */ 1579#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1905#define nDMA7_INT 0x0
1906 1580
1907/* Bit masks for USB_DMAxCONTROL */ 1581/* Bit masks for USB_DMAxCONTROL */
1908 1582
1909#define DMA_ENA 0x1 /* DMA enable */ 1583#define DMA_ENA 0x1 /* DMA enable */
1910#define nDMA_ENA 0x0
1911#define DIRECTION 0x2 /* direction of DMA transfer */ 1584#define DIRECTION 0x2 /* direction of DMA transfer */
1912#define nDIRECTION 0x0
1913#define MODE 0x4 /* DMA Bus error */ 1585#define MODE 0x4 /* DMA Bus error */
1914#define nMODE 0x0
1915#define INT_ENA 0x8 /* Interrupt enable */ 1586#define INT_ENA 0x8 /* Interrupt enable */
1916#define nINT_ENA 0x0
1917#define EPNUM 0xf0 /* EP number */ 1587#define EPNUM 0xf0 /* EP number */
1918#define BUSERROR 0x100 /* DMA Bus error */ 1588#define BUSERROR 0x100 /* DMA Bus error */
1919#define nBUSERROR 0x0
1920 1589
1921/* Bit masks for USB_DMAxADDRHIGH */ 1590/* Bit masks for USB_DMAxADDRHIGH */
1922 1591
@@ -1937,26 +1606,16 @@
1937/* Bit masks for HMDMAx_CONTROL */ 1606/* Bit masks for HMDMAx_CONTROL */
1938 1607
1939#define HMDMAEN 0x1 /* Handshake MDMA Enable */ 1608#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1940#define nHMDMAEN 0x0
1941#define REP 0x2 /* Handshake MDMA Request Polarity */ 1609#define REP 0x2 /* Handshake MDMA Request Polarity */
1942#define nREP 0x0
1943#define UTE 0x8 /* Urgency Threshold Enable */ 1610#define UTE 0x8 /* Urgency Threshold Enable */
1944#define nUTE 0x0
1945#define OIE 0x10 /* Overflow Interrupt Enable */ 1611#define OIE 0x10 /* Overflow Interrupt Enable */
1946#define nOIE 0x0
1947#define BDIE 0x20 /* Block Done Interrupt Enable */ 1612#define BDIE 0x20 /* Block Done Interrupt Enable */
1948#define nBDIE 0x0
1949#define MBDI 0x40 /* Mask Block Done Interrupt */ 1613#define MBDI 0x40 /* Mask Block Done Interrupt */
1950#define nMBDI 0x0
1951#define DRQ 0x300 /* Handshake MDMA Request Type */ 1614#define DRQ 0x300 /* Handshake MDMA Request Type */
1952#define RBC 0x1000 /* Force Reload of BCOUNT */ 1615#define RBC 0x1000 /* Force Reload of BCOUNT */
1953#define nRBC 0x0
1954#define PS 0x2000 /* Pin Status */ 1616#define PS 0x2000 /* Pin Status */
1955#define nPS 0x0
1956#define OI 0x4000 /* Overflow Interrupt Generated */ 1617#define OI 0x4000 /* Overflow Interrupt Generated */
1957#define nOI 0x0
1958#define BDI 0x8000 /* Block Done Interrupt Generated */ 1618#define BDI 0x8000 /* Block Done Interrupt Generated */
1959#define nBDI 0x0
1960 1619
1961/* ******************************************* */ 1620/* ******************************************* */
1962/* MULTI BIT MACRO ENUMERATIONS */ 1621/* MULTI BIT MACRO ENUMERATIONS */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
index b1cc1c073b41..c2f4734da48d 100644
--- a/include/asm-blackfin/mach-bf548/defBF549.h
+++ b/include/asm-blackfin/mach-bf548/defBF549.h
@@ -1070,21 +1070,13 @@
1070/* Bit masks for PIXC_CTL */ 1070/* Bit masks for PIXC_CTL */
1071 1071
1072#define PIXC_EN 0x1 /* Pixel Compositor Enable */ 1072#define PIXC_EN 0x1 /* Pixel Compositor Enable */
1073#define nPIXC_EN 0x0
1074#define OVR_A_EN 0x2 /* Overlay A Enable */ 1073#define OVR_A_EN 0x2 /* Overlay A Enable */
1075#define nOVR_A_EN 0x0
1076#define OVR_B_EN 0x4 /* Overlay B Enable */ 1074#define OVR_B_EN 0x4 /* Overlay B Enable */
1077#define nOVR_B_EN 0x0
1078#define IMG_FORM 0x8 /* Image Data Format */ 1075#define IMG_FORM 0x8 /* Image Data Format */
1079#define nIMG_FORM 0x0
1080#define OVR_FORM 0x10 /* Overlay Data Format */ 1076#define OVR_FORM 0x10 /* Overlay Data Format */
1081#define nOVR_FORM 0x0
1082#define OUT_FORM 0x20 /* Output Data Format */ 1077#define OUT_FORM 0x20 /* Output Data Format */
1083#define nOUT_FORM 0x0
1084#define UDS_MOD 0x40 /* Resampling Mode */ 1078#define UDS_MOD 0x40 /* Resampling Mode */
1085#define nUDS_MOD 0x0
1086#define TC_EN 0x80 /* Transparent Color Enable */ 1079#define TC_EN 0x80 /* Transparent Color Enable */
1087#define nTC_EN 0x0
1088#define IMG_STAT 0x300 /* Image FIFO Status */ 1080#define IMG_STAT 0x300 /* Image FIFO Status */
1089#define OVR_STAT 0xc00 /* Overlay FIFO Status */ 1081#define OVR_STAT 0xc00 /* Overlay FIFO Status */
1090#define WM_LVL 0x3000 /* FIFO Watermark Level */ 1082#define WM_LVL 0x3000 /* FIFO Watermark Level */
@@ -1132,13 +1124,9 @@
1132/* Bit masks for PIXC_INTRSTAT */ 1124/* Bit masks for PIXC_INTRSTAT */
1133 1125
1134#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */ 1126#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
1135#define nOVR_INT_EN 0x0
1136#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */ 1127#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
1137#define nFRM_INT_EN 0x0
1138#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */ 1128#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
1139#define nOVR_INT_STAT 0x0
1140#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */ 1129#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
1141#define nFRM_INT_STAT 0x0
1142 1130
1143/* Bit masks for PIXC_RYCON */ 1131/* Bit masks for PIXC_RYCON */
1144 1132
@@ -1146,7 +1134,6 @@
1146#define A12 0xffc00 /* A12 in the Coefficient Matrix */ 1134#define A12 0xffc00 /* A12 in the Coefficient Matrix */
1147#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */ 1135#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
1148#define RY_MULT4 0x40000000 /* Multiply Row by 4 */ 1136#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
1149#define nRY_MULT4 0x0
1150 1137
1151/* Bit masks for PIXC_GUCON */ 1138/* Bit masks for PIXC_GUCON */
1152 1139
@@ -1154,7 +1141,6 @@
1154#define A22 0xffc00 /* A22 in the Coefficient Matrix */ 1141#define A22 0xffc00 /* A22 in the Coefficient Matrix */
1155#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */ 1142#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
1156#define GU_MULT4 0x40000000 /* Multiply Row by 4 */ 1143#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
1157#define nGU_MULT4 0x0
1158 1144
1159/* Bit masks for PIXC_BVCON */ 1145/* Bit masks for PIXC_BVCON */
1160 1146
@@ -1162,7 +1148,6 @@
1162#define A32 0xffc00 /* A32 in the Coefficient Matrix */ 1148#define A32 0xffc00 /* A32 in the Coefficient Matrix */
1163#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */ 1149#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
1164#define BV_MULT4 0x40000000 /* Multiply Row by 4 */ 1150#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
1165#define nBV_MULT4 0x0
1166 1151
1167/* Bit masks for PIXC_CCBIAS */ 1152/* Bit masks for PIXC_CCBIAS */
1168 1153
@@ -1179,48 +1164,28 @@
1179/* Bit masks for HOST_CONTROL */ 1164/* Bit masks for HOST_CONTROL */
1180 1165
1181#define HOST_EN 0x1 /* Host Enable */ 1166#define HOST_EN 0x1 /* Host Enable */
1182#define nHOST_EN 0x0
1183#define HOST_END 0x2 /* Host Endianess */ 1167#define HOST_END 0x2 /* Host Endianess */
1184#define nHOST_END 0x0
1185#define DATA_SIZE 0x4 /* Data Size */ 1168#define DATA_SIZE 0x4 /* Data Size */
1186#define nDATA_SIZE 0x0
1187#define HOST_RST 0x8 /* Host Reset */ 1169#define HOST_RST 0x8 /* Host Reset */
1188#define nHOST_RST 0x0
1189#define HRDY_OVR 0x20 /* Host Ready Override */ 1170#define HRDY_OVR 0x20 /* Host Ready Override */
1190#define nHRDY_OVR 0x0
1191#define INT_MODE 0x40 /* Interrupt Mode */ 1171#define INT_MODE 0x40 /* Interrupt Mode */
1192#define nINT_MODE 0x0
1193#define BT_EN 0x80 /* Bus Timeout Enable */ 1172#define BT_EN 0x80 /* Bus Timeout Enable */
1194#define nBT_EN 0x0
1195#define EHW 0x100 /* Enable Host Write */ 1173#define EHW 0x100 /* Enable Host Write */
1196#define nEHW 0x0
1197#define EHR 0x200 /* Enable Host Read */ 1174#define EHR 0x200 /* Enable Host Read */
1198#define nEHR 0x0
1199#define BDR 0x400 /* Burst DMA Requests */ 1175#define BDR 0x400 /* Burst DMA Requests */
1200#define nBDR 0x0
1201 1176
1202/* Bit masks for HOST_STATUS */ 1177/* Bit masks for HOST_STATUS */
1203 1178
1204#define READY 0x1 /* DMA Ready */ 1179#define READY 0x1 /* DMA Ready */
1205#define nREADY 0x0
1206#define FIFOFULL 0x2 /* FIFO Full */ 1180#define FIFOFULL 0x2 /* FIFO Full */
1207#define nFIFOFULL 0x0
1208#define FIFOEMPTY 0x4 /* FIFO Empty */ 1181#define FIFOEMPTY 0x4 /* FIFO Empty */
1209#define nFIFOEMPTY 0x0 1182#define DMA_COMPLETE 0x8 /* DMA Complete */
1210#define COMPLETE 0x8 /* DMA Complete */
1211#define nCOMPLETE 0x0
1212#define HSHK 0x10 /* Host Handshake */ 1183#define HSHK 0x10 /* Host Handshake */
1213#define nHSHK 0x0
1214#define TIMEOUT 0x20 /* Host Timeout */ 1184#define TIMEOUT 0x20 /* Host Timeout */
1215#define nTIMEOUT 0x0
1216#define HIRQ 0x40 /* Host Interrupt Request */ 1185#define HIRQ 0x40 /* Host Interrupt Request */
1217#define nHIRQ 0x0
1218#define ALLOW_CNFG 0x80 /* Allow New Configuration */ 1186#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1219#define nALLOW_CNFG 0x0
1220#define DMA_DIR 0x100 /* DMA Direction */ 1187#define DMA_DIR 0x100 /* DMA Direction */
1221#define nDMA_DIR 0x0
1222#define BTE 0x200 /* Bus Timeout Enabled */ 1188#define BTE 0x200 /* Bus Timeout Enabled */
1223#define nBTE 0x0
1224 1189
1225/* Bit masks for HOST_TIMEOUT */ 1190/* Bit masks for HOST_TIMEOUT */
1226 1191
@@ -1229,71 +1194,41 @@
1229/* Bit masks for MXVR_CONFIG */ 1194/* Bit masks for MXVR_CONFIG */
1230 1195
1231#define MXVREN 0x1 /* MXVR Enable */ 1196#define MXVREN 0x1 /* MXVR Enable */
1232#define nMXVREN 0x0
1233#define MMSM 0x2 /* MXVR Master/Slave Mode Select */ 1197#define MMSM 0x2 /* MXVR Master/Slave Mode Select */
1234#define nMMSM 0x0
1235#define ACTIVE 0x4 /* Active Mode */ 1198#define ACTIVE 0x4 /* Active Mode */
1236#define nACTIVE 0x0
1237#define SDELAY 0x8 /* Synchronous Data Delay */ 1199#define SDELAY 0x8 /* Synchronous Data Delay */
1238#define nSDELAY 0x0
1239#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */ 1200#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */
1240#define nNCMRXEN 0x0
1241#define RWRRXEN 0x20 /* Remote Write Receive Enable */ 1201#define RWRRXEN 0x20 /* Remote Write Receive Enable */
1242#define nRWRRXEN 0x0
1243#define MTXEN 0x40 /* MXVR Transmit Data Enable */ 1202#define MTXEN 0x40 /* MXVR Transmit Data Enable */
1244#define nMTXEN 0x0
1245#define MTXONB 0x80 /* MXVR Phy Transmitter On */ 1203#define MTXONB 0x80 /* MXVR Phy Transmitter On */
1246#define nMTXONB 0x0
1247#define EPARITY 0x100 /* Even Parity Select */ 1204#define EPARITY 0x100 /* Even Parity Select */
1248#define nEPARITY 0x0
1249#define MSB 0x1e00 /* Master Synchronous Boundary */ 1205#define MSB 0x1e00 /* Master Synchronous Boundary */
1250#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */ 1206#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */
1251#define nAPRXEN 0x0
1252#define WAKEUP 0x4000 /* Wake-Up */ 1207#define WAKEUP 0x4000 /* Wake-Up */
1253#define nWAKEUP 0x0
1254#define LMECH 0x8000 /* Lock Mechanism Select */ 1208#define LMECH 0x8000 /* Lock Mechanism Select */
1255#define nLMECH 0x0
1256 1209
1257/* Bit masks for MXVR_STATE_0 */ 1210/* Bit masks for MXVR_STATE_0 */
1258 1211
1259#define NACT 0x1 /* Network Activity */ 1212#define NACT 0x1 /* Network Activity */
1260#define nNACT 0x0
1261#define SBLOCK 0x2 /* Super Block Lock */ 1213#define SBLOCK 0x2 /* Super Block Lock */
1262#define nSBLOCK 0x0
1263#define FMPLLST 0xc /* Frequency Multiply PLL SM State */ 1214#define FMPLLST 0xc /* Frequency Multiply PLL SM State */
1264#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */ 1215#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */
1265#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */ 1216#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */
1266#define nAPBSY 0x0
1267#define APARB 0x200 /* Asynchronous Packet Arbitrating */ 1217#define APARB 0x200 /* Asynchronous Packet Arbitrating */
1268#define nAPARB 0x0
1269#define APTX 0x400 /* Asynchronous Packet Transmitting */ 1218#define APTX 0x400 /* Asynchronous Packet Transmitting */
1270#define nAPTX 0x0
1271#define APRX 0x800 /* Receiving Asynchronous Packet */ 1219#define APRX 0x800 /* Receiving Asynchronous Packet */
1272#define nAPRX 0x0
1273#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */ 1220#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */
1274#define nCMBSY 0x0
1275#define CMARB 0x2000 /* Control Message Arbitrating */ 1221#define CMARB 0x2000 /* Control Message Arbitrating */
1276#define nCMARB 0x0
1277#define CMTX 0x4000 /* Control Message Transmitting */ 1222#define CMTX 0x4000 /* Control Message Transmitting */
1278#define nCMTX 0x0
1279#define CMRX 0x8000 /* Receiving Control Message */ 1223#define CMRX 0x8000 /* Receiving Control Message */
1280#define nCMRX 0x0
1281#define MRXONB 0x10000 /* MRXONB Pin State */ 1224#define MRXONB 0x10000 /* MRXONB Pin State */
1282#define nMRXONB 0x0
1283#define RGSIP 0x20000 /* Remote Get Source In Progress */ 1225#define RGSIP 0x20000 /* Remote Get Source In Progress */
1284#define nRGSIP 0x0
1285#define DALIP 0x40000 /* Resource Deallocate In Progress */ 1226#define DALIP 0x40000 /* Resource Deallocate In Progress */
1286#define nDALIP 0x0
1287#define ALIP 0x80000 /* Resource Allocate In Progress */ 1227#define ALIP 0x80000 /* Resource Allocate In Progress */
1288#define nALIP 0x0
1289#define RRDIP 0x100000 /* Remote Read In Progress */ 1228#define RRDIP 0x100000 /* Remote Read In Progress */
1290#define nRRDIP 0x0
1291#define RWRIP 0x200000 /* Remote Write In Progress */ 1229#define RWRIP 0x200000 /* Remote Write In Progress */
1292#define nRWRIP 0x0
1293#define FLOCK 0x400000 /* Frame Lock */ 1230#define FLOCK 0x400000 /* Frame Lock */
1294#define nFLOCK 0x0
1295#define BLOCK 0x800000 /* Block Lock */ 1231#define BLOCK 0x800000 /* Block Lock */
1296#define nBLOCK 0x0
1297#define RSB 0xf000000 /* Received Synchronous Boundary */ 1232#define RSB 0xf000000 /* Received Synchronous Boundary */
1298#define DERRNUM 0xf0000000 /* DMA Error Channel Number */ 1233#define DERRNUM 0xf0000000 /* DMA Error Channel Number */
1299 1234
@@ -1302,535 +1237,343 @@
1302#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */ 1237#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */
1303#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */ 1238#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */
1304#define APCONT 0x100 /* Asynchronous Packet Continuation */ 1239#define APCONT 0x100 /* Asynchronous Packet Continuation */
1305#define nAPCONT 0x0
1306#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */ 1240#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */
1307#define DMAACTIVE0 0x10000 /* DMA0 Active */ 1241#define DMAACTIVE0 0x10000 /* DMA0 Active */
1308#define nDMAACTIVE0 0x0
1309#define DMAACTIVE1 0x20000 /* DMA1 Active */ 1242#define DMAACTIVE1 0x20000 /* DMA1 Active */
1310#define nDMAACTIVE1 0x0
1311#define DMAACTIVE2 0x40000 /* DMA2 Active */ 1243#define DMAACTIVE2 0x40000 /* DMA2 Active */
1312#define nDMAACTIVE2 0x0
1313#define DMAACTIVE3 0x80000 /* DMA3 Active */ 1244#define DMAACTIVE3 0x80000 /* DMA3 Active */
1314#define nDMAACTIVE3 0x0
1315#define DMAACTIVE4 0x100000 /* DMA4 Active */ 1245#define DMAACTIVE4 0x100000 /* DMA4 Active */
1316#define nDMAACTIVE4 0x0
1317#define DMAACTIVE5 0x200000 /* DMA5 Active */ 1246#define DMAACTIVE5 0x200000 /* DMA5 Active */
1318#define nDMAACTIVE5 0x0
1319#define DMAACTIVE6 0x400000 /* DMA6 Active */ 1247#define DMAACTIVE6 0x400000 /* DMA6 Active */
1320#define nDMAACTIVE6 0x0
1321#define DMAACTIVE7 0x800000 /* DMA7 Active */ 1248#define DMAACTIVE7 0x800000 /* DMA7 Active */
1322#define nDMAACTIVE7 0x0
1323#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */ 1249#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */
1324#define nDMAPMEN0 0x0
1325#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */ 1250#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */
1326#define nDMAPMEN1 0x0
1327#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */ 1251#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */
1328#define nDMAPMEN2 0x0
1329#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */ 1252#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */
1330#define nDMAPMEN3 0x0
1331#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */ 1253#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */
1332#define nDMAPMEN4 0x0
1333#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */ 1254#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */
1334#define nDMAPMEN5 0x0
1335#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */ 1255#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */
1336#define nDMAPMEN6 0x0
1337#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */ 1256#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */
1338#define nDMAPMEN7 0x0
1339 1257
1340/* Bit masks for MXVR_INT_STAT_0 */ 1258/* Bit masks for MXVR_INT_STAT_0 */
1341 1259
1342#define NI2A 0x1 /* Network Inactive to Active */ 1260#define NI2A 0x1 /* Network Inactive to Active */
1343#define nNI2A 0x0
1344#define NA2I 0x2 /* Network Active to Inactive */ 1261#define NA2I 0x2 /* Network Active to Inactive */
1345#define nNA2I 0x0
1346#define SBU2L 0x4 /* Super Block Unlock to Lock */ 1262#define SBU2L 0x4 /* Super Block Unlock to Lock */
1347#define nSBU2L 0x0
1348#define SBL2U 0x8 /* Super Block Lock to Unlock */ 1263#define SBL2U 0x8 /* Super Block Lock to Unlock */
1349#define nSBL2U 0x0
1350#define PRU 0x10 /* Position Register Updated */ 1264#define PRU 0x10 /* Position Register Updated */
1351#define nPRU 0x0
1352#define MPRU 0x20 /* Maximum Position Register Updated */ 1265#define MPRU 0x20 /* Maximum Position Register Updated */
1353#define nMPRU 0x0
1354#define DRU 0x40 /* Delay Register Updated */ 1266#define DRU 0x40 /* Delay Register Updated */
1355#define nDRU 0x0
1356#define MDRU 0x80 /* Maximum Delay Register Updated */ 1267#define MDRU 0x80 /* Maximum Delay Register Updated */
1357#define nMDRU 0x0
1358#define SBU 0x100 /* Synchronous Boundary Updated */ 1268#define SBU 0x100 /* Synchronous Boundary Updated */
1359#define nSBU 0x0
1360#define ATU 0x200 /* Allocation Table Updated */ 1269#define ATU 0x200 /* Allocation Table Updated */
1361#define nATU 0x0
1362#define FCZ0 0x400 /* Frame Counter 0 Zero */ 1270#define FCZ0 0x400 /* Frame Counter 0 Zero */
1363#define nFCZ0 0x0
1364#define FCZ1 0x800 /* Frame Counter 1 Zero */ 1271#define FCZ1 0x800 /* Frame Counter 1 Zero */
1365#define nFCZ1 0x0
1366#define PERR 0x1000 /* Parity Error */ 1272#define PERR 0x1000 /* Parity Error */
1367#define nPERR 0x0
1368#define MH2L 0x2000 /* MRXONB High to Low */ 1273#define MH2L 0x2000 /* MRXONB High to Low */
1369#define nMH2L 0x0
1370#define ML2H 0x4000 /* MRXONB Low to High */ 1274#define ML2H 0x4000 /* MRXONB Low to High */
1371#define nML2H 0x0
1372#define WUP 0x8000 /* Wake-Up Preamble Received */ 1275#define WUP 0x8000 /* Wake-Up Preamble Received */
1373#define nWUP 0x0
1374#define FU2L 0x10000 /* Frame Unlock to Lock */ 1276#define FU2L 0x10000 /* Frame Unlock to Lock */
1375#define nFU2L 0x0
1376#define FL2U 0x20000 /* Frame Lock to Unlock */ 1277#define FL2U 0x20000 /* Frame Lock to Unlock */
1377#define nFL2U 0x0
1378#define BU2L 0x40000 /* Block Unlock to Lock */ 1278#define BU2L 0x40000 /* Block Unlock to Lock */
1379#define nBU2L 0x0
1380#define BL2U 0x80000 /* Block Lock to Unlock */ 1279#define BL2U 0x80000 /* Block Lock to Unlock */
1381#define nBL2U 0x0
1382#define OBERR 0x100000 /* DMA Out of Bounds Error */ 1280#define OBERR 0x100000 /* DMA Out of Bounds Error */
1383#define nOBERR 0x0
1384#define PFL 0x200000 /* PLL Frequency Locked */ 1281#define PFL 0x200000 /* PLL Frequency Locked */
1385#define nPFL 0x0
1386#define SCZ 0x400000 /* System Clock Counter Zero */ 1282#define SCZ 0x400000 /* System Clock Counter Zero */
1387#define nSCZ 0x0
1388#define FERR 0x800000 /* FIFO Error */ 1283#define FERR 0x800000 /* FIFO Error */
1389#define nFERR 0x0
1390#define CMR 0x1000000 /* Control Message Received */ 1284#define CMR 0x1000000 /* Control Message Received */
1391#define nCMR 0x0
1392#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */ 1285#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */
1393#define nCMROF 0x0
1394#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */ 1286#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */
1395#define nCMTS 0x0
1396#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */ 1287#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */
1397#define nCMTC 0x0
1398#define RWRC 0x10000000 /* Remote Write Control Message Completed */ 1288#define RWRC 0x10000000 /* Remote Write Control Message Completed */
1399#define nRWRC 0x0
1400#define BCZ 0x20000000 /* Block Counter Zero */ 1289#define BCZ 0x20000000 /* Block Counter Zero */
1401#define nBCZ 0x0
1402#define BMERR 0x40000000 /* Biphase Mark Coding Error */ 1290#define BMERR 0x40000000 /* Biphase Mark Coding Error */
1403#define nBMERR 0x0
1404#define DERR 0x80000000 /* DMA Error */ 1291#define DERR 0x80000000 /* DMA Error */
1405#define nDERR 0x0
1406 1292
1407/* Bit masks for MXVR_INT_STAT_1 */ 1293/* Bit masks for MXVR_INT_STAT_1 */
1408 1294
1409#define HDONE0 0x1 /* DMA0 Half Done */ 1295#define HDONE0 0x1 /* DMA0 Half Done */
1410#define nHDONE0 0x0
1411#define DONE0 0x2 /* DMA0 Done */ 1296#define DONE0 0x2 /* DMA0 Done */
1412#define nDONE0 0x0
1413#define APR 0x4 /* Asynchronous Packet Received */ 1297#define APR 0x4 /* Asynchronous Packet Received */
1414#define nAPR 0x0
1415#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */ 1298#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */
1416#define nAPROF 0x0
1417#define HDONE1 0x10 /* DMA1 Half Done */ 1299#define HDONE1 0x10 /* DMA1 Half Done */
1418#define nHDONE1 0x0
1419#define DONE1 0x20 /* DMA1 Done */ 1300#define DONE1 0x20 /* DMA1 Done */
1420#define nDONE1 0x0
1421#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */ 1301#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */
1422#define nAPTS 0x0
1423#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */ 1302#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
1424#define nAPTC 0x0
1425#define HDONE2 0x100 /* DMA2 Half Done */ 1303#define HDONE2 0x100 /* DMA2 Half Done */
1426#define nHDONE2 0x0
1427#define DONE2 0x200 /* DMA2 Done */ 1304#define DONE2 0x200 /* DMA2 Done */
1428#define nDONE2 0x0
1429#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */ 1305#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */
1430#define nAPRCE 0x0
1431#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */ 1306#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */
1432#define nAPRPE 0x0
1433#define HDONE3 0x1000 /* DMA3 Half Done */ 1307#define HDONE3 0x1000 /* DMA3 Half Done */
1434#define nHDONE3 0x0
1435#define DONE3 0x2000 /* DMA3 Done */ 1308#define DONE3 0x2000 /* DMA3 Done */
1436#define nDONE3 0x0
1437#define HDONE4 0x10000 /* DMA4 Half Done */ 1309#define HDONE4 0x10000 /* DMA4 Half Done */
1438#define nHDONE4 0x0
1439#define DONE4 0x20000 /* DMA4 Done */ 1310#define DONE4 0x20000 /* DMA4 Done */
1440#define nDONE4 0x0
1441#define HDONE5 0x100000 /* DMA5 Half Done */ 1311#define HDONE5 0x100000 /* DMA5 Half Done */
1442#define nHDONE5 0x0
1443#define DONE5 0x200000 /* DMA5 Done */ 1312#define DONE5 0x200000 /* DMA5 Done */
1444#define nDONE5 0x0
1445#define HDONE6 0x1000000 /* DMA6 Half Done */ 1313#define HDONE6 0x1000000 /* DMA6 Half Done */
1446#define nHDONE6 0x0
1447#define DONE6 0x2000000 /* DMA6 Done */ 1314#define DONE6 0x2000000 /* DMA6 Done */
1448#define nDONE6 0x0
1449#define HDONE7 0x10000000 /* DMA7 Half Done */ 1315#define HDONE7 0x10000000 /* DMA7 Half Done */
1450#define nHDONE7 0x0
1451#define DONE7 0x20000000 /* DMA7 Done */ 1316#define DONE7 0x20000000 /* DMA7 Done */
1452#define nDONE7 0x0
1453 1317
1454/* Bit masks for MXVR_INT_EN_0 */ 1318/* Bit masks for MXVR_INT_EN_0 */
1455 1319
1456#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */ 1320#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */
1457#define nNI2AEN 0x0
1458#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */ 1321#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */
1459#define nNA2IEN 0x0
1460#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */ 1322#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */
1461#define nSBU2LEN 0x0
1462#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */ 1323#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */
1463#define nSBL2UEN 0x0
1464#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */ 1324#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */
1465#define nPRUEN 0x0
1466#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */ 1325#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */
1467#define nMPRUEN 0x0
1468#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */ 1326#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */
1469#define nDRUEN 0x0
1470#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */ 1327#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */
1471#define nMDRUEN 0x0
1472#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */ 1328#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */
1473#define nSBUEN 0x0
1474#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */ 1329#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */
1475#define nATUEN 0x0
1476#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */ 1330#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */
1477#define nFCZ0EN 0x0
1478#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */ 1331#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */
1479#define nFCZ1EN 0x0
1480#define PERREN 0x1000 /* Parity Error Interrupt Enable */ 1332#define PERREN 0x1000 /* Parity Error Interrupt Enable */
1481#define nPERREN 0x0
1482#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */ 1333#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */
1483#define nMH2LEN 0x0
1484#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */ 1334#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */
1485#define nML2HEN 0x0
1486#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */ 1335#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */
1487#define nWUPEN 0x0
1488#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */ 1336#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */
1489#define nFU2LEN 0x0
1490#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */ 1337#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */
1491#define nFL2UEN 0x0
1492#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */ 1338#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */
1493#define nBU2LEN 0x0
1494#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */ 1339#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */
1495#define nBL2UEN 0x0
1496#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */ 1340#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */
1497#define nOBERREN 0x0
1498#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */ 1341#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */
1499#define nPFLEN 0x0
1500#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */ 1342#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */
1501#define nSCZEN 0x0
1502#define FERREN 0x800000 /* FIFO Error Interrupt Enable */ 1343#define FERREN 0x800000 /* FIFO Error Interrupt Enable */
1503#define nFERREN 0x0
1504#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */ 1344#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */
1505#define nCMREN 0x0
1506#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */ 1345#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */
1507#define nCMROFEN 0x0
1508#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */ 1346#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
1509#define nCMTSEN 0x0
1510#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */ 1347#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
1511#define nCMTCEN 0x0
1512#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */ 1348#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
1513#define nRWRCEN 0x0
1514#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */ 1349#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */
1515#define nBCZEN 0x0
1516#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */ 1350#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
1517#define nBMERREN 0x0
1518#define DERREN 0x80000000 /* DMA Error Interrupt Enable */ 1351#define DERREN 0x80000000 /* DMA Error Interrupt Enable */
1519#define nDERREN 0x0
1520 1352
1521/* Bit masks for MXVR_INT_EN_1 */ 1353/* Bit masks for MXVR_INT_EN_1 */
1522 1354
1523#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */ 1355#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */
1524#define nHDONEEN0 0x0
1525#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */ 1356#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */
1526#define nDONEEN0 0x0
1527#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */ 1357#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */
1528#define nAPREN 0x0
1529#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */ 1358#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
1530#define nAPROFEN 0x0
1531#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */ 1359#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */
1532#define nHDONEEN1 0x0
1533#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */ 1360#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */
1534#define nDONEEN1 0x0
1535#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */ 1361#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
1536#define nAPTSEN 0x0
1537#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */ 1362#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
1538#define nAPTCEN 0x0
1539#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */ 1363#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */
1540#define nHDONEEN2 0x0
1541#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */ 1364#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */
1542#define nDONEEN2 0x0
1543#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */ 1365#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */
1544#define nAPRCEEN 0x0
1545#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */ 1366#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */
1546#define nAPRPEEN 0x0
1547#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */ 1367#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */
1548#define nHDONEEN3 0x0
1549#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */ 1368#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */
1550#define nDONEEN3 0x0
1551#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */ 1369#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */
1552#define nHDONEEN4 0x0
1553#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */ 1370#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */
1554#define nDONEEN4 0x0
1555#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */ 1371#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */
1556#define nHDONEEN5 0x0
1557#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */ 1372#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */
1558#define nDONEEN5 0x0
1559#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */ 1373#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */
1560#define nHDONEEN6 0x0
1561#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */ 1374#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */
1562#define nDONEEN6 0x0
1563#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */ 1375#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */
1564#define nHDONEEN7 0x0
1565#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */ 1376#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */
1566#define nDONEEN7 0x0
1567 1377
1568/* Bit masks for MXVR_POSITION */ 1378/* Bit masks for MXVR_POSITION */
1569 1379
1570#define POSITION 0x3f /* Node Position */ 1380#define POSITION 0x3f /* Node Position */
1571#define PVALID 0x8000 /* Node Position Valid */ 1381#define PVALID 0x8000 /* Node Position Valid */
1572#define nPVALID 0x0
1573 1382
1574/* Bit masks for MXVR_MAX_POSITION */ 1383/* Bit masks for MXVR_MAX_POSITION */
1575 1384
1576#define MPOSITION 0x3f /* Maximum Node Position */ 1385#define MPOSITION 0x3f /* Maximum Node Position */
1577#define MPVALID 0x8000 /* Maximum Node Position Valid */ 1386#define MPVALID 0x8000 /* Maximum Node Position Valid */
1578#define nMPVALID 0x0
1579 1387
1580/* Bit masks for MXVR_DELAY */ 1388/* Bit masks for MXVR_DELAY */
1581 1389
1582#define DELAY 0x3f /* Node Frame Delay */ 1390#define DELAY 0x3f /* Node Frame Delay */
1583#define DVALID 0x8000 /* Node Frame Delay Valid */ 1391#define DVALID 0x8000 /* Node Frame Delay Valid */
1584#define nDVALID 0x0
1585 1392
1586/* Bit masks for MXVR_MAX_DELAY */ 1393/* Bit masks for MXVR_MAX_DELAY */
1587 1394
1588#define MDELAY 0x3f /* Maximum Node Frame Delay */ 1395#define MDELAY 0x3f /* Maximum Node Frame Delay */
1589#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */ 1396#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */
1590#define nMDVALID 0x0
1591 1397
1592/* Bit masks for MXVR_LADDR */ 1398/* Bit masks for MXVR_LADDR */
1593 1399
1594#define LADDR 0xffff /* Logical Address */ 1400#define LADDR 0xffff /* Logical Address */
1595#define LVALID 0x80000000 /* Logical Address Valid */ 1401#define LVALID 0x80000000 /* Logical Address Valid */
1596#define nLVALID 0x0
1597 1402
1598/* Bit masks for MXVR_GADDR */ 1403/* Bit masks for MXVR_GADDR */
1599 1404
1600#define GADDRL 0xff /* Group Address Lower Byte */ 1405#define GADDRL 0xff /* Group Address Lower Byte */
1601#define GVALID 0x8000 /* Group Address Valid */ 1406#define GVALID 0x8000 /* Group Address Valid */
1602#define nGVALID 0x0
1603 1407
1604/* Bit masks for MXVR_AADDR */ 1408/* Bit masks for MXVR_AADDR */
1605 1409
1606#define AADDR 0xffff /* Alternate Address */ 1410#define AADDR 0xffff /* Alternate Address */
1607#define AVALID 0x80000000 /* Alternate Address Valid */ 1411#define AVALID 0x80000000 /* Alternate Address Valid */
1608#define nAVALID 0x0
1609 1412
1610/* Bit masks for MXVR_ALLOC_0 */ 1413/* Bit masks for MXVR_ALLOC_0 */
1611 1414
1612#define CL0 0x7f /* Channel 0 Connection Label */ 1415#define CL0 0x7f /* Channel 0 Connection Label */
1613#define CIU0 0x80 /* Channel 0 In Use */ 1416#define CIU0 0x80 /* Channel 0 In Use */
1614#define nCIU0 0x0
1615#define CL1 0x7f00 /* Channel 0 Connection Label */ 1417#define CL1 0x7f00 /* Channel 0 Connection Label */
1616#define CIU1 0x8000 /* Channel 0 In Use */ 1418#define CIU1 0x8000 /* Channel 0 In Use */
1617#define nCIU1 0x0
1618#define CL2 0x7f0000 /* Channel 0 Connection Label */ 1419#define CL2 0x7f0000 /* Channel 0 Connection Label */
1619#define CIU2 0x800000 /* Channel 0 In Use */ 1420#define CIU2 0x800000 /* Channel 0 In Use */
1620#define nCIU2 0x0
1621#define CL3 0x7f000000 /* Channel 0 Connection Label */ 1421#define CL3 0x7f000000 /* Channel 0 Connection Label */
1622#define CIU3 0x80000000 /* Channel 0 In Use */ 1422#define CIU3 0x80000000 /* Channel 0 In Use */
1623#define nCIU3 0x0
1624 1423
1625/* Bit masks for MXVR_ALLOC_1 */ 1424/* Bit masks for MXVR_ALLOC_1 */
1626 1425
1627#define CL4 0x7f /* Channel 4 Connection Label */ 1426#define CL4 0x7f /* Channel 4 Connection Label */
1628#define CIU4 0x80 /* Channel 4 In Use */ 1427#define CIU4 0x80 /* Channel 4 In Use */
1629#define nCIU4 0x0
1630#define CL5 0x7f00 /* Channel 5 Connection Label */ 1428#define CL5 0x7f00 /* Channel 5 Connection Label */
1631#define CIU5 0x8000 /* Channel 5 In Use */ 1429#define CIU5 0x8000 /* Channel 5 In Use */
1632#define nCIU5 0x0
1633#define CL6 0x7f0000 /* Channel 6 Connection Label */ 1430#define CL6 0x7f0000 /* Channel 6 Connection Label */
1634#define CIU6 0x800000 /* Channel 6 In Use */ 1431#define CIU6 0x800000 /* Channel 6 In Use */
1635#define nCIU6 0x0
1636#define CL7 0x7f000000 /* Channel 7 Connection Label */ 1432#define CL7 0x7f000000 /* Channel 7 Connection Label */
1637#define CIU7 0x80000000 /* Channel 7 In Use */ 1433#define CIU7 0x80000000 /* Channel 7 In Use */
1638#define nCIU7 0x0
1639 1434
1640/* Bit masks for MXVR_ALLOC_2 */ 1435/* Bit masks for MXVR_ALLOC_2 */
1641 1436
1642#define CL8 0x7f /* Channel 8 Connection Label */ 1437#define CL8 0x7f /* Channel 8 Connection Label */
1643#define CIU8 0x80 /* Channel 8 In Use */ 1438#define CIU8 0x80 /* Channel 8 In Use */
1644#define nCIU8 0x0
1645#define CL9 0x7f00 /* Channel 9 Connection Label */ 1439#define CL9 0x7f00 /* Channel 9 Connection Label */
1646#define CIU9 0x8000 /* Channel 9 In Use */ 1440#define CIU9 0x8000 /* Channel 9 In Use */
1647#define nCIU9 0x0
1648#define CL10 0x7f0000 /* Channel 10 Connection Label */ 1441#define CL10 0x7f0000 /* Channel 10 Connection Label */
1649#define CIU10 0x800000 /* Channel 10 In Use */ 1442#define CIU10 0x800000 /* Channel 10 In Use */
1650#define nCIU10 0x0
1651#define CL11 0x7f000000 /* Channel 11 Connection Label */ 1443#define CL11 0x7f000000 /* Channel 11 Connection Label */
1652#define CIU11 0x80000000 /* Channel 11 In Use */ 1444#define CIU11 0x80000000 /* Channel 11 In Use */
1653#define nCIU11 0x0
1654 1445
1655/* Bit masks for MXVR_ALLOC_3 */ 1446/* Bit masks for MXVR_ALLOC_3 */
1656 1447
1657#define CL12 0x7f /* Channel 12 Connection Label */ 1448#define CL12 0x7f /* Channel 12 Connection Label */
1658#define CIU12 0x80 /* Channel 12 In Use */ 1449#define CIU12 0x80 /* Channel 12 In Use */
1659#define nCIU12 0x0
1660#define CL13 0x7f00 /* Channel 13 Connection Label */ 1450#define CL13 0x7f00 /* Channel 13 Connection Label */
1661#define CIU13 0x8000 /* Channel 13 In Use */ 1451#define CIU13 0x8000 /* Channel 13 In Use */
1662#define nCIU13 0x0
1663#define CL14 0x7f0000 /* Channel 14 Connection Label */ 1452#define CL14 0x7f0000 /* Channel 14 Connection Label */
1664#define CIU14 0x800000 /* Channel 14 In Use */ 1453#define CIU14 0x800000 /* Channel 14 In Use */
1665#define nCIU14 0x0
1666#define CL15 0x7f000000 /* Channel 15 Connection Label */ 1454#define CL15 0x7f000000 /* Channel 15 Connection Label */
1667#define CIU15 0x80000000 /* Channel 15 In Use */ 1455#define CIU15 0x80000000 /* Channel 15 In Use */
1668#define nCIU15 0x0
1669 1456
1670/* Bit masks for MXVR_ALLOC_4 */ 1457/* Bit masks for MXVR_ALLOC_4 */
1671 1458
1672#define CL16 0x7f /* Channel 16 Connection Label */ 1459#define CL16 0x7f /* Channel 16 Connection Label */
1673#define CIU16 0x80 /* Channel 16 In Use */ 1460#define CIU16 0x80 /* Channel 16 In Use */
1674#define nCIU16 0x0
1675#define CL17 0x7f00 /* Channel 17 Connection Label */ 1461#define CL17 0x7f00 /* Channel 17 Connection Label */
1676#define CIU17 0x8000 /* Channel 17 In Use */ 1462#define CIU17 0x8000 /* Channel 17 In Use */
1677#define nCIU17 0x0
1678#define CL18 0x7f0000 /* Channel 18 Connection Label */ 1463#define CL18 0x7f0000 /* Channel 18 Connection Label */
1679#define CIU18 0x800000 /* Channel 18 In Use */ 1464#define CIU18 0x800000 /* Channel 18 In Use */
1680#define nCIU18 0x0
1681#define CL19 0x7f000000 /* Channel 19 Connection Label */ 1465#define CL19 0x7f000000 /* Channel 19 Connection Label */
1682#define CIU19 0x80000000 /* Channel 19 In Use */ 1466#define CIU19 0x80000000 /* Channel 19 In Use */
1683#define nCIU19 0x0
1684 1467
1685/* Bit masks for MXVR_ALLOC_5 */ 1468/* Bit masks for MXVR_ALLOC_5 */
1686 1469
1687#define CL20 0x7f /* Channel 20 Connection Label */ 1470#define CL20 0x7f /* Channel 20 Connection Label */
1688#define CIU20 0x80 /* Channel 20 In Use */ 1471#define CIU20 0x80 /* Channel 20 In Use */
1689#define nCIU20 0x0
1690#define CL21 0x7f00 /* Channel 21 Connection Label */ 1472#define CL21 0x7f00 /* Channel 21 Connection Label */
1691#define CIU21 0x8000 /* Channel 21 In Use */ 1473#define CIU21 0x8000 /* Channel 21 In Use */
1692#define nCIU21 0x0
1693#define CL22 0x7f0000 /* Channel 22 Connection Label */ 1474#define CL22 0x7f0000 /* Channel 22 Connection Label */
1694#define CIU22 0x800000 /* Channel 22 In Use */ 1475#define CIU22 0x800000 /* Channel 22 In Use */
1695#define nCIU22 0x0
1696#define CL23 0x7f000000 /* Channel 23 Connection Label */ 1476#define CL23 0x7f000000 /* Channel 23 Connection Label */
1697#define CIU23 0x80000000 /* Channel 23 In Use */ 1477#define CIU23 0x80000000 /* Channel 23 In Use */
1698#define nCIU23 0x0
1699 1478
1700/* Bit masks for MXVR_ALLOC_6 */ 1479/* Bit masks for MXVR_ALLOC_6 */
1701 1480
1702#define CL24 0x7f /* Channel 24 Connection Label */ 1481#define CL24 0x7f /* Channel 24 Connection Label */
1703#define CIU24 0x80 /* Channel 24 In Use */ 1482#define CIU24 0x80 /* Channel 24 In Use */
1704#define nCIU24 0x0
1705#define CL25 0x7f00 /* Channel 25 Connection Label */ 1483#define CL25 0x7f00 /* Channel 25 Connection Label */
1706#define CIU25 0x8000 /* Channel 25 In Use */ 1484#define CIU25 0x8000 /* Channel 25 In Use */
1707#define nCIU25 0x0
1708#define CL26 0x7f0000 /* Channel 26 Connection Label */ 1485#define CL26 0x7f0000 /* Channel 26 Connection Label */
1709#define CIU26 0x800000 /* Channel 26 In Use */ 1486#define CIU26 0x800000 /* Channel 26 In Use */
1710#define nCIU26 0x0
1711#define CL27 0x7f000000 /* Channel 27 Connection Label */ 1487#define CL27 0x7f000000 /* Channel 27 Connection Label */
1712#define CIU27 0x80000000 /* Channel 27 In Use */ 1488#define CIU27 0x80000000 /* Channel 27 In Use */
1713#define nCIU27 0x0
1714 1489
1715/* Bit masks for MXVR_ALLOC_7 */ 1490/* Bit masks for MXVR_ALLOC_7 */
1716 1491
1717#define CL28 0x7f /* Channel 28 Connection Label */ 1492#define CL28 0x7f /* Channel 28 Connection Label */
1718#define CIU28 0x80 /* Channel 28 In Use */ 1493#define CIU28 0x80 /* Channel 28 In Use */
1719#define nCIU28 0x0
1720#define CL29 0x7f00 /* Channel 29 Connection Label */ 1494#define CL29 0x7f00 /* Channel 29 Connection Label */
1721#define CIU29 0x8000 /* Channel 29 In Use */ 1495#define CIU29 0x8000 /* Channel 29 In Use */
1722#define nCIU29 0x0
1723#define CL30 0x7f0000 /* Channel 30 Connection Label */ 1496#define CL30 0x7f0000 /* Channel 30 Connection Label */
1724#define CIU30 0x800000 /* Channel 30 In Use */ 1497#define CIU30 0x800000 /* Channel 30 In Use */
1725#define nCIU30 0x0
1726#define CL31 0x7f000000 /* Channel 31 Connection Label */ 1498#define CL31 0x7f000000 /* Channel 31 Connection Label */
1727#define CIU31 0x80000000 /* Channel 31 In Use */ 1499#define CIU31 0x80000000 /* Channel 31 In Use */
1728#define nCIU31 0x0
1729 1500
1730/* Bit masks for MXVR_ALLOC_8 */ 1501/* Bit masks for MXVR_ALLOC_8 */
1731 1502
1732#define CL32 0x7f /* Channel 32 Connection Label */ 1503#define CL32 0x7f /* Channel 32 Connection Label */
1733#define CIU32 0x80 /* Channel 32 In Use */ 1504#define CIU32 0x80 /* Channel 32 In Use */
1734#define nCIU32 0x0
1735#define CL33 0x7f00 /* Channel 33 Connection Label */ 1505#define CL33 0x7f00 /* Channel 33 Connection Label */
1736#define CIU33 0x8000 /* Channel 33 In Use */ 1506#define CIU33 0x8000 /* Channel 33 In Use */
1737#define nCIU33 0x0
1738#define CL34 0x7f0000 /* Channel 34 Connection Label */ 1507#define CL34 0x7f0000 /* Channel 34 Connection Label */
1739#define CIU34 0x800000 /* Channel 34 In Use */ 1508#define CIU34 0x800000 /* Channel 34 In Use */
1740#define nCIU34 0x0
1741#define CL35 0x7f000000 /* Channel 35 Connection Label */ 1509#define CL35 0x7f000000 /* Channel 35 Connection Label */
1742#define CIU35 0x80000000 /* Channel 35 In Use */ 1510#define CIU35 0x80000000 /* Channel 35 In Use */
1743#define nCIU35 0x0
1744 1511
1745/* Bit masks for MXVR_ALLOC_9 */ 1512/* Bit masks for MXVR_ALLOC_9 */
1746 1513
1747#define CL36 0x7f /* Channel 36 Connection Label */ 1514#define CL36 0x7f /* Channel 36 Connection Label */
1748#define CIU36 0x80 /* Channel 36 In Use */ 1515#define CIU36 0x80 /* Channel 36 In Use */
1749#define nCIU36 0x0
1750#define CL37 0x7f00 /* Channel 37 Connection Label */ 1516#define CL37 0x7f00 /* Channel 37 Connection Label */
1751#define CIU37 0x8000 /* Channel 37 In Use */ 1517#define CIU37 0x8000 /* Channel 37 In Use */
1752#define nCIU37 0x0
1753#define CL38 0x7f0000 /* Channel 38 Connection Label */ 1518#define CL38 0x7f0000 /* Channel 38 Connection Label */
1754#define CIU38 0x800000 /* Channel 38 In Use */ 1519#define CIU38 0x800000 /* Channel 38 In Use */
1755#define nCIU38 0x0
1756#define CL39 0x7f000000 /* Channel 39 Connection Label */ 1520#define CL39 0x7f000000 /* Channel 39 Connection Label */
1757#define CIU39 0x80000000 /* Channel 39 In Use */ 1521#define CIU39 0x80000000 /* Channel 39 In Use */
1758#define nCIU39 0x0
1759 1522
1760/* Bit masks for MXVR_ALLOC_10 */ 1523/* Bit masks for MXVR_ALLOC_10 */
1761 1524
1762#define CL40 0x7f /* Channel 40 Connection Label */ 1525#define CL40 0x7f /* Channel 40 Connection Label */
1763#define CIU40 0x80 /* Channel 40 In Use */ 1526#define CIU40 0x80 /* Channel 40 In Use */
1764#define nCIU40 0x0
1765#define CL41 0x7f00 /* Channel 41 Connection Label */ 1527#define CL41 0x7f00 /* Channel 41 Connection Label */
1766#define CIU41 0x8000 /* Channel 41 In Use */ 1528#define CIU41 0x8000 /* Channel 41 In Use */
1767#define nCIU41 0x0
1768#define CL42 0x7f0000 /* Channel 42 Connection Label */ 1529#define CL42 0x7f0000 /* Channel 42 Connection Label */
1769#define CIU42 0x800000 /* Channel 42 In Use */ 1530#define CIU42 0x800000 /* Channel 42 In Use */
1770#define nCIU42 0x0
1771#define CL43 0x7f000000 /* Channel 43 Connection Label */ 1531#define CL43 0x7f000000 /* Channel 43 Connection Label */
1772#define CIU43 0x80000000 /* Channel 43 In Use */ 1532#define CIU43 0x80000000 /* Channel 43 In Use */
1773#define nCIU43 0x0
1774 1533
1775/* Bit masks for MXVR_ALLOC_11 */ 1534/* Bit masks for MXVR_ALLOC_11 */
1776 1535
1777#define CL44 0x7f /* Channel 44 Connection Label */ 1536#define CL44 0x7f /* Channel 44 Connection Label */
1778#define CIU44 0x80 /* Channel 44 In Use */ 1537#define CIU44 0x80 /* Channel 44 In Use */
1779#define nCIU44 0x0
1780#define CL45 0x7f00 /* Channel 45 Connection Label */ 1538#define CL45 0x7f00 /* Channel 45 Connection Label */
1781#define CIU45 0x8000 /* Channel 45 In Use */ 1539#define CIU45 0x8000 /* Channel 45 In Use */
1782#define nCIU45 0x0
1783#define CL46 0x7f0000 /* Channel 46 Connection Label */ 1540#define CL46 0x7f0000 /* Channel 46 Connection Label */
1784#define CIU46 0x800000 /* Channel 46 In Use */ 1541#define CIU46 0x800000 /* Channel 46 In Use */
1785#define nCIU46 0x0
1786#define CL47 0x7f000000 /* Channel 47 Connection Label */ 1542#define CL47 0x7f000000 /* Channel 47 Connection Label */
1787#define CIU47 0x80000000 /* Channel 47 In Use */ 1543#define CIU47 0x80000000 /* Channel 47 In Use */
1788#define nCIU47 0x0
1789 1544
1790/* Bit masks for MXVR_ALLOC_12 */ 1545/* Bit masks for MXVR_ALLOC_12 */
1791 1546
1792#define CL48 0x7f /* Channel 48 Connection Label */ 1547#define CL48 0x7f /* Channel 48 Connection Label */
1793#define CIU48 0x80 /* Channel 48 In Use */ 1548#define CIU48 0x80 /* Channel 48 In Use */
1794#define nCIU48 0x0
1795#define CL49 0x7f00 /* Channel 49 Connection Label */ 1549#define CL49 0x7f00 /* Channel 49 Connection Label */
1796#define CIU49 0x8000 /* Channel 49 In Use */ 1550#define CIU49 0x8000 /* Channel 49 In Use */
1797#define nCIU49 0x0
1798#define CL50 0x7f0000 /* Channel 50 Connection Label */ 1551#define CL50 0x7f0000 /* Channel 50 Connection Label */
1799#define CIU50 0x800000 /* Channel 50 In Use */ 1552#define CIU50 0x800000 /* Channel 50 In Use */
1800#define nCIU50 0x0
1801#define CL51 0x7f000000 /* Channel 51 Connection Label */ 1553#define CL51 0x7f000000 /* Channel 51 Connection Label */
1802#define CIU51 0x80000000 /* Channel 51 In Use */ 1554#define CIU51 0x80000000 /* Channel 51 In Use */
1803#define nCIU51 0x0
1804 1555
1805/* Bit masks for MXVR_ALLOC_13 */ 1556/* Bit masks for MXVR_ALLOC_13 */
1806 1557
1807#define CL52 0x7f /* Channel 52 Connection Label */ 1558#define CL52 0x7f /* Channel 52 Connection Label */
1808#define CIU52 0x80 /* Channel 52 In Use */ 1559#define CIU52 0x80 /* Channel 52 In Use */
1809#define nCIU52 0x0
1810#define CL53 0x7f00 /* Channel 53 Connection Label */ 1560#define CL53 0x7f00 /* Channel 53 Connection Label */
1811#define CIU53 0x8000 /* Channel 53 In Use */ 1561#define CIU53 0x8000 /* Channel 53 In Use */
1812#define nCIU53 0x0
1813#define CL54 0x7f0000 /* Channel 54 Connection Label */ 1562#define CL54 0x7f0000 /* Channel 54 Connection Label */
1814#define CIU54 0x800000 /* Channel 54 In Use */ 1563#define CIU54 0x800000 /* Channel 54 In Use */
1815#define nCIU54 0x0
1816#define CL55 0x7f000000 /* Channel 55 Connection Label */ 1564#define CL55 0x7f000000 /* Channel 55 Connection Label */
1817#define CIU55 0x80000000 /* Channel 55 In Use */ 1565#define CIU55 0x80000000 /* Channel 55 In Use */
1818#define nCIU55 0x0
1819 1566
1820/* Bit masks for MXVR_ALLOC_14 */ 1567/* Bit masks for MXVR_ALLOC_14 */
1821 1568
1822#define CL56 0x7f /* Channel 56 Connection Label */ 1569#define CL56 0x7f /* Channel 56 Connection Label */
1823#define CIU56 0x80 /* Channel 56 In Use */ 1570#define CIU56 0x80 /* Channel 56 In Use */
1824#define nCIU56 0x0
1825#define CL57 0x7f00 /* Channel 57 Connection Label */ 1571#define CL57 0x7f00 /* Channel 57 Connection Label */
1826#define CIU57 0x8000 /* Channel 57 In Use */ 1572#define CIU57 0x8000 /* Channel 57 In Use */
1827#define nCIU57 0x0
1828#define CL58 0x7f0000 /* Channel 58 Connection Label */ 1573#define CL58 0x7f0000 /* Channel 58 Connection Label */
1829#define CIU58 0x800000 /* Channel 58 In Use */ 1574#define CIU58 0x800000 /* Channel 58 In Use */
1830#define nCIU58 0x0
1831#define CL59 0x7f000000 /* Channel 59 Connection Label */ 1575#define CL59 0x7f000000 /* Channel 59 Connection Label */
1832#define CIU59 0x80000000 /* Channel 59 In Use */ 1576#define CIU59 0x80000000 /* Channel 59 In Use */
1833#define nCIU59 0x0
1834 1577
1835/* MXVR_SYNC_LCHAN_0 Masks */ 1578/* MXVR_SYNC_LCHAN_0 Masks */
1836 1579
@@ -1926,19 +1669,13 @@
1926/* Bit masks for MXVR_DMAx_CONFIG */ 1669/* Bit masks for MXVR_DMAx_CONFIG */
1927 1670
1928#define MDMAEN 0x1 /* DMA Channel Enable */ 1671#define MDMAEN 0x1 /* DMA Channel Enable */
1929#define nMDMAEN 0x0
1930#define DD 0x2 /* DMA Channel Direction */ 1672#define DD 0x2 /* DMA Channel Direction */
1931#define nDD 0x0
1932#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ 1673#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
1933#define nBY4SWAPEN 0x0
1934#define LCHAN 0x3c0 /* DMA Channel Logical Channel */ 1674#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
1935#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ 1675#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
1936#define nBITSWAPEN 0x0
1937#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */ 1676#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */
1938#define nBY2SWAPEN 0x0
1939#define MFLOW 0x7000 /* DMA Channel Operation Flow */ 1677#define MFLOW 0x7000 /* DMA Channel Operation Flow */
1940#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */ 1678#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */
1941#define nFIXEDPM 0x0
1942#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */ 1679#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */
1943#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */ 1680#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */
1944#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */ 1681#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */
@@ -1946,94 +1683,71 @@
1946/* Bit masks for MXVR_AP_CTL */ 1683/* Bit masks for MXVR_AP_CTL */
1947 1684
1948#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */ 1685#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */
1949#define nSTARTAP 0x0
1950#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */ 1686#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */
1951#define nCANCELAP 0x0
1952#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */ 1687#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */
1953#define nRESETAP 0x0
1954#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */ 1688#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */
1955#define nAPRBE0 0x0
1956#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */ 1689#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */
1957#define nAPRBE1 0x0
1958 1690
1959/* Bit masks for MXVR_APRB_START_ADDR */ 1691/* Bit masks for MXVR_APRB_START_ADDR */
1960 1692
1961#define MXVR_APRB_START_ADDR 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */ 1693#define MXVR_APRB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */
1962 1694
1963/* Bit masks for MXVR_APRB_CURR_ADDR */ 1695/* Bit masks for MXVR_APRB_CURR_ADDR */
1964 1696
1965#define MXVR_APRB_CURR_ADDR 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */ 1697#define MXVR_APRB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
1966 1698
1967/* Bit masks for MXVR_APTB_START_ADDR */ 1699/* Bit masks for MXVR_APTB_START_ADDR */
1968 1700
1969#define MXVR_APTB_START_ADDR 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */ 1701#define MXVR_APTB_START_ADDR_MASK 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */
1970 1702
1971/* Bit masks for MXVR_APTB_CURR_ADDR */ 1703/* Bit masks for MXVR_APTB_CURR_ADDR */
1972 1704
1973#define MXVR_APTB_CURR_ADDR 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */ 1705#define MXVR_APTB_CURR_ADDR_MASK 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
1974 1706
1975/* Bit masks for MXVR_CM_CTL */ 1707/* Bit masks for MXVR_CM_CTL */
1976 1708
1977#define STARTCM 0x1 /* Start Control Message Transmission */ 1709#define STARTCM 0x1 /* Start Control Message Transmission */
1978#define nSTARTCM 0x0
1979#define CANCELCM 0x2 /* Cancel Control Message Transmission */ 1710#define CANCELCM 0x2 /* Cancel Control Message Transmission */
1980#define nCANCELCM 0x0
1981#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */ 1711#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */
1982#define nCMRBE0 0x0
1983#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */ 1712#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */
1984#define nCMRBE1 0x0
1985#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */ 1713#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */
1986#define nCMRBE2 0x0
1987#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */ 1714#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */
1988#define nCMRBE3 0x0
1989#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */ 1715#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */
1990#define nCMRBE4 0x0
1991#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */ 1716#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */
1992#define nCMRBE5 0x0
1993#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */ 1717#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */
1994#define nCMRBE6 0x0
1995#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */ 1718#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */
1996#define nCMRBE7 0x0
1997#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */ 1719#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */
1998#define nCMRBE8 0x0
1999#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */ 1720#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */
2000#define nCMRBE9 0x0
2001#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */ 1721#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */
2002#define nCMRBE10 0x0
2003#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */ 1722#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */
2004#define nCMRBE11 0x0
2005#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */ 1723#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */
2006#define nCMRBE12 0x0
2007#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */ 1724#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */
2008#define nCMRBE13 0x0
2009#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */ 1725#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */
2010#define nCMRBE14 0x0
2011#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */ 1726#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */
2012#define nCMRBE15 0x0
2013 1727
2014/* Bit masks for MXVR_CMRB_START_ADDR */ 1728/* Bit masks for MXVR_CMRB_START_ADDR */
2015 1729
2016#define MXVR_CMRB_START_ADDR 0x1fffffe /* Control Message Receive Buffer Start Address */ 1730#define MXVR_CMRB_START_ADDR_MASK 0x1fffffe /* Control Message Receive Buffer Start Address */
2017 1731
2018/* Bit masks for MXVR_CMRB_CURR_ADDR */ 1732/* Bit masks for MXVR_CMRB_CURR_ADDR */
2019 1733
2020#define MXVR_CMRB_CURR_ADDR 0xffffffff /* Control Message Receive Buffer Current Address */ 1734#define MXVR_CMRB_CURR_ADDR_MASK 0xffffffff /* Control Message Receive Buffer Current Address */
2021 1735
2022/* Bit masks for MXVR_CMTB_START_ADDR */ 1736/* Bit masks for MXVR_CMTB_START_ADDR */
2023 1737
2024#define MXVR_CMTB_START_ADDR 0x1fffffe /* Control Message Transmit Buffer Start Address */ 1738#define MXVR_CMTB_START_ADDR_MASK 0x1fffffe /* Control Message Transmit Buffer Start Address */
2025 1739
2026/* Bit masks for MXVR_CMTB_CURR_ADDR */ 1740/* Bit masks for MXVR_CMTB_CURR_ADDR */
2027 1741
2028#define MXVR_CMTB_CURR_ADDR 0xffffffff /* Control Message Transmit Buffer Current Address */ 1742#define MXVR_CMTB_CURR_ADDR_MASK 0xffffffff /* Control Message Transmit Buffer Current Address */
2029 1743
2030/* Bit masks for MXVR_RRDB_START_ADDR */ 1744/* Bit masks for MXVR_RRDB_START_ADDR */
2031 1745
2032#define MXVR_RRDB_START_ADDR 0x1fffffe /* Remote Read Buffer Start Address */ 1746#define MXVR_RRDB_START_ADDR_MASK 0x1fffffe /* Remote Read Buffer Start Address */
2033 1747
2034/* Bit masks for MXVR_RRDB_CURR_ADDR */ 1748/* Bit masks for MXVR_RRDB_CURR_ADDR */
2035 1749
2036#define MXVR_RRDB_CURR_ADDR 0xffffffff /* Remote Read Buffer Current Address */ 1750#define MXVR_RRDB_CURR_ADDR_MASK 0xffffffff /* Remote Read Buffer Current Address */
2037 1751
2038/* Bit masks for MXVR_PAT_DATAx */ 1752/* Bit masks for MXVR_PAT_DATAx */
2039 1753
@@ -2045,136 +1759,72 @@
2045/* Bit masks for MXVR_PAT_EN_0 */ 1759/* Bit masks for MXVR_PAT_EN_0 */
2046 1760
2047#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ 1761#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
2048#define nMATCH_EN_0_0 0x0
2049#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ 1762#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
2050#define nMATCH_EN_0_1 0x0
2051#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ 1763#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
2052#define nMATCH_EN_0_2 0x0
2053#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ 1764#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
2054#define nMATCH_EN_0_3 0x0
2055#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ 1765#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
2056#define nMATCH_EN_0_4 0x0
2057#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ 1766#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
2058#define nMATCH_EN_0_5 0x0
2059#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ 1767#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
2060#define nMATCH_EN_0_6 0x0
2061#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ 1768#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
2062#define nMATCH_EN_0_7 0x0
2063#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ 1769#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
2064#define nMATCH_EN_1_0 0x0
2065#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ 1770#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
2066#define nMATCH_EN_1_1 0x0
2067#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ 1771#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
2068#define nMATCH_EN_1_2 0x0
2069#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ 1772#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
2070#define nMATCH_EN_1_3 0x0
2071#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ 1773#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
2072#define nMATCH_EN_1_4 0x0
2073#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ 1774#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
2074#define nMATCH_EN_1_5 0x0
2075#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ 1775#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
2076#define nMATCH_EN_1_6 0x0
2077#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ 1776#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
2078#define nMATCH_EN_1_7 0x0
2079#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ 1777#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
2080#define nMATCH_EN_2_0 0x0
2081#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ 1778#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
2082#define nMATCH_EN_2_1 0x0
2083#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ 1779#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
2084#define nMATCH_EN_2_2 0x0
2085#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ 1780#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
2086#define nMATCH_EN_2_3 0x0
2087#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ 1781#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
2088#define nMATCH_EN_2_4 0x0
2089#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ 1782#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
2090#define nMATCH_EN_2_5 0x0
2091#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ 1783#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
2092#define nMATCH_EN_2_6 0x0
2093#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ 1784#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
2094#define nMATCH_EN_2_7 0x0
2095#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ 1785#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
2096#define nMATCH_EN_3_0 0x0
2097#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ 1786#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
2098#define nMATCH_EN_3_1 0x0
2099#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ 1787#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
2100#define nMATCH_EN_3_2 0x0
2101#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ 1788#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
2102#define nMATCH_EN_3_3 0x0
2103#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ 1789#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
2104#define nMATCH_EN_3_4 0x0
2105#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ 1790#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
2106#define nMATCH_EN_3_5 0x0
2107#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ 1791#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
2108#define nMATCH_EN_3_6 0x0
2109#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ 1792#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
2110#define nMATCH_EN_3_7 0x0
2111 1793
2112/* Bit masks for MXVR_PAT_EN_1 */ 1794/* Bit masks for MXVR_PAT_EN_1 */
2113 1795
2114#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */ 1796#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
2115#define nMATCH_EN_0_0 0x0
2116#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */ 1797#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
2117#define nMATCH_EN_0_1 0x0
2118#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */ 1798#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
2119#define nMATCH_EN_0_2 0x0
2120#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */ 1799#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
2121#define nMATCH_EN_0_3 0x0
2122#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */ 1800#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
2123#define nMATCH_EN_0_4 0x0
2124#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */ 1801#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
2125#define nMATCH_EN_0_5 0x0
2126#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */ 1802#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
2127#define nMATCH_EN_0_6 0x0
2128#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */ 1803#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
2129#define nMATCH_EN_0_7 0x0
2130#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */ 1804#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
2131#define nMATCH_EN_1_0 0x0
2132#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */ 1805#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
2133#define nMATCH_EN_1_1 0x0
2134#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */ 1806#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
2135#define nMATCH_EN_1_2 0x0
2136#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */ 1807#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
2137#define nMATCH_EN_1_3 0x0
2138#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */ 1808#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
2139#define nMATCH_EN_1_4 0x0
2140#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */ 1809#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
2141#define nMATCH_EN_1_5 0x0
2142#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */ 1810#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
2143#define nMATCH_EN_1_6 0x0
2144#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */ 1811#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
2145#define nMATCH_EN_1_7 0x0
2146#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */ 1812#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
2147#define nMATCH_EN_2_0 0x0
2148#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */ 1813#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
2149#define nMATCH_EN_2_1 0x0
2150#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */ 1814#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
2151#define nMATCH_EN_2_2 0x0
2152#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */ 1815#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
2153#define nMATCH_EN_2_3 0x0
2154#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */ 1816#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
2155#define nMATCH_EN_2_4 0x0
2156#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */ 1817#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
2157#define nMATCH_EN_2_5 0x0
2158#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */ 1818#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
2159#define nMATCH_EN_2_6 0x0
2160#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */ 1819#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
2161#define nMATCH_EN_2_7 0x0
2162#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */ 1820#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
2163#define nMATCH_EN_3_0 0x0
2164#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */ 1821#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
2165#define nMATCH_EN_3_1 0x0
2166#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */ 1822#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
2167#define nMATCH_EN_3_2 0x0
2168#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */ 1823#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
2169#define nMATCH_EN_3_3 0x0
2170#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */ 1824#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
2171#define nMATCH_EN_3_4 0x0
2172#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */ 1825#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
2173#define nMATCH_EN_3_5 0x0
2174#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */ 1826#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
2175#define nMATCH_EN_3_6 0x0
2176#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */ 1827#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
2177#define nMATCH_EN_3_7 0x0
2178 1828
2179/* Bit masks for MXVR_FRAME_CNT_0 */ 1829/* Bit masks for MXVR_FRAME_CNT_0 */
2180 1830
@@ -2188,226 +1838,166 @@
2188 1838
2189#define TX_CH0 0x3f /* Transmit Channel 0 */ 1839#define TX_CH0 0x3f /* Transmit Channel 0 */
2190#define MUTE_CH0 0x80 /* Mute Channel 0 */ 1840#define MUTE_CH0 0x80 /* Mute Channel 0 */
2191#define nMUTE_CH0 0x0
2192#define TX_CH1 0x3f00 /* Transmit Channel 0 */ 1841#define TX_CH1 0x3f00 /* Transmit Channel 0 */
2193#define MUTE_CH1 0x8000 /* Mute Channel 0 */ 1842#define MUTE_CH1 0x8000 /* Mute Channel 0 */
2194#define nMUTE_CH1 0x0
2195#define TX_CH2 0x3f0000 /* Transmit Channel 0 */ 1843#define TX_CH2 0x3f0000 /* Transmit Channel 0 */
2196#define MUTE_CH2 0x800000 /* Mute Channel 0 */ 1844#define MUTE_CH2 0x800000 /* Mute Channel 0 */
2197#define nMUTE_CH2 0x0
2198#define TX_CH3 0x3f000000 /* Transmit Channel 0 */ 1845#define TX_CH3 0x3f000000 /* Transmit Channel 0 */
2199#define MUTE_CH3 0x80000000 /* Mute Channel 0 */ 1846#define MUTE_CH3 0x80000000 /* Mute Channel 0 */
2200#define nMUTE_CH3 0x0
2201 1847
2202/* Bit masks for MXVR_ROUTING_1 */ 1848/* Bit masks for MXVR_ROUTING_1 */
2203 1849
2204#define TX_CH4 0x3f /* Transmit Channel 4 */ 1850#define TX_CH4 0x3f /* Transmit Channel 4 */
2205#define MUTE_CH4 0x80 /* Mute Channel 4 */ 1851#define MUTE_CH4 0x80 /* Mute Channel 4 */
2206#define nMUTE_CH4 0x0
2207#define TX_CH5 0x3f00 /* Transmit Channel 5 */ 1852#define TX_CH5 0x3f00 /* Transmit Channel 5 */
2208#define MUTE_CH5 0x8000 /* Mute Channel 5 */ 1853#define MUTE_CH5 0x8000 /* Mute Channel 5 */
2209#define nMUTE_CH5 0x0
2210#define TX_CH6 0x3f0000 /* Transmit Channel 6 */ 1854#define TX_CH6 0x3f0000 /* Transmit Channel 6 */
2211#define MUTE_CH6 0x800000 /* Mute Channel 6 */ 1855#define MUTE_CH6 0x800000 /* Mute Channel 6 */
2212#define nMUTE_CH6 0x0
2213#define TX_CH7 0x3f000000 /* Transmit Channel 7 */ 1856#define TX_CH7 0x3f000000 /* Transmit Channel 7 */
2214#define MUTE_CH7 0x80000000 /* Mute Channel 7 */ 1857#define MUTE_CH7 0x80000000 /* Mute Channel 7 */
2215#define nMUTE_CH7 0x0
2216 1858
2217/* Bit masks for MXVR_ROUTING_2 */ 1859/* Bit masks for MXVR_ROUTING_2 */
2218 1860
2219#define TX_CH8 0x3f /* Transmit Channel 8 */ 1861#define TX_CH8 0x3f /* Transmit Channel 8 */
2220#define MUTE_CH8 0x80 /* Mute Channel 8 */ 1862#define MUTE_CH8 0x80 /* Mute Channel 8 */
2221#define nMUTE_CH8 0x0
2222#define TX_CH9 0x3f00 /* Transmit Channel 9 */ 1863#define TX_CH9 0x3f00 /* Transmit Channel 9 */
2223#define MUTE_CH9 0x8000 /* Mute Channel 9 */ 1864#define MUTE_CH9 0x8000 /* Mute Channel 9 */
2224#define nMUTE_CH9 0x0
2225#define TX_CH10 0x3f0000 /* Transmit Channel 10 */ 1865#define TX_CH10 0x3f0000 /* Transmit Channel 10 */
2226#define MUTE_CH10 0x800000 /* Mute Channel 10 */ 1866#define MUTE_CH10 0x800000 /* Mute Channel 10 */
2227#define nMUTE_CH10 0x0
2228#define TX_CH11 0x3f000000 /* Transmit Channel 11 */ 1867#define TX_CH11 0x3f000000 /* Transmit Channel 11 */
2229#define MUTE_CH11 0x80000000 /* Mute Channel 11 */ 1868#define MUTE_CH11 0x80000000 /* Mute Channel 11 */
2230#define nMUTE_CH11 0x0
2231 1869
2232/* Bit masks for MXVR_ROUTING_3 */ 1870/* Bit masks for MXVR_ROUTING_3 */
2233 1871
2234#define TX_CH12 0x3f /* Transmit Channel 12 */ 1872#define TX_CH12 0x3f /* Transmit Channel 12 */
2235#define MUTE_CH12 0x80 /* Mute Channel 12 */ 1873#define MUTE_CH12 0x80 /* Mute Channel 12 */
2236#define nMUTE_CH12 0x0
2237#define TX_CH13 0x3f00 /* Transmit Channel 13 */ 1874#define TX_CH13 0x3f00 /* Transmit Channel 13 */
2238#define MUTE_CH13 0x8000 /* Mute Channel 13 */ 1875#define MUTE_CH13 0x8000 /* Mute Channel 13 */
2239#define nMUTE_CH13 0x0
2240#define TX_CH14 0x3f0000 /* Transmit Channel 14 */ 1876#define TX_CH14 0x3f0000 /* Transmit Channel 14 */
2241#define MUTE_CH14 0x800000 /* Mute Channel 14 */ 1877#define MUTE_CH14 0x800000 /* Mute Channel 14 */
2242#define nMUTE_CH14 0x0
2243#define TX_CH15 0x3f000000 /* Transmit Channel 15 */ 1878#define TX_CH15 0x3f000000 /* Transmit Channel 15 */
2244#define MUTE_CH15 0x80000000 /* Mute Channel 15 */ 1879#define MUTE_CH15 0x80000000 /* Mute Channel 15 */
2245#define nMUTE_CH15 0x0
2246 1880
2247/* Bit masks for MXVR_ROUTING_4 */ 1881/* Bit masks for MXVR_ROUTING_4 */
2248 1882
2249#define TX_CH16 0x3f /* Transmit Channel 16 */ 1883#define TX_CH16 0x3f /* Transmit Channel 16 */
2250#define MUTE_CH16 0x80 /* Mute Channel 16 */ 1884#define MUTE_CH16 0x80 /* Mute Channel 16 */
2251#define nMUTE_CH16 0x0
2252#define TX_CH17 0x3f00 /* Transmit Channel 17 */ 1885#define TX_CH17 0x3f00 /* Transmit Channel 17 */
2253#define MUTE_CH17 0x8000 /* Mute Channel 17 */ 1886#define MUTE_CH17 0x8000 /* Mute Channel 17 */
2254#define nMUTE_CH17 0x0
2255#define TX_CH18 0x3f0000 /* Transmit Channel 18 */ 1887#define TX_CH18 0x3f0000 /* Transmit Channel 18 */
2256#define MUTE_CH18 0x800000 /* Mute Channel 18 */ 1888#define MUTE_CH18 0x800000 /* Mute Channel 18 */
2257#define nMUTE_CH18 0x0
2258#define TX_CH19 0x3f000000 /* Transmit Channel 19 */ 1889#define TX_CH19 0x3f000000 /* Transmit Channel 19 */
2259#define MUTE_CH19 0x80000000 /* Mute Channel 19 */ 1890#define MUTE_CH19 0x80000000 /* Mute Channel 19 */
2260#define nMUTE_CH19 0x0
2261 1891
2262/* Bit masks for MXVR_ROUTING_5 */ 1892/* Bit masks for MXVR_ROUTING_5 */
2263 1893
2264#define TX_CH20 0x3f /* Transmit Channel 20 */ 1894#define TX_CH20 0x3f /* Transmit Channel 20 */
2265#define MUTE_CH20 0x80 /* Mute Channel 20 */ 1895#define MUTE_CH20 0x80 /* Mute Channel 20 */
2266#define nMUTE_CH20 0x0
2267#define TX_CH21 0x3f00 /* Transmit Channel 21 */ 1896#define TX_CH21 0x3f00 /* Transmit Channel 21 */
2268#define MUTE_CH21 0x8000 /* Mute Channel 21 */ 1897#define MUTE_CH21 0x8000 /* Mute Channel 21 */
2269#define nMUTE_CH21 0x0
2270#define TX_CH22 0x3f0000 /* Transmit Channel 22 */ 1898#define TX_CH22 0x3f0000 /* Transmit Channel 22 */
2271#define MUTE_CH22 0x800000 /* Mute Channel 22 */ 1899#define MUTE_CH22 0x800000 /* Mute Channel 22 */
2272#define nMUTE_CH22 0x0
2273#define TX_CH23 0x3f000000 /* Transmit Channel 23 */ 1900#define TX_CH23 0x3f000000 /* Transmit Channel 23 */
2274#define MUTE_CH23 0x80000000 /* Mute Channel 23 */ 1901#define MUTE_CH23 0x80000000 /* Mute Channel 23 */
2275#define nMUTE_CH23 0x0
2276 1902
2277/* Bit masks for MXVR_ROUTING_6 */ 1903/* Bit masks for MXVR_ROUTING_6 */
2278 1904
2279#define TX_CH24 0x3f /* Transmit Channel 24 */ 1905#define TX_CH24 0x3f /* Transmit Channel 24 */
2280#define MUTE_CH24 0x80 /* Mute Channel 24 */ 1906#define MUTE_CH24 0x80 /* Mute Channel 24 */
2281#define nMUTE_CH24 0x0
2282#define TX_CH25 0x3f00 /* Transmit Channel 25 */ 1907#define TX_CH25 0x3f00 /* Transmit Channel 25 */
2283#define MUTE_CH25 0x8000 /* Mute Channel 25 */ 1908#define MUTE_CH25 0x8000 /* Mute Channel 25 */
2284#define nMUTE_CH25 0x0
2285#define TX_CH26 0x3f0000 /* Transmit Channel 26 */ 1909#define TX_CH26 0x3f0000 /* Transmit Channel 26 */
2286#define MUTE_CH26 0x800000 /* Mute Channel 26 */ 1910#define MUTE_CH26 0x800000 /* Mute Channel 26 */
2287#define nMUTE_CH26 0x0
2288#define TX_CH27 0x3f000000 /* Transmit Channel 27 */ 1911#define TX_CH27 0x3f000000 /* Transmit Channel 27 */
2289#define MUTE_CH27 0x80000000 /* Mute Channel 27 */ 1912#define MUTE_CH27 0x80000000 /* Mute Channel 27 */
2290#define nMUTE_CH27 0x0
2291 1913
2292/* Bit masks for MXVR_ROUTING_7 */ 1914/* Bit masks for MXVR_ROUTING_7 */
2293 1915
2294#define TX_CH28 0x3f /* Transmit Channel 28 */ 1916#define TX_CH28 0x3f /* Transmit Channel 28 */
2295#define MUTE_CH28 0x80 /* Mute Channel 28 */ 1917#define MUTE_CH28 0x80 /* Mute Channel 28 */
2296#define nMUTE_CH28 0x0
2297#define TX_CH29 0x3f00 /* Transmit Channel 29 */ 1918#define TX_CH29 0x3f00 /* Transmit Channel 29 */
2298#define MUTE_CH29 0x8000 /* Mute Channel 29 */ 1919#define MUTE_CH29 0x8000 /* Mute Channel 29 */
2299#define nMUTE_CH29 0x0
2300#define TX_CH30 0x3f0000 /* Transmit Channel 30 */ 1920#define TX_CH30 0x3f0000 /* Transmit Channel 30 */
2301#define MUTE_CH30 0x800000 /* Mute Channel 30 */ 1921#define MUTE_CH30 0x800000 /* Mute Channel 30 */
2302#define nMUTE_CH30 0x0
2303#define TX_CH31 0x3f000000 /* Transmit Channel 31 */ 1922#define TX_CH31 0x3f000000 /* Transmit Channel 31 */
2304#define MUTE_CH31 0x80000000 /* Mute Channel 31 */ 1923#define MUTE_CH31 0x80000000 /* Mute Channel 31 */
2305#define nMUTE_CH31 0x0
2306 1924
2307/* Bit masks for MXVR_ROUTING_8 */ 1925/* Bit masks for MXVR_ROUTING_8 */
2308 1926
2309#define TX_CH32 0x3f /* Transmit Channel 32 */ 1927#define TX_CH32 0x3f /* Transmit Channel 32 */
2310#define MUTE_CH32 0x80 /* Mute Channel 32 */ 1928#define MUTE_CH32 0x80 /* Mute Channel 32 */
2311#define nMUTE_CH32 0x0
2312#define TX_CH33 0x3f00 /* Transmit Channel 33 */ 1929#define TX_CH33 0x3f00 /* Transmit Channel 33 */
2313#define MUTE_CH33 0x8000 /* Mute Channel 33 */ 1930#define MUTE_CH33 0x8000 /* Mute Channel 33 */
2314#define nMUTE_CH33 0x0
2315#define TX_CH34 0x3f0000 /* Transmit Channel 34 */ 1931#define TX_CH34 0x3f0000 /* Transmit Channel 34 */
2316#define MUTE_CH34 0x800000 /* Mute Channel 34 */ 1932#define MUTE_CH34 0x800000 /* Mute Channel 34 */
2317#define nMUTE_CH34 0x0
2318#define TX_CH35 0x3f000000 /* Transmit Channel 35 */ 1933#define TX_CH35 0x3f000000 /* Transmit Channel 35 */
2319#define MUTE_CH35 0x80000000 /* Mute Channel 35 */ 1934#define MUTE_CH35 0x80000000 /* Mute Channel 35 */
2320#define nMUTE_CH35 0x0
2321 1935
2322/* Bit masks for MXVR_ROUTING_9 */ 1936/* Bit masks for MXVR_ROUTING_9 */
2323 1937
2324#define TX_CH36 0x3f /* Transmit Channel 36 */ 1938#define TX_CH36 0x3f /* Transmit Channel 36 */
2325#define MUTE_CH36 0x80 /* Mute Channel 36 */ 1939#define MUTE_CH36 0x80 /* Mute Channel 36 */
2326#define nMUTE_CH36 0x0
2327#define TX_CH37 0x3f00 /* Transmit Channel 37 */ 1940#define TX_CH37 0x3f00 /* Transmit Channel 37 */
2328#define MUTE_CH37 0x8000 /* Mute Channel 37 */ 1941#define MUTE_CH37 0x8000 /* Mute Channel 37 */
2329#define nMUTE_CH37 0x0
2330#define TX_CH38 0x3f0000 /* Transmit Channel 38 */ 1942#define TX_CH38 0x3f0000 /* Transmit Channel 38 */
2331#define MUTE_CH38 0x800000 /* Mute Channel 38 */ 1943#define MUTE_CH38 0x800000 /* Mute Channel 38 */
2332#define nMUTE_CH38 0x0
2333#define TX_CH39 0x3f000000 /* Transmit Channel 39 */ 1944#define TX_CH39 0x3f000000 /* Transmit Channel 39 */
2334#define MUTE_CH39 0x80000000 /* Mute Channel 39 */ 1945#define MUTE_CH39 0x80000000 /* Mute Channel 39 */
2335#define nMUTE_CH39 0x0
2336 1946
2337/* Bit masks for MXVR_ROUTING_10 */ 1947/* Bit masks for MXVR_ROUTING_10 */
2338 1948
2339#define TX_CH40 0x3f /* Transmit Channel 40 */ 1949#define TX_CH40 0x3f /* Transmit Channel 40 */
2340#define MUTE_CH40 0x80 /* Mute Channel 40 */ 1950#define MUTE_CH40 0x80 /* Mute Channel 40 */
2341#define nMUTE_CH40 0x0
2342#define TX_CH41 0x3f00 /* Transmit Channel 41 */ 1951#define TX_CH41 0x3f00 /* Transmit Channel 41 */
2343#define MUTE_CH41 0x8000 /* Mute Channel 41 */ 1952#define MUTE_CH41 0x8000 /* Mute Channel 41 */
2344#define nMUTE_CH41 0x0
2345#define TX_CH42 0x3f0000 /* Transmit Channel 42 */ 1953#define TX_CH42 0x3f0000 /* Transmit Channel 42 */
2346#define MUTE_CH42 0x800000 /* Mute Channel 42 */ 1954#define MUTE_CH42 0x800000 /* Mute Channel 42 */
2347#define nMUTE_CH42 0x0
2348#define TX_CH43 0x3f000000 /* Transmit Channel 43 */ 1955#define TX_CH43 0x3f000000 /* Transmit Channel 43 */
2349#define MUTE_CH43 0x80000000 /* Mute Channel 43 */ 1956#define MUTE_CH43 0x80000000 /* Mute Channel 43 */
2350#define nMUTE_CH43 0x0
2351 1957
2352/* Bit masks for MXVR_ROUTING_11 */ 1958/* Bit masks for MXVR_ROUTING_11 */
2353 1959
2354#define TX_CH44 0x3f /* Transmit Channel 44 */ 1960#define TX_CH44 0x3f /* Transmit Channel 44 */
2355#define MUTE_CH44 0x80 /* Mute Channel 44 */ 1961#define MUTE_CH44 0x80 /* Mute Channel 44 */
2356#define nMUTE_CH44 0x0
2357#define TX_CH45 0x3f00 /* Transmit Channel 45 */ 1962#define TX_CH45 0x3f00 /* Transmit Channel 45 */
2358#define MUTE_CH45 0x8000 /* Mute Channel 45 */ 1963#define MUTE_CH45 0x8000 /* Mute Channel 45 */
2359#define nMUTE_CH45 0x0
2360#define TX_CH46 0x3f0000 /* Transmit Channel 46 */ 1964#define TX_CH46 0x3f0000 /* Transmit Channel 46 */
2361#define MUTE_CH46 0x800000 /* Mute Channel 46 */ 1965#define MUTE_CH46 0x800000 /* Mute Channel 46 */
2362#define nMUTE_CH46 0x0
2363#define TX_CH47 0x3f000000 /* Transmit Channel 47 */ 1966#define TX_CH47 0x3f000000 /* Transmit Channel 47 */
2364#define MUTE_CH47 0x80000000 /* Mute Channel 47 */ 1967#define MUTE_CH47 0x80000000 /* Mute Channel 47 */
2365#define nMUTE_CH47 0x0
2366 1968
2367/* Bit masks for MXVR_ROUTING_12 */ 1969/* Bit masks for MXVR_ROUTING_12 */
2368 1970
2369#define TX_CH48 0x3f /* Transmit Channel 48 */ 1971#define TX_CH48 0x3f /* Transmit Channel 48 */
2370#define MUTE_CH48 0x80 /* Mute Channel 48 */ 1972#define MUTE_CH48 0x80 /* Mute Channel 48 */
2371#define nMUTE_CH48 0x0
2372#define TX_CH49 0x3f00 /* Transmit Channel 49 */ 1973#define TX_CH49 0x3f00 /* Transmit Channel 49 */
2373#define MUTE_CH49 0x8000 /* Mute Channel 49 */ 1974#define MUTE_CH49 0x8000 /* Mute Channel 49 */
2374#define nMUTE_CH49 0x0
2375#define TX_CH50 0x3f0000 /* Transmit Channel 50 */ 1975#define TX_CH50 0x3f0000 /* Transmit Channel 50 */
2376#define MUTE_CH50 0x800000 /* Mute Channel 50 */ 1976#define MUTE_CH50 0x800000 /* Mute Channel 50 */
2377#define nMUTE_CH50 0x0
2378#define TX_CH51 0x3f000000 /* Transmit Channel 51 */ 1977#define TX_CH51 0x3f000000 /* Transmit Channel 51 */
2379#define MUTE_CH51 0x80000000 /* Mute Channel 51 */ 1978#define MUTE_CH51 0x80000000 /* Mute Channel 51 */
2380#define nMUTE_CH51 0x0
2381 1979
2382/* Bit masks for MXVR_ROUTING_13 */ 1980/* Bit masks for MXVR_ROUTING_13 */
2383 1981
2384#define TX_CH52 0x3f /* Transmit Channel 52 */ 1982#define TX_CH52 0x3f /* Transmit Channel 52 */
2385#define MUTE_CH52 0x80 /* Mute Channel 52 */ 1983#define MUTE_CH52 0x80 /* Mute Channel 52 */
2386#define nMUTE_CH52 0x0
2387#define TX_CH53 0x3f00 /* Transmit Channel 53 */ 1984#define TX_CH53 0x3f00 /* Transmit Channel 53 */
2388#define MUTE_CH53 0x8000 /* Mute Channel 53 */ 1985#define MUTE_CH53 0x8000 /* Mute Channel 53 */
2389#define nMUTE_CH53 0x0
2390#define TX_CH54 0x3f0000 /* Transmit Channel 54 */ 1986#define TX_CH54 0x3f0000 /* Transmit Channel 54 */
2391#define MUTE_CH54 0x800000 /* Mute Channel 54 */ 1987#define MUTE_CH54 0x800000 /* Mute Channel 54 */
2392#define nMUTE_CH54 0x0
2393#define TX_CH55 0x3f000000 /* Transmit Channel 55 */ 1988#define TX_CH55 0x3f000000 /* Transmit Channel 55 */
2394#define MUTE_CH55 0x80000000 /* Mute Channel 55 */ 1989#define MUTE_CH55 0x80000000 /* Mute Channel 55 */
2395#define nMUTE_CH55 0x0
2396 1990
2397/* Bit masks for MXVR_ROUTING_14 */ 1991/* Bit masks for MXVR_ROUTING_14 */
2398 1992
2399#define TX_CH56 0x3f /* Transmit Channel 56 */ 1993#define TX_CH56 0x3f /* Transmit Channel 56 */
2400#define MUTE_CH56 0x80 /* Mute Channel 56 */ 1994#define MUTE_CH56 0x80 /* Mute Channel 56 */
2401#define nMUTE_CH56 0x0
2402#define TX_CH57 0x3f00 /* Transmit Channel 57 */ 1995#define TX_CH57 0x3f00 /* Transmit Channel 57 */
2403#define MUTE_CH57 0x8000 /* Mute Channel 57 */ 1996#define MUTE_CH57 0x8000 /* Mute Channel 57 */
2404#define nMUTE_CH57 0x0
2405#define TX_CH58 0x3f0000 /* Transmit Channel 58 */ 1997#define TX_CH58 0x3f0000 /* Transmit Channel 58 */
2406#define MUTE_CH58 0x800000 /* Mute Channel 58 */ 1998#define MUTE_CH58 0x800000 /* Mute Channel 58 */
2407#define nMUTE_CH58 0x0
2408#define TX_CH59 0x3f000000 /* Transmit Channel 59 */ 1999#define TX_CH59 0x3f000000 /* Transmit Channel 59 */
2409#define MUTE_CH59 0x80000000 /* Mute Channel 59 */ 2000#define MUTE_CH59 0x80000000 /* Mute Channel 59 */
2410#define nMUTE_CH59 0x0
2411 2001
2412/* Bit masks for MXVR_BLOCK_CNT */ 2002/* Bit masks for MXVR_BLOCK_CNT */
2413 2003
@@ -2416,53 +2006,37 @@
2416/* Bit masks for MXVR_CLK_CTL */ 2006/* Bit masks for MXVR_CLK_CTL */
2417 2007
2418#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */ 2008#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */
2419#define nMXTALCEN 0x0
2420#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */ 2009#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */
2421#define nMXTALFEN 0x0
2422#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */ 2010#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */
2423#define CLKX3SEL 0x80 /* Clock Generation Source Select */ 2011#define CLKX3SEL 0x80 /* Clock Generation Source Select */
2424#define nCLKX3SEL 0x0
2425#define MMCLKEN 0x100 /* Master Clock Enable */ 2012#define MMCLKEN 0x100 /* Master Clock Enable */
2426#define nMMCLKEN 0x0
2427#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */ 2013#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */
2428#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */ 2014#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */
2429#define MBCLKEN 0x10000 /* Bit Clock Enable */ 2015#define MBCLKEN 0x10000 /* Bit Clock Enable */
2430#define nMBCLKEN 0x0
2431#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */ 2016#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */
2432#define INVRX 0x800000 /* Invert Receive Data */ 2017#define INVRX 0x800000 /* Invert Receive Data */
2433#define nINVRX 0x0
2434#define MFSEN 0x1000000 /* Frame Sync Enable */ 2018#define MFSEN 0x1000000 /* Frame Sync Enable */
2435#define nMFSEN 0x0
2436#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */ 2019#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */
2437#define MFSSEL 0x60000000 /* Frame Sync Select */ 2020#define MFSSEL 0x60000000 /* Frame Sync Select */
2438#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */ 2021#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */
2439#define nMFSSYNC 0x0
2440 2022
2441/* Bit masks for MXVR_CDRPLL_CTL */ 2023/* Bit masks for MXVR_CDRPLL_CTL */
2442 2024
2443#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */ 2025#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */
2444#define nCDRSMEN 0x0
2445#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */ 2026#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */
2446#define nCDRRSTB 0x0
2447#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */ 2027#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */
2448#define nCDRSVCO 0x0
2449#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */ 2028#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */
2450#define nCDRMODE 0x0
2451#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */ 2029#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */
2452#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */ 2030#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */
2453#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */ 2031#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */
2454#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */ 2032#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */
2455#define nCDRSHPEN 0x0
2456#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */ 2033#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
2457 2034
2458/* Bit masks for MXVR_FMPLL_CTL */ 2035/* Bit masks for MXVR_FMPLL_CTL */
2459 2036
2460#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */ 2037#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */
2461#define nFMSMEN 0x0
2462#define FMRSTB 0x2 /* MXVR FMPLL Reset */ 2038#define FMRSTB 0x2 /* MXVR FMPLL Reset */
2463#define nFMRSTB 0x0
2464#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */ 2039#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */
2465#define nFMSVCO 0x0
2466#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */ 2040#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */
2467#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */ 2041#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */
2468#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */ 2042#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */
@@ -2470,15 +2044,10 @@
2470/* Bit masks for MXVR_PIN_CTL */ 2044/* Bit masks for MXVR_PIN_CTL */
2471 2045
2472#define MTXONBOD 0x1 /* MTXONB Open Drain Select */ 2046#define MTXONBOD 0x1 /* MTXONB Open Drain Select */
2473#define nMTXONBOD 0x0
2474#define MTXONBG 0x2 /* MTXONB Gates MTX Select */ 2047#define MTXONBG 0x2 /* MTXONB Gates MTX Select */
2475#define nMTXONBG 0x0
2476#define MFSOE 0x10 /* MFS Output Enable */ 2048#define MFSOE 0x10 /* MFS Output Enable */
2477#define nMFSOE 0x0
2478#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */ 2049#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */
2479#define nMFSGPSEL 0x0
2480#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */ 2050#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */
2481#define nMFSGPDAT 0x0
2482 2051
2483/* Bit masks for MXVR_SCLK_CNT */ 2052/* Bit masks for MXVR_SCLK_CNT */
2484 2053
@@ -2487,7 +2056,6 @@
2487/* Bit masks for KPAD_CTL */ 2056/* Bit masks for KPAD_CTL */
2488 2057
2489#define KPAD_EN 0x1 /* Keypad Enable */ 2058#define KPAD_EN 0x1 /* Keypad Enable */
2490#define nKPAD_EN 0x0
2491#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */ 2059#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
2492#define KPAD_ROWEN 0x1c00 /* Row Enable Width */ 2060#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
2493#define KPAD_COLEN 0xe000 /* Column Enable Width */ 2061#define KPAD_COLEN 0xe000 /* Column Enable Width */
@@ -2509,29 +2077,21 @@
2509/* Bit masks for KPAD_STAT */ 2077/* Bit masks for KPAD_STAT */
2510 2078
2511#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */ 2079#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
2512#define nKPAD_IRQ 0x0
2513#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */ 2080#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
2514#define KPAD_PRESSED 0x8 /* Key press current status */ 2081#define KPAD_PRESSED 0x8 /* Key press current status */
2515#define nKPAD_PRESSED 0x0
2516 2082
2517/* Bit masks for KPAD_SOFTEVAL */ 2083/* Bit masks for KPAD_SOFTEVAL */
2518 2084
2519#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */ 2085#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
2520#define nKPAD_SOFTEVAL_E 0x0
2521 2086
2522/* Bit masks for SDH_COMMAND */ 2087/* Bit masks for SDH_COMMAND */
2523 2088
2524#define CMD_IDX 0x3f /* Command Index */ 2089#define CMD_IDX 0x3f /* Command Index */
2525#define CMD_RSP 0x40 /* Response */ 2090#define CMD_RSP 0x40 /* Response */
2526#define nCMD_RSP 0x0
2527#define CMD_L_RSP 0x80 /* Long Response */ 2091#define CMD_L_RSP 0x80 /* Long Response */
2528#define nCMD_L_RSP 0x0
2529#define CMD_INT_E 0x100 /* Command Interrupt */ 2092#define CMD_INT_E 0x100 /* Command Interrupt */
2530#define nCMD_INT_E 0x0
2531#define CMD_PEND_E 0x200 /* Command Pending */ 2093#define CMD_PEND_E 0x200 /* Command Pending */
2532#define nCMD_PEND_E 0x0
2533#define CMD_E 0x400 /* Command Enable */ 2094#define CMD_E 0x400 /* Command Enable */
2534#define nCMD_E 0x0
2535 2095
2536/* Bit masks for SDH_PWR_CTL */ 2096/* Bit masks for SDH_PWR_CTL */
2537 2097
@@ -2540,21 +2100,15 @@
2540#define TBD 0x3c /* TBD */ 2100#define TBD 0x3c /* TBD */
2541#endif 2101#endif
2542#define SD_CMD_OD 0x40 /* Open Drain Output */ 2102#define SD_CMD_OD 0x40 /* Open Drain Output */
2543#define nSD_CMD_OD 0x0
2544#define ROD_CTL 0x80 /* Rod Control */ 2103#define ROD_CTL 0x80 /* Rod Control */
2545#define nROD_CTL 0x0
2546 2104
2547/* Bit masks for SDH_CLK_CTL */ 2105/* Bit masks for SDH_CLK_CTL */
2548 2106
2549#define CLKDIV 0xff /* MC_CLK Divisor */ 2107#define CLKDIV 0xff /* MC_CLK Divisor */
2550#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ 2108#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
2551#define nCLK_E 0x0
2552#define PWR_SV_E 0x200 /* Power Save Enable */ 2109#define PWR_SV_E 0x200 /* Power Save Enable */
2553#define nPWR_SV_E 0x0
2554#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ 2110#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
2555#define nCLKDIV_BYPASS 0x0
2556#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ 2111#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
2557#define nWIDE_BUS 0x0
2558 2112
2559/* Bit masks for SDH_RESP_CMD */ 2113/* Bit masks for SDH_RESP_CMD */
2560 2114
@@ -2563,133 +2117,74 @@
2563/* Bit masks for SDH_DATA_CTL */ 2117/* Bit masks for SDH_DATA_CTL */
2564 2118
2565#define DTX_E 0x1 /* Data Transfer Enable */ 2119#define DTX_E 0x1 /* Data Transfer Enable */
2566#define nDTX_E 0x0
2567#define DTX_DIR 0x2 /* Data Transfer Direction */ 2120#define DTX_DIR 0x2 /* Data Transfer Direction */
2568#define nDTX_DIR 0x0
2569#define DTX_MODE 0x4 /* Data Transfer Mode */ 2121#define DTX_MODE 0x4 /* Data Transfer Mode */
2570#define nDTX_MODE 0x0
2571#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ 2122#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
2572#define nDTX_DMA_E 0x0
2573#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ 2123#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
2574 2124
2575/* Bit masks for SDH_STATUS */ 2125/* Bit masks for SDH_STATUS */
2576 2126
2577#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ 2127#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
2578#define nCMD_CRC_FAIL 0x0
2579#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ 2128#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
2580#define nDAT_CRC_FAIL 0x0 2129#define CMD_TIME_OUT 0x4 /* CMD Time Out */
2581#define CMD_TIMEOUT 0x4 /* CMD Time Out */ 2130#define DAT_TIME_OUT 0x8 /* Data Time Out */
2582#define nCMD_TIMEOUT 0x0
2583#define DAT_TIMEOUT 0x8 /* Data Time Out */
2584#define nDAT_TIMEOUT 0x0
2585#define TX_UNDERRUN 0x10 /* Transmit Underrun */ 2131#define TX_UNDERRUN 0x10 /* Transmit Underrun */
2586#define nTX_UNDERRUN 0x0
2587#define RX_OVERRUN 0x20 /* Receive Overrun */ 2132#define RX_OVERRUN 0x20 /* Receive Overrun */
2588#define nRX_OVERRUN 0x0
2589#define CMD_RESP_END 0x40 /* CMD Response End */ 2133#define CMD_RESP_END 0x40 /* CMD Response End */
2590#define nCMD_RESP_END 0x0
2591#define CMD_SENT 0x80 /* CMD Sent */ 2134#define CMD_SENT 0x80 /* CMD Sent */
2592#define nCMD_SENT 0x0
2593#define DAT_END 0x100 /* Data End */ 2135#define DAT_END 0x100 /* Data End */
2594#define nDAT_END 0x0
2595#define START_BIT_ERR 0x200 /* Start Bit Error */ 2136#define START_BIT_ERR 0x200 /* Start Bit Error */
2596#define nSTART_BIT_ERR 0x0
2597#define DAT_BLK_END 0x400 /* Data Block End */ 2137#define DAT_BLK_END 0x400 /* Data Block End */
2598#define nDAT_BLK_END 0x0
2599#define CMD_ACT 0x800 /* CMD Active */ 2138#define CMD_ACT 0x800 /* CMD Active */
2600#define nCMD_ACT 0x0
2601#define TX_ACT 0x1000 /* Transmit Active */ 2139#define TX_ACT 0x1000 /* Transmit Active */
2602#define nTX_ACT 0x0
2603#define RX_ACT 0x2000 /* Receive Active */ 2140#define RX_ACT 0x2000 /* Receive Active */
2604#define nRX_ACT 0x0
2605#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ 2141#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
2606#define nTX_FIFO_STAT 0x0
2607#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ 2142#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
2608#define nRX_FIFO_STAT 0x0
2609#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ 2143#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
2610#define nTX_FIFO_FULL 0x0
2611#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ 2144#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
2612#define nRX_FIFO_FULL 0x0
2613#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ 2145#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
2614#define nTX_FIFO_ZERO 0x0
2615#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ 2146#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
2616#define nRX_DAT_ZERO 0x0
2617#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ 2147#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
2618#define nTX_DAT_RDY 0x0
2619#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ 2148#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
2620#define nRX_FIFO_RDY 0x0
2621 2149
2622/* Bit masks for SDH_STATUS_CLR */ 2150/* Bit masks for SDH_STATUS_CLR */
2623 2151
2624#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ 2152#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
2625#define nCMD_CRC_FAIL_STAT 0x0
2626#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ 2153#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
2627#define nDAT_CRC_FAIL_STAT 0x0
2628#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ 2154#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
2629#define nCMD_TIMEOUT_STAT 0x0
2630#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ 2155#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
2631#define nDAT_TIMEOUT_STAT 0x0
2632#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ 2156#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
2633#define nTX_UNDERRUN_STAT 0x0
2634#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ 2157#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
2635#define nRX_OVERRUN_STAT 0x0
2636#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ 2158#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
2637#define nCMD_RESP_END_STAT 0x0
2638#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ 2159#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
2639#define nCMD_SENT_STAT 0x0
2640#define DAT_END_STAT 0x100 /* Data End Status */ 2160#define DAT_END_STAT 0x100 /* Data End Status */
2641#define nDAT_END_STAT 0x0
2642#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ 2161#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
2643#define nSTART_BIT_ERR_STAT 0x0
2644#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ 2162#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
2645#define nDAT_BLK_END_STAT 0x0
2646 2163
2647/* Bit masks for SDH_MASK0 */ 2164/* Bit masks for SDH_MASK0 */
2648 2165
2649#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ 2166#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
2650#define nCMD_CRC_FAIL_MASK 0x0
2651#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ 2167#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
2652#define nDAT_CRC_FAIL_MASK 0x0
2653#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ 2168#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
2654#define nCMD_TIMEOUT_MASK 0x0
2655#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ 2169#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
2656#define nDAT_TIMEOUT_MASK 0x0
2657#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ 2170#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
2658#define nTX_UNDERRUN_MASK 0x0
2659#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ 2171#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
2660#define nRX_OVERRUN_MASK 0x0
2661#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ 2172#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
2662#define nCMD_RESP_END_MASK 0x0
2663#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ 2173#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
2664#define nCMD_SENT_MASK 0x0
2665#define DAT_END_MASK 0x100 /* Data End Mask */ 2174#define DAT_END_MASK 0x100 /* Data End Mask */
2666#define nDAT_END_MASK 0x0
2667#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ 2175#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
2668#define nSTART_BIT_ERR_MASK 0x0
2669#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ 2176#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
2670#define nDAT_BLK_END_MASK 0x0
2671#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ 2177#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
2672#define nCMD_ACT_MASK 0x0
2673#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ 2178#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
2674#define nTX_ACT_MASK 0x0
2675#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ 2179#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
2676#define nRX_ACT_MASK 0x0
2677#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ 2180#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
2678#define nTX_FIFO_STAT_MASK 0x0
2679#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ 2181#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
2680#define nRX_FIFO_STAT_MASK 0x0
2681#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ 2182#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
2682#define nTX_FIFO_FULL_MASK 0x0
2683#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ 2183#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
2684#define nRX_FIFO_FULL_MASK 0x0
2685#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ 2184#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
2686#define nTX_FIFO_ZERO_MASK 0x0
2687#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ 2185#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
2688#define nRX_DAT_ZERO_MASK 0x0
2689#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ 2186#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
2690#define nTX_DAT_RDY_MASK 0x0
2691#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ 2187#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
2692#define nRX_FIFO_RDY_MASK 0x0
2693 2188
2694/* Bit masks for SDH_FIFO_CNT */ 2189/* Bit masks for SDH_FIFO_CNT */
2695 2190
@@ -2698,73 +2193,47 @@
2698/* Bit masks for SDH_E_STATUS */ 2193/* Bit masks for SDH_E_STATUS */
2699 2194
2700#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ 2195#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
2701#define nSDIO_INT_DET 0x0
2702#define SD_CARD_DET 0x10 /* SD Card Detect */ 2196#define SD_CARD_DET 0x10 /* SD Card Detect */
2703#define nSD_CARD_DET 0x0
2704 2197
2705/* Bit masks for SDH_E_MASK */ 2198/* Bit masks for SDH_E_MASK */
2706 2199
2707#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ 2200#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
2708#define nSDIO_MSK 0x0
2709#define SCD_MSK 0x40 /* Mask Card Detect */ 2201#define SCD_MSK 0x40 /* Mask Card Detect */
2710#define nSCD_MSK 0x0
2711 2202
2712/* Bit masks for SDH_CFG */ 2203/* Bit masks for SDH_CFG */
2713 2204
2714#define CLKS_EN 0x1 /* Clocks Enable */ 2205#define CLKS_EN 0x1 /* Clocks Enable */
2715#define nCLKS_EN 0x0
2716#define SD4E 0x4 /* SDIO 4-Bit Enable */ 2206#define SD4E 0x4 /* SDIO 4-Bit Enable */
2717#define nSD4E 0x0
2718#define MWE 0x8 /* Moving Window Enable */ 2207#define MWE 0x8 /* Moving Window Enable */
2719#define nMWE 0x0
2720#define SD_RST 0x10 /* SDMMC Reset */ 2208#define SD_RST 0x10 /* SDMMC Reset */
2721#define nSD_RST 0x0
2722#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ 2209#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
2723#define nPUP_SDDAT 0x0
2724#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ 2210#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
2725#define nPUP_SDDAT3 0x0
2726#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ 2211#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
2727#define nPD_SDDAT3 0x0
2728 2212
2729/* Bit masks for SDH_RD_WAIT_EN */ 2213/* Bit masks for SDH_RD_WAIT_EN */
2730 2214
2731#define RWR 0x1 /* Read Wait Request */ 2215#define RWR 0x1 /* Read Wait Request */
2732#define nRWR 0x0
2733 2216
2734/* Bit masks for ATAPI_CONTROL */ 2217/* Bit masks for ATAPI_CONTROL */
2735 2218
2736#define PIO_START 0x1 /* Start PIO/Reg Op */ 2219#define PIO_START 0x1 /* Start PIO/Reg Op */
2737#define nPIO_START 0x0
2738#define MULTI_START 0x2 /* Start Multi-DMA Op */ 2220#define MULTI_START 0x2 /* Start Multi-DMA Op */
2739#define nMULTI_START 0x0
2740#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ 2221#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
2741#define nULTRA_START 0x0
2742#define XFER_DIR 0x8 /* Transfer Direction */ 2222#define XFER_DIR 0x8 /* Transfer Direction */
2743#define nXFER_DIR 0x0
2744#define IORDY_EN 0x10 /* IORDY Enable */ 2223#define IORDY_EN 0x10 /* IORDY Enable */
2745#define nIORDY_EN 0x0
2746#define FIFO_FLUSH 0x20 /* Flush FIFOs */ 2224#define FIFO_FLUSH 0x20 /* Flush FIFOs */
2747#define nFIFO_FLUSH 0x0
2748#define SOFT_RST 0x40 /* Soft Reset */ 2225#define SOFT_RST 0x40 /* Soft Reset */
2749#define nSOFT_RST 0x0
2750#define DEV_RST 0x80 /* Device Reset */ 2226#define DEV_RST 0x80 /* Device Reset */
2751#define nDEV_RST 0x0
2752#define TFRCNT_RST 0x100 /* Trans Count Reset */ 2227#define TFRCNT_RST 0x100 /* Trans Count Reset */
2753#define nTFRCNT_RST 0x0
2754#define END_ON_TERM 0x200 /* End/Terminate Select */ 2228#define END_ON_TERM 0x200 /* End/Terminate Select */
2755#define nEND_ON_TERM 0x0
2756#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ 2229#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
2757#define nPIO_USE_DMA 0x0
2758#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ 2230#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
2759 2231
2760/* Bit masks for ATAPI_STATUS */ 2232/* Bit masks for ATAPI_STATUS */
2761 2233
2762#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ 2234#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
2763#define nPIO_XFER_ON 0x0
2764#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ 2235#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
2765#define nMULTI_XFER_ON 0x0
2766#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ 2236#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
2767#define nULTRA_XFER_ON 0x0
2768#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ 2237#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
2769 2238
2770/* Bit masks for ATAPI_DEV_ADDR */ 2239/* Bit masks for ATAPI_DEV_ADDR */
@@ -2774,66 +2243,39 @@
2774/* Bit masks for ATAPI_INT_MASK */ 2243/* Bit masks for ATAPI_INT_MASK */
2775 2244
2776#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ 2245#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
2777#define nATAPI_DEV_INT_MASK 0x0
2778#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ 2246#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
2779#define nPIO_DONE_MASK 0x0
2780#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ 2247#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
2781#define nMULTI_DONE_MASK 0x0
2782#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ 2248#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
2783#define nUDMAIN_DONE_MASK 0x0
2784#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ 2249#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
2785#define nUDMAOUT_DONE_MASK 0x0
2786#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ 2250#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
2787#define nHOST_TERM_XFER_MASK 0x0
2788#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ 2251#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
2789#define nMULTI_TERM_MASK 0x0
2790#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ 2252#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
2791#define nUDMAIN_TERM_MASK 0x0
2792#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ 2253#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
2793#define nUDMAOUT_TERM_MASK 0x0
2794 2254
2795/* Bit masks for ATAPI_INT_STATUS */ 2255/* Bit masks for ATAPI_INT_STATUS */
2796 2256
2797#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ 2257#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
2798#define nATAPI_DEV_INT 0x0
2799#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ 2258#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
2800#define nPIO_DONE_INT 0x0
2801#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ 2259#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
2802#define nMULTI_DONE_INT 0x0
2803#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ 2260#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
2804#define nUDMAIN_DONE_INT 0x0
2805#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ 2261#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
2806#define nUDMAOUT_DONE_INT 0x0
2807#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ 2262#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
2808#define nHOST_TERM_XFER_INT 0x0
2809#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ 2263#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
2810#define nMULTI_TERM_INT 0x0
2811#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ 2264#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
2812#define nUDMAIN_TERM_INT 0x0
2813#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ 2265#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
2814#define nUDMAOUT_TERM_INT 0x0
2815 2266
2816/* Bit masks for ATAPI_LINE_STATUS */ 2267/* Bit masks for ATAPI_LINE_STATUS */
2817 2268
2818#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ 2269#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
2819#define nATAPI_INTR 0x0
2820#define ATAPI_DASP 0x2 /* Device dasp to host line status */ 2270#define ATAPI_DASP 0x2 /* Device dasp to host line status */
2821#define nATAPI_DASP 0x0
2822#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ 2271#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
2823#define nATAPI_CS0N 0x0
2824#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ 2272#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
2825#define nATAPI_CS1N 0x0
2826#define ATAPI_ADDR 0x70 /* ATAPI address line status */ 2273#define ATAPI_ADDR 0x70 /* ATAPI address line status */
2827#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ 2274#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
2828#define nATAPI_DMAREQ 0x0
2829#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ 2275#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
2830#define nATAPI_DMAACKN 0x0
2831#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ 2276#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
2832#define nATAPI_DIOWN 0x0
2833#define ATAPI_DIORN 0x400 /* ATAPI read line status */ 2277#define ATAPI_DIORN 0x400 /* ATAPI read line status */
2834#define nATAPI_DIORN 0x0
2835#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ 2278#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
2836#define nATAPI_IORDY 0x0
2837 2279
2838/* Bit masks for ATAPI_SM_STATE */ 2280/* Bit masks for ATAPI_SM_STATE */
2839 2281
@@ -2845,7 +2287,6 @@
2845/* Bit masks for ATAPI_TERMINATE */ 2287/* Bit masks for ATAPI_TERMINATE */
2846 2288
2847#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ 2289#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
2848#define nATAPI_HOST_TERM 0x0
2849 2290
2850/* Bit masks for ATAPI_REG_TIM_0 */ 2291/* Bit masks for ATAPI_REG_TIM_0 */
2851 2292
@@ -2900,41 +2341,26 @@
2900/* Bit masks for TIMER_ENABLE1 */ 2341/* Bit masks for TIMER_ENABLE1 */
2901 2342
2902#define TIMEN8 0x1 /* Timer 8 Enable */ 2343#define TIMEN8 0x1 /* Timer 8 Enable */
2903#define nTIMEN8 0x0
2904#define TIMEN9 0x2 /* Timer 9 Enable */ 2344#define TIMEN9 0x2 /* Timer 9 Enable */
2905#define nTIMEN9 0x0
2906#define TIMEN10 0x4 /* Timer 10 Enable */ 2345#define TIMEN10 0x4 /* Timer 10 Enable */
2907#define nTIMEN10 0x0
2908 2346
2909/* Bit masks for TIMER_DISABLE1 */ 2347/* Bit masks for TIMER_DISABLE1 */
2910 2348
2911#define TIMDIS8 0x1 /* Timer 8 Disable */ 2349#define TIMDIS8 0x1 /* Timer 8 Disable */
2912#define nTIMDIS8 0x0
2913#define TIMDIS9 0x2 /* Timer 9 Disable */ 2350#define TIMDIS9 0x2 /* Timer 9 Disable */
2914#define nTIMDIS9 0x0
2915#define TIMDIS10 0x4 /* Timer 10 Disable */ 2351#define TIMDIS10 0x4 /* Timer 10 Disable */
2916#define nTIMDIS10 0x0
2917 2352
2918/* Bit masks for TIMER_STATUS1 */ 2353/* Bit masks for TIMER_STATUS1 */
2919 2354
2920#define TIMIL8 0x1 /* Timer 8 Interrupt */ 2355#define TIMIL8 0x1 /* Timer 8 Interrupt */
2921#define nTIMIL8 0x0
2922#define TIMIL9 0x2 /* Timer 9 Interrupt */ 2356#define TIMIL9 0x2 /* Timer 9 Interrupt */
2923#define nTIMIL9 0x0
2924#define TIMIL10 0x4 /* Timer 10 Interrupt */ 2357#define TIMIL10 0x4 /* Timer 10 Interrupt */
2925#define nTIMIL10 0x0
2926#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */ 2358#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
2927#define nTOVF_ERR8 0x0
2928#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */ 2359#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
2929#define nTOVF_ERR9 0x0
2930#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */ 2360#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
2931#define nTOVF_ERR10 0x0
2932#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */ 2361#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
2933#define nTRUN8 0x0
2934#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */ 2362#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
2935#define nTRUN9 0x0
2936#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */ 2363#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
2937#define nTRUN10 0x0
2938 2364
2939/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ 2365/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
2940 2366
@@ -2945,131 +2371,77 @@
2945/* Bit masks for USB_POWER */ 2371/* Bit masks for USB_POWER */
2946 2372
2947#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ 2373#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
2948#define nENABLE_SUSPENDM 0x0
2949#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ 2374#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
2950#define nSUSPEND_MODE 0x0
2951#define RESUME_MODE 0x4 /* DMA Mode */ 2375#define RESUME_MODE 0x4 /* DMA Mode */
2952#define nRESUME_MODE 0x0
2953#define RESET 0x8 /* Reset indicator */ 2376#define RESET 0x8 /* Reset indicator */
2954#define nRESET 0x0
2955#define HS_MODE 0x10 /* High Speed mode indicator */ 2377#define HS_MODE 0x10 /* High Speed mode indicator */
2956#define nHS_MODE 0x0
2957#define HS_ENABLE 0x20 /* high Speed Enable */ 2378#define HS_ENABLE 0x20 /* high Speed Enable */
2958#define nHS_ENABLE 0x0
2959#define SOFT_CONN 0x40 /* Soft connect */ 2379#define SOFT_CONN 0x40 /* Soft connect */
2960#define nSOFT_CONN 0x0
2961#define ISO_UPDATE 0x80 /* Isochronous update */ 2380#define ISO_UPDATE 0x80 /* Isochronous update */
2962#define nISO_UPDATE 0x0
2963 2381
2964/* Bit masks for USB_INTRTX */ 2382/* Bit masks for USB_INTRTX */
2965 2383
2966#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ 2384#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
2967#define nEP0_TX 0x0
2968#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ 2385#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
2969#define nEP1_TX 0x0
2970#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ 2386#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
2971#define nEP2_TX 0x0
2972#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ 2387#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
2973#define nEP3_TX 0x0
2974#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ 2388#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
2975#define nEP4_TX 0x0
2976#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ 2389#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
2977#define nEP5_TX 0x0
2978#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ 2390#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
2979#define nEP6_TX 0x0
2980#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ 2391#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
2981#define nEP7_TX 0x0
2982 2392
2983/* Bit masks for USB_INTRRX */ 2393/* Bit masks for USB_INTRRX */
2984 2394
2985#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ 2395#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
2986#define nEP1_RX 0x0
2987#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ 2396#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
2988#define nEP2_RX 0x0
2989#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ 2397#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
2990#define nEP3_RX 0x0
2991#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ 2398#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
2992#define nEP4_RX 0x0
2993#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ 2399#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
2994#define nEP5_RX 0x0
2995#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ 2400#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
2996#define nEP6_RX 0x0
2997#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ 2401#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
2998#define nEP7_RX 0x0
2999 2402
3000/* Bit masks for USB_INTRTXE */ 2403/* Bit masks for USB_INTRTXE */
3001 2404
3002#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ 2405#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
3003#define nEP0_TX_E 0x0
3004#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */ 2406#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
3005#define nEP1_TX_E 0x0
3006#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */ 2407#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
3007#define nEP2_TX_E 0x0
3008#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */ 2408#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
3009#define nEP3_TX_E 0x0
3010#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */ 2409#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
3011#define nEP4_TX_E 0x0
3012#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */ 2410#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
3013#define nEP5_TX_E 0x0
3014#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */ 2411#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
3015#define nEP6_TX_E 0x0
3016#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */ 2412#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
3017#define nEP7_TX_E 0x0
3018 2413
3019/* Bit masks for USB_INTRRXE */ 2414/* Bit masks for USB_INTRRXE */
3020 2415
3021#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */ 2416#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
3022#define nEP1_RX_E 0x0
3023#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */ 2417#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
3024#define nEP2_RX_E 0x0
3025#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */ 2418#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
3026#define nEP3_RX_E 0x0
3027#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */ 2419#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
3028#define nEP4_RX_E 0x0
3029#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */ 2420#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
3030#define nEP5_RX_E 0x0
3031#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */ 2421#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
3032#define nEP6_RX_E 0x0
3033#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */ 2422#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
3034#define nEP7_RX_E 0x0
3035 2423
3036/* Bit masks for USB_INTRUSB */ 2424/* Bit masks for USB_INTRUSB */
3037 2425
3038#define SUSPEND_B 0x1 /* Suspend indicator */ 2426#define SUSPEND_B 0x1 /* Suspend indicator */
3039#define nSUSPEND_B 0x0
3040#define RESUME_B 0x2 /* Resume indicator */ 2427#define RESUME_B 0x2 /* Resume indicator */
3041#define nRESUME_B 0x0
3042#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */ 2428#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
3043#define nRESET_OR_BABLE_B 0x0
3044#define SOF_B 0x8 /* Start of frame */ 2429#define SOF_B 0x8 /* Start of frame */
3045#define nSOF_B 0x0
3046#define CONN_B 0x10 /* Connection indicator */ 2430#define CONN_B 0x10 /* Connection indicator */
3047#define nCONN_B 0x0
3048#define DISCON_B 0x20 /* Disconnect indicator */ 2431#define DISCON_B 0x20 /* Disconnect indicator */
3049#define nDISCON_B 0x0
3050#define SESSION_REQ_B 0x40 /* Session Request */ 2432#define SESSION_REQ_B 0x40 /* Session Request */
3051#define nSESSION_REQ_B 0x0
3052#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ 2433#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
3053#define nVBUS_ERROR_B 0x0
3054 2434
3055/* Bit masks for USB_INTRUSBE */ 2435/* Bit masks for USB_INTRUSBE */
3056 2436
3057#define SUSPEND_BE 0x1 /* Suspend indicator int enable */ 2437#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
3058#define nSUSPEND_BE 0x0
3059#define RESUME_BE 0x2 /* Resume indicator int enable */ 2438#define RESUME_BE 0x2 /* Resume indicator int enable */
3060#define nRESUME_BE 0x0
3061#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */ 2439#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
3062#define nRESET_OR_BABLE_BE 0x0
3063#define SOF_BE 0x8 /* Start of frame int enable */ 2440#define SOF_BE 0x8 /* Start of frame int enable */
3064#define nSOF_BE 0x0
3065#define CONN_BE 0x10 /* Connection indicator int enable */ 2441#define CONN_BE 0x10 /* Connection indicator int enable */
3066#define nCONN_BE 0x0
3067#define DISCON_BE 0x20 /* Disconnect indicator int enable */ 2442#define DISCON_BE 0x20 /* Disconnect indicator int enable */
3068#define nDISCON_BE 0x0
3069#define SESSION_REQ_BE 0x40 /* Session Request int enable */ 2443#define SESSION_REQ_BE 0x40 /* Session Request int enable */
3070#define nSESSION_REQ_BE 0x0
3071#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ 2444#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
3072#define nVBUS_ERROR_BE 0x0
3073 2445
3074/* Bit masks for USB_FRAME */ 2446/* Bit masks for USB_FRAME */
3075 2447
@@ -3082,117 +2454,67 @@
3082/* Bit masks for USB_GLOBAL_CTL */ 2454/* Bit masks for USB_GLOBAL_CTL */
3083 2455
3084#define GLOBAL_ENA 0x1 /* enables USB module */ 2456#define GLOBAL_ENA 0x1 /* enables USB module */
3085#define nGLOBAL_ENA 0x0
3086#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */ 2457#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
3087#define nEP1_TX_ENA 0x0
3088#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */ 2458#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
3089#define nEP2_TX_ENA 0x0
3090#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */ 2459#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
3091#define nEP3_TX_ENA 0x0
3092#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */ 2460#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
3093#define nEP4_TX_ENA 0x0
3094#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */ 2461#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
3095#define nEP5_TX_ENA 0x0
3096#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */ 2462#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
3097#define nEP6_TX_ENA 0x0
3098#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */ 2463#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
3099#define nEP7_TX_ENA 0x0
3100#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */ 2464#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
3101#define nEP1_RX_ENA 0x0
3102#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */ 2465#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
3103#define nEP2_RX_ENA 0x0
3104#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */ 2466#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
3105#define nEP3_RX_ENA 0x0
3106#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */ 2467#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
3107#define nEP4_RX_ENA 0x0
3108#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ 2468#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
3109#define nEP5_RX_ENA 0x0
3110#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ 2469#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
3111#define nEP6_RX_ENA 0x0
3112#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ 2470#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
3113#define nEP7_RX_ENA 0x0
3114 2471
3115/* Bit masks for USB_OTG_DEV_CTL */ 2472/* Bit masks for USB_OTG_DEV_CTL */
3116 2473
3117#define SESSION 0x1 /* session indicator */ 2474#define SESSION 0x1 /* session indicator */
3118#define nSESSION 0x0
3119#define HOST_REQ 0x2 /* Host negotiation request */ 2475#define HOST_REQ 0x2 /* Host negotiation request */
3120#define nHOST_REQ 0x0
3121#define HOST_MODE 0x4 /* indicates USBDRC is a host */ 2476#define HOST_MODE 0x4 /* indicates USBDRC is a host */
3122#define nHOST_MODE 0x0
3123#define VBUS0 0x8 /* Vbus level indicator[0] */ 2477#define VBUS0 0x8 /* Vbus level indicator[0] */
3124#define nVBUS0 0x0
3125#define VBUS1 0x10 /* Vbus level indicator[1] */ 2478#define VBUS1 0x10 /* Vbus level indicator[1] */
3126#define nVBUS1 0x0
3127#define LSDEV 0x20 /* Low-speed indicator */ 2479#define LSDEV 0x20 /* Low-speed indicator */
3128#define nLSDEV 0x0
3129#define FSDEV 0x40 /* Full or High-speed indicator */ 2480#define FSDEV 0x40 /* Full or High-speed indicator */
3130#define nFSDEV 0x0
3131#define B_DEVICE 0x80 /* A' or 'B' device indicator */ 2481#define B_DEVICE 0x80 /* A' or 'B' device indicator */
3132#define nB_DEVICE 0x0
3133 2482
3134/* Bit masks for USB_OTG_VBUS_IRQ */ 2483/* Bit masks for USB_OTG_VBUS_IRQ */
3135 2484
3136#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ 2485#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
3137#define nDRIVE_VBUS_ON 0x0
3138#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ 2486#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
3139#define nDRIVE_VBUS_OFF 0x0
3140#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ 2487#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
3141#define nCHRG_VBUS_START 0x0
3142#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ 2488#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
3143#define nCHRG_VBUS_END 0x0
3144#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ 2489#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
3145#define nDISCHRG_VBUS_START 0x0
3146#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ 2490#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
3147#define nDISCHRG_VBUS_END 0x0
3148 2491
3149/* Bit masks for USB_OTG_VBUS_MASK */ 2492/* Bit masks for USB_OTG_VBUS_MASK */
3150 2493
3151#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */ 2494#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
3152#define nDRIVE_VBUS_ON_ENA 0x0
3153#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */ 2495#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
3154#define nDRIVE_VBUS_OFF_ENA 0x0
3155#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */ 2496#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
3156#define nCHRG_VBUS_START_ENA 0x0
3157#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */ 2497#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
3158#define nCHRG_VBUS_END_ENA 0x0
3159#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ 2498#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
3160#define nDISCHRG_VBUS_START_ENA 0x0
3161#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ 2499#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
3162#define nDISCHRG_VBUS_END_ENA 0x0
3163 2500
3164/* Bit masks for USB_CSR0 */ 2501/* Bit masks for USB_CSR0 */
3165 2502
3166#define RXPKTRDY 0x1 /* data packet receive indicator */ 2503#define RXPKTRDY 0x1 /* data packet receive indicator */
3167#define nRXPKTRDY 0x0
3168#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ 2504#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
3169#define nTXPKTRDY 0x0
3170#define STALL_SENT 0x4 /* STALL handshake sent */ 2505#define STALL_SENT 0x4 /* STALL handshake sent */
3171#define nSTALL_SENT 0x0
3172#define DATAEND 0x8 /* Data end indicator */ 2506#define DATAEND 0x8 /* Data end indicator */
3173#define nDATAEND 0x0
3174#define SETUPEND 0x10 /* Setup end */ 2507#define SETUPEND 0x10 /* Setup end */
3175#define nSETUPEND 0x0
3176#define SENDSTALL 0x20 /* Send STALL handshake */ 2508#define SENDSTALL 0x20 /* Send STALL handshake */
3177#define nSENDSTALL 0x0
3178#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ 2509#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
3179#define nSERVICED_RXPKTRDY 0x0
3180#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ 2510#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
3181#define nSERVICED_SETUPEND 0x0
3182#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ 2511#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
3183#define nFLUSHFIFO 0x0
3184#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ 2512#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
3185#define nSTALL_RECEIVED_H 0x0
3186#define SETUPPKT_H 0x8 /* send Setup token host mode */ 2513#define SETUPPKT_H 0x8 /* send Setup token host mode */
3187#define nSETUPPKT_H 0x0
3188#define ERROR_H 0x10 /* timeout error indicator host mode */ 2514#define ERROR_H 0x10 /* timeout error indicator host mode */
3189#define nERROR_H 0x0
3190#define REQPKT_H 0x20 /* Request an IN transaction host mode */ 2515#define REQPKT_H 0x20 /* Request an IN transaction host mode */
3191#define nREQPKT_H 0x0
3192#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ 2516#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
3193#define nSTATUSPKT_H 0x0
3194#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ 2517#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
3195#define nNAK_TIMEOUT_H 0x0
3196 2518
3197/* Bit masks for USB_COUNT0 */ 2519/* Bit masks for USB_COUNT0 */
3198 2520
@@ -3213,37 +2535,21 @@
3213/* Bit masks for USB_TXCSR */ 2535/* Bit masks for USB_TXCSR */
3214 2536
3215#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ 2537#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
3216#define nTXPKTRDY_T 0x0
3217#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ 2538#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
3218#define nFIFO_NOT_EMPTY_T 0x0
3219#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ 2539#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
3220#define nUNDERRUN_T 0x0
3221#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ 2540#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
3222#define nFLUSHFIFO_T 0x0
3223#define STALL_SEND_T 0x10 /* issue a Stall handshake */ 2541#define STALL_SEND_T 0x10 /* issue a Stall handshake */
3224#define nSTALL_SEND_T 0x0
3225#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ 2542#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
3226#define nSTALL_SENT_T 0x0
3227#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ 2543#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
3228#define nCLEAR_DATATOGGLE_T 0x0
3229#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ 2544#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
3230#define nINCOMPTX_T 0x0
3231#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ 2545#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
3232#define nDMAREQMODE_T 0x0
3233#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ 2546#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
3234#define nFORCE_DATATOGGLE_T 0x0
3235#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ 2547#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
3236#define nDMAREQ_ENA_T 0x0
3237#define ISO_T 0x4000 /* enable Isochronous transfers */ 2548#define ISO_T 0x4000 /* enable Isochronous transfers */
3238#define nISO_T 0x0
3239#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ 2549#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
3240#define nAUTOSET_T 0x0
3241#define ERROR_TH 0x4 /* error condition host mode */ 2550#define ERROR_TH 0x4 /* error condition host mode */
3242#define nERROR_TH 0x0
3243#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ 2551#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
3244#define nSTALL_RECEIVED_TH 0x0
3245#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ 2552#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
3246#define nNAK_TIMEOUT_TH 0x0
3247 2553
3248/* Bit masks for USB_TXCOUNT */ 2554/* Bit masks for USB_TXCOUNT */
3249 2555
@@ -3252,45 +2558,25 @@
3252/* Bit masks for USB_RXCSR */ 2558/* Bit masks for USB_RXCSR */
3253 2559
3254#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ 2560#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
3255#define nRXPKTRDY_R 0x0
3256#define FIFO_FULL_R 0x2 /* FIFO not empty */ 2561#define FIFO_FULL_R 0x2 /* FIFO not empty */
3257#define nFIFO_FULL_R 0x0
3258#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ 2562#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
3259#define nOVERRUN_R 0x0
3260#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ 2563#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
3261#define nDATAERROR_R 0x0
3262#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ 2564#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
3263#define nFLUSHFIFO_R 0x0
3264#define STALL_SEND_R 0x20 /* issue a Stall handshake */ 2565#define STALL_SEND_R 0x20 /* issue a Stall handshake */
3265#define nSTALL_SEND_R 0x0
3266#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ 2566#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
3267#define nSTALL_SENT_R 0x0
3268#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ 2567#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
3269#define nCLEAR_DATATOGGLE_R 0x0
3270#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ 2568#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
3271#define nINCOMPRX_R 0x0
3272#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ 2569#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
3273#define nDMAREQMODE_R 0x0
3274#define DISNYET_R 0x1000 /* disable Nyet handshakes */ 2570#define DISNYET_R 0x1000 /* disable Nyet handshakes */
3275#define nDISNYET_R 0x0
3276#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ 2571#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
3277#define nDMAREQ_ENA_R 0x0
3278#define ISO_R 0x4000 /* enable Isochronous transfers */ 2572#define ISO_R 0x4000 /* enable Isochronous transfers */
3279#define nISO_R 0x0
3280#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ 2573#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
3281#define nAUTOCLEAR_R 0x0
3282#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ 2574#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
3283#define nERROR_RH 0x0
3284#define REQPKT_RH 0x20 /* request an IN transaction host mode */ 2575#define REQPKT_RH 0x20 /* request an IN transaction host mode */
3285#define nREQPKT_RH 0x0
3286#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ 2576#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
3287#define nSTALL_RECEIVED_RH 0x0
3288#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */ 2577#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
3289#define nINCOMPRX_RH 0x0
3290#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ 2578#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
3291#define nDMAREQMODE_RH 0x0
3292#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ 2579#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
3293#define nAUTOREQ_RH 0x0
3294 2580
3295/* Bit masks for USB_RXCOUNT */ 2581/* Bit masks for USB_RXCOUNT */
3296 2582
@@ -3317,35 +2603,22 @@
3317/* Bit masks for USB_DMA_INTERRUPT */ 2603/* Bit masks for USB_DMA_INTERRUPT */
3318 2604
3319#define DMA0_INT 0x1 /* DMA0 pending interrupt */ 2605#define DMA0_INT 0x1 /* DMA0 pending interrupt */
3320#define nDMA0_INT 0x0
3321#define DMA1_INT 0x2 /* DMA1 pending interrupt */ 2606#define DMA1_INT 0x2 /* DMA1 pending interrupt */
3322#define nDMA1_INT 0x0
3323#define DMA2_INT 0x4 /* DMA2 pending interrupt */ 2607#define DMA2_INT 0x4 /* DMA2 pending interrupt */
3324#define nDMA2_INT 0x0
3325#define DMA3_INT 0x8 /* DMA3 pending interrupt */ 2608#define DMA3_INT 0x8 /* DMA3 pending interrupt */
3326#define nDMA3_INT 0x0
3327#define DMA4_INT 0x10 /* DMA4 pending interrupt */ 2609#define DMA4_INT 0x10 /* DMA4 pending interrupt */
3328#define nDMA4_INT 0x0
3329#define DMA5_INT 0x20 /* DMA5 pending interrupt */ 2610#define DMA5_INT 0x20 /* DMA5 pending interrupt */
3330#define nDMA5_INT 0x0
3331#define DMA6_INT 0x40 /* DMA6 pending interrupt */ 2611#define DMA6_INT 0x40 /* DMA6 pending interrupt */
3332#define nDMA6_INT 0x0
3333#define DMA7_INT 0x80 /* DMA7 pending interrupt */ 2612#define DMA7_INT 0x80 /* DMA7 pending interrupt */
3334#define nDMA7_INT 0x0
3335 2613
3336/* Bit masks for USB_DMAxCONTROL */ 2614/* Bit masks for USB_DMAxCONTROL */
3337 2615
3338#define DMA_ENA 0x1 /* DMA enable */ 2616#define DMA_ENA 0x1 /* DMA enable */
3339#define nDMA_ENA 0x0
3340#define DIRECTION 0x2 /* direction of DMA transfer */ 2617#define DIRECTION 0x2 /* direction of DMA transfer */
3341#define nDIRECTION 0x0
3342#define MODE 0x4 /* DMA Bus error */ 2618#define MODE 0x4 /* DMA Bus error */
3343#define nMODE 0x0
3344#define INT_ENA 0x8 /* Interrupt enable */ 2619#define INT_ENA 0x8 /* Interrupt enable */
3345#define nINT_ENA 0x0
3346#define EPNUM 0xf0 /* EP number */ 2620#define EPNUM 0xf0 /* EP number */
3347#define BUSERROR 0x100 /* DMA Bus error */ 2621#define BUSERROR 0x100 /* DMA Bus error */
3348#define nBUSERROR 0x0
3349 2622
3350/* Bit masks for USB_DMAxADDRHIGH */ 2623/* Bit masks for USB_DMAxADDRHIGH */
3351 2624
@@ -3366,26 +2639,16 @@
3366/* Bit masks for HMDMAx_CONTROL */ 2639/* Bit masks for HMDMAx_CONTROL */
3367 2640
3368#define HMDMAEN 0x1 /* Handshake MDMA Enable */ 2641#define HMDMAEN 0x1 /* Handshake MDMA Enable */
3369#define nHMDMAEN 0x0
3370#define REP 0x2 /* Handshake MDMA Request Polarity */ 2642#define REP 0x2 /* Handshake MDMA Request Polarity */
3371#define nREP 0x0
3372#define UTE 0x8 /* Urgency Threshold Enable */ 2643#define UTE 0x8 /* Urgency Threshold Enable */
3373#define nUTE 0x0
3374#define OIE 0x10 /* Overflow Interrupt Enable */ 2644#define OIE 0x10 /* Overflow Interrupt Enable */
3375#define nOIE 0x0
3376#define BDIE 0x20 /* Block Done Interrupt Enable */ 2645#define BDIE 0x20 /* Block Done Interrupt Enable */
3377#define nBDIE 0x0
3378#define MBDI 0x40 /* Mask Block Done Interrupt */ 2646#define MBDI 0x40 /* Mask Block Done Interrupt */
3379#define nMBDI 0x0
3380#define DRQ 0x300 /* Handshake MDMA Request Type */ 2647#define DRQ 0x300 /* Handshake MDMA Request Type */
3381#define RBC 0x1000 /* Force Reload of BCOUNT */ 2648#define RBC 0x1000 /* Force Reload of BCOUNT */
3382#define nRBC 0x0
3383#define PS 0x2000 /* Pin Status */ 2649#define PS 0x2000 /* Pin Status */
3384#define nPS 0x0
3385#define OI 0x4000 /* Overflow Interrupt Generated */ 2650#define OI 0x4000 /* Overflow Interrupt Generated */
3386#define nOI 0x0
3387#define BDI 0x8000 /* Block Done Interrupt Generated */ 2651#define BDI 0x8000 /* Block Done Interrupt Generated */
3388#define nBDI 0x0
3389 2652
3390/* ******************************************* */ 2653/* ******************************************* */
3391/* MULTI BIT MACRO ENUMERATIONS */ 2654/* MULTI BIT MACRO ENUMERATIONS */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index a1b200fe6a1f..895ddd40a838 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -46,7 +46,7 @@
46 46
47/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */ 47/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
48 48
49#define CHIPID 0xffc00014 49#define CHIPID 0xffc00014
50 50
51/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */ 51/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
52 52
@@ -1512,231 +1512,144 @@
1512/* and MULTI BIT READ MACROS */ 1512/* and MULTI BIT READ MACROS */
1513/* ********************************************************** */ 1513/* ********************************************************** */
1514 1514
1515/* SIC_IMASK Masks */
1516#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
1517#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
1518#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
1519#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
1520
1521/* SIC_IWR Masks */
1522#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
1523#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
1524#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
1525#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
1526
1515/* Bit masks for SIC_IAR0 */ 1527/* Bit masks for SIC_IAR0 */
1516 1528
1517#define IRQ_PLL_WAKEUP 0x1 /* PLL Wakeup */ 1529#define PLL_WAKEUP 0x1 /* PLL Wakeup */
1518#define nIRQ_PLL_WAKEUP 0x0
1519 1530
1520/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */ 1531/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
1521 1532
1522#define IRQ_DMA0_ERR 0x2 /* DMA Controller 0 Error */ 1533#define DMA0_ERR 0x2 /* DMA Controller 0 Error */
1523#define nIRQ_DMA0_ERR 0x0 1534#define EPPI0_ERR 0x4 /* EPPI0 Error */
1524#define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */ 1535#define SPORT0_ERR 0x8 /* SPORT0 Error */
1525#define nIRQ_EPPI0_ERR 0x0 1536#define SPORT1_ERR 0x10 /* SPORT1 Error */
1526#define IRQ_SPORT0_ERR 0x8 /* SPORT0 Error */ 1537#define SPI0_ERR 0x20 /* SPI0 Error */
1527#define nIRQ_SPORT0_ERR 0x0 1538#define UART0_ERR 0x40 /* UART0 Error */
1528#define IRQ_SPORT1_ERR 0x10 /* SPORT1 Error */ 1539#define RTC 0x80 /* Real-Time Clock */
1529#define nIRQ_SPORT1_ERR 0x0 1540#define DMA12 0x100 /* DMA Channel 12 */
1530#define IRQ_SPI0_ERR 0x20 /* SPI0 Error */ 1541#define DMA0 0x200 /* DMA Channel 0 */
1531#define nIRQ_SPI0_ERR 0x0 1542#define DMA1 0x400 /* DMA Channel 1 */
1532#define IRQ_UART0_ERR 0x40 /* UART0 Error */ 1543#define DMA2 0x800 /* DMA Channel 2 */
1533#define nIRQ_UART0_ERR 0x0 1544#define DMA3 0x1000 /* DMA Channel 3 */
1534#define IRQ_RTC 0x80 /* Real-Time Clock */ 1545#define DMA4 0x2000 /* DMA Channel 4 */
1535#define nIRQ_RTC 0x0 1546#define DMA6 0x4000 /* DMA Channel 6 */
1536#define IRQ_DMA12 0x100 /* DMA Channel 12 */ 1547#define DMA7 0x8000 /* DMA Channel 7 */
1537#define nIRQ_DMA12 0x0 1548#define PINT0 0x80000 /* Pin Interrupt 0 */
1538#define IRQ_DMA0 0x200 /* DMA Channel 0 */ 1549#define PINT1 0x100000 /* Pin Interrupt 1 */
1539#define nIRQ_DMA0 0x0 1550#define MDMA0 0x200000 /* Memory DMA Stream 0 */
1540#define IRQ_DMA1 0x400 /* DMA Channel 1 */ 1551#define MDMA1 0x400000 /* Memory DMA Stream 1 */
1541#define nIRQ_DMA1 0x0 1552#define WDOG 0x800000 /* Watchdog Timer */
1542#define IRQ_DMA2 0x800 /* DMA Channel 2 */ 1553#define DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
1543#define nIRQ_DMA2 0x0 1554#define SPORT2_ERR 0x2000000 /* SPORT2 Error */
1544#define IRQ_DMA3 0x1000 /* DMA Channel 3 */ 1555#define SPORT3_ERR 0x4000000 /* SPORT3 Error */
1545#define nIRQ_DMA3 0x0 1556#define MXVR_SD 0x8000000 /* MXVR Synchronous Data */
1546#define IRQ_DMA4 0x2000 /* DMA Channel 4 */ 1557#define SPI1_ERR 0x10000000 /* SPI1 Error */
1547#define nIRQ_DMA4 0x0 1558#define SPI2_ERR 0x20000000 /* SPI2 Error */
1548#define IRQ_DMA6 0x4000 /* DMA Channel 6 */ 1559#define UART1_ERR 0x40000000 /* UART1 Error */
1549#define nIRQ_DMA6 0x0 1560#define UART2_ERR 0x80000000 /* UART2 Error */
1550#define IRQ_DMA7 0x8000 /* DMA Channel 7 */
1551#define nIRQ_DMA7 0x0
1552#define IRQ_PINT0 0x80000 /* Pin Interrupt 0 */
1553#define nIRQ_PINT0 0x0
1554#define IRQ_PINT1 0x100000 /* Pin Interrupt 1 */
1555#define nIRQ_PINT1 0x0
1556#define IRQ_MDMA0 0x200000 /* Memory DMA Stream 0 */
1557#define nIRQ_MDMA0 0x0
1558#define IRQ_MDMA1 0x400000 /* Memory DMA Stream 1 */
1559#define nIRQ_MDMA1 0x0
1560#define IRQ_WDOG 0x800000 /* Watchdog Timer */
1561#define nIRQ_WDOG 0x0
1562#define IRQ_DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
1563#define nIRQ_DMA1_ERR 0x0
1564#define IRQ_SPORT2_ERR 0x2000000 /* SPORT2 Error */
1565#define nIRQ_SPORT2_ERR 0x0
1566#define IRQ_SPORT3_ERR 0x4000000 /* SPORT3 Error */
1567#define nIRQ_SPORT3_ERR 0x0
1568#define IRQ_MXVR_SD 0x8000000 /* MXVR Synchronous Data */
1569#define nIRQ_MXVR_SD 0x0
1570#define IRQ_SPI1_ERR 0x10000000 /* SPI1 Error */
1571#define nIRQ_SPI1_ERR 0x0
1572#define IRQ_SPI2_ERR 0x20000000 /* SPI2 Error */
1573#define nIRQ_SPI2_ERR 0x0
1574#define IRQ_UART1_ERR 0x40000000 /* UART1 Error */
1575#define nIRQ_UART1_ERR 0x0
1576#define IRQ_UART2_ERR 0x80000000 /* UART2 Error */
1577#define nIRQ_UART2_ERR 0x0
1578 1561
1579/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */ 1562/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
1580 1563
1581#define IRQ_CAN0_ERR 0x1 /* CAN0 Error */ 1564#define CAN0_ERR 0x1 /* CAN0 Error */
1582#define nIRQ_CAN0_ERR 0x0 1565#define DMA18 0x2 /* DMA Channel 18 */
1583#define IRQ_DMA18 0x2 /* DMA Channel 18 */ 1566#define DMA19 0x4 /* DMA Channel 19 */
1584#define nIRQ_DMA18 0x0 1567#define DMA20 0x8 /* DMA Channel 20 */
1585#define IRQ_DMA19 0x4 /* DMA Channel 19 */ 1568#define DMA21 0x10 /* DMA Channel 21 */
1586#define nIRQ_DMA19 0x0 1569#define DMA13 0x20 /* DMA Channel 13 */
1587#define IRQ_DMA20 0x8 /* DMA Channel 20 */ 1570#define DMA14 0x40 /* DMA Channel 14 */
1588#define nIRQ_DMA20 0x0 1571#define DMA5 0x80 /* DMA Channel 5 */
1589#define IRQ_DMA21 0x10 /* DMA Channel 21 */ 1572#define DMA23 0x100 /* DMA Channel 23 */
1590#define nIRQ_DMA21 0x0 1573#define DMA8 0x200 /* DMA Channel 8 */
1591#define IRQ_DMA13 0x20 /* DMA Channel 13 */ 1574#define DMA9 0x400 /* DMA Channel 9 */
1592#define nIRQ_DMA13 0x0 1575#define DMA10 0x800 /* DMA Channel 10 */
1593#define IRQ_DMA14 0x40 /* DMA Channel 14 */ 1576#define DMA11 0x1000 /* DMA Channel 11 */
1594#define nIRQ_DMA14 0x0 1577#define TWI0 0x2000 /* TWI0 */
1595#define IRQ_DMA5 0x80 /* DMA Channel 5 */ 1578#define TWI1 0x4000 /* TWI1 */
1596#define nIRQ_DMA5 0x0 1579#define CAN0_RX 0x8000 /* CAN0 Receive */
1597#define IRQ_DMA23 0x100 /* DMA Channel 23 */ 1580#define CAN0_TX 0x10000 /* CAN0 Transmit */
1598#define nIRQ_DMA23 0x0 1581#define MDMA2 0x20000 /* Memory DMA Stream 0 */
1599#define IRQ_DMA8 0x200 /* DMA Channel 8 */ 1582#define MDMA3 0x40000 /* Memory DMA Stream 1 */
1600#define nIRQ_DMA8 0x0 1583#define MXVR_STAT 0x80000 /* MXVR Status */
1601#define IRQ_DMA9 0x400 /* DMA Channel 9 */ 1584#define MXVR_CM 0x100000 /* MXVR Control Message */
1602#define nIRQ_DMA9 0x0 1585#define MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
1603#define IRQ_DMA10 0x800 /* DMA Channel 10 */ 1586#define EPPI1_ERR 0x400000 /* EPPI1 Error */
1604#define nIRQ_DMA10 0x0 1587#define EPPI2_ERR 0x800000 /* EPPI2 Error */
1605#define IRQ_DMA11 0x1000 /* DMA Channel 11 */ 1588#define UART3_ERR 0x1000000 /* UART3 Error */
1606#define nIRQ_DMA11 0x0 1589#define HOST_ERR 0x2000000 /* Host DMA Port Error */
1607#define IRQ_TWI0 0x2000 /* TWI0 */ 1590#define USB_ERR 0x4000000 /* USB Error */
1608#define nIRQ_TWI0 0x0 1591#define PIXC_ERR 0x8000000 /* Pixel Compositor Error */
1609#define IRQ_TWI1 0x4000 /* TWI1 */ 1592#define NFC_ERR 0x10000000 /* Nand Flash Controller Error */
1610#define nIRQ_TWI1 0x0 1593#define ATAPI_ERR 0x20000000 /* ATAPI Error */
1611#define IRQ_CAN0_RX 0x8000 /* CAN0 Receive */ 1594#define CAN1_ERR 0x40000000 /* CAN1 Error */
1612#define nIRQ_CAN0_RX 0x0 1595#define DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
1613#define IRQ_CAN0_TX 0x10000 /* CAN0 Transmit */ 1596#define DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
1614#define nIRQ_CAN0_TX 0x0 1597#define DMAR0 0x80000000 /* DMAR0 Block */
1615#define IRQ_MDMA2 0x20000 /* Memory DMA Stream 0 */ 1598#define DMAR1 0x80000000 /* DMAR1 Block */
1616#define nIRQ_MDMA2 0x0
1617#define IRQ_MDMA3 0x40000 /* Memory DMA Stream 1 */
1618#define nIRQ_MDMA3 0x0
1619#define IRQ_MXVR_STAT 0x80000 /* MXVR Status */
1620#define nIRQ_MXVR_STAT 0x0
1621#define IRQ_MXVR_CM 0x100000 /* MXVR Control Message */
1622#define nIRQ_MXVR_CM 0x0
1623#define IRQ_MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
1624#define nIRQ_MXVR_AP 0x0
1625#define IRQ_EPPI1_ERR 0x400000 /* EPPI1 Error */
1626#define nIRQ_EPPI1_ERR 0x0
1627#define IRQ_EPPI2_ERR 0x800000 /* EPPI2 Error */
1628#define nIRQ_EPPI2_ERR 0x0
1629#define IRQ_UART3_ERR 0x1000000 /* UART3 Error */
1630#define nIRQ_UART3_ERR 0x0
1631#define IRQ_HOST_ERR 0x2000000 /* Host DMA Port Error */
1632#define nIRQ_HOST_ERR 0x0
1633#define IRQ_USB_ERR 0x4000000 /* USB Error */
1634#define nIRQ_USB_ERR 0x0
1635#define IRQ_PIXC_ERR 0x8000000 /* Pixel Compositor Error */
1636#define nIRQ_PIXC_ERR 0x0
1637#define IRQ_NFC_ERR 0x10000000 /* Nand Flash Controller Error */
1638#define nIRQ_NFC_ERR 0x0
1639#define IRQ_ATAPI_ERR 0x20000000 /* ATAPI Error */
1640#define nIRQ_ATAPI_ERR 0x0
1641#define IRQ_CAN1_ERR 0x40000000 /* CAN1 Error */
1642#define nIRQ_CAN1_ERR 0x0
1643#define IRQ_DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
1644#define nIRQ_DMAR0_ERR 0x0
1645#define IRQ_DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
1646#define nIRQ_DMAR1_ERR 0x0
1647#define IRQ_DMAR0 0x80000000 /* DMAR0 Block */
1648#define nIRQ_DMAR0 0x0
1649#define IRQ_DMAR1 0x80000000 /* DMAR1 Block */
1650#define nIRQ_DMAR1 0x0
1651 1599
1652/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */ 1600/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
1653 1601
1654#define IRQ_DMA15 0x1 /* DMA Channel 15 */ 1602#define DMA15 0x1 /* DMA Channel 15 */
1655#define nIRQ_DMA15 0x0 1603#define DMA16 0x2 /* DMA Channel 16 */
1656#define IRQ_DMA16 0x2 /* DMA Channel 16 */ 1604#define DMA17 0x4 /* DMA Channel 17 */
1657#define nIRQ_DMA16 0x0 1605#define DMA22 0x8 /* DMA Channel 22 */
1658#define IRQ_DMA17 0x4 /* DMA Channel 17 */ 1606#define CNT 0x10 /* Counter */
1659#define nIRQ_DMA17 0x0 1607#define KEY 0x20 /* Keypad */
1660#define IRQ_DMA22 0x8 /* DMA Channel 22 */ 1608#define CAN1_RX 0x40 /* CAN1 Receive */
1661#define nIRQ_DMA22 0x0 1609#define CAN1_TX 0x80 /* CAN1 Transmit */
1662#define IRQ_CNT 0x10 /* Counter */ 1610#define SDH_INT_MASK0 0x100 /* SDH Mask 0 */
1663#define nIRQ_CNT 0x0 1611#define SDH_INT_MASK1 0x200 /* SDH Mask 1 */
1664#define IRQ_KEY 0x20 /* Keypad */ 1612#define USB_EINT 0x400 /* USB Exception */
1665#define nIRQ_KEY 0x0 1613#define USB_INT0 0x800 /* USB Interrupt 0 */
1666#define IRQ_CAN1_RX 0x40 /* CAN1 Receive */ 1614#define USB_INT1 0x1000 /* USB Interrupt 1 */
1667#define nIRQ_CAN1_RX 0x0 1615#define USB_INT2 0x2000 /* USB Interrupt 2 */
1668#define IRQ_CAN1_TX 0x80 /* CAN1 Transmit */ 1616#define USB_DMAINT 0x4000 /* USB DMA */
1669#define nIRQ_CAN1_TX 0x0 1617#define OTPSEC 0x8000 /* OTP Access Complete */
1670#define IRQ_SDH_MASK0 0x100 /* SDH Mask 0 */ 1618#define TIMER0 0x400000 /* Timer 0 */
1671#define nIRQ_SDH_MASK0 0x0 1619#define TIMER1 0x800000 /* Timer 1 */
1672#define IRQ_SDH_MASK1 0x200 /* SDH Mask 1 */ 1620#define TIMER2 0x1000000 /* Timer 2 */
1673#define nIRQ_SDH_MASK1 0x0 1621#define TIMER3 0x2000000 /* Timer 3 */
1674#define IRQ_USB_EINT 0x400 /* USB Exception */ 1622#define TIMER4 0x4000000 /* Timer 4 */
1675#define nIRQ_USB_EINT 0x0 1623#define TIMER5 0x8000000 /* Timer 5 */
1676#define IRQ_USB_INT0 0x800 /* USB Interrupt 0 */ 1624#define TIMER6 0x10000000 /* Timer 6 */
1677#define nIRQ_USB_INT0 0x0 1625#define TIMER7 0x20000000 /* Timer 7 */
1678#define IRQ_USB_INT1 0x1000 /* USB Interrupt 1 */ 1626#define PINT2 0x40000000 /* Pin Interrupt 2 */
1679#define nIRQ_USB_INT1 0x0 1627#define PINT3 0x80000000 /* Pin Interrupt 3 */
1680#define IRQ_USB_INT2 0x2000 /* USB Interrupt 2 */
1681#define nIRQ_USB_INT2 0x0
1682#define IRQ_USB_DMAINT 0x4000 /* USB DMA */
1683#define nIRQ_USB_DMAINT 0x0
1684#define IRQ_OTPSEC 0x8000 /* OTP Access Complete */
1685#define nIRQ_OTPSEC 0x0
1686#define IRQ_TIMER0 0x400000 /* Timer 0 */
1687#define nIRQ_TIMER0 0x0
1688#define IRQ_TIMER1 0x800000 /* Timer 1 */
1689#define nIRQ_TIMER1 0x0
1690#define IRQ_TIMER2 0x1000000 /* Timer 2 */
1691#define nIRQ_TIMER2 0x0
1692#define IRQ_TIMER3 0x2000000 /* Timer 3 */
1693#define nIRQ_TIMER3 0x0
1694#define IRQ_TIMER4 0x4000000 /* Timer 4 */
1695#define nIRQ_TIMER4 0x0
1696#define IRQ_TIMER5 0x8000000 /* Timer 5 */
1697#define nIRQ_TIMER5 0x0
1698#define IRQ_TIMER6 0x10000000 /* Timer 6 */
1699#define nIRQ_TIMER6 0x0
1700#define IRQ_TIMER7 0x20000000 /* Timer 7 */
1701#define nIRQ_TIMER7 0x0
1702#define IRQ_PINT2 0x40000000 /* Pin Interrupt 2 */
1703#define nIRQ_PINT2 0x0
1704#define IRQ_PINT3 0x80000000 /* Pin Interrupt 3 */
1705#define nIRQ_PINT3 0x0
1706 1628
1707/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */ 1629/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
1708 1630
1709#define DMAEN 0x1 /* DMA Channel Enable */ 1631#define DMAEN 0x1 /* DMA Channel Enable */
1710#define nDMAEN 0x0
1711#define WNR 0x2 /* DMA Direction */ 1632#define WNR 0x2 /* DMA Direction */
1712#define nWNR 0x0 1633#define WDSIZE_8 0x0 /* Transfer Word Size = 8 */
1713#define WDSIZE 0xc /* Transfer Word Size */ 1634#define WDSIZE_16 0x4 /* Transfer Word Size = 16 */
1635#define WDSIZE_32 0x8 /* Transfer Word Size = 32 */
1714#define DMA2D 0x10 /* DMA Mode */ 1636#define DMA2D 0x10 /* DMA Mode */
1715#define nDMA2D 0x0
1716#define RESTART 0x20 /* Work Unit Transitions */ 1637#define RESTART 0x20 /* Work Unit Transitions */
1717#define nRESTART 0x0
1718#define DI_SEL 0x40 /* Data Interrupt Timing Select */ 1638#define DI_SEL 0x40 /* Data Interrupt Timing Select */
1719#define nDI_SEL 0x0
1720#define DI_EN 0x80 /* Data Interrupt Enable */ 1639#define DI_EN 0x80 /* Data Interrupt Enable */
1721#define nDI_EN 0x0
1722#define NDSIZE 0xf00 /* Flex Descriptor Size */ 1640#define NDSIZE 0xf00 /* Flex Descriptor Size */
1723#define DMAFLOW 0xf000 /* Next Operation */ 1641#define DMAFLOW 0xf000 /* Next Operation */
1724 1642
1725/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ 1643/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1726 1644
1727#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */ 1645#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
1728#define nDMA_DONE 0x0
1729#define DMA_ERR 0x2 /* DMA Error Interrupt Status */ 1646#define DMA_ERR 0x2 /* DMA Error Interrupt Status */
1730#define nDMA_ERR 0x0
1731#define DFETCH 0x4 /* DMA Descriptor Fetch */ 1647#define DFETCH 0x4 /* DMA Descriptor Fetch */
1732#define nDFETCH 0x0
1733#define DMA_RUN 0x8 /* DMA Channel Running */ 1648#define DMA_RUN 0x8 /* DMA Channel Running */
1734#define nDMA_RUN 0x0
1735 1649
1736/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */ 1650/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1737 1651
1738#define CTYPE 0x40 /* DMA Channel Type */ 1652#define CTYPE 0x40 /* DMA Channel Type */
1739#define nCTYPE 0x0
1740#define PMAP 0xf000 /* Peripheral Mapped To This Channel */ 1653#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
1741 1654
1742/* Bit masks for DMACx_TCPER */ 1655/* Bit masks for DMACx_TCPER */
@@ -1756,29 +1669,28 @@
1756/* Bit masks for DMAC1_PERIMUX */ 1669/* Bit masks for DMAC1_PERIMUX */
1757 1670
1758#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */ 1671#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
1759#define nPMUXSDH 0x0
1760 1672
1761/* Bit masks for EBIU_AMGCTL */ 1673/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1674/* EBIU_AMGCTL Masks */
1675#define AMCKEN 0x0001 /* Enable CLKOUT */
1676#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1677#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1678#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1679#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1680#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1762 1681
1763#define AMCKEN 0x1 /* Async Memory Enable */
1764#define nAMCKEN 0x0
1765#define AMBEN 0xe /* Async bank enable */
1766 1682
1767/* Bit masks for EBIU_AMBCTL0 */ 1683/* Bit masks for EBIU_AMBCTL0 */
1768 1684
1769#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */ 1685#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
1770#define nB0RDYEN 0x0
1771#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */ 1686#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
1772#define nB0RDYPOL 0x0
1773#define B0TT 0xc /* Bank 0 transition time */ 1687#define B0TT 0xc /* Bank 0 transition time */
1774#define B0ST 0x30 /* Bank 0 Setup time */ 1688#define B0ST 0x30 /* Bank 0 Setup time */
1775#define B0HT 0xc0 /* Bank 0 Hold time */ 1689#define B0HT 0xc0 /* Bank 0 Hold time */
1776#define B0RAT 0xf00 /* Bank 0 Read access time */ 1690#define B0RAT 0xf00 /* Bank 0 Read access time */
1777#define B0WAT 0xf000 /* Bank 0 write access time */ 1691#define B0WAT 0xf000 /* Bank 0 write access time */
1778#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */ 1692#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
1779#define nB1RDYEN 0x0
1780#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */ 1693#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
1781#define nB1RDYPOL 0x0
1782#define B1TT 0xc0000 /* Bank 1 transition time */ 1694#define B1TT 0xc0000 /* Bank 1 transition time */
1783#define B1ST 0x300000 /* Bank 1 Setup time */ 1695#define B1ST 0x300000 /* Bank 1 Setup time */
1784#define B1HT 0xc00000 /* Bank 1 Hold time */ 1696#define B1HT 0xc00000 /* Bank 1 Hold time */
@@ -1788,18 +1700,14 @@
1788/* Bit masks for EBIU_AMBCTL1 */ 1700/* Bit masks for EBIU_AMBCTL1 */
1789 1701
1790#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */ 1702#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
1791#define nB2RDYEN 0x0
1792#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */ 1703#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
1793#define nB2RDYPOL 0x0
1794#define B2TT 0xc /* Bank 2 transition time */ 1704#define B2TT 0xc /* Bank 2 transition time */
1795#define B2ST 0x30 /* Bank 2 Setup time */ 1705#define B2ST 0x30 /* Bank 2 Setup time */
1796#define B2HT 0xc0 /* Bank 2 Hold time */ 1706#define B2HT 0xc0 /* Bank 2 Hold time */
1797#define B2RAT 0xf00 /* Bank 2 Read access time */ 1707#define B2RAT 0xf00 /* Bank 2 Read access time */
1798#define B2WAT 0xf000 /* Bank 2 write access time */ 1708#define B2WAT 0xf000 /* Bank 2 write access time */
1799#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */ 1709#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
1800#define nB3RDYEN 0x0
1801#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */ 1710#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
1802#define nB3RDYPOL 0x0
1803#define B3TT 0xc0000 /* Bank 3 transition time */ 1711#define B3TT 0xc0000 /* Bank 3 transition time */
1804#define B3ST 0x300000 /* Bank 3 Setup time */ 1712#define B3ST 0x300000 /* Bank 3 Setup time */
1805#define B3HT 0xc00000 /* Bank 3 Hold time */ 1713#define B3HT 0xc00000 /* Bank 3 Hold time */
@@ -1823,19 +1731,15 @@
1823/* Bit masks for EBIU_FCTL */ 1731/* Bit masks for EBIU_FCTL */
1824 1732
1825#define TESTSETLOCK 0x1 /* Test set lock */ 1733#define TESTSETLOCK 0x1 /* Test set lock */
1826#define nTESTSETLOCK 0x0
1827#define BCLK 0x6 /* Burst clock frequency */ 1734#define BCLK 0x6 /* Burst clock frequency */
1828#define PGWS 0x38 /* Page wait states */ 1735#define PGWS 0x38 /* Page wait states */
1829#define PGSZ 0x40 /* Page size */ 1736#define PGSZ 0x40 /* Page size */
1830#define nPGSZ 0x0
1831#define RDDL 0x380 /* Read data delay */ 1737#define RDDL 0x380 /* Read data delay */
1832 1738
1833/* Bit masks for EBIU_ARBSTAT */ 1739/* Bit masks for EBIU_ARBSTAT */
1834 1740
1835#define ARBSTAT 0x1 /* Arbitration status */ 1741#define ARBSTAT 0x1 /* Arbitration status */
1836#define nARBSTAT 0x0
1837#define BGSTAT 0x2 /* Bus grant status */ 1742#define BGSTAT 0x2 /* Bus grant status */
1838#define nBGSTAT 0x0
1839 1743
1840/* Bit masks for EBIU_DDRCTL0 */ 1744/* Bit masks for EBIU_DDRCTL0 */
1841 1745
@@ -1861,9 +1765,7 @@
1861#define BURSTLENGTH 0x7 /* Burst length */ 1765#define BURSTLENGTH 0x7 /* Burst length */
1862#define CASLATENCY 0x70 /* CAS latency */ 1766#define CASLATENCY 0x70 /* CAS latency */
1863#define DLLRESET 0x100 /* DLL Reset */ 1767#define DLLRESET 0x100 /* DLL Reset */
1864#define nDLLRESET 0x0
1865#define REGE 0x1000 /* Register mode enable */ 1768#define REGE 0x1000 /* Register mode enable */
1866#define nREGE 0x0
1867 1769
1868/* Bit masks for EBIU_DDRCTL3 */ 1770/* Bit masks for EBIU_DDRCTL3 */
1869 1771
@@ -1876,30 +1778,19 @@
1876#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */ 1778#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
1877#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */ 1779#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
1878#define DEB1_URGENT 0x1000 /* DEB1 Urgent */ 1780#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
1879#define nDEB1_URGENT 0x0
1880#define DEB2_URGENT 0x2000 /* DEB2 Urgent */ 1781#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
1881#define nDEB2_URGENT 0x0
1882#define DEB3_URGENT 0x4000 /* DEB3 Urgent */ 1782#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
1883#define nDEB3_URGENT 0x0
1884 1783
1885/* Bit masks for EBIU_ERRMST */ 1784/* Bit masks for EBIU_ERRMST */
1886 1785
1887#define DEB1_ERROR 0x1 /* DEB1 Error */ 1786#define DEB1_ERROR 0x1 /* DEB1 Error */
1888#define nDEB1_ERROR 0x0
1889#define DEB2_ERROR 0x2 /* DEB2 Error */ 1787#define DEB2_ERROR 0x2 /* DEB2 Error */
1890#define nDEB2_ERROR 0x0
1891#define DEB3_ERROR 0x4 /* DEB3 Error */ 1788#define DEB3_ERROR 0x4 /* DEB3 Error */
1892#define nDEB3_ERROR 0x0
1893#define CORE_ERROR 0x8 /* Core error */ 1789#define CORE_ERROR 0x8 /* Core error */
1894#define nCORE_ERROR 0x0
1895#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */ 1790#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
1896#define nDEB_MERROR 0x0
1897#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */ 1791#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
1898#define nDEB2_MERROR 0x0
1899#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */ 1792#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
1900#define nDEB3_MERROR 0x0
1901#define CORE_MERROR 0x80 /* Core Error (2nd) */ 1793#define CORE_MERROR 0x80 /* Core Error (2nd) */
1902#define nCORE_MERROR 0x0
1903 1794
1904/* Bit masks for EBIU_ERRADD */ 1795/* Bit masks for EBIU_ERRADD */
1905 1796
@@ -1908,15 +1799,10 @@
1908/* Bit masks for EBIU_RSTCTL */ 1799/* Bit masks for EBIU_RSTCTL */
1909 1800
1910#define DDRSRESET 0x1 /* DDR soft reset */ 1801#define DDRSRESET 0x1 /* DDR soft reset */
1911#define nDDRSRESET 0x0
1912#define PFTCHSRESET 0x4 /* DDR prefetch reset */ 1802#define PFTCHSRESET 0x4 /* DDR prefetch reset */
1913#define nPFTCHSRESET 0x0
1914#define SRREQ 0x8 /* Self-refresh request */ 1803#define SRREQ 0x8 /* Self-refresh request */
1915#define nSRREQ 0x0
1916#define SRACK 0x10 /* Self-refresh acknowledge */ 1804#define SRACK 0x10 /* Self-refresh acknowledge */
1917#define nSRACK 0x0
1918#define MDDRENABLE 0x20 /* Mobile DDR enable */ 1805#define MDDRENABLE 0x20 /* Mobile DDR enable */
1919#define nMDDRENABLE 0x0
1920 1806
1921/* Bit masks for EBIU_DDRBRC0 */ 1807/* Bit masks for EBIU_DDRBRC0 */
1922 1808
@@ -2013,136 +1899,74 @@
2013/* Bit masks for EBIU_DDRMCEN */ 1899/* Bit masks for EBIU_DDRMCEN */
2014 1900
2015#define B0WCENABLE 0x1 /* Bank 0 write count enable */ 1901#define B0WCENABLE 0x1 /* Bank 0 write count enable */
2016#define nB0WCENABLE 0x0
2017#define B1WCENABLE 0x2 /* Bank 1 write count enable */ 1902#define B1WCENABLE 0x2 /* Bank 1 write count enable */
2018#define nB1WCENABLE 0x0
2019#define B2WCENABLE 0x4 /* Bank 2 write count enable */ 1903#define B2WCENABLE 0x4 /* Bank 2 write count enable */
2020#define nB2WCENABLE 0x0
2021#define B3WCENABLE 0x8 /* Bank 3 write count enable */ 1904#define B3WCENABLE 0x8 /* Bank 3 write count enable */
2022#define nB3WCENABLE 0x0
2023#define B4WCENABLE 0x10 /* Bank 4 write count enable */ 1905#define B4WCENABLE 0x10 /* Bank 4 write count enable */
2024#define nB4WCENABLE 0x0
2025#define B5WCENABLE 0x20 /* Bank 5 write count enable */ 1906#define B5WCENABLE 0x20 /* Bank 5 write count enable */
2026#define nB5WCENABLE 0x0
2027#define B6WCENABLE 0x40 /* Bank 6 write count enable */ 1907#define B6WCENABLE 0x40 /* Bank 6 write count enable */
2028#define nB6WCENABLE 0x0
2029#define B7WCENABLE 0x80 /* Bank 7 write count enable */ 1908#define B7WCENABLE 0x80 /* Bank 7 write count enable */
2030#define nB7WCENABLE 0x0
2031#define B0RCENABLE 0x100 /* Bank 0 read count enable */ 1909#define B0RCENABLE 0x100 /* Bank 0 read count enable */
2032#define nB0RCENABLE 0x0
2033#define B1RCENABLE 0x200 /* Bank 1 read count enable */ 1910#define B1RCENABLE 0x200 /* Bank 1 read count enable */
2034#define nB1RCENABLE 0x0
2035#define B2RCENABLE 0x400 /* Bank 2 read count enable */ 1911#define B2RCENABLE 0x400 /* Bank 2 read count enable */
2036#define nB2RCENABLE 0x0
2037#define B3RCENABLE 0x800 /* Bank 3 read count enable */ 1912#define B3RCENABLE 0x800 /* Bank 3 read count enable */
2038#define nB3RCENABLE 0x0
2039#define B4RCENABLE 0x1000 /* Bank 4 read count enable */ 1913#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
2040#define nB4RCENABLE 0x0
2041#define B5RCENABLE 0x2000 /* Bank 5 read count enable */ 1914#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
2042#define nB5RCENABLE 0x0
2043#define B6RCENABLE 0x4000 /* Bank 6 read count enable */ 1915#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
2044#define nB6RCENABLE 0x0
2045#define B7RCENABLE 0x8000 /* Bank 7 read count enable */ 1916#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
2046#define nB7RCENABLE 0x0
2047#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */ 1917#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
2048#define nROWACTCENABLE 0x0
2049#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */ 1918#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
2050#define nRWTCENABLE 0x0
2051#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */ 1919#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
2052#define nARCENABLE 0x0
2053#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */ 1920#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
2054#define nGC0ENABLE 0x0
2055#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */ 1921#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
2056#define nGC1ENABLE 0x0
2057#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */ 1922#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
2058#define nGC2ENABLE 0x0
2059#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */ 1923#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
2060#define nGC3ENABLE 0x0
2061#define GCCONTROL 0x3000000 /* DDR Grant Count Control */ 1924#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
2062 1925
2063/* Bit masks for EBIU_DDRMCCL */ 1926/* Bit masks for EBIU_DDRMCCL */
2064 1927
2065#define CB0WCOUNT 0x1 /* Clear write count 0 */ 1928#define CB0WCOUNT 0x1 /* Clear write count 0 */
2066#define nCB0WCOUNT 0x0
2067#define CB1WCOUNT 0x2 /* Clear write count 1 */ 1929#define CB1WCOUNT 0x2 /* Clear write count 1 */
2068#define nCB1WCOUNT 0x0
2069#define CB2WCOUNT 0x4 /* Clear write count 2 */ 1930#define CB2WCOUNT 0x4 /* Clear write count 2 */
2070#define nCB2WCOUNT 0x0
2071#define CB3WCOUNT 0x8 /* Clear write count 3 */ 1931#define CB3WCOUNT 0x8 /* Clear write count 3 */
2072#define nCB3WCOUNT 0x0
2073#define CB4WCOUNT 0x10 /* Clear write count 4 */ 1932#define CB4WCOUNT 0x10 /* Clear write count 4 */
2074#define nCB4WCOUNT 0x0
2075#define CB5WCOUNT 0x20 /* Clear write count 5 */ 1933#define CB5WCOUNT 0x20 /* Clear write count 5 */
2076#define nCB5WCOUNT 0x0
2077#define CB6WCOUNT 0x40 /* Clear write count 6 */ 1934#define CB6WCOUNT 0x40 /* Clear write count 6 */
2078#define nCB6WCOUNT 0x0
2079#define CB7WCOUNT 0x80 /* Clear write count 7 */ 1935#define CB7WCOUNT 0x80 /* Clear write count 7 */
2080#define nCB7WCOUNT 0x0
2081#define CBRCOUNT 0x100 /* Clear read count 0 */ 1936#define CBRCOUNT 0x100 /* Clear read count 0 */
2082#define nCBRCOUNT 0x0
2083#define CB1RCOUNT 0x200 /* Clear read count 1 */ 1937#define CB1RCOUNT 0x200 /* Clear read count 1 */
2084#define nCB1RCOUNT 0x0
2085#define CB2RCOUNT 0x400 /* Clear read count 2 */ 1938#define CB2RCOUNT 0x400 /* Clear read count 2 */
2086#define nCB2RCOUNT 0x0
2087#define CB3RCOUNT 0x800 /* Clear read count 3 */ 1939#define CB3RCOUNT 0x800 /* Clear read count 3 */
2088#define nCB3RCOUNT 0x0
2089#define CB4RCOUNT 0x1000 /* Clear read count 4 */ 1940#define CB4RCOUNT 0x1000 /* Clear read count 4 */
2090#define nCB4RCOUNT 0x0
2091#define CB5RCOUNT 0x2000 /* Clear read count 5 */ 1941#define CB5RCOUNT 0x2000 /* Clear read count 5 */
2092#define nCB5RCOUNT 0x0
2093#define CB6RCOUNT 0x4000 /* Clear read count 6 */ 1942#define CB6RCOUNT 0x4000 /* Clear read count 6 */
2094#define nCB6RCOUNT 0x0
2095#define CB7RCOUNT 0x8000 /* Clear read count 7 */ 1943#define CB7RCOUNT 0x8000 /* Clear read count 7 */
2096#define nCB7RCOUNT 0x0
2097#define CRACOUNT 0x10000 /* Clear row activation count */ 1944#define CRACOUNT 0x10000 /* Clear row activation count */
2098#define nCRACOUNT 0x0
2099#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */ 1945#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
2100#define nCRWTACOUNT 0x0
2101#define CARCOUNT 0x40000 /* Clear auto-refresh count */ 1946#define CARCOUNT 0x40000 /* Clear auto-refresh count */
2102#define nCARCOUNT 0x0
2103#define CG0COUNT 0x100000 /* Clear grant count 0 */ 1947#define CG0COUNT 0x100000 /* Clear grant count 0 */
2104#define nCG0COUNT 0x0
2105#define CG1COUNT 0x200000 /* Clear grant count 1 */ 1948#define CG1COUNT 0x200000 /* Clear grant count 1 */
2106#define nCG1COUNT 0x0
2107#define CG2COUNT 0x400000 /* Clear grant count 2 */ 1949#define CG2COUNT 0x400000 /* Clear grant count 2 */
2108#define nCG2COUNT 0x0
2109#define CG3COUNT 0x800000 /* Clear grant count 3 */ 1950#define CG3COUNT 0x800000 /* Clear grant count 3 */
2110#define nCG3COUNT 0x0
2111 1951
2112/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */ 1952/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
2113 1953
2114#define Px0 0x1 /* GPIO 0 */ 1954#define Px0 0x1 /* GPIO 0 */
2115#define nPx0 0x0
2116#define Px1 0x2 /* GPIO 1 */ 1955#define Px1 0x2 /* GPIO 1 */
2117#define nPx1 0x0
2118#define Px2 0x4 /* GPIO 2 */ 1956#define Px2 0x4 /* GPIO 2 */
2119#define nPx2 0x0
2120#define Px3 0x8 /* GPIO 3 */ 1957#define Px3 0x8 /* GPIO 3 */
2121#define nPx3 0x0
2122#define Px4 0x10 /* GPIO 4 */ 1958#define Px4 0x10 /* GPIO 4 */
2123#define nPx4 0x0
2124#define Px5 0x20 /* GPIO 5 */ 1959#define Px5 0x20 /* GPIO 5 */
2125#define nPx5 0x0
2126#define Px6 0x40 /* GPIO 6 */ 1960#define Px6 0x40 /* GPIO 6 */
2127#define nPx6 0x0
2128#define Px7 0x80 /* GPIO 7 */ 1961#define Px7 0x80 /* GPIO 7 */
2129#define nPx7 0x0
2130#define Px8 0x100 /* GPIO 8 */ 1962#define Px8 0x100 /* GPIO 8 */
2131#define nPx8 0x0
2132#define Px9 0x200 /* GPIO 9 */ 1963#define Px9 0x200 /* GPIO 9 */
2133#define nPx9 0x0
2134#define Px10 0x400 /* GPIO 10 */ 1964#define Px10 0x400 /* GPIO 10 */
2135#define nPx10 0x0
2136#define Px11 0x800 /* GPIO 11 */ 1965#define Px11 0x800 /* GPIO 11 */
2137#define nPx11 0x0
2138#define Px12 0x1000 /* GPIO 12 */ 1966#define Px12 0x1000 /* GPIO 12 */
2139#define nPx12 0x0
2140#define Px13 0x2000 /* GPIO 13 */ 1967#define Px13 0x2000 /* GPIO 13 */
2141#define nPx13 0x0
2142#define Px14 0x4000 /* GPIO 14 */ 1968#define Px14 0x4000 /* GPIO 14 */
2143#define nPx14 0x0
2144#define Px15 0x8000 /* GPIO 15 */ 1969#define Px15 0x8000 /* GPIO 15 */
2145#define nPx15 0x0
2146 1970
2147/* Bit masks for PORTA_MUX - PORTJ_MUX */ 1971/* Bit masks for PORTA_MUX - PORTJ_MUX */
2148 1972
@@ -2167,223 +1991,129 @@
2167/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */ 1991/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
2168 1992
2169#define IB0 0x1 /* Interrupt Bit 0 */ 1993#define IB0 0x1 /* Interrupt Bit 0 */
2170#define nIB0 0x0
2171#define IB1 0x2 /* Interrupt Bit 1 */ 1994#define IB1 0x2 /* Interrupt Bit 1 */
2172#define nIB1 0x0
2173#define IB2 0x4 /* Interrupt Bit 2 */ 1995#define IB2 0x4 /* Interrupt Bit 2 */
2174#define nIB2 0x0
2175#define IB3 0x8 /* Interrupt Bit 3 */ 1996#define IB3 0x8 /* Interrupt Bit 3 */
2176#define nIB3 0x0
2177#define IB4 0x10 /* Interrupt Bit 4 */ 1997#define IB4 0x10 /* Interrupt Bit 4 */
2178#define nIB4 0x0
2179#define IB5 0x20 /* Interrupt Bit 5 */ 1998#define IB5 0x20 /* Interrupt Bit 5 */
2180#define nIB5 0x0
2181#define IB6 0x40 /* Interrupt Bit 6 */ 1999#define IB6 0x40 /* Interrupt Bit 6 */
2182#define nIB6 0x0
2183#define IB7 0x80 /* Interrupt Bit 7 */ 2000#define IB7 0x80 /* Interrupt Bit 7 */
2184#define nIB7 0x0
2185#define IB8 0x100 /* Interrupt Bit 8 */ 2001#define IB8 0x100 /* Interrupt Bit 8 */
2186#define nIB8 0x0
2187#define IB9 0x200 /* Interrupt Bit 9 */ 2002#define IB9 0x200 /* Interrupt Bit 9 */
2188#define nIB9 0x0
2189#define IB10 0x400 /* Interrupt Bit 10 */ 2003#define IB10 0x400 /* Interrupt Bit 10 */
2190#define nIB10 0x0
2191#define IB11 0x800 /* Interrupt Bit 11 */ 2004#define IB11 0x800 /* Interrupt Bit 11 */
2192#define nIB11 0x0
2193#define IB12 0x1000 /* Interrupt Bit 12 */ 2005#define IB12 0x1000 /* Interrupt Bit 12 */
2194#define nIB12 0x0
2195#define IB13 0x2000 /* Interrupt Bit 13 */ 2006#define IB13 0x2000 /* Interrupt Bit 13 */
2196#define nIB13 0x0
2197#define IB14 0x4000 /* Interrupt Bit 14 */ 2007#define IB14 0x4000 /* Interrupt Bit 14 */
2198#define nIB14 0x0
2199#define IB15 0x8000 /* Interrupt Bit 15 */ 2008#define IB15 0x8000 /* Interrupt Bit 15 */
2200#define nIB15 0x0
2201 2009
2202/* Bit masks for TIMERx_CONFIG */ 2010/* Bit masks for TIMERx_CONFIG */
2203 2011
2204#define TMODE 0x3 /* Timer Mode */ 2012#define TMODE 0x3 /* Timer Mode */
2205#define PULSE_HI 0x4 /* Pulse Polarity */ 2013#define PULSE_HI 0x4 /* Pulse Polarity */
2206#define nPULSE_HI 0x0
2207#define PERIOD_CNT 0x8 /* Period Count */ 2014#define PERIOD_CNT 0x8 /* Period Count */
2208#define nPERIOD_CNT 0x0
2209#define IRQ_ENA 0x10 /* Interrupt Request Enable */ 2015#define IRQ_ENA 0x10 /* Interrupt Request Enable */
2210#define nIRQ_ENA 0x0
2211#define TIN_SEL 0x20 /* Timer Input Select */ 2016#define TIN_SEL 0x20 /* Timer Input Select */
2212#define nTIN_SEL 0x0
2213#define OUT_DIS 0x40 /* Output Pad Disable */ 2017#define OUT_DIS 0x40 /* Output Pad Disable */
2214#define nOUT_DIS 0x0
2215#define CLK_SEL 0x80 /* Timer Clock Select */ 2018#define CLK_SEL 0x80 /* Timer Clock Select */
2216#define nCLK_SEL 0x0
2217#define TOGGLE_HI 0x100 /* Toggle Mode */ 2019#define TOGGLE_HI 0x100 /* Toggle Mode */
2218#define nTOGGLE_HI 0x0
2219#define EMU_RUN 0x200 /* Emulation Behavior Select */ 2020#define EMU_RUN 0x200 /* Emulation Behavior Select */
2220#define nEMU_RUN 0x0
2221#define ERR_TYP 0xc000 /* Error Type */ 2021#define ERR_TYP 0xc000 /* Error Type */
2222 2022
2223/* Bit masks for TIMER_ENABLE0 */ 2023/* Bit masks for TIMER_ENABLE0 */
2224 2024
2225#define TIMEN0 0x1 /* Timer 0 Enable */ 2025#define TIMEN0 0x1 /* Timer 0 Enable */
2226#define nTIMEN0 0x0
2227#define TIMEN1 0x2 /* Timer 1 Enable */ 2026#define TIMEN1 0x2 /* Timer 1 Enable */
2228#define nTIMEN1 0x0
2229#define TIMEN2 0x4 /* Timer 2 Enable */ 2027#define TIMEN2 0x4 /* Timer 2 Enable */
2230#define nTIMEN2 0x0
2231#define TIMEN3 0x8 /* Timer 3 Enable */ 2028#define TIMEN3 0x8 /* Timer 3 Enable */
2232#define nTIMEN3 0x0
2233#define TIMEN4 0x10 /* Timer 4 Enable */ 2029#define TIMEN4 0x10 /* Timer 4 Enable */
2234#define nTIMEN4 0x0
2235#define TIMEN5 0x20 /* Timer 5 Enable */ 2030#define TIMEN5 0x20 /* Timer 5 Enable */
2236#define nTIMEN5 0x0
2237#define TIMEN6 0x40 /* Timer 6 Enable */ 2031#define TIMEN6 0x40 /* Timer 6 Enable */
2238#define nTIMEN6 0x0
2239#define TIMEN7 0x80 /* Timer 7 Enable */ 2032#define TIMEN7 0x80 /* Timer 7 Enable */
2240#define nTIMEN7 0x0
2241 2033
2242/* Bit masks for TIMER_DISABLE0 */ 2034/* Bit masks for TIMER_DISABLE0 */
2243 2035
2244#define TIMDIS0 0x1 /* Timer 0 Disable */ 2036#define TIMDIS0 0x1 /* Timer 0 Disable */
2245#define nTIMDIS0 0x0
2246#define TIMDIS1 0x2 /* Timer 1 Disable */ 2037#define TIMDIS1 0x2 /* Timer 1 Disable */
2247#define nTIMDIS1 0x0
2248#define TIMDIS2 0x4 /* Timer 2 Disable */ 2038#define TIMDIS2 0x4 /* Timer 2 Disable */
2249#define nTIMDIS2 0x0
2250#define TIMDIS3 0x8 /* Timer 3 Disable */ 2039#define TIMDIS3 0x8 /* Timer 3 Disable */
2251#define nTIMDIS3 0x0
2252#define TIMDIS4 0x10 /* Timer 4 Disable */ 2040#define TIMDIS4 0x10 /* Timer 4 Disable */
2253#define nTIMDIS4 0x0
2254#define TIMDIS5 0x20 /* Timer 5 Disable */ 2041#define TIMDIS5 0x20 /* Timer 5 Disable */
2255#define nTIMDIS5 0x0
2256#define TIMDIS6 0x40 /* Timer 6 Disable */ 2042#define TIMDIS6 0x40 /* Timer 6 Disable */
2257#define nTIMDIS6 0x0
2258#define TIMDIS7 0x80 /* Timer 7 Disable */ 2043#define TIMDIS7 0x80 /* Timer 7 Disable */
2259#define nTIMDIS7 0x0
2260 2044
2261/* Bit masks for TIMER_STATUS0 */ 2045/* Bit masks for TIMER_STATUS0 */
2262 2046
2263#define TIMIL0 0x1 /* Timer 0 Interrupt */ 2047#define TIMIL0 0x1 /* Timer 0 Interrupt */
2264#define nTIMIL0 0x0
2265#define TIMIL1 0x2 /* Timer 1 Interrupt */ 2048#define TIMIL1 0x2 /* Timer 1 Interrupt */
2266#define nTIMIL1 0x0
2267#define TIMIL2 0x4 /* Timer 2 Interrupt */ 2049#define TIMIL2 0x4 /* Timer 2 Interrupt */
2268#define nTIMIL2 0x0
2269#define TIMIL3 0x8 /* Timer 3 Interrupt */ 2050#define TIMIL3 0x8 /* Timer 3 Interrupt */
2270#define nTIMIL3 0x0
2271#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */ 2051#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
2272#define nTOVF_ERR0 0x0
2273#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */ 2052#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
2274#define nTOVF_ERR1 0x0
2275#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */ 2053#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
2276#define nTOVF_ERR2 0x0
2277#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */ 2054#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
2278#define nTOVF_ERR3 0x0
2279#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */ 2055#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
2280#define nTRUN0 0x0
2281#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */ 2056#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
2282#define nTRUN1 0x0
2283#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */ 2057#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
2284#define nTRUN2 0x0
2285#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */ 2058#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
2286#define nTRUN3 0x0
2287#define TIMIL4 0x10000 /* Timer 4 Interrupt */ 2059#define TIMIL4 0x10000 /* Timer 4 Interrupt */
2288#define nTIMIL4 0x0
2289#define TIMIL5 0x20000 /* Timer 5 Interrupt */ 2060#define TIMIL5 0x20000 /* Timer 5 Interrupt */
2290#define nTIMIL5 0x0
2291#define TIMIL6 0x40000 /* Timer 6 Interrupt */ 2061#define TIMIL6 0x40000 /* Timer 6 Interrupt */
2292#define nTIMIL6 0x0
2293#define TIMIL7 0x80000 /* Timer 7 Interrupt */ 2062#define TIMIL7 0x80000 /* Timer 7 Interrupt */
2294#define nTIMIL7 0x0
2295#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */ 2063#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
2296#define nTOVF_ERR4 0x0
2297#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */ 2064#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
2298#define nTOVF_ERR5 0x0
2299#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */ 2065#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
2300#define nTOVF_ERR6 0x0
2301#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */ 2066#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
2302#define nTOVF_ERR7 0x0
2303#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ 2067#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
2304#define nTRUN4 0x0
2305#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ 2068#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
2306#define nTRUN5 0x0
2307#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ 2069#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
2308#define nTRUN6 0x0
2309#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ 2070#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
2310#define nTRUN7 0x0
2311 2071
2312/* Bit masks for WDOG_CTL */ 2072/* Bit masks for WDOG_CTL */
2313 2073
2314#define WDEV 0x6 /* Watchdog Event */ 2074#define WDEV 0x6 /* Watchdog Event */
2315#define WDEN 0xff0 /* Watchdog Enable */ 2075#define WDEN 0xff0 /* Watchdog Enable */
2316#define WDRO 0x8000 /* Watchdog Rolled Over */ 2076#define WDRO 0x8000 /* Watchdog Rolled Over */
2317#define nWDRO 0x0
2318 2077
2319/* Bit masks for CNT_CONFIG */ 2078/* Bit masks for CNT_CONFIG */
2320 2079
2321#define CNTE 0x1 /* Counter Enable */ 2080#define CNTE 0x1 /* Counter Enable */
2322#define nCNTE 0x0
2323#define DEBE 0x2 /* Debounce Enable */ 2081#define DEBE 0x2 /* Debounce Enable */
2324#define nDEBE 0x0
2325#define CDGINV 0x10 /* CDG Pin Polarity Invert */ 2082#define CDGINV 0x10 /* CDG Pin Polarity Invert */
2326#define nCDGINV 0x0
2327#define CUDINV 0x20 /* CUD Pin Polarity Invert */ 2083#define CUDINV 0x20 /* CUD Pin Polarity Invert */
2328#define nCUDINV 0x0
2329#define CZMINV 0x40 /* CZM Pin Polarity Invert */ 2084#define CZMINV 0x40 /* CZM Pin Polarity Invert */
2330#define nCZMINV 0x0
2331#define CNTMODE 0x700 /* Counter Operating Mode */ 2085#define CNTMODE 0x700 /* Counter Operating Mode */
2332#define ZMZC 0x800 /* CZM Zeroes Counter Enable */ 2086#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
2333#define nZMZC 0x0
2334#define BNDMODE 0x3000 /* Boundary register Mode */ 2087#define BNDMODE 0x3000 /* Boundary register Mode */
2335#define INPDIS 0x8000 /* CUG and CDG Input Disable */ 2088#define INPDIS 0x8000 /* CUG and CDG Input Disable */
2336#define nINPDIS 0x0
2337 2089
2338/* Bit masks for CNT_IMASK */ 2090/* Bit masks for CNT_IMASK */
2339 2091
2340#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */ 2092#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
2341#define nICIE 0x0
2342#define UCIE 0x2 /* Up count Interrupt Enable */ 2093#define UCIE 0x2 /* Up count Interrupt Enable */
2343#define nUCIE 0x0
2344#define DCIE 0x4 /* Down count Interrupt Enable */ 2094#define DCIE 0x4 /* Down count Interrupt Enable */
2345#define nDCIE 0x0
2346#define MINCIE 0x8 /* Min Count Interrupt Enable */ 2095#define MINCIE 0x8 /* Min Count Interrupt Enable */
2347#define nMINCIE 0x0
2348#define MAXCIE 0x10 /* Max Count Interrupt Enable */ 2096#define MAXCIE 0x10 /* Max Count Interrupt Enable */
2349#define nMAXCIE 0x0
2350#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */ 2097#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
2351#define nCOV31IE 0x0
2352#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */ 2098#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
2353#define nCOV15IE 0x0
2354#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */ 2099#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
2355#define nCZEROIE 0x0
2356#define CZMIE 0x100 /* CZM Pin Interrupt Enable */ 2100#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
2357#define nCZMIE 0x0
2358#define CZMEIE 0x200 /* CZM Error Interrupt Enable */ 2101#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
2359#define nCZMEIE 0x0
2360#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */ 2102#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
2361#define nCZMZIE 0x0
2362 2103
2363/* Bit masks for CNT_STATUS */ 2104/* Bit masks for CNT_STATUS */
2364 2105
2365#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */ 2106#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
2366#define nICII 0x0
2367#define UCII 0x2 /* Up count Interrupt Identifier */ 2107#define UCII 0x2 /* Up count Interrupt Identifier */
2368#define nUCII 0x0
2369#define DCII 0x4 /* Down count Interrupt Identifier */ 2108#define DCII 0x4 /* Down count Interrupt Identifier */
2370#define nDCII 0x0
2371#define MINCII 0x8 /* Min Count Interrupt Identifier */ 2109#define MINCII 0x8 /* Min Count Interrupt Identifier */
2372#define nMINCII 0x0
2373#define MAXCII 0x10 /* Max Count Interrupt Identifier */ 2110#define MAXCII 0x10 /* Max Count Interrupt Identifier */
2374#define nMAXCII 0x0
2375#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */ 2111#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
2376#define nCOV31II 0x0
2377#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */ 2112#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
2378#define nCOV15II 0x0
2379#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */ 2113#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
2380#define nCZEROII 0x0
2381#define CZMII 0x100 /* CZM Pin Interrupt Identifier */ 2114#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
2382#define nCZMII 0x0
2383#define CZMEII 0x200 /* CZM Error Interrupt Identifier */ 2115#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
2384#define nCZMEII 0x0
2385#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */ 2116#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
2386#define nCZMZII 0x0
2387 2117
2388/* Bit masks for CNT_COMMAND */ 2118/* Bit masks for CNT_COMMAND */
2389 2119
@@ -2391,7 +2121,6 @@
2391#define W1LMIN 0xf0 /* Load Min Register */ 2121#define W1LMIN 0xf0 /* Load Min Register */
2392#define W1LMAX 0xf00 /* Load Max Register */ 2122#define W1LMAX 0xf00 /* Load Max Register */
2393#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */ 2123#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
2394#define nW1ZMONCE 0x0
2395 2124
2396/* Bit masks for CNT_DEBOUNCE */ 2125/* Bit masks for CNT_DEBOUNCE */
2397 2126
@@ -2407,42 +2136,25 @@
2407/* Bit masks for RTC_ICTL */ 2136/* Bit masks for RTC_ICTL */
2408 2137
2409#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */ 2138#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */
2410#define nSTOPWATCH_INTERRUPT_ENABLE 0x0
2411#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */ 2139#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */
2412#define nALARM_INTERRUPT_ENABLE 0x0
2413#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */ 2140#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */
2414#define nSECONDS_INTERRUPT_ENABLE 0x0
2415#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */ 2141#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */
2416#define nMINUTES_INTERRUPT_ENABLE 0x0
2417#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */ 2142#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */
2418#define nHOURS_INTERRUPT_ENABLE 0x0
2419#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */ 2143#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */
2420#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x0
2421#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */ 2144#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */
2422#define nDAY_ALARM_INTERRUPT_ENABLE 0x0
2423#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */ 2145#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */
2424#define nWRITE_COMPLETE_INTERRUPT_ENABLE 0x0
2425 2146
2426/* Bit masks for RTC_ISTAT */ 2147/* Bit masks for RTC_ISTAT */
2427 2148
2428#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */ 2149#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */
2429#define nSTOPWATCH_EVENT_FLAG 0x0
2430#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */ 2150#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */
2431#define nALARM_EVENT_FLAG 0x0
2432#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */ 2151#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */
2433#define nSECONDS_EVENT_FLAG 0x0
2434#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */ 2152#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */
2435#define nMINUTES_EVENT_FLAG 0x0
2436#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */ 2153#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */
2437#define nHOURS_EVENT_FLAG 0x0
2438#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */ 2154#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */
2439#define nTWENTY_FOUR_HOURS_EVENT_FLAG 0x0
2440#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */ 2155#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */
2441#define nDAY_ALARM_EVENT_FLAG 0x0
2442#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */ 2156#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */
2443#define nWRITE_PENDING__STATUS 0x0
2444#define WRITE_COMPLETE 0x8000 /* Write Complete */ 2157#define WRITE_COMPLETE 0x8000 /* Write Complete */
2445#define nWRITE_COMPLETE 0x0
2446 2158
2447/* Bit masks for RTC_SWCNT */ 2159/* Bit masks for RTC_SWCNT */
2448 2160
@@ -2458,21 +2170,15 @@
2458/* Bit masks for RTC_PREN */ 2170/* Bit masks for RTC_PREN */
2459 2171
2460#define PREN 0x1 /* Prescaler Enable */ 2172#define PREN 0x1 /* Prescaler Enable */
2461#define nPREN 0x0
2462 2173
2463/* Bit masks for OTP_CONTROL */ 2174/* Bit masks for OTP_CONTROL */
2464 2175
2465#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */ 2176#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
2466#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */ 2177#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
2467#define nFIEN 0x0
2468#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */ 2178#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
2469#define nFTESTDEC 0x0
2470#define FWRTEST 0x2000 /* OTP/Fuse Write Test */ 2179#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
2471#define nFWRTEST 0x0
2472#define FRDEN 0x4000 /* OTP/Fuse Read Enable */ 2180#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
2473#define nFRDEN 0x0
2474#define FWREN 0x8000 /* OTP/Fuse Write Enable */ 2181#define FWREN 0x8000 /* OTP/Fuse Write Enable */
2475#define nFWREN 0x0
2476 2182
2477/* Bit masks for OTP_BEN */ 2183/* Bit masks for OTP_BEN */
2478 2184
@@ -2481,15 +2187,10 @@
2481/* Bit masks for OTP_STATUS */ 2187/* Bit masks for OTP_STATUS */
2482 2188
2483#define FCOMP 0x1 /* OTP/Fuse Access Complete */ 2189#define FCOMP 0x1 /* OTP/Fuse Access Complete */
2484#define nFCOMP 0x0
2485#define FERROR 0x2 /* OTP/Fuse Access Error */ 2190#define FERROR 0x2 /* OTP/Fuse Access Error */
2486#define nFERROR 0x0
2487#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */ 2191#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
2488#define nMMRGLOAD 0x0
2489#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */ 2192#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
2490#define nMMRGLOCK 0x0
2491#define FPGMEN 0x40 /* OTP/Fuse Program Enable */ 2193#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
2492#define nFPGMEN 0x0
2493 2194
2494/* Bit masks for OTP_TIMING */ 2195/* Bit masks for OTP_TIMING */
2495 2196
@@ -2503,42 +2204,29 @@
2503/* Bit masks for SECURE_SYSSWT */ 2204/* Bit masks for SECURE_SYSSWT */
2504 2205
2505#define EMUDABL 0x1 /* Emulation Disable. */ 2206#define EMUDABL 0x1 /* Emulation Disable. */
2506#define nEMUDABL 0x0
2507#define RSTDABL 0x2 /* Reset Disable */ 2207#define RSTDABL 0x2 /* Reset Disable */
2508#define nRSTDABL 0x0
2509#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */ 2208#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
2510#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */ 2209#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
2511#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */ 2210#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
2512#define DMA0OVR 0x800 /* DMA0 Memory Access Override */ 2211#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
2513#define nDMA0OVR 0x0
2514#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */ 2212#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
2515#define nDMA1OVR 0x0
2516#define EMUOVR 0x4000 /* Emulation Override */ 2213#define EMUOVR 0x4000 /* Emulation Override */
2517#define nEMUOVR 0x0
2518#define OTPSEN 0x8000 /* OTP Secrets Enable. */ 2214#define OTPSEN 0x8000 /* OTP Secrets Enable. */
2519#define nOTPSEN 0x0
2520#define L2DABL 0x70000 /* L2 Memory Disable. */ 2215#define L2DABL 0x70000 /* L2 Memory Disable. */
2521 2216
2522/* Bit masks for SECURE_CONTROL */ 2217/* Bit masks for SECURE_CONTROL */
2523 2218
2524#define SECURE0 0x1 /* SECURE 0 */ 2219#define SECURE0 0x1 /* SECURE 0 */
2525#define nSECURE0 0x0
2526#define SECURE1 0x2 /* SECURE 1 */ 2220#define SECURE1 0x2 /* SECURE 1 */
2527#define nSECURE1 0x0
2528#define SECURE2 0x4 /* SECURE 2 */ 2221#define SECURE2 0x4 /* SECURE 2 */
2529#define nSECURE2 0x0
2530#define SECURE3 0x8 /* SECURE 3 */ 2222#define SECURE3 0x8 /* SECURE 3 */
2531#define nSECURE3 0x0
2532 2223
2533/* Bit masks for SECURE_STATUS */ 2224/* Bit masks for SECURE_STATUS */
2534 2225
2535#define SECMODE 0x3 /* Secured Mode Control State */ 2226#define SECMODE 0x3 /* Secured Mode Control State */
2536#define NMI 0x4 /* Non Maskable Interrupt */ 2227#define NMI 0x4 /* Non Maskable Interrupt */
2537#define nNMI 0x0
2538#define AFVALID 0x8 /* Authentication Firmware Valid */ 2228#define AFVALID 0x8 /* Authentication Firmware Valid */
2539#define nAFVALID 0x0
2540#define AFEXIT 0x10 /* Authentication Firmware Exit */ 2229#define AFEXIT 0x10 /* Authentication Firmware Exit */
2541#define nAFEXIT 0x0
2542#define SECSTAT 0xe0 /* Secure Status */ 2230#define SECSTAT 0xe0 /* Secure Status */
2543 2231
2544/* Bit masks for PLL_DIV */ 2232/* Bit masks for PLL_DIV */
@@ -2550,42 +2238,25 @@
2550 2238
2551#define MSEL 0x7e00 /* Multiplier Select */ 2239#define MSEL 0x7e00 /* Multiplier Select */
2552#define BYPASS 0x100 /* PLL Bypass Enable */ 2240#define BYPASS 0x100 /* PLL Bypass Enable */
2553#define nBYPASS 0x0
2554#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */ 2241#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
2555#define nOUTPUT_DELAY 0x0
2556#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */ 2242#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
2557#define nINPUT_DELAY 0x0
2558#define PDWN 0x20 /* Power Down */ 2243#define PDWN 0x20 /* Power Down */
2559#define nPDWN 0x0
2560#define STOPCK 0x8 /* Stop Clock */ 2244#define STOPCK 0x8 /* Stop Clock */
2561#define nSTOPCK 0x0
2562#define PLL_OFF 0x2 /* Disable PLL */ 2245#define PLL_OFF 0x2 /* Disable PLL */
2563#define nPLL_OFF 0x0
2564#define DF 0x1 /* Divide Frequency */ 2246#define DF 0x1 /* Divide Frequency */
2565#define nDF 0x0
2566 2247
2567/* Bit masks for PLL_STAT */ 2248/* Bit masks for PLL_STAT */
2568 2249
2569#define PLL_LOCKED 0x20 /* PLL Locked Status */ 2250#define PLL_LOCKED 0x20 /* PLL Locked Status */
2570#define nPLL_LOCKED 0x0
2571#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */ 2251#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
2572#define nACTIVE_PLLDISABLED 0x0
2573#define FULL_ON 0x2 /* Full-On Mode */ 2252#define FULL_ON 0x2 /* Full-On Mode */
2574#define nFULL_ON 0x0
2575#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */ 2253#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
2576#define nACTIVE_PLLENABLED 0x0
2577#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */ 2254#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
2578#define nRTCWS 0x0
2579#define CANWS 0x800 /* CAN Wake-Up Status */ 2255#define CANWS 0x800 /* CAN Wake-Up Status */
2580#define nCANWS 0x0
2581#define USBWS 0x2000 /* USB Wake-Up Status */ 2256#define USBWS 0x2000 /* USB Wake-Up Status */
2582#define nUSBWS 0x0
2583#define KPADWS 0x4000 /* Keypad Wake-Up Status */ 2257#define KPADWS 0x4000 /* Keypad Wake-Up Status */
2584#define nKPADWS 0x0
2585#define ROTWS 0x8000 /* Rotary Wake-Up Status */ 2258#define ROTWS 0x8000 /* Rotary Wake-Up Status */
2586#define nROTWS 0x0
2587#define GPWS 0x1000 /* General-Purpose Wake-Up Status */ 2259#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
2588#define nGPWS 0x0
2589 2260
2590/* Bit masks for VR_CTL */ 2261/* Bit masks for VR_CTL */
2591 2262
@@ -2593,79 +2264,52 @@
2593#define GAIN 0xc /* Voltage Output Level Gain */ 2264#define GAIN 0xc /* Voltage Output Level Gain */
2594#define VLEV 0xf0 /* Internal Voltage Level */ 2265#define VLEV 0xf0 /* Internal Voltage Level */
2595#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */ 2266#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
2596#define nSCKELOW 0x0
2597#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */ 2267#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
2598#define nWAKE 0x0
2599#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */ 2268#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
2600#define nCANWE 0x0
2601#define GPWE 0x400 /* General-Purpose Wake-Up Enable */ 2269#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
2602#define nGPWE 0x0
2603#define USBWE 0x800 /* USB Wake-Up Enable */ 2270#define USBWE 0x800 /* USB Wake-Up Enable */
2604#define nUSBWE 0x0
2605#define KPADWE 0x1000 /* Keypad Wake-Up Enable */ 2271#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
2606#define nKPADWE 0x0
2607#define ROTWE 0x2000 /* Rotary Wake-Up Enable */ 2272#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
2608#define nROTWE 0x0
2609 2273
2610/* Bit masks for NFC_CTL */ 2274/* Bit masks for NFC_CTL */
2611 2275
2612#define WR_DLY 0xf /* Write Strobe Delay */ 2276#define WR_DLY 0xf /* Write Strobe Delay */
2613#define RD_DLY 0xf0 /* Read Strobe Delay */ 2277#define RD_DLY 0xf0 /* Read Strobe Delay */
2614#define NWIDTH 0x100 /* NAND Data Width */ 2278#define NWIDTH 0x100 /* NAND Data Width */
2615#define nNWIDTH 0x0
2616#define PG_SIZE 0x200 /* Page Size */ 2279#define PG_SIZE 0x200 /* Page Size */
2617#define nPG_SIZE 0x0
2618 2280
2619/* Bit masks for NFC_STAT */ 2281/* Bit masks for NFC_STAT */
2620 2282
2621#define NBUSY 0x1 /* Not Busy */ 2283#define NBUSY 0x1 /* Not Busy */
2622#define nNBUSY 0x0
2623#define WB_FULL 0x2 /* Write Buffer Full */ 2284#define WB_FULL 0x2 /* Write Buffer Full */
2624#define nWB_FULL 0x0
2625#define PG_WR_STAT 0x4 /* Page Write Pending */ 2285#define PG_WR_STAT 0x4 /* Page Write Pending */
2626#define nPG_WR_STAT 0x0
2627#define PG_RD_STAT 0x8 /* Page Read Pending */ 2286#define PG_RD_STAT 0x8 /* Page Read Pending */
2628#define nPG_RD_STAT 0x0
2629#define WB_EMPTY 0x10 /* Write Buffer Empty */ 2287#define WB_EMPTY 0x10 /* Write Buffer Empty */
2630#define nWB_EMPTY 0x0
2631 2288
2632/* Bit masks for NFC_IRQSTAT */ 2289/* Bit masks for NFC_IRQSTAT */
2633 2290
2634#define NBUSYIRQ 0x1 /* Not Busy IRQ */ 2291#define NBUSYIRQ 0x1 /* Not Busy IRQ */
2635#define nNBUSYIRQ 0x0
2636#define WB_OVF 0x2 /* Write Buffer Overflow */ 2292#define WB_OVF 0x2 /* Write Buffer Overflow */
2637#define nWB_OVF 0x0
2638#define WB_EDGE 0x4 /* Write Buffer Edge Detect */ 2293#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
2639#define nWB_EDGE 0x0
2640#define RD_RDY 0x8 /* Read Data Ready */ 2294#define RD_RDY 0x8 /* Read Data Ready */
2641#define nRD_RDY 0x0
2642#define WR_DONE 0x10 /* Page Write Done */ 2295#define WR_DONE 0x10 /* Page Write Done */
2643#define nWR_DONE 0x0
2644 2296
2645/* Bit masks for NFC_IRQMASK */ 2297/* Bit masks for NFC_IRQMASK */
2646 2298
2647#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */ 2299#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
2648#define nMASK_BUSYIRQ 0x0
2649#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */ 2300#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
2650#define nMASK_WBOVF 0x0
2651#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */ 2301#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
2652#define nMASK_WBEMPTY 0x0
2653#define MASK_RDRDY 0x8 /* Mask Read Data Ready */ 2302#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
2654#define nMASK_RDRDY 0x0
2655#define MASK_WRDONE 0x10 /* Mask Write Done */ 2303#define MASK_WRDONE 0x10 /* Mask Write Done */
2656#define nMASK_WRDONE 0x0
2657 2304
2658/* Bit masks for NFC_RST */ 2305/* Bit masks for NFC_RST */
2659 2306
2660#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */ 2307#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
2661#define nECC_RST 0x0
2662 2308
2663/* Bit masks for NFC_PGCTL */ 2309/* Bit masks for NFC_PGCTL */
2664 2310
2665#define PG_RD_START 0x1 /* Page Read Start */ 2311#define PG_RD_START 0x1 /* Page Read Start */
2666#define nPG_RD_START 0x0
2667#define PG_WR_START 0x2 /* Page Write Start */ 2312#define PG_WR_START 0x2 /* Page Write Start */
2668#define nPG_WR_START 0x0
2669 2313
2670/* Bit masks for NFC_ECC0 */ 2314/* Bit masks for NFC_ECC0 */
2671 2315
@@ -2690,56 +2334,34 @@
2690/* Bit masks for CAN0_CONTROL */ 2334/* Bit masks for CAN0_CONTROL */
2691 2335
2692#define SRS 0x1 /* Software Reset */ 2336#define SRS 0x1 /* Software Reset */
2693#define nSRS 0x0
2694#define DNM 0x2 /* DeviceNet Mode */ 2337#define DNM 0x2 /* DeviceNet Mode */
2695#define nDNM 0x0
2696#define ABO 0x4 /* Auto Bus On */ 2338#define ABO 0x4 /* Auto Bus On */
2697#define nABO 0x0
2698#define WBA 0x10 /* Wakeup On CAN Bus Activity */ 2339#define WBA 0x10 /* Wakeup On CAN Bus Activity */
2699#define nWBA 0x0
2700#define SMR 0x20 /* Sleep Mode Request */ 2340#define SMR 0x20 /* Sleep Mode Request */
2701#define nSMR 0x0
2702#define CSR 0x40 /* CAN Suspend Mode Request */ 2341#define CSR 0x40 /* CAN Suspend Mode Request */
2703#define nCSR 0x0
2704#define CCR 0x80 /* CAN Configuration Mode Request */ 2342#define CCR 0x80 /* CAN Configuration Mode Request */
2705#define nCCR 0x0
2706 2343
2707/* Bit masks for CAN0_STATUS */ 2344/* Bit masks for CAN0_STATUS */
2708 2345
2709#define WT 0x1 /* CAN Transmit Warning Flag */ 2346#define WT 0x1 /* CAN Transmit Warning Flag */
2710#define nWT 0x0
2711#define WR 0x2 /* CAN Receive Warning Flag */ 2347#define WR 0x2 /* CAN Receive Warning Flag */
2712#define nWR 0x0
2713#define EP 0x4 /* CAN Error Passive Mode */ 2348#define EP 0x4 /* CAN Error Passive Mode */
2714#define nEP 0x0
2715#define EBO 0x8 /* CAN Error Bus Off Mode */ 2349#define EBO 0x8 /* CAN Error Bus Off Mode */
2716#define nEBO 0x0
2717#define CSA 0x40 /* CAN Suspend Mode Acknowledge */ 2350#define CSA 0x40 /* CAN Suspend Mode Acknowledge */
2718#define nCSA 0x0
2719#define CCA 0x80 /* CAN Configuration Mode Acknowledge */ 2351#define CCA 0x80 /* CAN Configuration Mode Acknowledge */
2720#define nCCA 0x0
2721#define MBPTR 0x1f00 /* Mailbox Pointer */ 2352#define MBPTR 0x1f00 /* Mailbox Pointer */
2722#define TRM 0x4000 /* Transmit Mode Status */ 2353#define TRM 0x4000 /* Transmit Mode Status */
2723#define nTRM 0x0
2724#define REC 0x8000 /* Receive Mode Status */ 2354#define REC 0x8000 /* Receive Mode Status */
2725#define nREC 0x0
2726 2355
2727/* Bit masks for CAN0_DEBUG */ 2356/* Bit masks for CAN0_DEBUG */
2728 2357
2729#define DEC 0x1 /* Disable Transmit/Receive Error Counters */ 2358#define DEC 0x1 /* Disable Transmit/Receive Error Counters */
2730#define nDEC 0x0
2731#define DRI 0x2 /* Disable CANRX Input Pin */ 2359#define DRI 0x2 /* Disable CANRX Input Pin */
2732#define nDRI 0x0
2733#define DTO 0x4 /* Disable CANTX Output Pin */ 2360#define DTO 0x4 /* Disable CANTX Output Pin */
2734#define nDTO 0x0
2735#define DIL 0x8 /* Disable Internal Loop */ 2361#define DIL 0x8 /* Disable Internal Loop */
2736#define nDIL 0x0
2737#define MAA 0x10 /* Mode Auto-Acknowledge */ 2362#define MAA 0x10 /* Mode Auto-Acknowledge */
2738#define nMAA 0x0
2739#define MRB 0x20 /* Mode Read Back */ 2363#define MRB 0x20 /* Mode Read Back */
2740#define nMRB 0x0
2741#define CDE 0x8000 /* CAN Debug Mode Enable */ 2364#define CDE 0x8000 /* CAN Debug Mode Enable */
2742#define nCDE 0x0
2743 2365
2744/* Bit masks for CAN0_CLOCK */ 2366/* Bit masks for CAN0_CLOCK */
2745 2367
@@ -2749,111 +2371,69 @@
2749 2371
2750#define SJW 0x300 /* Synchronization Jump Width */ 2372#define SJW 0x300 /* Synchronization Jump Width */
2751#define SAM 0x80 /* Sampling */ 2373#define SAM 0x80 /* Sampling */
2752#define nSAM 0x0
2753#define TSEG2 0x70 /* Time Segment 2 */ 2374#define TSEG2 0x70 /* Time Segment 2 */
2754#define TSEG1 0xf /* Time Segment 1 */ 2375#define TSEG1 0xf /* Time Segment 1 */
2755 2376
2756/* Bit masks for CAN0_INTR */ 2377/* Bit masks for CAN0_INTR */
2757 2378
2758#define CANRX 0x80 /* Serial Input From Transceiver */ 2379#define CANRX 0x80 /* Serial Input From Transceiver */
2759#define nCANRX 0x0
2760#define CANTX 0x40 /* Serial Output To Transceiver */ 2380#define CANTX 0x40 /* Serial Output To Transceiver */
2761#define nCANTX 0x0
2762#define SMACK 0x8 /* Sleep Mode Acknowledge */ 2381#define SMACK 0x8 /* Sleep Mode Acknowledge */
2763#define nSMACK 0x0
2764#define GIRQ 0x4 /* Global Interrupt Request Status */ 2382#define GIRQ 0x4 /* Global Interrupt Request Status */
2765#define nGIRQ 0x0
2766#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */ 2383#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */
2767#define nMBTIRQ 0x0
2768#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */ 2384#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */
2769#define nMBRIRQ 0x0
2770 2385
2771/* Bit masks for CAN0_GIM */ 2386/* Bit masks for CAN0_GIM */
2772 2387
2773#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */ 2388#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */
2774#define nEWTIM 0x0
2775#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */ 2389#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */
2776#define nEWRIM 0x0
2777#define EPIM 0x4 /* Error Passive Interrupt Mask */ 2390#define EPIM 0x4 /* Error Passive Interrupt Mask */
2778#define nEPIM 0x0
2779#define BOIM 0x8 /* Bus Off Interrupt Mask */ 2391#define BOIM 0x8 /* Bus Off Interrupt Mask */
2780#define nBOIM 0x0
2781#define WUIM 0x10 /* Wakeup Interrupt Mask */ 2392#define WUIM 0x10 /* Wakeup Interrupt Mask */
2782#define nWUIM 0x0
2783#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */ 2393#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */
2784#define nUIAIM 0x0
2785#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */ 2394#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */
2786#define nAAIM 0x0
2787#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */ 2395#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */
2788#define nRMLIM 0x0
2789#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */ 2396#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */
2790#define nUCEIM 0x0
2791#define ADIM 0x400 /* Access Denied Interrupt Mask */ 2397#define ADIM 0x400 /* Access Denied Interrupt Mask */
2792#define nADIM 0x0
2793 2398
2794/* Bit masks for CAN0_GIS */ 2399/* Bit masks for CAN0_GIS */
2795 2400
2796#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */ 2401#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */
2797#define nEWTIS 0x0
2798#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */ 2402#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */
2799#define nEWRIS 0x0
2800#define EPIS 0x4 /* Error Passive Interrupt Status */ 2403#define EPIS 0x4 /* Error Passive Interrupt Status */
2801#define nEPIS 0x0
2802#define BOIS 0x8 /* Bus Off Interrupt Status */ 2404#define BOIS 0x8 /* Bus Off Interrupt Status */
2803#define nBOIS 0x0
2804#define WUIS 0x10 /* Wakeup Interrupt Status */ 2405#define WUIS 0x10 /* Wakeup Interrupt Status */
2805#define nWUIS 0x0
2806#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */ 2406#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */
2807#define nUIAIS 0x0
2808#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */ 2407#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */
2809#define nAAIS 0x0
2810#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */ 2408#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */
2811#define nRMLIS 0x0
2812#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */ 2409#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */
2813#define nUCEIS 0x0
2814#define ADIS 0x400 /* Access Denied Interrupt Status */ 2410#define ADIS 0x400 /* Access Denied Interrupt Status */
2815#define nADIS 0x0
2816 2411
2817/* Bit masks for CAN0_GIF */ 2412/* Bit masks for CAN0_GIF */
2818 2413
2819#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */ 2414#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */
2820#define nEWTIF 0x0
2821#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */ 2415#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */
2822#define nEWRIF 0x0
2823#define EPIF 0x4 /* Error Passive Interrupt Flag */ 2416#define EPIF 0x4 /* Error Passive Interrupt Flag */
2824#define nEPIF 0x0
2825#define BOIF 0x8 /* Bus Off Interrupt Flag */ 2417#define BOIF 0x8 /* Bus Off Interrupt Flag */
2826#define nBOIF 0x0
2827#define WUIF 0x10 /* Wakeup Interrupt Flag */ 2418#define WUIF 0x10 /* Wakeup Interrupt Flag */
2828#define nWUIF 0x0
2829#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */ 2419#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */
2830#define nUIAIF 0x0
2831#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */ 2420#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */
2832#define nAAIF 0x0
2833#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */ 2421#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */
2834#define nRMLIF 0x0
2835#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */ 2422#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */
2836#define nUCEIF 0x0
2837#define ADIF 0x400 /* Access Denied Interrupt Flag */ 2423#define ADIF 0x400 /* Access Denied Interrupt Flag */
2838#define nADIF 0x0
2839 2424
2840/* Bit masks for CAN0_MBTD */ 2425/* Bit masks for CAN0_MBTD */
2841 2426
2842#define TDR 0x80 /* Temporary Disable Request */ 2427#define TDR 0x80 /* Temporary Disable Request */
2843#define nTDR 0x0
2844#define TDA 0x40 /* Temporary Disable Acknowledge */ 2428#define TDA 0x40 /* Temporary Disable Acknowledge */
2845#define nTDA 0x0
2846#define TDPTR 0x1f /* Temporary Disable Pointer */ 2429#define TDPTR 0x1f /* Temporary Disable Pointer */
2847 2430
2848/* Bit masks for CAN0_UCCNF */ 2431/* Bit masks for CAN0_UCCNF */
2849 2432
2850#define UCCNF 0xf /* Universal Counter Configuration */ 2433#define UCCNF 0xf /* Universal Counter Configuration */
2851#define UCRC 0x20 /* Universal Counter Reload/Clear */ 2434#define UCRC 0x20 /* Universal Counter Reload/Clear */
2852#define nUCRC 0x0
2853#define UCCT 0x40 /* Universal Counter CAN Trigger */ 2435#define UCCT 0x40 /* Universal Counter CAN Trigger */
2854#define nUCCT 0x0
2855#define UCE 0x80 /* Universal Counter Enable */ 2436#define UCE 0x80 /* Universal Counter Enable */
2856#define nUCE 0x0
2857 2437
2858/* Bit masks for CAN0_UCCNT */ 2438/* Bit masks for CAN0_UCCNT */
2859 2439
@@ -2871,17 +2451,11 @@
2871/* Bit masks for CAN0_ESR */ 2451/* Bit masks for CAN0_ESR */
2872 2452
2873#define FER 0x80 /* Form Error */ 2453#define FER 0x80 /* Form Error */
2874#define nFER 0x0
2875#define BEF 0x40 /* Bit Error Flag */ 2454#define BEF 0x40 /* Bit Error Flag */
2876#define nBEF 0x0
2877#define SA0 0x20 /* Stuck At Dominant */ 2455#define SA0 0x20 /* Stuck At Dominant */
2878#define nSA0 0x0
2879#define CRCE 0x10 /* CRC Error */ 2456#define CRCE 0x10 /* CRC Error */
2880#define nCRCE 0x0
2881#define SER 0x8 /* Stuff Bit Error */ 2457#define SER 0x8 /* Stuff Bit Error */
2882#define nSER 0x0
2883#define ACKE 0x4 /* Acknowledge Error */ 2458#define ACKE 0x4 /* Acknowledge Error */
2884#define nACKE 0x0
2885 2459
2886/* Bit masks for CAN0_EWR */ 2460/* Bit masks for CAN0_EWR */
2887 2461
@@ -2891,11 +2465,8 @@
2891/* Bit masks for CAN0_AMxx_H */ 2465/* Bit masks for CAN0_AMxx_H */
2892 2466
2893#define FDF 0x8000 /* Filter On Data Field */ 2467#define FDF 0x8000 /* Filter On Data Field */
2894#define nFDF 0x0
2895#define FMD 0x4000 /* Full Mask Data */ 2468#define FMD 0x4000 /* Full Mask Data */
2896#define nFMD 0x0
2897#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */ 2469#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */
2898#define nAMIDE 0x0
2899#define BASEID 0x1ffc /* Base Identifier */ 2470#define BASEID 0x1ffc /* Base Identifier */
2900#define EXTID_HI 0x3 /* Extended Identifier High Bits */ 2471#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2901 2472
@@ -2907,11 +2478,8 @@
2907/* Bit masks for CAN0_MBxx_ID1 */ 2478/* Bit masks for CAN0_MBxx_ID1 */
2908 2479
2909#define AME 0x8000 /* Acceptance Mask Enable */ 2480#define AME 0x8000 /* Acceptance Mask Enable */
2910#define nAME 0x0
2911#define RTR 0x4000 /* Remote Transmission Request */ 2481#define RTR 0x4000 /* Remote Transmission Request */
2912#define nRTR 0x0
2913#define IDE 0x2000 /* Identifier Extension */ 2482#define IDE 0x2000 /* Identifier Extension */
2914#define nIDE 0x0
2915#define BASEID 0x1ffc /* Base Identifier */ 2483#define BASEID 0x1ffc /* Base Identifier */
2916#define EXTID_HI 0x3 /* Extended Identifier High Bits */ 2484#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2917 2485
@@ -2951,980 +2519,546 @@
2951/* Bit masks for CAN0_MC1 */ 2519/* Bit masks for CAN0_MC1 */
2952 2520
2953#define MC0 0x1 /* Mailbox 0 Enable */ 2521#define MC0 0x1 /* Mailbox 0 Enable */
2954#define nMC0 0x0
2955#define MC1 0x2 /* Mailbox 1 Enable */ 2522#define MC1 0x2 /* Mailbox 1 Enable */
2956#define nMC1 0x0
2957#define MC2 0x4 /* Mailbox 2 Enable */ 2523#define MC2 0x4 /* Mailbox 2 Enable */
2958#define nMC2 0x0
2959#define MC3 0x8 /* Mailbox 3 Enable */ 2524#define MC3 0x8 /* Mailbox 3 Enable */
2960#define nMC3 0x0
2961#define MC4 0x10 /* Mailbox 4 Enable */ 2525#define MC4 0x10 /* Mailbox 4 Enable */
2962#define nMC4 0x0
2963#define MC5 0x20 /* Mailbox 5 Enable */ 2526#define MC5 0x20 /* Mailbox 5 Enable */
2964#define nMC5 0x0
2965#define MC6 0x40 /* Mailbox 6 Enable */ 2527#define MC6 0x40 /* Mailbox 6 Enable */
2966#define nMC6 0x0
2967#define MC7 0x80 /* Mailbox 7 Enable */ 2528#define MC7 0x80 /* Mailbox 7 Enable */
2968#define nMC7 0x0
2969#define MC8 0x100 /* Mailbox 8 Enable */ 2529#define MC8 0x100 /* Mailbox 8 Enable */
2970#define nMC8 0x0
2971#define MC9 0x200 /* Mailbox 9 Enable */ 2530#define MC9 0x200 /* Mailbox 9 Enable */
2972#define nMC9 0x0
2973#define MC10 0x400 /* Mailbox 10 Enable */ 2531#define MC10 0x400 /* Mailbox 10 Enable */
2974#define nMC10 0x0
2975#define MC11 0x800 /* Mailbox 11 Enable */ 2532#define MC11 0x800 /* Mailbox 11 Enable */
2976#define nMC11 0x0
2977#define MC12 0x1000 /* Mailbox 12 Enable */ 2533#define MC12 0x1000 /* Mailbox 12 Enable */
2978#define nMC12 0x0
2979#define MC13 0x2000 /* Mailbox 13 Enable */ 2534#define MC13 0x2000 /* Mailbox 13 Enable */
2980#define nMC13 0x0
2981#define MC14 0x4000 /* Mailbox 14 Enable */ 2535#define MC14 0x4000 /* Mailbox 14 Enable */
2982#define nMC14 0x0
2983#define MC15 0x8000 /* Mailbox 15 Enable */ 2536#define MC15 0x8000 /* Mailbox 15 Enable */
2984#define nMC15 0x0
2985 2537
2986/* Bit masks for CAN0_MC2 */ 2538/* Bit masks for CAN0_MC2 */
2987 2539
2988#define MC16 0x1 /* Mailbox 16 Enable */ 2540#define MC16 0x1 /* Mailbox 16 Enable */
2989#define nMC16 0x0
2990#define MC17 0x2 /* Mailbox 17 Enable */ 2541#define MC17 0x2 /* Mailbox 17 Enable */
2991#define nMC17 0x0
2992#define MC18 0x4 /* Mailbox 18 Enable */ 2542#define MC18 0x4 /* Mailbox 18 Enable */
2993#define nMC18 0x0
2994#define MC19 0x8 /* Mailbox 19 Enable */ 2543#define MC19 0x8 /* Mailbox 19 Enable */
2995#define nMC19 0x0
2996#define MC20 0x10 /* Mailbox 20 Enable */ 2544#define MC20 0x10 /* Mailbox 20 Enable */
2997#define nMC20 0x0
2998#define MC21 0x20 /* Mailbox 21 Enable */ 2545#define MC21 0x20 /* Mailbox 21 Enable */
2999#define nMC21 0x0
3000#define MC22 0x40 /* Mailbox 22 Enable */ 2546#define MC22 0x40 /* Mailbox 22 Enable */
3001#define nMC22 0x0
3002#define MC23 0x80 /* Mailbox 23 Enable */ 2547#define MC23 0x80 /* Mailbox 23 Enable */
3003#define nMC23 0x0
3004#define MC24 0x100 /* Mailbox 24 Enable */ 2548#define MC24 0x100 /* Mailbox 24 Enable */
3005#define nMC24 0x0
3006#define MC25 0x200 /* Mailbox 25 Enable */ 2549#define MC25 0x200 /* Mailbox 25 Enable */
3007#define nMC25 0x0
3008#define MC26 0x400 /* Mailbox 26 Enable */ 2550#define MC26 0x400 /* Mailbox 26 Enable */
3009#define nMC26 0x0
3010#define MC27 0x800 /* Mailbox 27 Enable */ 2551#define MC27 0x800 /* Mailbox 27 Enable */
3011#define nMC27 0x0
3012#define MC28 0x1000 /* Mailbox 28 Enable */ 2552#define MC28 0x1000 /* Mailbox 28 Enable */
3013#define nMC28 0x0
3014#define MC29 0x2000 /* Mailbox 29 Enable */ 2553#define MC29 0x2000 /* Mailbox 29 Enable */
3015#define nMC29 0x0
3016#define MC30 0x4000 /* Mailbox 30 Enable */ 2554#define MC30 0x4000 /* Mailbox 30 Enable */
3017#define nMC30 0x0
3018#define MC31 0x8000 /* Mailbox 31 Enable */ 2555#define MC31 0x8000 /* Mailbox 31 Enable */
3019#define nMC31 0x0
3020 2556
3021/* Bit masks for CAN0_MD1 */ 2557/* Bit masks for CAN0_MD1 */
3022 2558
3023#define MD0 0x1 /* Mailbox 0 Receive Enable */ 2559#define MD0 0x1 /* Mailbox 0 Receive Enable */
3024#define nMD0 0x0
3025#define MD1 0x2 /* Mailbox 1 Receive Enable */ 2560#define MD1 0x2 /* Mailbox 1 Receive Enable */
3026#define nMD1 0x0
3027#define MD2 0x4 /* Mailbox 2 Receive Enable */ 2561#define MD2 0x4 /* Mailbox 2 Receive Enable */
3028#define nMD2 0x0
3029#define MD3 0x8 /* Mailbox 3 Receive Enable */ 2562#define MD3 0x8 /* Mailbox 3 Receive Enable */
3030#define nMD3 0x0
3031#define MD4 0x10 /* Mailbox 4 Receive Enable */ 2563#define MD4 0x10 /* Mailbox 4 Receive Enable */
3032#define nMD4 0x0
3033#define MD5 0x20 /* Mailbox 5 Receive Enable */ 2564#define MD5 0x20 /* Mailbox 5 Receive Enable */
3034#define nMD5 0x0
3035#define MD6 0x40 /* Mailbox 6 Receive Enable */ 2565#define MD6 0x40 /* Mailbox 6 Receive Enable */
3036#define nMD6 0x0
3037#define MD7 0x80 /* Mailbox 7 Receive Enable */ 2566#define MD7 0x80 /* Mailbox 7 Receive Enable */
3038#define nMD7 0x0
3039#define MD8 0x100 /* Mailbox 8 Receive Enable */ 2567#define MD8 0x100 /* Mailbox 8 Receive Enable */
3040#define nMD8 0x0
3041#define MD9 0x200 /* Mailbox 9 Receive Enable */ 2568#define MD9 0x200 /* Mailbox 9 Receive Enable */
3042#define nMD9 0x0
3043#define MD10 0x400 /* Mailbox 10 Receive Enable */ 2569#define MD10 0x400 /* Mailbox 10 Receive Enable */
3044#define nMD10 0x0
3045#define MD11 0x800 /* Mailbox 11 Receive Enable */ 2570#define MD11 0x800 /* Mailbox 11 Receive Enable */
3046#define nMD11 0x0
3047#define MD12 0x1000 /* Mailbox 12 Receive Enable */ 2571#define MD12 0x1000 /* Mailbox 12 Receive Enable */
3048#define nMD12 0x0
3049#define MD13 0x2000 /* Mailbox 13 Receive Enable */ 2572#define MD13 0x2000 /* Mailbox 13 Receive Enable */
3050#define nMD13 0x0
3051#define MD14 0x4000 /* Mailbox 14 Receive Enable */ 2573#define MD14 0x4000 /* Mailbox 14 Receive Enable */
3052#define nMD14 0x0
3053#define MD15 0x8000 /* Mailbox 15 Receive Enable */ 2574#define MD15 0x8000 /* Mailbox 15 Receive Enable */
3054#define nMD15 0x0
3055 2575
3056/* Bit masks for CAN0_MD2 */ 2576/* Bit masks for CAN0_MD2 */
3057 2577
3058#define MD16 0x1 /* Mailbox 16 Receive Enable */ 2578#define MD16 0x1 /* Mailbox 16 Receive Enable */
3059#define nMD16 0x0
3060#define MD17 0x2 /* Mailbox 17 Receive Enable */ 2579#define MD17 0x2 /* Mailbox 17 Receive Enable */
3061#define nMD17 0x0
3062#define MD18 0x4 /* Mailbox 18 Receive Enable */ 2580#define MD18 0x4 /* Mailbox 18 Receive Enable */
3063#define nMD18 0x0
3064#define MD19 0x8 /* Mailbox 19 Receive Enable */ 2581#define MD19 0x8 /* Mailbox 19 Receive Enable */
3065#define nMD19 0x0
3066#define MD20 0x10 /* Mailbox 20 Receive Enable */ 2582#define MD20 0x10 /* Mailbox 20 Receive Enable */
3067#define nMD20 0x0
3068#define MD21 0x20 /* Mailbox 21 Receive Enable */ 2583#define MD21 0x20 /* Mailbox 21 Receive Enable */
3069#define nMD21 0x0
3070#define MD22 0x40 /* Mailbox 22 Receive Enable */ 2584#define MD22 0x40 /* Mailbox 22 Receive Enable */
3071#define nMD22 0x0
3072#define MD23 0x80 /* Mailbox 23 Receive Enable */ 2585#define MD23 0x80 /* Mailbox 23 Receive Enable */
3073#define nMD23 0x0
3074#define MD24 0x100 /* Mailbox 24 Receive Enable */ 2586#define MD24 0x100 /* Mailbox 24 Receive Enable */
3075#define nMD24 0x0
3076#define MD25 0x200 /* Mailbox 25 Receive Enable */ 2587#define MD25 0x200 /* Mailbox 25 Receive Enable */
3077#define nMD25 0x0
3078#define MD26 0x400 /* Mailbox 26 Receive Enable */ 2588#define MD26 0x400 /* Mailbox 26 Receive Enable */
3079#define nMD26 0x0
3080#define MD27 0x800 /* Mailbox 27 Receive Enable */ 2589#define MD27 0x800 /* Mailbox 27 Receive Enable */
3081#define nMD27 0x0
3082#define MD28 0x1000 /* Mailbox 28 Receive Enable */ 2590#define MD28 0x1000 /* Mailbox 28 Receive Enable */
3083#define nMD28 0x0
3084#define MD29 0x2000 /* Mailbox 29 Receive Enable */ 2591#define MD29 0x2000 /* Mailbox 29 Receive Enable */
3085#define nMD29 0x0
3086#define MD30 0x4000 /* Mailbox 30 Receive Enable */ 2592#define MD30 0x4000 /* Mailbox 30 Receive Enable */
3087#define nMD30 0x0
3088#define MD31 0x8000 /* Mailbox 31 Receive Enable */ 2593#define MD31 0x8000 /* Mailbox 31 Receive Enable */
3089#define nMD31 0x0
3090 2594
3091/* Bit masks for CAN0_RMP1 */ 2595/* Bit masks for CAN0_RMP1 */
3092 2596
3093#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */ 2597#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */
3094#define nRMP0 0x0
3095#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */ 2598#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */
3096#define nRMP1 0x0
3097#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */ 2599#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
3098#define nRMP2 0x0
3099#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */ 2600#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */
3100#define nRMP3 0x0
3101#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */ 2601#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */
3102#define nRMP4 0x0
3103#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */ 2602#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */
3104#define nRMP5 0x0
3105#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */ 2603#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */
3106#define nRMP6 0x0
3107#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */ 2604#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */
3108#define nRMP7 0x0
3109#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */ 2605#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */
3110#define nRMP8 0x0
3111#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */ 2606#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */
3112#define nRMP9 0x0
3113#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */ 2607#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */
3114#define nRMP10 0x0
3115#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */ 2608#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */
3116#define nRMP11 0x0
3117#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */ 2609#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */
3118#define nRMP12 0x0
3119#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */ 2610#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */
3120#define nRMP13 0x0
3121#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */ 2611#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */
3122#define nRMP14 0x0
3123#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */ 2612#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */
3124#define nRMP15 0x0
3125 2613
3126/* Bit masks for CAN0_RMP2 */ 2614/* Bit masks for CAN0_RMP2 */
3127 2615
3128#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */ 2616#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */
3129#define nRMP16 0x0
3130#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */ 2617#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */
3131#define nRMP17 0x0
3132#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */ 2618#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
3133#define nRMP18 0x0
3134#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */ 2619#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */
3135#define nRMP19 0x0
3136#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */ 2620#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */
3137#define nRMP20 0x0
3138#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */ 2621#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */
3139#define nRMP21 0x0
3140#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */ 2622#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */
3141#define nRMP22 0x0
3142#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */ 2623#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */
3143#define nRMP23 0x0
3144#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */ 2624#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */
3145#define nRMP24 0x0
3146#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */ 2625#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */
3147#define nRMP25 0x0
3148#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */ 2626#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */
3149#define nRMP26 0x0
3150#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */ 2627#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */
3151#define nRMP27 0x0
3152#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */ 2628#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */
3153#define nRMP28 0x0
3154#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */ 2629#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */
3155#define nRMP29 0x0
3156#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */ 2630#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */
3157#define nRMP30 0x0
3158#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */ 2631#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */
3159#define nRMP31 0x0
3160 2632
3161/* Bit masks for CAN0_RML1 */ 2633/* Bit masks for CAN0_RML1 */
3162 2634
3163#define RML0 0x1 /* Mailbox 0 Receive Message Lost */ 2635#define RML0 0x1 /* Mailbox 0 Receive Message Lost */
3164#define nRML0 0x0
3165#define RML1 0x2 /* Mailbox 1 Receive Message Lost */ 2636#define RML1 0x2 /* Mailbox 1 Receive Message Lost */
3166#define nRML1 0x0
3167#define RML2 0x4 /* Mailbox 2 Receive Message Lost */ 2637#define RML2 0x4 /* Mailbox 2 Receive Message Lost */
3168#define nRML2 0x0
3169#define RML3 0x8 /* Mailbox 3 Receive Message Lost */ 2638#define RML3 0x8 /* Mailbox 3 Receive Message Lost */
3170#define nRML3 0x0
3171#define RML4 0x10 /* Mailbox 4 Receive Message Lost */ 2639#define RML4 0x10 /* Mailbox 4 Receive Message Lost */
3172#define nRML4 0x0
3173#define RML5 0x20 /* Mailbox 5 Receive Message Lost */ 2640#define RML5 0x20 /* Mailbox 5 Receive Message Lost */
3174#define nRML5 0x0
3175#define RML6 0x40 /* Mailbox 6 Receive Message Lost */ 2641#define RML6 0x40 /* Mailbox 6 Receive Message Lost */
3176#define nRML6 0x0
3177#define RML7 0x80 /* Mailbox 7 Receive Message Lost */ 2642#define RML7 0x80 /* Mailbox 7 Receive Message Lost */
3178#define nRML7 0x0
3179#define RML8 0x100 /* Mailbox 8 Receive Message Lost */ 2643#define RML8 0x100 /* Mailbox 8 Receive Message Lost */
3180#define nRML8 0x0
3181#define RML9 0x200 /* Mailbox 9 Receive Message Lost */ 2644#define RML9 0x200 /* Mailbox 9 Receive Message Lost */
3182#define nRML9 0x0
3183#define RML10 0x400 /* Mailbox 10 Receive Message Lost */ 2645#define RML10 0x400 /* Mailbox 10 Receive Message Lost */
3184#define nRML10 0x0
3185#define RML11 0x800 /* Mailbox 11 Receive Message Lost */ 2646#define RML11 0x800 /* Mailbox 11 Receive Message Lost */
3186#define nRML11 0x0
3187#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */ 2647#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */
3188#define nRML12 0x0
3189#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */ 2648#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */
3190#define nRML13 0x0
3191#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */ 2649#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */
3192#define nRML14 0x0
3193#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */ 2650#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */
3194#define nRML15 0x0
3195 2651
3196/* Bit masks for CAN0_RML2 */ 2652/* Bit masks for CAN0_RML2 */
3197 2653
3198#define RML16 0x1 /* Mailbox 16 Receive Message Lost */ 2654#define RML16 0x1 /* Mailbox 16 Receive Message Lost */
3199#define nRML16 0x0
3200#define RML17 0x2 /* Mailbox 17 Receive Message Lost */ 2655#define RML17 0x2 /* Mailbox 17 Receive Message Lost */
3201#define nRML17 0x0
3202#define RML18 0x4 /* Mailbox 18 Receive Message Lost */ 2656#define RML18 0x4 /* Mailbox 18 Receive Message Lost */
3203#define nRML18 0x0
3204#define RML19 0x8 /* Mailbox 19 Receive Message Lost */ 2657#define RML19 0x8 /* Mailbox 19 Receive Message Lost */
3205#define nRML19 0x0
3206#define RML20 0x10 /* Mailbox 20 Receive Message Lost */ 2658#define RML20 0x10 /* Mailbox 20 Receive Message Lost */
3207#define nRML20 0x0
3208#define RML21 0x20 /* Mailbox 21 Receive Message Lost */ 2659#define RML21 0x20 /* Mailbox 21 Receive Message Lost */
3209#define nRML21 0x0
3210#define RML22 0x40 /* Mailbox 22 Receive Message Lost */ 2660#define RML22 0x40 /* Mailbox 22 Receive Message Lost */
3211#define nRML22 0x0
3212#define RML23 0x80 /* Mailbox 23 Receive Message Lost */ 2661#define RML23 0x80 /* Mailbox 23 Receive Message Lost */
3213#define nRML23 0x0
3214#define RML24 0x100 /* Mailbox 24 Receive Message Lost */ 2662#define RML24 0x100 /* Mailbox 24 Receive Message Lost */
3215#define nRML24 0x0
3216#define RML25 0x200 /* Mailbox 25 Receive Message Lost */ 2663#define RML25 0x200 /* Mailbox 25 Receive Message Lost */
3217#define nRML25 0x0
3218#define RML26 0x400 /* Mailbox 26 Receive Message Lost */ 2664#define RML26 0x400 /* Mailbox 26 Receive Message Lost */
3219#define nRML26 0x0
3220#define RML27 0x800 /* Mailbox 27 Receive Message Lost */ 2665#define RML27 0x800 /* Mailbox 27 Receive Message Lost */
3221#define nRML27 0x0
3222#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */ 2666#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */
3223#define nRML28 0x0
3224#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */ 2667#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */
3225#define nRML29 0x0
3226#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */ 2668#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */
3227#define nRML30 0x0
3228#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */ 2669#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */
3229#define nRML31 0x0
3230 2670
3231/* Bit masks for CAN0_OPSS1 */ 2671/* Bit masks for CAN0_OPSS1 */
3232 2672
3233#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */ 2673#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
3234#define nOPSS0 0x0
3235#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */ 2674#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
3236#define nOPSS1 0x0
3237#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */ 2675#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
3238#define nOPSS2 0x0
3239#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */ 2676#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
3240#define nOPSS3 0x0
3241#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */ 2677#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
3242#define nOPSS4 0x0
3243#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */ 2678#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
3244#define nOPSS5 0x0
3245#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */ 2679#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
3246#define nOPSS6 0x0
3247#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */ 2680#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
3248#define nOPSS7 0x0
3249#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */ 2681#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
3250#define nOPSS8 0x0
3251#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */ 2682#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
3252#define nOPSS9 0x0
3253#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */ 2683#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
3254#define nOPSS10 0x0
3255#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */ 2684#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
3256#define nOPSS11 0x0
3257#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */ 2685#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
3258#define nOPSS12 0x0
3259#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */ 2686#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
3260#define nOPSS13 0x0
3261#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */ 2687#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
3262#define nOPSS14 0x0
3263#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */ 2688#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
3264#define nOPSS15 0x0
3265 2689
3266/* Bit masks for CAN0_OPSS2 */ 2690/* Bit masks for CAN0_OPSS2 */
3267 2691
3268#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */ 2692#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
3269#define nOPSS16 0x0
3270#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */ 2693#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
3271#define nOPSS17 0x0
3272#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */ 2694#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
3273#define nOPSS18 0x0
3274#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */ 2695#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
3275#define nOPSS19 0x0
3276#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */ 2696#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
3277#define nOPSS20 0x0
3278#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */ 2697#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
3279#define nOPSS21 0x0
3280#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */ 2698#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
3281#define nOPSS22 0x0
3282#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */ 2699#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
3283#define nOPSS23 0x0
3284#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */ 2700#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
3285#define nOPSS24 0x0
3286#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */ 2701#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
3287#define nOPSS25 0x0
3288#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */ 2702#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
3289#define nOPSS26 0x0
3290#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */ 2703#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
3291#define nOPSS27 0x0
3292#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */ 2704#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
3293#define nOPSS28 0x0
3294#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */ 2705#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
3295#define nOPSS29 0x0
3296#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */ 2706#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
3297#define nOPSS30 0x0
3298#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */ 2707#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
3299#define nOPSS31 0x0
3300 2708
3301/* Bit masks for CAN0_TRS1 */ 2709/* Bit masks for CAN0_TRS1 */
3302 2710
3303#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */ 2711#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */
3304#define nTRS0 0x0
3305#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */ 2712#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */
3306#define nTRS1 0x0
3307#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */ 2713#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
3308#define nTRS2 0x0
3309#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */ 2714#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */
3310#define nTRS3 0x0
3311#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */ 2715#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */
3312#define nTRS4 0x0
3313#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */ 2716#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */
3314#define nTRS5 0x0
3315#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */ 2717#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */
3316#define nTRS6 0x0
3317#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */ 2718#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */
3318#define nTRS7 0x0
3319#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */ 2719#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */
3320#define nTRS8 0x0
3321#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */ 2720#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */
3322#define nTRS9 0x0
3323#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */ 2721#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */
3324#define nTRS10 0x0
3325#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */ 2722#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */
3326#define nTRS11 0x0
3327#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */ 2723#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */
3328#define nTRS12 0x0
3329#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */ 2724#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */
3330#define nTRS13 0x0
3331#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */ 2725#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */
3332#define nTRS14 0x0
3333#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */ 2726#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */
3334#define nTRS15 0x0
3335 2727
3336/* Bit masks for CAN0_TRS2 */ 2728/* Bit masks for CAN0_TRS2 */
3337 2729
3338#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */ 2730#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */
3339#define nTRS16 0x0
3340#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */ 2731#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */
3341#define nTRS17 0x0
3342#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */ 2732#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
3343#define nTRS18 0x0
3344#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */ 2733#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */
3345#define nTRS19 0x0
3346#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */ 2734#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */
3347#define nTRS20 0x0
3348#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */ 2735#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */
3349#define nTRS21 0x0
3350#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */ 2736#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */
3351#define nTRS22 0x0
3352#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */ 2737#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */
3353#define nTRS23 0x0
3354#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */ 2738#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */
3355#define nTRS24 0x0
3356#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */ 2739#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */
3357#define nTRS25 0x0
3358#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */ 2740#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */
3359#define nTRS26 0x0
3360#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */ 2741#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */
3361#define nTRS27 0x0
3362#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */ 2742#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */
3363#define nTRS28 0x0
3364#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */ 2743#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */
3365#define nTRS29 0x0
3366#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */ 2744#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */
3367#define nTRS30 0x0
3368#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */ 2745#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */
3369#define nTRS31 0x0
3370 2746
3371/* Bit masks for CAN0_TRR1 */ 2747/* Bit masks for CAN0_TRR1 */
3372 2748
3373#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */ 2749#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */
3374#define nTRR0 0x0
3375#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */ 2750#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */
3376#define nTRR1 0x0
3377#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */ 2751#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
3378#define nTRR2 0x0
3379#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */ 2752#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */
3380#define nTRR3 0x0
3381#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */ 2753#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */
3382#define nTRR4 0x0
3383#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */ 2754#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */
3384#define nTRR5 0x0
3385#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */ 2755#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */
3386#define nTRR6 0x0
3387#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */ 2756#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */
3388#define nTRR7 0x0
3389#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */ 2757#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */
3390#define nTRR8 0x0
3391#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */ 2758#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */
3392#define nTRR9 0x0
3393#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */ 2759#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */
3394#define nTRR10 0x0
3395#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */ 2760#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */
3396#define nTRR11 0x0
3397#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */ 2761#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */
3398#define nTRR12 0x0
3399#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */ 2762#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */
3400#define nTRR13 0x0
3401#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */ 2763#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */
3402#define nTRR14 0x0
3403#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */ 2764#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */
3404#define nTRR15 0x0
3405 2765
3406/* Bit masks for CAN0_TRR2 */ 2766/* Bit masks for CAN0_TRR2 */
3407 2767
3408#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */ 2768#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */
3409#define nTRR16 0x0
3410#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */ 2769#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */
3411#define nTRR17 0x0
3412#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */ 2770#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
3413#define nTRR18 0x0
3414#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */ 2771#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */
3415#define nTRR19 0x0
3416#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */ 2772#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */
3417#define nTRR20 0x0
3418#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */ 2773#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */
3419#define nTRR21 0x0
3420#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */ 2774#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */
3421#define nTRR22 0x0
3422#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */ 2775#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */
3423#define nTRR23 0x0
3424#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */ 2776#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */
3425#define nTRR24 0x0
3426#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */ 2777#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */
3427#define nTRR25 0x0
3428#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */ 2778#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */
3429#define nTRR26 0x0
3430#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */ 2779#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */
3431#define nTRR27 0x0
3432#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */ 2780#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */
3433#define nTRR28 0x0
3434#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */ 2781#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */
3435#define nTRR29 0x0
3436#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */ 2782#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */
3437#define nTRR30 0x0
3438#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */ 2783#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */
3439#define nTRR31 0x0
3440 2784
3441/* Bit masks for CAN0_AA1 */ 2785/* Bit masks for CAN0_AA1 */
3442 2786
3443#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */ 2787#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */
3444#define nAA0 0x0
3445#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */ 2788#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */
3446#define nAA1 0x0
3447#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */ 2789#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
3448#define nAA2 0x0
3449#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */ 2790#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */
3450#define nAA3 0x0
3451#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */ 2791#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */
3452#define nAA4 0x0
3453#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */ 2792#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */
3454#define nAA5 0x0
3455#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */ 2793#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */
3456#define nAA6 0x0
3457#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */ 2794#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */
3458#define nAA7 0x0
3459#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */ 2795#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */
3460#define nAA8 0x0
3461#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */ 2796#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */
3462#define nAA9 0x0
3463#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */ 2797#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */
3464#define nAA10 0x0
3465#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */ 2798#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */
3466#define nAA11 0x0
3467#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */ 2799#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */
3468#define nAA12 0x0
3469#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */ 2800#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */
3470#define nAA13 0x0
3471#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */ 2801#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */
3472#define nAA14 0x0
3473#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */ 2802#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */
3474#define nAA15 0x0
3475 2803
3476/* Bit masks for CAN0_AA2 */ 2804/* Bit masks for CAN0_AA2 */
3477 2805
3478#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */ 2806#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */
3479#define nAA16 0x0
3480#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */ 2807#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */
3481#define nAA17 0x0
3482#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */ 2808#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
3483#define nAA18 0x0
3484#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */ 2809#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */
3485#define nAA19 0x0
3486#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */ 2810#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */
3487#define nAA20 0x0
3488#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */ 2811#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */
3489#define nAA21 0x0
3490#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */ 2812#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */
3491#define nAA22 0x0
3492#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */ 2813#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */
3493#define nAA23 0x0
3494#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */ 2814#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */
3495#define nAA24 0x0
3496#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */ 2815#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */
3497#define nAA25 0x0
3498#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */ 2816#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */
3499#define nAA26 0x0
3500#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */ 2817#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */
3501#define nAA27 0x0
3502#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */ 2818#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */
3503#define nAA28 0x0
3504#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */ 2819#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */
3505#define nAA29 0x0
3506#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */ 2820#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */
3507#define nAA30 0x0
3508#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */ 2821#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */
3509#define nAA31 0x0
3510 2822
3511/* Bit masks for CAN0_TA1 */ 2823/* Bit masks for CAN0_TA1 */
3512 2824
3513#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */ 2825#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */
3514#define nTA0 0x0
3515#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */ 2826#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */
3516#define nTA1 0x0
3517#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */ 2827#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
3518#define nTA2 0x0
3519#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */ 2828#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */
3520#define nTA3 0x0
3521#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */ 2829#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */
3522#define nTA4 0x0
3523#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */ 2830#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */
3524#define nTA5 0x0
3525#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */ 2831#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */
3526#define nTA6 0x0
3527#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */ 2832#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */
3528#define nTA7 0x0
3529#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */ 2833#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */
3530#define nTA8 0x0
3531#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */ 2834#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */
3532#define nTA9 0x0
3533#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */ 2835#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */
3534#define nTA10 0x0
3535#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */ 2836#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */
3536#define nTA11 0x0
3537#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */ 2837#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */
3538#define nTA12 0x0
3539#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */ 2838#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */
3540#define nTA13 0x0
3541#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */ 2839#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */
3542#define nTA14 0x0
3543#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */ 2840#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */
3544#define nTA15 0x0
3545 2841
3546/* Bit masks for CAN0_TA2 */ 2842/* Bit masks for CAN0_TA2 */
3547 2843
3548#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */ 2844#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */
3549#define nTA16 0x0
3550#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */ 2845#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */
3551#define nTA17 0x0
3552#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */ 2846#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
3553#define nTA18 0x0
3554#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */ 2847#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */
3555#define nTA19 0x0
3556#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */ 2848#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */
3557#define nTA20 0x0
3558#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */ 2849#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */
3559#define nTA21 0x0
3560#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */ 2850#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */
3561#define nTA22 0x0
3562#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */ 2851#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */
3563#define nTA23 0x0
3564#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */ 2852#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */
3565#define nTA24 0x0
3566#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */ 2853#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */
3567#define nTA25 0x0
3568#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */ 2854#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */
3569#define nTA26 0x0
3570#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */ 2855#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */
3571#define nTA27 0x0
3572#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */ 2856#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */
3573#define nTA28 0x0
3574#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */ 2857#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */
3575#define nTA29 0x0
3576#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */ 2858#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */
3577#define nTA30 0x0
3578#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */ 2859#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */
3579#define nTA31 0x0
3580 2860
3581/* Bit masks for CAN0_RFH1 */ 2861/* Bit masks for CAN0_RFH1 */
3582 2862
3583#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */ 2863#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */
3584#define nRFH0 0x0
3585#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */ 2864#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */
3586#define nRFH1 0x0
3587#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */ 2865#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
3588#define nRFH2 0x0
3589#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */ 2866#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */
3590#define nRFH3 0x0
3591#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */ 2867#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */
3592#define nRFH4 0x0
3593#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */ 2868#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */
3594#define nRFH5 0x0
3595#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */ 2869#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */
3596#define nRFH6 0x0
3597#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */ 2870#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */
3598#define nRFH7 0x0
3599#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */ 2871#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */
3600#define nRFH8 0x0
3601#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */ 2872#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */
3602#define nRFH9 0x0
3603#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */ 2873#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */
3604#define nRFH10 0x0
3605#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */ 2874#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */
3606#define nRFH11 0x0
3607#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */ 2875#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */
3608#define nRFH12 0x0
3609#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */ 2876#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */
3610#define nRFH13 0x0
3611#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */ 2877#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */
3612#define nRFH14 0x0
3613#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */ 2878#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */
3614#define nRFH15 0x0
3615 2879
3616/* Bit masks for CAN0_RFH2 */ 2880/* Bit masks for CAN0_RFH2 */
3617 2881
3618#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */ 2882#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */
3619#define nRFH16 0x0
3620#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */ 2883#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */
3621#define nRFH17 0x0
3622#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */ 2884#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
3623#define nRFH18 0x0
3624#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */ 2885#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */
3625#define nRFH19 0x0
3626#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */ 2886#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */
3627#define nRFH20 0x0
3628#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */ 2887#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */
3629#define nRFH21 0x0
3630#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */ 2888#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */
3631#define nRFH22 0x0
3632#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */ 2889#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */
3633#define nRFH23 0x0
3634#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */ 2890#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */
3635#define nRFH24 0x0
3636#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */ 2891#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */
3637#define nRFH25 0x0
3638#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */ 2892#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */
3639#define nRFH26 0x0
3640#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */ 2893#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */
3641#define nRFH27 0x0
3642#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */ 2894#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */
3643#define nRFH28 0x0
3644#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */ 2895#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */
3645#define nRFH29 0x0
3646#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */ 2896#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */
3647#define nRFH30 0x0
3648#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */ 2897#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */
3649#define nRFH31 0x0
3650 2898
3651/* Bit masks for CAN0_MBIM1 */ 2899/* Bit masks for CAN0_MBIM1 */
3652 2900
3653#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */ 2901#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */
3654#define nMBIM0 0x0
3655#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */ 2902#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */
3656#define nMBIM1 0x0
3657#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */ 2903#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
3658#define nMBIM2 0x0
3659#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */ 2904#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */
3660#define nMBIM3 0x0
3661#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */ 2905#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */
3662#define nMBIM4 0x0
3663#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */ 2906#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */
3664#define nMBIM5 0x0
3665#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */ 2907#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */
3666#define nMBIM6 0x0
3667#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */ 2908#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */
3668#define nMBIM7 0x0
3669#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */ 2909#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */
3670#define nMBIM8 0x0
3671#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */ 2910#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */
3672#define nMBIM9 0x0
3673#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */ 2911#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */
3674#define nMBIM10 0x0
3675#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */ 2912#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */
3676#define nMBIM11 0x0
3677#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */ 2913#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */
3678#define nMBIM12 0x0
3679#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */ 2914#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */
3680#define nMBIM13 0x0
3681#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */ 2915#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */
3682#define nMBIM14 0x0
3683#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */ 2916#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */
3684#define nMBIM15 0x0
3685 2917
3686/* Bit masks for CAN0_MBIM2 */ 2918/* Bit masks for CAN0_MBIM2 */
3687 2919
3688#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */ 2920#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */
3689#define nMBIM16 0x0
3690#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */ 2921#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */
3691#define nMBIM17 0x0
3692#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */ 2922#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
3693#define nMBIM18 0x0
3694#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */ 2923#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */
3695#define nMBIM19 0x0
3696#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */ 2924#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */
3697#define nMBIM20 0x0
3698#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */ 2925#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */
3699#define nMBIM21 0x0
3700#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */ 2926#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */
3701#define nMBIM22 0x0
3702#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */ 2927#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */
3703#define nMBIM23 0x0
3704#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */ 2928#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */
3705#define nMBIM24 0x0
3706#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */ 2929#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */
3707#define nMBIM25 0x0
3708#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */ 2930#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */
3709#define nMBIM26 0x0
3710#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */ 2931#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */
3711#define nMBIM27 0x0
3712#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */ 2932#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */
3713#define nMBIM28 0x0
3714#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */ 2933#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */
3715#define nMBIM29 0x0
3716#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */ 2934#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */
3717#define nMBIM30 0x0
3718#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */ 2935#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */
3719#define nMBIM31 0x0
3720 2936
3721/* Bit masks for CAN0_MBTIF1 */ 2937/* Bit masks for CAN0_MBTIF1 */
3722 2938
3723#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */ 2939#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */
3724#define nMBTIF0 0x0
3725#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */ 2940#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */
3726#define nMBTIF1 0x0
3727#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */ 2941#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
3728#define nMBTIF2 0x0
3729#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */ 2942#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */
3730#define nMBTIF3 0x0
3731#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */ 2943#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */
3732#define nMBTIF4 0x0
3733#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */ 2944#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */
3734#define nMBTIF5 0x0
3735#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */ 2945#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */
3736#define nMBTIF6 0x0
3737#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */ 2946#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */
3738#define nMBTIF7 0x0
3739#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */ 2947#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */
3740#define nMBTIF8 0x0
3741#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */ 2948#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */
3742#define nMBTIF9 0x0
3743#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */ 2949#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */
3744#define nMBTIF10 0x0
3745#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */ 2950#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */
3746#define nMBTIF11 0x0
3747#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */ 2951#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */
3748#define nMBTIF12 0x0
3749#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */ 2952#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */
3750#define nMBTIF13 0x0
3751#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */ 2953#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */
3752#define nMBTIF14 0x0
3753#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */ 2954#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */
3754#define nMBTIF15 0x0
3755 2955
3756/* Bit masks for CAN0_MBTIF2 */ 2956/* Bit masks for CAN0_MBTIF2 */
3757 2957
3758#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */ 2958#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */
3759#define nMBTIF16 0x0
3760#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */ 2959#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */
3761#define nMBTIF17 0x0
3762#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */ 2960#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
3763#define nMBTIF18 0x0
3764#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */ 2961#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */
3765#define nMBTIF19 0x0
3766#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */ 2962#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */
3767#define nMBTIF20 0x0
3768#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */ 2963#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */
3769#define nMBTIF21 0x0
3770#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */ 2964#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */
3771#define nMBTIF22 0x0
3772#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */ 2965#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */
3773#define nMBTIF23 0x0
3774#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */ 2966#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */
3775#define nMBTIF24 0x0
3776#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */ 2967#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */
3777#define nMBTIF25 0x0
3778#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */ 2968#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */
3779#define nMBTIF26 0x0
3780#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */ 2969#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */
3781#define nMBTIF27 0x0
3782#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */ 2970#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */
3783#define nMBTIF28 0x0
3784#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */ 2971#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */
3785#define nMBTIF29 0x0
3786#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */ 2972#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */
3787#define nMBTIF30 0x0
3788#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */ 2973#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */
3789#define nMBTIF31 0x0
3790 2974
3791/* Bit masks for CAN0_MBRIF1 */ 2975/* Bit masks for CAN0_MBRIF1 */
3792 2976
3793#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */ 2977#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */
3794#define nMBRIF0 0x0
3795#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */ 2978#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */
3796#define nMBRIF1 0x0
3797#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */ 2979#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
3798#define nMBRIF2 0x0
3799#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */ 2980#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */
3800#define nMBRIF3 0x0
3801#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */ 2981#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */
3802#define nMBRIF4 0x0
3803#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */ 2982#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */
3804#define nMBRIF5 0x0
3805#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */ 2983#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */
3806#define nMBRIF6 0x0
3807#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */ 2984#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */
3808#define nMBRIF7 0x0
3809#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */ 2985#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */
3810#define nMBRIF8 0x0
3811#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */ 2986#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */
3812#define nMBRIF9 0x0
3813#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */ 2987#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */
3814#define nMBRIF10 0x0
3815#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */ 2988#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */
3816#define nMBRIF11 0x0
3817#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */ 2989#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */
3818#define nMBRIF12 0x0
3819#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */ 2990#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */
3820#define nMBRIF13 0x0
3821#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */ 2991#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */
3822#define nMBRIF14 0x0
3823#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */ 2992#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */
3824#define nMBRIF15 0x0
3825 2993
3826/* Bit masks for CAN0_MBRIF2 */ 2994/* Bit masks for CAN0_MBRIF2 */
3827 2995
3828#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */ 2996#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */
3829#define nMBRIF16 0x0
3830#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */ 2997#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */
3831#define nMBRIF17 0x0
3832#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */ 2998#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
3833#define nMBRIF18 0x0
3834#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */ 2999#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */
3835#define nMBRIF19 0x0
3836#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */ 3000#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */
3837#define nMBRIF20 0x0
3838#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */ 3001#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */
3839#define nMBRIF21 0x0
3840#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */ 3002#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */
3841#define nMBRIF22 0x0
3842#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */ 3003#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */
3843#define nMBRIF23 0x0
3844#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */ 3004#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */
3845#define nMBRIF24 0x0
3846#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */ 3005#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */
3847#define nMBRIF25 0x0
3848#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */ 3006#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */
3849#define nMBRIF26 0x0
3850#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */ 3007#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */
3851#define nMBRIF27 0x0
3852#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */ 3008#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */
3853#define nMBRIF28 0x0
3854#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */ 3009#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */
3855#define nMBRIF29 0x0
3856#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */ 3010#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */
3857#define nMBRIF30 0x0
3858#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */ 3011#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */
3859#define nMBRIF31 0x0
3860 3012
3861/* Bit masks for EPPIx_STATUS */ 3013/* Bit masks for EPPIx_STATUS */
3862 3014
3863#define CFIFO_ERR 0x1 /* Chroma FIFO Error */ 3015#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
3864#define nCFIFO_ERR 0x0
3865#define YFIFO_ERR 0x2 /* Luma FIFO Error */ 3016#define YFIFO_ERR 0x2 /* Luma FIFO Error */
3866#define nYFIFO_ERR 0x0
3867#define LTERR_OVR 0x4 /* Line Track Overflow */ 3017#define LTERR_OVR 0x4 /* Line Track Overflow */
3868#define nLTERR_OVR 0x0
3869#define LTERR_UNDR 0x8 /* Line Track Underflow */ 3018#define LTERR_UNDR 0x8 /* Line Track Underflow */
3870#define nLTERR_UNDR 0x0
3871#define FTERR_OVR 0x10 /* Frame Track Overflow */ 3019#define FTERR_OVR 0x10 /* Frame Track Overflow */
3872#define nFTERR_OVR 0x0
3873#define FTERR_UNDR 0x20 /* Frame Track Underflow */ 3020#define FTERR_UNDR 0x20 /* Frame Track Underflow */
3874#define nFTERR_UNDR 0x0
3875#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */ 3021#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
3876#define nERR_NCOR 0x0
3877#define DMA1URQ 0x80 /* DMA1 Urgent Request */ 3022#define DMA1URQ 0x80 /* DMA1 Urgent Request */
3878#define nDMA1URQ 0x0
3879#define DMA0URQ 0x100 /* DMA0 Urgent Request */ 3023#define DMA0URQ 0x100 /* DMA0 Urgent Request */
3880#define nDMA0URQ 0x0
3881#define ERR_DET 0x4000 /* Preamble Error Detected */ 3024#define ERR_DET 0x4000 /* Preamble Error Detected */
3882#define nERR_DET 0x0
3883#define FLD 0x8000 /* Field */ 3025#define FLD 0x8000 /* Field */
3884#define nFLD 0x0
3885 3026
3886/* Bit masks for EPPIx_CONTROL */ 3027/* Bit masks for EPPIx_CONTROL */
3887 3028
3888#define EPPI_EN 0x1 /* Enable */ 3029#define EPPI_EN 0x1 /* Enable */
3889#define nEPPI_EN 0x0
3890#define EPPI_DIR 0x2 /* Direction */ 3030#define EPPI_DIR 0x2 /* Direction */
3891#define nEPPI_DIR 0x0
3892#define XFR_TYPE 0xc /* Operating Mode */ 3031#define XFR_TYPE 0xc /* Operating Mode */
3893#define FS_CFG 0x30 /* Frame Sync Configuration */ 3032#define FS_CFG 0x30 /* Frame Sync Configuration */
3894#define FLD_SEL 0x40 /* Field Select/Trigger */ 3033#define FLD_SEL 0x40 /* Field Select/Trigger */
3895#define nFLD_SEL 0x0
3896#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */ 3034#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
3897#define nITU_TYPE 0x0
3898#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */ 3035#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
3899#define nBLANKGEN 0x0
3900#define ICLKGEN 0x200 /* Internal Clock Generation */ 3036#define ICLKGEN 0x200 /* Internal Clock Generation */
3901#define nICLKGEN 0x0
3902#define IFSGEN 0x400 /* Internal Frame Sync Generation */ 3037#define IFSGEN 0x400 /* Internal Frame Sync Generation */
3903#define nIFSGEN 0x0
3904#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */ 3038#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
3905#define POLS 0x6000 /* Frame Sync Polarity */ 3039#define POLS 0x6000 /* Frame Sync Polarity */
3906#define DLENGTH 0x38000 /* Data Length */ 3040#define DLENGTH 0x38000 /* Data Length */
3907#define SKIP_EN 0x40000 /* Skip Enable */ 3041#define SKIP_EN 0x40000 /* Skip Enable */
3908#define nSKIP_EN 0x0
3909#define SKIP_EO 0x80000 /* Skip Even or Odd */ 3042#define SKIP_EO 0x80000 /* Skip Even or Odd */
3910#define nSKIP_EO 0x0
3911#define PACKEN 0x100000 /* Packing/Unpacking Enable */ 3043#define PACKEN 0x100000 /* Packing/Unpacking Enable */
3912#define nPACKEN 0x0
3913#define SWAPEN 0x200000 /* Swap Enable */ 3044#define SWAPEN 0x200000 /* Swap Enable */
3914#define nSWAPEN 0x0
3915#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */ 3045#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
3916#define nSIGN_EXT 0x0
3917#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */ 3046#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
3918#define nSPLT_EVEN_ODD 0x0
3919#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */ 3047#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
3920#define nSUBSPLT_ODD 0x0
3921#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */ 3048#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
3922#define nDMACFG 0x0
3923#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */ 3049#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
3924#define nRGB_FMT_EN 0x0
3925#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */ 3050#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
3926#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */ 3051#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
3927 3052
3053#define DLEN_8 (0 << 15) /* 000 - 8 bits */
3054#define DLEN_10 (1 << 15) /* 001 - 10 bits */
3055#define DLEN_12 (2 << 15) /* 010 - 12 bits */
3056#define DLEN_14 (3 << 15) /* 011 - 14 bits */
3057#define DLEN_16 (4 << 15) /* 100 - 16 bits */
3058#define DLEN_18 (5 << 15) /* 101 - 18 bits */
3059#define DLEN_24 (6 << 15) /* 110 - 24 bits */
3060
3061
3928/* Bit masks for EPPIx_FS2W_LVB */ 3062/* Bit masks for EPPIx_FS2W_LVB */
3929 3063
3930#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */ 3064#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */
@@ -3951,60 +3085,36 @@
3951/* Bit masks for SPIx_CTL */ 3085/* Bit masks for SPIx_CTL */
3952 3086
3953#define SPE 0x4000 /* SPI Enable */ 3087#define SPE 0x4000 /* SPI Enable */
3954#define nSPE 0x0
3955#define WOM 0x2000 /* Write Open Drain Master */ 3088#define WOM 0x2000 /* Write Open Drain Master */
3956#define nWOM 0x0
3957#define MSTR 0x1000 /* Master Mode */ 3089#define MSTR 0x1000 /* Master Mode */
3958#define nMSTR 0x0
3959#define CPOL 0x800 /* Clock Polarity */ 3090#define CPOL 0x800 /* Clock Polarity */
3960#define nCPOL 0x0
3961#define CPHA 0x400 /* Clock Phase */ 3091#define CPHA 0x400 /* Clock Phase */
3962#define nCPHA 0x0
3963#define LSBF 0x200 /* LSB First */ 3092#define LSBF 0x200 /* LSB First */
3964#define nLSBF 0x0
3965#define SIZE 0x100 /* Size of Words */ 3093#define SIZE 0x100 /* Size of Words */
3966#define nSIZE 0x0
3967#define EMISO 0x20 /* Enable MISO Output */ 3094#define EMISO 0x20 /* Enable MISO Output */
3968#define nEMISO 0x0
3969#define PSSE 0x10 /* Slave-Select Enable */ 3095#define PSSE 0x10 /* Slave-Select Enable */
3970#define nPSSE 0x0
3971#define GM 0x8 /* Get More Data */ 3096#define GM 0x8 /* Get More Data */
3972#define nGM 0x0
3973#define SZ 0x4 /* Send Zero */ 3097#define SZ 0x4 /* Send Zero */
3974#define nSZ 0x0
3975#define TIMOD 0x3 /* Transfer Initiation Mode */ 3098#define TIMOD 0x3 /* Transfer Initiation Mode */
3976 3099
3977/* Bit masks for SPIx_FLG */ 3100/* Bit masks for SPIx_FLG */
3978 3101
3979#define FLS1 0x2 /* Slave Select Enable 1 */ 3102#define FLS1 0x2 /* Slave Select Enable 1 */
3980#define nFLS1 0x0
3981#define FLS2 0x4 /* Slave Select Enable 2 */ 3103#define FLS2 0x4 /* Slave Select Enable 2 */
3982#define nFLS2 0x0
3983#define FLS3 0x8 /* Slave Select Enable 3 */ 3104#define FLS3 0x8 /* Slave Select Enable 3 */
3984#define nFLS3 0x0
3985#define FLG1 0x200 /* Slave Select Value 1 */ 3105#define FLG1 0x200 /* Slave Select Value 1 */
3986#define nFLG1 0x0
3987#define FLG2 0x400 /* Slave Select Value 2 */ 3106#define FLG2 0x400 /* Slave Select Value 2 */
3988#define nFLG2 0x0
3989#define FLG3 0x800 /* Slave Select Value 3 */ 3107#define FLG3 0x800 /* Slave Select Value 3 */
3990#define nFLG3 0x0
3991 3108
3992/* Bit masks for SPIx_STAT */ 3109/* Bit masks for SPIx_STAT */
3993 3110
3994#define TXCOL 0x40 /* Transmit Collision Error */ 3111#define TXCOL 0x40 /* Transmit Collision Error */
3995#define nTXCOL 0x0
3996#define RXS 0x20 /* RDBR Data Buffer Status */ 3112#define RXS 0x20 /* RDBR Data Buffer Status */
3997#define nRXS 0x0
3998#define RBSY 0x10 /* Receive Error */ 3113#define RBSY 0x10 /* Receive Error */
3999#define nRBSY 0x0
4000#define TXS 0x8 /* TDBR Data Buffer Status */ 3114#define TXS 0x8 /* TDBR Data Buffer Status */
4001#define nTXS 0x0
4002#define TXE 0x4 /* Transmission Error */ 3115#define TXE 0x4 /* Transmission Error */
4003#define nTXE 0x0
4004#define MODF 0x2 /* Mode Fault Error */ 3116#define MODF 0x2 /* Mode Fault Error */
4005#define nMODF 0x0
4006#define SPIF 0x1 /* SPI Finished */ 3117#define SPIF 0x1 /* SPI Finished */
4007#define nSPIF 0x0
4008 3118
4009/* Bit masks for SPIx_TDBR */ 3119/* Bit masks for SPIx_TDBR */
4010 3120
@@ -4028,9 +3138,7 @@
4028 3138
4029#define PRESCALE 0x7f /* Prescale Value */ 3139#define PRESCALE 0x7f /* Prescale Value */
4030#define TWI_ENA 0x80 /* TWI Enable */ 3140#define TWI_ENA 0x80 /* TWI Enable */
4031#define nTWI_ENA 0x0
4032#define SCCB 0x200 /* Serial Camera Control Bus */ 3141#define SCCB 0x200 /* Serial Camera Control Bus */
4033#define nSCCB 0x0
4034 3142
4035/* Bit maskes for TWIx_CLKDIV */ 3143/* Bit maskes for TWIx_CLKDIV */
4036 3144
@@ -4040,13 +3148,9 @@
4040/* Bit maskes for TWIx_SLAVE_CTL */ 3148/* Bit maskes for TWIx_SLAVE_CTL */
4041 3149
4042#define SEN 0x1 /* Slave Enable */ 3150#define SEN 0x1 /* Slave Enable */
4043#define nSEN 0x0
4044#define STDVAL 0x4 /* Slave Transmit Data Valid */ 3151#define STDVAL 0x4 /* Slave Transmit Data Valid */
4045#define nSTDVAL 0x0
4046#define NAK 0x8 /* Not Acknowledge */ 3152#define NAK 0x8 /* Not Acknowledge */
4047#define nNAK 0x0
4048#define GEN 0x10 /* General Call Enable */ 3153#define GEN 0x10 /* General Call Enable */
4049#define nGEN 0x0
4050 3154
4051/* Bit maskes for TWIx_SLAVE_ADDR */ 3155/* Bit maskes for TWIx_SLAVE_ADDR */
4052 3156
@@ -4055,27 +3159,18 @@
4055/* Bit maskes for TWIx_SLAVE_STAT */ 3159/* Bit maskes for TWIx_SLAVE_STAT */
4056 3160
4057#define SDIR 0x1 /* Slave Transfer Direction */ 3161#define SDIR 0x1 /* Slave Transfer Direction */
4058#define nSDIR 0x0
4059#define GCALL 0x2 /* General Call */ 3162#define GCALL 0x2 /* General Call */
4060#define nGCALL 0x0
4061 3163
4062/* Bit maskes for TWIx_MASTER_CTL */ 3164/* Bit maskes for TWIx_MASTER_CTL */
4063 3165
4064#define MEN 0x1 /* Master Mode Enable */ 3166#define MEN 0x1 /* Master Mode Enable */
4065#define nMEN 0x0
4066#define MDIR 0x4 /* Master Transfer Direction */ 3167#define MDIR 0x4 /* Master Transfer Direction */
4067#define nMDIR 0x0
4068#define FAST 0x8 /* Fast Mode */ 3168#define FAST 0x8 /* Fast Mode */
4069#define nFAST 0x0
4070#define STOP 0x10 /* Issue Stop Condition */ 3169#define STOP 0x10 /* Issue Stop Condition */
4071#define nSTOP 0x0
4072#define RSTART 0x20 /* Repeat Start */ 3170#define RSTART 0x20 /* Repeat Start */
4073#define nRSTART 0x0
4074#define DCNT 0x3fc0 /* Data Transfer Count */ 3171#define DCNT 0x3fc0 /* Data Transfer Count */
4075#define SDAOVR 0x4000 /* Serial Data Override */ 3172#define SDAOVR 0x4000 /* Serial Data Override */
4076#define nSDAOVR 0x0
4077#define SCLOVR 0x8000 /* Serial Clock Override */ 3173#define SCLOVR 0x8000 /* Serial Clock Override */
4078#define nSCLOVR 0x0
4079 3174
4080/* Bit maskes for TWIx_MASTER_ADDR */ 3175/* Bit maskes for TWIx_MASTER_ADDR */
4081 3176
@@ -4084,34 +3179,21 @@
4084/* Bit maskes for TWIx_MASTER_STAT */ 3179/* Bit maskes for TWIx_MASTER_STAT */
4085 3180
4086#define MPROG 0x1 /* Master Transfer in Progress */ 3181#define MPROG 0x1 /* Master Transfer in Progress */
4087#define nMPROG 0x0
4088#define LOSTARB 0x2 /* Lost Arbitration */ 3182#define LOSTARB 0x2 /* Lost Arbitration */
4089#define nLOSTARB 0x0
4090#define ANAK 0x4 /* Address Not Acknowledged */ 3183#define ANAK 0x4 /* Address Not Acknowledged */
4091#define nANAK 0x0
4092#define DNAK 0x8 /* Data Not Acknowledged */ 3184#define DNAK 0x8 /* Data Not Acknowledged */
4093#define nDNAK 0x0
4094#define BUFRDERR 0x10 /* Buffer Read Error */ 3185#define BUFRDERR 0x10 /* Buffer Read Error */
4095#define nBUFRDERR 0x0
4096#define BUFWRERR 0x20 /* Buffer Write Error */ 3186#define BUFWRERR 0x20 /* Buffer Write Error */
4097#define nBUFWRERR 0x0
4098#define SDASEN 0x40 /* Serial Data Sense */ 3187#define SDASEN 0x40 /* Serial Data Sense */
4099#define nSDASEN 0x0
4100#define SCLSEN 0x80 /* Serial Clock Sense */ 3188#define SCLSEN 0x80 /* Serial Clock Sense */
4101#define nSCLSEN 0x0
4102#define BUSBUSY 0x100 /* Bus Busy */ 3189#define BUSBUSY 0x100 /* Bus Busy */
4103#define nBUSBUSY 0x0
4104 3190
4105/* Bit maskes for TWIx_FIFO_CTL */ 3191/* Bit maskes for TWIx_FIFO_CTL */
4106 3192
4107#define XMTFLUSH 0x1 /* Transmit Buffer Flush */ 3193#define XMTFLUSH 0x1 /* Transmit Buffer Flush */
4108#define nXMTFLUSH 0x0
4109#define RCVFLUSH 0x2 /* Receive Buffer Flush */ 3194#define RCVFLUSH 0x2 /* Receive Buffer Flush */
4110#define nRCVFLUSH 0x0
4111#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */ 3195#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
4112#define nXMTINTLEN 0x0
4113#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */ 3196#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
4114#define nRCVINTLEN 0x0
4115 3197
4116/* Bit maskes for TWIx_FIFO_STAT */ 3198/* Bit maskes for TWIx_FIFO_STAT */
4117 3199
@@ -4121,40 +3203,24 @@
4121/* Bit maskes for TWIx_INT_MASK */ 3203/* Bit maskes for TWIx_INT_MASK */
4122 3204
4123#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */ 3205#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
4124#define nSINITM 0x0
4125#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */ 3206#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
4126#define nSCOMPM 0x0
4127#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */ 3207#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
4128#define nSERRM 0x0
4129#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */ 3208#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
4130#define nSOVFM 0x0
4131#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */ 3209#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
4132#define nMCOMPM 0x0
4133#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */ 3210#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
4134#define nMERRM 0x0
4135#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */ 3211#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
4136#define nXMTSERVM 0x0
4137#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */ 3212#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
4138#define nRCVSERVM 0x0
4139 3213
4140/* Bit maskes for TWIx_INT_STAT */ 3214/* Bit maskes for TWIx_INT_STAT */
4141 3215
4142#define SINIT 0x1 /* Slave Transfer Initiated */ 3216#define SINIT 0x1 /* Slave Transfer Initiated */
4143#define nSINIT 0x0
4144#define SCOMP 0x2 /* Slave Transfer Complete */ 3217#define SCOMP 0x2 /* Slave Transfer Complete */
4145#define nSCOMP 0x0
4146#define SERR 0x4 /* Slave Transfer Error */ 3218#define SERR 0x4 /* Slave Transfer Error */
4147#define nSERR 0x0
4148#define SOVF 0x8 /* Slave Overflow */ 3219#define SOVF 0x8 /* Slave Overflow */
4149#define nSOVF 0x0
4150#define MCOMP 0x10 /* Master Transfer Complete */ 3220#define MCOMP 0x10 /* Master Transfer Complete */
4151#define nMCOMP 0x0
4152#define MERR 0x20 /* Master Transfer Error */ 3221#define MERR 0x20 /* Master Transfer Error */
4153#define nMERR 0x0
4154#define XMTSERV 0x40 /* Transmit FIFO Service */ 3222#define XMTSERV 0x40 /* Transmit FIFO Service */
4155#define nXMTSERV 0x0
4156#define RCVSERV 0x80 /* Receive FIFO Service */ 3223#define RCVSERV 0x80 /* Receive FIFO Service */
4157#define nRCVSERV 0x0
4158 3224
4159/* Bit maskes for TWIx_XMT_DATA8 */ 3225/* Bit maskes for TWIx_XMT_DATA8 */
4160 3226
@@ -4175,81 +3241,51 @@
4175/* Bit masks for SPORTx_TCR1 */ 3241/* Bit masks for SPORTx_TCR1 */
4176 3242
4177#define TCKFE 0x4000 /* Clock Falling Edge Select */ 3243#define TCKFE 0x4000 /* Clock Falling Edge Select */
4178#define nTCKFE 0x0
4179#define LATFS 0x2000 /* Late Transmit Frame Sync */ 3244#define LATFS 0x2000 /* Late Transmit Frame Sync */
4180#define nLATFS 0x0
4181#define LTFS 0x1000 /* Low Transmit Frame Sync Select */ 3245#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
4182#define nLTFS 0x0
4183#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */ 3246#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
4184#define nDITFS 0x0
4185#define TFSR 0x400 /* Transmit Frame Sync Required Select */ 3247#define TFSR 0x400 /* Transmit Frame Sync Required Select */
4186#define nTFSR 0x0
4187#define ITFS 0x200 /* Internal Transmit Frame Sync Select */ 3248#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
4188#define nITFS 0x0
4189#define TLSBIT 0x10 /* Transmit Bit Order */ 3249#define TLSBIT 0x10 /* Transmit Bit Order */
4190#define nTLSBIT 0x0
4191#define TDTYPE 0xc /* Data Formatting Type Select */ 3250#define TDTYPE 0xc /* Data Formatting Type Select */
4192#define ITCLK 0x2 /* Internal Transmit Clock Select */ 3251#define ITCLK 0x2 /* Internal Transmit Clock Select */
4193#define nITCLK 0x0
4194#define TSPEN 0x1 /* Transmit Enable */ 3252#define TSPEN 0x1 /* Transmit Enable */
4195#define nTSPEN 0x0
4196 3253
4197/* Bit masks for SPORTx_TCR2 */ 3254/* Bit masks for SPORTx_TCR2 */
4198 3255
4199#define TRFST 0x400 /* Left/Right Order */ 3256#define TRFST 0x400 /* Left/Right Order */
4200#define nTRFST 0x0
4201#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */ 3257#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
4202#define nTSFSE 0x0
4203#define TXSE 0x100 /* TxSEC Enable */ 3258#define TXSE 0x100 /* TxSEC Enable */
4204#define nTXSE 0x0
4205#define SLEN_T 0x1f /* SPORT Word Length */ 3259#define SLEN_T 0x1f /* SPORT Word Length */
4206 3260
4207/* Bit masks for SPORTx_RCR1 */ 3261/* Bit masks for SPORTx_RCR1 */
4208 3262
4209#define RCKFE 0x4000 /* Clock Falling Edge Select */ 3263#define RCKFE 0x4000 /* Clock Falling Edge Select */
4210#define nRCKFE 0x0
4211#define LARFS 0x2000 /* Late Receive Frame Sync */ 3264#define LARFS 0x2000 /* Late Receive Frame Sync */
4212#define nLARFS 0x0
4213#define LRFS 0x1000 /* Low Receive Frame Sync Select */ 3265#define LRFS 0x1000 /* Low Receive Frame Sync Select */
4214#define nLRFS 0x0
4215#define RFSR 0x400 /* Receive Frame Sync Required Select */ 3266#define RFSR 0x400 /* Receive Frame Sync Required Select */
4216#define nRFSR 0x0
4217#define IRFS 0x200 /* Internal Receive Frame Sync Select */ 3267#define IRFS 0x200 /* Internal Receive Frame Sync Select */
4218#define nIRFS 0x0
4219#define RLSBIT 0x10 /* Receive Bit Order */ 3268#define RLSBIT 0x10 /* Receive Bit Order */
4220#define nRLSBIT 0x0
4221#define RDTYPE 0xc /* Data Formatting Type Select */ 3269#define RDTYPE 0xc /* Data Formatting Type Select */
4222#define IRCLK 0x2 /* Internal Receive Clock Select */ 3270#define IRCLK 0x2 /* Internal Receive Clock Select */
4223#define nIRCLK 0x0
4224#define RSPEN 0x1 /* Receive Enable */ 3271#define RSPEN 0x1 /* Receive Enable */
4225#define nRSPEN 0x0
4226 3272
4227/* Bit masks for SPORTx_RCR2 */ 3273/* Bit masks for SPORTx_RCR2 */
4228 3274
4229#define RRFST 0x400 /* Left/Right Order */ 3275#define RRFST 0x400 /* Left/Right Order */
4230#define nRRFST 0x0
4231#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */ 3276#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
4232#define nRSFSE 0x0
4233#define RXSE 0x100 /* RxSEC Enable */ 3277#define RXSE 0x100 /* RxSEC Enable */
4234#define nRXSE 0x0
4235#define SLEN_R 0x1f /* SPORT Word Length */ 3278#define SLEN_R 0x1f /* SPORT Word Length */
4236 3279
4237/* Bit masks for SPORTx_STAT */ 3280/* Bit masks for SPORTx_STAT */
4238 3281
4239#define TXHRE 0x40 /* Transmit Hold Register Empty */ 3282#define TXHRE 0x40 /* Transmit Hold Register Empty */
4240#define nTXHRE 0x0
4241#define TOVF 0x20 /* Sticky Transmit Overflow Status */ 3283#define TOVF 0x20 /* Sticky Transmit Overflow Status */
4242#define nTOVF 0x0
4243#define TUVF 0x10 /* Sticky Transmit Underflow Status */ 3284#define TUVF 0x10 /* Sticky Transmit Underflow Status */
4244#define nTUVF 0x0
4245#define TXF 0x8 /* Transmit FIFO Full Status */ 3285#define TXF 0x8 /* Transmit FIFO Full Status */
4246#define nTXF 0x0
4247#define ROVF 0x4 /* Sticky Receive Overflow Status */ 3286#define ROVF 0x4 /* Sticky Receive Overflow Status */
4248#define nROVF 0x0
4249#define RUVF 0x2 /* Sticky Receive Underflow Status */ 3287#define RUVF 0x2 /* Sticky Receive Underflow Status */
4250#define nRUVF 0x0
4251#define RXNE 0x1 /* Receive FIFO Not Empty Status */ 3288#define RXNE 0x1 /* Receive FIFO Not Empty Status */
4252#define nRXNE 0x0
4253 3289
4254/* Bit masks for SPORTx_MCMC1 */ 3290/* Bit masks for SPORTx_MCMC1 */
4255 3291
@@ -4260,13 +3296,9 @@
4260 3296
4261#define MFD 0xf000 /* Multi channel Frame Delay */ 3297#define MFD 0xf000 /* Multi channel Frame Delay */
4262#define FSDR 0x80 /* Frame Sync to Data Relationship */ 3298#define FSDR 0x80 /* Frame Sync to Data Relationship */
4263#define nFSDR 0x0
4264#define MCMEM 0x10 /* Multi channel Frame Mode Enable */ 3299#define MCMEM 0x10 /* Multi channel Frame Mode Enable */
4265#define nMCMEM 0x0
4266#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */ 3300#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
4267#define nMCDRXPE 0x0
4268#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */ 3301#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
4269#define nMCDTXPE 0x0
4270#define MCCRM 0x3 /* 2X Clock Recovery Mode */ 3302#define MCCRM 0x3 /* 2X Clock Recovery Mode */
4271 3303
4272/* Bit masks for SPORTx_CHNL */ 3304/* Bit masks for SPORTx_CHNL */
@@ -4280,115 +3312,59 @@
4280#define WLS 0x3 /* Word Length Select */ 3312#define WLS 0x3 /* Word Length Select */
4281#endif 3313#endif
4282#define STB 0x4 /* Stop Bits */ 3314#define STB 0x4 /* Stop Bits */
4283#define nSTB 0x0
4284#define PEN 0x8 /* Parity Enable */ 3315#define PEN 0x8 /* Parity Enable */
4285#define nPEN 0x0
4286#define EPS 0x10 /* Even Parity Select */ 3316#define EPS 0x10 /* Even Parity Select */
4287#define nEPS 0x0
4288#define STP 0x20 /* Sticky Parity */ 3317#define STP 0x20 /* Sticky Parity */
4289#define nSTP 0x0
4290#define SB 0x40 /* Set Break */ 3318#define SB 0x40 /* Set Break */
4291#define nSB 0x0
4292 3319
4293/* Bit masks for UARTx_MCR */ 3320/* Bit masks for UARTx_MCR */
4294 3321
4295#define XOFF 0x1 /* Transmitter Off */ 3322#define XOFF 0x1 /* Transmitter Off */
4296#define nXOFF 0x0
4297#define MRTS 0x2 /* Manual Request To Send */ 3323#define MRTS 0x2 /* Manual Request To Send */
4298#define nMRTS 0x0
4299#define RFIT 0x4 /* Receive FIFO IRQ Threshold */ 3324#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
4300#define nRFIT 0x0
4301#define RFRT 0x8 /* Receive FIFO RTS Threshold */ 3325#define RFRT 0x8 /* Receive FIFO RTS Threshold */
4302#define nRFRT 0x0
4303#define LOOP_ENA 0x10 /* Loopback Mode Enable */ 3326#define LOOP_ENA 0x10 /* Loopback Mode Enable */
4304#define nLOOP_ENA 0x0
4305#define FCPOL 0x20 /* Flow Control Pin Polarity */ 3327#define FCPOL 0x20 /* Flow Control Pin Polarity */
4306#define nFCPOL 0x0
4307#define ARTS 0x40 /* Automatic Request To Send */ 3328#define ARTS 0x40 /* Automatic Request To Send */
4308#define nARTS 0x0
4309#define ACTS 0x80 /* Automatic Clear To Send */ 3329#define ACTS 0x80 /* Automatic Clear To Send */
4310#define nACTS 0x0
4311 3330
4312/* Bit masks for UARTx_LSR */ 3331/* Bit masks for UARTx_LSR */
4313 3332
4314#define DR 0x1 /* Data Ready */ 3333#define DR 0x1 /* Data Ready */
4315#define nDR 0x0
4316#define OE 0x2 /* Overrun Error */ 3334#define OE 0x2 /* Overrun Error */
4317#define nOE 0x0
4318#define PE 0x4 /* Parity Error */ 3335#define PE 0x4 /* Parity Error */
4319#define nPE 0x0
4320#define FE 0x8 /* Framing Error */ 3336#define FE 0x8 /* Framing Error */
4321#define nFE 0x0
4322#define BI 0x10 /* Break Interrupt */ 3337#define BI 0x10 /* Break Interrupt */
4323#define nBI 0x0
4324#define THRE 0x20 /* THR Empty */ 3338#define THRE 0x20 /* THR Empty */
4325#define nTHRE 0x0
4326#define TEMT 0x40 /* Transmitter Empty */ 3339#define TEMT 0x40 /* Transmitter Empty */
4327#define nTEMT 0x0
4328#define TFI 0x80 /* Transmission Finished Indicator */ 3340#define TFI 0x80 /* Transmission Finished Indicator */
4329#define nTFI 0x0
4330 3341
4331/* Bit masks for UARTx_MSR */ 3342/* Bit masks for UARTx_MSR */
4332 3343
4333#define SCTS 0x1 /* Sticky CTS */ 3344#define SCTS 0x1 /* Sticky CTS */
4334#define nSCTS 0x0
4335#define CTS 0x10 /* Clear To Send */ 3345#define CTS 0x10 /* Clear To Send */
4336#define nCTS 0x0
4337#define RFCS 0x20 /* Receive FIFO Count Status */ 3346#define RFCS 0x20 /* Receive FIFO Count Status */
4338#define nRFCS 0x0 3347
4339 3348/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
4340/* Bit masks for UARTx_IER_SET */ 3349
4341 3350#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
4342#define ERBFI_S 0x1 /* Enable Receive Buffer Full Interrupt */ 3351#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
4343#define nERBFI_S 0x0 3352#define ELSI 0x4 /* Enable Receive Status Interrupt */
4344#define ETBEI_S 0x2 /* Enable Transmit Buffer Empty Interrupt */ 3353#define EDSSI 0x8 /* Enable Modem Status Interrupt */
4345#define nETBEI_S 0x0 3354#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
4346#define ELSI_S 0x4 /* Enable Receive Status Interrupt */ 3355#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
4347#define nELSI_S 0x0 3356#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
4348#define EDSSI_S 0x8 /* Enable Modem Status Interrupt */
4349#define nEDSSI_S 0x0
4350#define EDTPTI_S 0x10 /* Enable DMA Transmit PIRQ Interrupt */
4351#define nEDTPTI_S 0x0
4352#define ETFI_S 0x20 /* Enable Transmission Finished Interrupt */
4353#define nETFI_S 0x0
4354#define ERFCI_S 0x40 /* Enable Receive FIFO Count Interrupt */
4355#define nERFCI_S 0x0
4356
4357/* Bit masks for UARTx_IER_CLEAR */
4358
4359#define ERBFI_C 0x1 /* Enable Receive Buffer Full Interrupt */
4360#define nERBFI_C 0x0
4361#define ETBEI_C 0x2 /* Enable Transmit Buffer Empty Interrupt */
4362#define nETBEI_C 0x0
4363#define ELSI_C 0x4 /* Enable Receive Status Interrupt */
4364#define nELSI_C 0x0
4365#define EDSSI_C 0x8 /* Enable Modem Status Interrupt */
4366#define nEDSSI_C 0x0
4367#define EDTPTI_C 0x10 /* Enable DMA Transmit PIRQ Interrupt */
4368#define nEDTPTI_C 0x0
4369#define ETFI_C 0x20 /* Enable Transmission Finished Interrupt */
4370#define nETFI_C 0x0
4371#define ERFCI_C 0x40 /* Enable Receive FIFO Count Interrupt */
4372#define nERFCI_C 0x0
4373 3357
4374/* Bit masks for UARTx_GCTL */ 3358/* Bit masks for UARTx_GCTL */
4375 3359
4376#define UCEN 0x1 /* UART Enable */ 3360#define UCEN 0x1 /* UART Enable */
4377#define nUCEN 0x0
4378#define IREN 0x2 /* IrDA Mode Enable */ 3361#define IREN 0x2 /* IrDA Mode Enable */
4379#define nIREN 0x0
4380#define TPOLC 0x4 /* IrDA TX Polarity Change */ 3362#define TPOLC 0x4 /* IrDA TX Polarity Change */
4381#define nTPOLC 0x0
4382#define RPOLC 0x8 /* IrDA RX Polarity Change */ 3363#define RPOLC 0x8 /* IrDA RX Polarity Change */
4383#define nRPOLC 0x0
4384#define FPE 0x10 /* Force Parity Error */ 3364#define FPE 0x10 /* Force Parity Error */
4385#define nFPE 0x0
4386#define FFE 0x20 /* Force Framing Error */ 3365#define FFE 0x20 /* Force Framing Error */
4387#define nFFE 0x0
4388#define EDBO 0x40 /* Enable Divide-by-One */ 3366#define EDBO 0x40 /* Enable Divide-by-One */
4389#define nEDBO 0x0
4390#define EGLSI 0x80 /* Enable Global LS Interrupt */ 3367#define EGLSI 0x80 /* Enable Global LS Interrupt */
4391#define nEGLSI 0x0
4392 3368
4393 3369
4394/* ******************************************* */ 3370/* ******************************************* */
@@ -4398,32 +3374,32 @@
4398/* BCODE bit field options (SYSCFG register) */ 3374/* BCODE bit field options (SYSCFG register) */
4399 3375
4400#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */ 3376#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
4401#define BCODE_FULLBOOT 0x0010 /* always perform full boot */ 3377#define BCODE_FULLBOOT 0x0010 /* always perform full boot */
4402#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */ 3378#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
4403#define BCODE_NOBOOT 0x0030 /* always perform full boot */ 3379#define BCODE_NOBOOT 0x0030 /* always perform full boot */
4404 3380
4405/* CNT_COMMAND bit field options */ 3381/* CNT_COMMAND bit field options */
4406 3382
4407#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */ 3383#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
4408#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */ 3384#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
4409#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */ 3385#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
4410 3386
4411#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */ 3387#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
4412#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */ 3388#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
4413#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */ 3389#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
4414 3390
4415#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */ 3391#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
4416#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */ 3392#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
4417#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */ 3393#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
4418 3394
4419/* CNT_CONFIG bit field options */ 3395/* CNT_CONFIG bit field options */
4420 3396
4421#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */ 3397#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
4422#define CNTMODE_BINENC 0x0100 /* binary encoder mode */ 3398#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
4423#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */ 3399#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
4424#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */ 3400#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
4425#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */ 3401#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
4426 3402
4427#define BNDMODE_COMP 0x0000 /* boundary compare mode */ 3403#define BNDMODE_COMP 0x0000 /* boundary compare mode */
4428#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */ 3404#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
4429#define BNDMODE_CAPT 0x2000 /* boundary capture mode */ 3405#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
@@ -4436,7 +3412,7 @@
4436#define EXT_CLK 0x0003 3412#define EXT_CLK 0x0003
4437 3413
4438/* UARTx_LCR bit field options */ 3414/* UARTx_LCR bit field options */
4439 3415
4440#define WLS_5 0x0000 /* 5 data bits */ 3416#define WLS_5 0x0000 /* 5 data bits */
4441#define WLS_6 0x0001 /* 6 data bits */ 3417#define WLS_6 0x0001 /* 6 data bits */
4442#define WLS_7 0x0002 /* 7 data bits */ 3418#define WLS_7 0x0002 /* 7 data bits */
@@ -4484,7 +3460,7 @@
4484#define PIQ30 0x40000000 3460#define PIQ30 0x40000000
4485#define PIQ31 0x80000000 3461#define PIQ31 0x80000000
4486 3462
4487/* PORT A Bit Definitions for the registers 3463/* PORT A Bit Definitions for the registers
4488PORTA, PORTA_SET, PORTA_CLEAR, 3464PORTA, PORTA_SET, PORTA_CLEAR,
4489PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN, 3465PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
4490PORTA_FER registers 3466PORTA_FER registers
@@ -4507,7 +3483,7 @@ PORTA_FER registers
4507#define PA14 0x4000 3483#define PA14 0x4000
4508#define PA15 0x8000 3484#define PA15 0x8000
4509 3485
4510/* PORT B Bit Definitions for the registers 3486/* PORT B Bit Definitions for the registers
4511PORTB, PORTB_SET, PORTB_CLEAR, 3487PORTB, PORTB_SET, PORTB_CLEAR,
4512PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN, 3488PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
4513PORTB_FER registers 3489PORTB_FER registers
@@ -4530,7 +3506,7 @@ PORTB_FER registers
4530#define PB14 0x4000 3506#define PB14 0x4000
4531 3507
4532 3508
4533/* PORT C Bit Definitions for the registers 3509/* PORT C Bit Definitions for the registers
4534PORTC, PORTC_SET, PORTC_CLEAR, 3510PORTC, PORTC_SET, PORTC_CLEAR,
4535PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN, 3511PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
4536PORTC_FER registers 3512PORTC_FER registers
@@ -4553,7 +3529,7 @@ PORTC_FER registers
4553#define PC13 0x2000 3529#define PC13 0x2000
4554 3530
4555 3531
4556/* PORT D Bit Definitions for the registers 3532/* PORT D Bit Definitions for the registers
4557PORTD, PORTD_SET, PORTD_CLEAR, 3533PORTD, PORTD_SET, PORTD_CLEAR,
4558PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN, 3534PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
4559PORTD_FER registers 3535PORTD_FER registers
@@ -4576,7 +3552,7 @@ PORTD_FER registers
4576#define PD14 0x4000 3552#define PD14 0x4000
4577#define PD15 0x8000 3553#define PD15 0x8000
4578 3554
4579/* PORT E Bit Definitions for the registers 3555/* PORT E Bit Definitions for the registers
4580PORTE, PORTE_SET, PORTE_CLEAR, 3556PORTE, PORTE_SET, PORTE_CLEAR,
4581PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN, 3557PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
4582PORTE_FER registers 3558PORTE_FER registers
@@ -4600,7 +3576,7 @@ PORTE_FER registers
4600#define PE14 0x4000 3576#define PE14 0x4000
4601#define PE15 0x8000 3577#define PE15 0x8000
4602 3578
4603/* PORT F Bit Definitions for the registers 3579/* PORT F Bit Definitions for the registers
4604PORTF, PORTF_SET, PORTF_CLEAR, 3580PORTF, PORTF_SET, PORTF_CLEAR,
4605PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN, 3581PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
4606PORTF_FER registers 3582PORTF_FER registers
@@ -4624,7 +3600,7 @@ PORTF_FER registers
4624#define PF14 0x4000 3600#define PF14 0x4000
4625#define PF15 0x8000 3601#define PF15 0x8000
4626 3602
4627/* PORT G Bit Definitions for the registers 3603/* PORT G Bit Definitions for the registers
4628PORTG, PORTG_SET, PORTG_CLEAR, 3604PORTG, PORTG_SET, PORTG_CLEAR,
4629PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN, 3605PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
4630PORTG_FER registers 3606PORTG_FER registers
@@ -4648,7 +3624,7 @@ PORTG_FER registers
4648#define PG14 0x4000 3624#define PG14 0x4000
4649#define PG15 0x8000 3625#define PG15 0x8000
4650 3626
4651/* PORT H Bit Definitions for the registers 3627/* PORT H Bit Definitions for the registers
4652PORTH, PORTH_SET, PORTH_CLEAR, 3628PORTH, PORTH_SET, PORTH_CLEAR,
4653PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN, 3629PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
4654PORTH_FER registers 3630PORTH_FER registers
@@ -4671,7 +3647,7 @@ PORTH_FER registers
4671#define PH13 0x2000 3647#define PH13 0x2000
4672 3648
4673 3649
4674/* PORT I Bit Definitions for the registers 3650/* PORT I Bit Definitions for the registers
4675PORTI, PORTI_SET, PORTI_CLEAR, 3651PORTI, PORTI_SET, PORTI_CLEAR,
4676PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN, 3652PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
4677PORTI_FER registers 3653PORTI_FER registers
@@ -4695,7 +3671,7 @@ PORTI_FER registers
4695#define PI14 0x4000 3671#define PI14 0x4000
4696#define PI15 0x8000 3672#define PI15 0x8000
4697 3673
4698/* PORT J Bit Definitions for the registers 3674/* PORT J Bit Definitions for the registers
4699PORTJ, PORTJ_SET, PORTJ_CLEAR, 3675PORTJ, PORTJ_SET, PORTJ_CLEAR,
4700PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN, 3676PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
4701PORTJ_FER registers 3677PORTJ_FER registers
@@ -4716,7 +3692,7 @@ PORTJ_FER registers
4716#define PJ11 0x0800 3692#define PJ11 0x0800
4717#define PJ12 0x1000 3693#define PJ12 0x1000
4718#define PJ13 0x2000 3694#define PJ13 0x2000
4719 3695
4720 3696
4721/* Port Muxing Bit Fields for PORTx_MUX Registers */ 3697/* Port Muxing Bit Fields for PORTx_MUX Registers */
4722 3698
@@ -4860,7 +3836,7 @@ PORTJ_FER registers
4860#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */ 3836#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
4861#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */ 3837#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
4862 3838
4863#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */ 3839#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
4864#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */ 3840#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
4865#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */ 3841#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
4866#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */ 3842#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
@@ -4869,27 +3845,27 @@ PORTJ_FER registers
4869#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */ 3845#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
4870#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */ 3846#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
4871 3847
4872#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */ 3848#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
4873#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */ 3849#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
4874#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */ 3850#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
4875#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */ 3851#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
4876#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */ 3852#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
4877#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */ 3853#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
4878#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */ 3854#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
4879#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */ 3855#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
4880 3856
4881#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */ 3857#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
4882#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */ 3858#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
4883#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */ 3859#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
4884#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */ 3860#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
4885#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */ 3861#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
4886#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */ 3862#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
4887#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */ 3863#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
4888#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */ 3864#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
4889 3865
4890 3866
4891/* for legacy compatibility */ 3867/* for legacy compatibility */
4892 3868
4893#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */ 3869#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
4894#define W1LMAX_MAX W1LMAX_MIN 3870#define W1LMAX_MAX W1LMAX_MIN
4895#define EBIU_AMCBCTL0 EBIU_AMBCTL0 3871#define EBIU_AMCBCTL0 EBIU_AMBCTL0
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
new file mode 100644
index 000000000000..fcc8b4c34c6a
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/dma.h
@@ -0,0 +1,73 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/dma.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _MACH_DMA_H_
33#define _MACH_DMA_H_
34
35#define CH_SPORT0_RX 0
36#define CH_SPORT0_TX 1
37#define CH_SPORT1_RX 2
38#define CH_SPORT1_TX 3
39#define CH_SPI0 4
40#define CH_SPI1 5
41#define CH_UART0_RX 6
42#define CH_UART0_TX 7
43#define CH_UART1_RX 8
44#define CH_UART1_TX 9
45#define CH_ATAPI_RX 10
46#define CH_ATAPI_TX 11
47#define CH_EPPI0 12
48#define CH_EPPI1 13
49#define CH_EPPI2 14
50#define CH_PIXC_IMAGE 15
51#define CH_PIXC_OVERLAY 16
52#define CH_PIXC_OUTPUT 17
53#define CH_SPORT2_RX 18
54#define CH_SPORT2_TX 19
55#define CH_SPORT3_RX 20
56#define CH_SPORT3_TX 21
57#define CH_SDH 22
58#define CH_SPI2 23
59
60#define CH_MEM_STREAM0_DEST 24
61#define CH_MEM_STREAM0_SRC 25
62#define CH_MEM_STREAM1_DEST 26
63#define CH_MEM_STREAM1_SRC 27
64#define CH_MEM_STREAM2_DEST 28
65#define CH_MEM_STREAM2_SRC 29
66#define CH_MEM_STREAM3_DEST 30
67#define CH_MEM_STREAM3_SRC 31
68
69#define MAX_BLACKFIN_DMA_CHANNEL 32
70
71extern int channel2irq(unsigned int channel);
72extern struct dma_register *base_addr[];
73#endif
diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h
new file mode 100644
index 000000000000..dbf66bcabe35
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/gpio.h
@@ -0,0 +1,216 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/gpio.h
3 * Based on:
4 * Author: Michael Hennerich (hennerich@blackfin.uclinux.org)
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2004-2007 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30
31
32#define GPIO_PA0 0
33#define GPIO_PA1 1
34#define GPIO_PA2 2
35#define GPIO_PA3 3
36#define GPIO_PA4 4
37#define GPIO_PA5 5
38#define GPIO_PA6 6
39#define GPIO_PA7 7
40#define GPIO_PA8 8
41#define GPIO_PA9 9
42#define GPIO_PA10 10
43#define GPIO_PA11 11
44#define GPIO_PA12 12
45#define GPIO_PA13 13
46#define GPIO_PA14 14
47#define GPIO_PA15 15
48#define GPIO_PB0 16
49#define GPIO_PB1 17
50#define GPIO_PB2 18
51#define GPIO_PB3 19
52#define GPIO_PB4 20
53#define GPIO_PB5 21
54#define GPIO_PB6 22
55#define GPIO_PB7 23
56#define GPIO_PB8 24
57#define GPIO_PB9 25
58#define GPIO_PB10 26
59#define GPIO_PB11 27
60#define GPIO_PB12 28
61#define GPIO_PB13 29
62#define GPIO_PB14 30
63#define GPIO_PB15 31 /* N/A */
64#define GPIO_PC0 32
65#define GPIO_PC1 33
66#define GPIO_PC2 34
67#define GPIO_PC3 35
68#define GPIO_PC4 36
69#define GPIO_PC5 37
70#define GPIO_PC6 38
71#define GPIO_PC7 39
72#define GPIO_PC8 40
73#define GPIO_PC9 41
74#define GPIO_PC10 42
75#define GPIO_PC11 43
76#define GPIO_PC12 44
77#define GPIO_PC13 45
78#define GPIO_PC14 46 /* N/A */
79#define GPIO_PC15 47 /* N/A */
80#define GPIO_PD0 48
81#define GPIO_PD1 49
82#define GPIO_PD2 50
83#define GPIO_PD3 51
84#define GPIO_PD4 52
85#define GPIO_PD5 53
86#define GPIO_PD6 54
87#define GPIO_PD7 55
88#define GPIO_PD8 56
89#define GPIO_PD9 57
90#define GPIO_PD10 58
91#define GPIO_PD11 59
92#define GPIO_PD12 60
93#define GPIO_PD13 61
94#define GPIO_PD14 62
95#define GPIO_PD15 63
96#define GPIO_PE0 64
97#define GPIO_PE1 65
98#define GPIO_PE2 66
99#define GPIO_PE3 67
100#define GPIO_PE4 68
101#define GPIO_PE5 69
102#define GPIO_PE6 70
103#define GPIO_PE7 71
104#define GPIO_PE8 72
105#define GPIO_PE9 73
106#define GPIO_PE10 74
107#define GPIO_PE11 75
108#define GPIO_PE12 76
109#define GPIO_PE13 77
110#define GPIO_PE14 78
111#define GPIO_PE15 79
112#define GPIO_PF0 80
113#define GPIO_PF1 81
114#define GPIO_PF2 82
115#define GPIO_PF3 83
116#define GPIO_PF4 84
117#define GPIO_PF5 85
118#define GPIO_PF6 86
119#define GPIO_PF7 87
120#define GPIO_PF8 88
121#define GPIO_PF9 89
122#define GPIO_PF10 90
123#define GPIO_PF11 91
124#define GPIO_PF12 92
125#define GPIO_PF13 93
126#define GPIO_PF14 94
127#define GPIO_PF15 95
128#define GPIO_PG0 96
129#define GPIO_PG1 97
130#define GPIO_PG2 98
131#define GPIO_PG3 99
132#define GPIO_PG4 100
133#define GPIO_PG5 101
134#define GPIO_PG6 102
135#define GPIO_PG7 103
136#define GPIO_PG8 104
137#define GPIO_PG9 105
138#define GPIO_PG10 106
139#define GPIO_PG11 107
140#define GPIO_PG12 108
141#define GPIO_PG13 109
142#define GPIO_PG14 110
143#define GPIO_PG15 111
144#define GPIO_PH0 112
145#define GPIO_PH1 113
146#define GPIO_PH2 114
147#define GPIO_PH3 115
148#define GPIO_PH4 116
149#define GPIO_PH5 117
150#define GPIO_PH6 118
151#define GPIO_PH7 119
152#define GPIO_PH8 120
153#define GPIO_PH9 121
154#define GPIO_PH10 122
155#define GPIO_PH11 123
156#define GPIO_PH12 124
157#define GPIO_PH13 125
158#define GPIO_PH14 126 /* N/A */
159#define GPIO_PH15 127 /* N/A */
160#define GPIO_PI0 128
161#define GPIO_PI1 129
162#define GPIO_PI2 130
163#define GPIO_PI3 131
164#define GPIO_PI4 132
165#define GPIO_PI5 133
166#define GPIO_PI6 134
167#define GPIO_PI7 135
168#define GPIO_PI8 136
169#define GPIO_PI9 137
170#define GPIO_PI10 138
171#define GPIO_PI11 139
172#define GPIO_PI12 140
173#define GPIO_PI13 141
174#define GPIO_PI14 142
175#define GPIO_PI15 143
176#define GPIO_PJ0 144
177#define GPIO_PJ1 145
178#define GPIO_PJ2 146
179#define GPIO_PJ3 147
180#define GPIO_PJ4 148
181#define GPIO_PJ5 149
182#define GPIO_PJ6 150
183#define GPIO_PJ7 151
184#define GPIO_PJ8 152
185#define GPIO_PJ9 153
186#define GPIO_PJ10 154
187#define GPIO_PJ11 155
188#define GPIO_PJ12 156
189#define GPIO_PJ13 157
190#define GPIO_PJ14 158 /* N/A */
191#define GPIO_PJ15 159 /* N/A */
192
193#define MAX_BLACKFIN_GPIOS 160
194
195struct gpio_port_t {
196 unsigned short port_fer;
197 unsigned short dummy1;
198 unsigned short port_data;
199 unsigned short dummy2;
200 unsigned short port_set;
201 unsigned short dummy3;
202 unsigned short port_clear;
203 unsigned short dummy4;
204 unsigned short port_dir_set;
205 unsigned short dummy5;
206 unsigned short port_dir_clear;
207 unsigned short dummy6;
208 unsigned short port_inen;
209 unsigned short dummy7;
210 unsigned int port_mux;
211};
212
213int gpio_request(unsigned short gpio, const char *label);
214void peripheral_free(unsigned short per);
215int peripheral_request_list(unsigned short per[], const char *label);
216void peripheral_free_list(unsigned short per[]);
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
new file mode 100644
index 000000000000..0b3325bb1fff
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -0,0 +1,467 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/irq.h
3 * based on: include/asm-blackfin/mach-bf537/irq.h
4 * author: Roy Huang (roy.huang@analog.com)
5 *
6 * created:
7 * description:
8 * system mmr register map
9 * rev:
10 *
11 * modified:
12 *
13 *
14 * bugs: enter bugs at http://blackfin.uclinux.org/
15 *
16 * this program is free software; you can redistribute it and/or modify
17 * it under the terms of the gnu general public license as published by
18 * the free software foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * this program is distributed in the hope that it will be useful,
22 * but without any warranty; without even the implied warranty of
23 * merchantability or fitness for a particular purpose. see the
24 * gnu general public license for more details.
25 *
26 * you should have received a copy of the gnu general public license
27 * along with this program; see the file copying.
28 * if not, write to the free software foundation,
29 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
30 */
31
32#ifndef _BF548_IRQ_H_
33#define _BF548_IRQ_H_
34
35/*
36 * Interrupt source definitions
37 Event Source Core Event Name
38Core Emulation **
39Events (highest priority) EMU 0
40 Reset RST 1
41 NMI NMI 2
42 Exception EVX 3
43 Reserved -- 4
44 Hardware Error IVHW 5
45 Core Timer IVTMR 6 *
46
47.....
48
49 Software Interrupt 1 IVG14 31
50 Software Interrupt 2 --
51 (lowest priority) IVG15 32 *
52 */
53
54#define NR_PERI_INTS (32 * 3)
55
56/* The ABSTRACT IRQ definitions */
57/** the first seven of the following are fixed, the rest you change if you need to **/
58#define IRQ_EMU 0 /* Emulation */
59#define IRQ_RST 1 /* reset */
60#define IRQ_NMI 2 /* Non Maskable */
61#define IRQ_EVX 3 /* Exception */
62#define IRQ_UNUSED 4 /* - unused interrupt*/
63#define IRQ_HWERR 5 /* Hardware Error */
64#define IRQ_CORETMR 6 /* Core timer */
65
66#define BFIN_IRQ(x) ((x) + 7)
67
68#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
69#define IRQ_DMAC0_ERR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
70#define IRQ_EPPI0_ERR BFIN_IRQ(2) /* EPPI0 Error Interrupt */
71#define IRQ_SPORT0_ERR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
72#define IRQ_SPORT1_ERR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
73#define IRQ_SPI0_ERR BFIN_IRQ(5) /* SPI0 Status(Error) Interrupt */
74#define IRQ_UART0_ERR BFIN_IRQ(6) /* UART0 Status(Error) Interrupt */
75#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
76#define IRQ_EPPI0 BFIN_IRQ(8) /* EPPI0 Interrupt (DMA12) */
77#define IRQ_SPORT0_RX BFIN_IRQ(9) /* SPORT0 RX Interrupt (DMA0) */
78#define IRQ_SPORT0_TX BFIN_IRQ(10) /* SPORT0 TX Interrupt (DMA1) */
79#define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
80#define IRQ_SPORT1_TX BFIN_IRQ(12) /* SPORT1 TX Interrupt (DMA3) */
81#define IRQ_SPI0 BFIN_IRQ(13) /* SPI0 Interrupt (DMA4) */
82#define IRQ_UART0_RX BFIN_IRQ(14) /* UART0 RX Interrupt (DMA6) */
83#define IRQ_UART0_TX BFIN_IRQ(15) /* UART0 TX Interrupt (DMA7) */
84#define IRQ_TIMER8 BFIN_IRQ(16) /* TIMER 8 Interrupt */
85#define IRQ_TIMER9 BFIN_IRQ(17) /* TIMER 9 Interrupt */
86#define IRQ_TIMER10 BFIN_IRQ(18) /* TIMER 10 Interrupt */
87#define IRQ_PINT0 BFIN_IRQ(19) /* PINT0 Interrupt */
88#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
89#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
90#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
91#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */
92#define IRQ_DMAC1_ERR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
93#define IRQ_SPORT2_ERR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
94#define IRQ_SPORT3_ERR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
95#define IRQ_MXVR_DATA BFIN_IRQ(27) /* MXVR Data Interrupt */
96#define IRQ_SPI1_ERR BFIN_IRQ(28) /* SPI1 Status (Error) Interrupt */
97#define IRQ_SPI2_ERR BFIN_IRQ(29) /* SPI2 Status (Error) Interrupt */
98#define IRQ_UART1_ERR BFIN_IRQ(30) /* UART1 Status (Error) Interrupt */
99#define IRQ_UART2_ERR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
100#define IRQ_CAN0_ERR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
101#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
102#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
103#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
104#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
105#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
106#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
107#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
108#define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
109#define IRQ_UART1_RX BFIN_IRQ(41) /* UART1 RX (DMA8) Interrupt */
110#define IRQ_UART1_TX BFIN_IRQ(42) /* UART1 TX (DMA9) Interrupt */
111#define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
112#define IRQ_ATAPI_TX BFIN_IRQ(44) /* ATAPI TX (DMA11) Interrupt */
113#define IRQ_TWI0 BFIN_IRQ(45) /* TWI0 Interrupt */
114#define IRQ_TWI1 BFIN_IRQ(46) /* TWI1 Interrupt */
115#define IRQ_CAN0_RX BFIN_IRQ(47) /* CAN0 Receive Interrupt */
116#define IRQ_CAN0_TX BFIN_IRQ(48) /* CAN0 Transmit Interrupt */
117#define IRQ_MDMAS2 BFIN_IRQ(49) /* MDMA Stream 2 Interrupt */
118#define IRQ_MDMAS3 BFIN_IRQ(50) /* MDMA Stream 3 Interrupt */
119#define IRQ_MXVR_ERR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
120#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
121#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
122#define IRQ_EPP1_ERR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
123#define IRQ_EPP2_ERR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
124#define IRQ_UART3_ERR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
125#define IRQ_HOST_ERR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
126#define IRQ_PIXC_ERR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
127#define IRQ_NFC_ERR BFIN_IRQ(60) /* NFC Error Interrupt */
128#define IRQ_ATAPI_ERR BFIN_IRQ(61) /* ATAPI Error Interrupt */
129#define IRQ_CAN1_ERR BFIN_IRQ(62) /* CAN1 Status (Error) Interrupt */
130#define IRQ_HS_DMA_ERR BFIN_IRQ(63) /* Handshake DMA Status Interrupt */
131#define IRQ_PIXC_IN0 BFIN_IRQ(64) /* PIXC IN0 (DMA15) Interrupt */
132#define IRQ_PIXC_IN1 BFIN_IRQ(65) /* PIXC IN1 (DMA16) Interrupt */
133#define IRQ_PIXC_OUT BFIN_IRQ(66) /* PIXC OUT (DMA17) Interrupt */
134#define IRQ_SDH BFIN_IRQ(67) /* SDH/NFC (DMA22) Interrupt */
135#define IRQ_CNT BFIN_IRQ(68) /* CNT Interrupt */
136#define IRQ_KEY BFIN_IRQ(69) /* KEY Interrupt */
137#define IRQ_CAN1_RX BFIN_IRQ(70) /* CAN1 RX Interrupt */
138#define IRQ_CAN1_TX BFIN_IRQ(71) /* CAN1 TX Interrupt */
139#define IRQ_SDH_MASK0 BFIN_IRQ(72) /* SDH Mask 0 Interrupt */
140#define IRQ_SDH_MASK1 BFIN_IRQ(73) /* SDH Mask 1 Interrupt */
141#define IRQ_USB_INT0 BFIN_IRQ(75) /* USB INT0 Interrupt */
142#define IRQ_USB_INT1 BFIN_IRQ(76) /* USB INT1 Interrupt */
143#define IRQ_USB_INT2 BFIN_IRQ(77) /* USB INT2 Interrupt */
144#define IRQ_USB_DMA BFIN_IRQ(78) /* USB DMA Interrupt */
145#define IRQ_OPTSEC BFIN_IRQ(79) /* OTPSEC Interrupt */
146#define IRQ_TIMER0 BFIN_IRQ(86) /* Timer 0 Interrupt */
147#define IRQ_TIMER1 BFIN_IRQ(87) /* Timer 1 Interrupt */
148#define IRQ_TIMER2 BFIN_IRQ(88) /* Timer 2 Interrupt */
149#define IRQ_TIMER3 BFIN_IRQ(89) /* Timer 3 Interrupt */
150#define IRQ_TIMER4 BFIN_IRQ(90) /* Timer 4 Interrupt */
151#define IRQ_TIMER5 BFIN_IRQ(91) /* Timer 5 Interrupt */
152#define IRQ_TIMER6 BFIN_IRQ(92) /* Timer 6 Interrupt */
153#define IRQ_TIMER7 BFIN_IRQ(93) /* Timer 7 Interrupt */
154#define IRQ_PINT2 BFIN_IRQ(94) /* PINT2 Interrupt */
155#define IRQ_PINT3 BFIN_IRQ(95) /* PINT3 Interrupt */
156
157#define SYS_IRQS IRQ_PINT3
158
159#define BFIN_PA_IRQ(x) ((x) + SYS_IRQS + 1)
160#define IRQ_PA0 BFIN_PA_IRQ(0)
161#define IRQ_PA1 BFIN_PA_IRQ(1)
162#define IRQ_PA2 BFIN_PA_IRQ(2)
163#define IRQ_PA3 BFIN_PA_IRQ(3)
164#define IRQ_PA4 BFIN_PA_IRQ(4)
165#define IRQ_PA5 BFIN_PA_IRQ(5)
166#define IRQ_PA6 BFIN_PA_IRQ(6)
167#define IRQ_PA7 BFIN_PA_IRQ(7)
168#define IRQ_PA8 BFIN_PA_IRQ(8)
169#define IRQ_PA9 BFIN_PA_IRQ(9)
170#define IRQ_PA10 BFIN_PA_IRQ(10)
171#define IRQ_PA11 BFIN_PA_IRQ(11)
172#define IRQ_PA12 BFIN_PA_IRQ(12)
173#define IRQ_PA13 BFIN_PA_IRQ(13)
174#define IRQ_PA14 BFIN_PA_IRQ(14)
175#define IRQ_PA15 BFIN_PA_IRQ(15)
176
177#define BFIN_PB_IRQ(x) ((x) + IRQ_PA15 + 1)
178#define IRQ_PB0 BFIN_PB_IRQ(0)
179#define IRQ_PB1 BFIN_PB_IRQ(1)
180#define IRQ_PB2 BFIN_PB_IRQ(2)
181#define IRQ_PB3 BFIN_PB_IRQ(3)
182#define IRQ_PB4 BFIN_PB_IRQ(4)
183#define IRQ_PB5 BFIN_PB_IRQ(5)
184#define IRQ_PB6 BFIN_PB_IRQ(6)
185#define IRQ_PB7 BFIN_PB_IRQ(7)
186#define IRQ_PB8 BFIN_PB_IRQ(8)
187#define IRQ_PB9 BFIN_PB_IRQ(9)
188#define IRQ_PB10 BFIN_PB_IRQ(10)
189#define IRQ_PB11 BFIN_PB_IRQ(11)
190#define IRQ_PB12 BFIN_PB_IRQ(12)
191#define IRQ_PB13 BFIN_PB_IRQ(13)
192#define IRQ_PB14 BFIN_PB_IRQ(14)
193#define IRQ_PB15 BFIN_PB_IRQ(15) /* N/A */
194
195#define BFIN_PC_IRQ(x) ((x) + IRQ_PB15 + 1)
196#define IRQ_PC0 BFIN_PC_IRQ(0)
197#define IRQ_PC1 BFIN_PC_IRQ(1)
198#define IRQ_PC2 BFIN_PC_IRQ(2)
199#define IRQ_PC3 BFIN_PC_IRQ(3)
200#define IRQ_PC4 BFIN_PC_IRQ(4)
201#define IRQ_PC5 BFIN_PC_IRQ(5)
202#define IRQ_PC6 BFIN_PC_IRQ(6)
203#define IRQ_PC7 BFIN_PC_IRQ(7)
204#define IRQ_PC8 BFIN_PC_IRQ(8)
205#define IRQ_PC9 BFIN_PC_IRQ(9)
206#define IRQ_PC10 BFIN_PC_IRQ(10)
207#define IRQ_PC11 BFIN_PC_IRQ(11)
208#define IRQ_PC12 BFIN_PC_IRQ(12)
209#define IRQ_PC13 BFIN_PC_IRQ(13)
210#define IRQ_PC14 BFIN_PC_IRQ(14) /* N/A */
211#define IRQ_PC15 BFIN_PC_IRQ(15) /* N/A */
212
213#define BFIN_PD_IRQ(x) ((x) + IRQ_PC15 + 1)
214#define IRQ_PD0 BFIN_PD_IRQ(0)
215#define IRQ_PD1 BFIN_PD_IRQ(1)
216#define IRQ_PD2 BFIN_PD_IRQ(2)
217#define IRQ_PD3 BFIN_PD_IRQ(3)
218#define IRQ_PD4 BFIN_PD_IRQ(4)
219#define IRQ_PD5 BFIN_PD_IRQ(5)
220#define IRQ_PD6 BFIN_PD_IRQ(6)
221#define IRQ_PD7 BFIN_PD_IRQ(7)
222#define IRQ_PD8 BFIN_PD_IRQ(8)
223#define IRQ_PD9 BFIN_PD_IRQ(9)
224#define IRQ_PD10 BFIN_PD_IRQ(10)
225#define IRQ_PD11 BFIN_PD_IRQ(11)
226#define IRQ_PD12 BFIN_PD_IRQ(12)
227#define IRQ_PD13 BFIN_PD_IRQ(13)
228#define IRQ_PD14 BFIN_PD_IRQ(14)
229#define IRQ_PD15 BFIN_PD_IRQ(15)
230
231#define BFIN_PE_IRQ(x) ((x) + IRQ_PD15 + 1)
232#define IRQ_PE0 BFIN_PE_IRQ(0)
233#define IRQ_PE1 BFIN_PE_IRQ(1)
234#define IRQ_PE2 BFIN_PE_IRQ(2)
235#define IRQ_PE3 BFIN_PE_IRQ(3)
236#define IRQ_PE4 BFIN_PE_IRQ(4)
237#define IRQ_PE5 BFIN_PE_IRQ(5)
238#define IRQ_PE6 BFIN_PE_IRQ(6)
239#define IRQ_PE7 BFIN_PE_IRQ(7)
240#define IRQ_PE8 BFIN_PE_IRQ(8)
241#define IRQ_PE9 BFIN_PE_IRQ(9)
242#define IRQ_PE10 BFIN_PE_IRQ(10)
243#define IRQ_PE11 BFIN_PE_IRQ(11)
244#define IRQ_PE12 BFIN_PE_IRQ(12)
245#define IRQ_PE13 BFIN_PE_IRQ(13)
246#define IRQ_PE14 BFIN_PE_IRQ(14)
247#define IRQ_PE15 BFIN_PE_IRQ(15)
248
249#define BFIN_PF_IRQ(x) ((x) + IRQ_PE15 + 1)
250#define IRQ_PF0 BFIN_PF_IRQ(0)
251#define IRQ_PF1 BFIN_PF_IRQ(1)
252#define IRQ_PF2 BFIN_PF_IRQ(2)
253#define IRQ_PF3 BFIN_PF_IRQ(3)
254#define IRQ_PF4 BFIN_PF_IRQ(4)
255#define IRQ_PF5 BFIN_PF_IRQ(5)
256#define IRQ_PF6 BFIN_PF_IRQ(6)
257#define IRQ_PF7 BFIN_PF_IRQ(7)
258#define IRQ_PF8 BFIN_PF_IRQ(8)
259#define IRQ_PF9 BFIN_PF_IRQ(9)
260#define IRQ_PF10 BFIN_PF_IRQ(10)
261#define IRQ_PF11 BFIN_PF_IRQ(11)
262#define IRQ_PF12 BFIN_PF_IRQ(12)
263#define IRQ_PF13 BFIN_PF_IRQ(13)
264#define IRQ_PF14 BFIN_PF_IRQ(14)
265#define IRQ_PF15 BFIN_PF_IRQ(15)
266
267#define BFIN_PG_IRQ(x) ((x) + IRQ_PF15 + 1)
268#define IRQ_PG0 BFIN_PG_IRQ(0)
269#define IRQ_PG1 BFIN_PG_IRQ(1)
270#define IRQ_PG2 BFIN_PG_IRQ(2)
271#define IRQ_PG3 BFIN_PG_IRQ(3)
272#define IRQ_PG4 BFIN_PG_IRQ(4)
273#define IRQ_PG5 BFIN_PG_IRQ(5)
274#define IRQ_PG6 BFIN_PG_IRQ(6)
275#define IRQ_PG7 BFIN_PG_IRQ(7)
276#define IRQ_PG8 BFIN_PG_IRQ(8)
277#define IRQ_PG9 BFIN_PG_IRQ(9)
278#define IRQ_PG10 BFIN_PG_IRQ(10)
279#define IRQ_PG11 BFIN_PG_IRQ(11)
280#define IRQ_PG12 BFIN_PG_IRQ(12)
281#define IRQ_PG13 BFIN_PG_IRQ(13)
282#define IRQ_PG14 BFIN_PG_IRQ(14)
283#define IRQ_PG15 BFIN_PG_IRQ(15)
284
285#define BFIN_PH_IRQ(x) ((x) + IRQ_PG15 + 1)
286#define IRQ_PH0 BFIN_PH_IRQ(0)
287#define IRQ_PH1 BFIN_PH_IRQ(1)
288#define IRQ_PH2 BFIN_PH_IRQ(2)
289#define IRQ_PH3 BFIN_PH_IRQ(3)
290#define IRQ_PH4 BFIN_PH_IRQ(4)
291#define IRQ_PH5 BFIN_PH_IRQ(5)
292#define IRQ_PH6 BFIN_PH_IRQ(6)
293#define IRQ_PH7 BFIN_PH_IRQ(7)
294#define IRQ_PH8 BFIN_PH_IRQ(8)
295#define IRQ_PH9 BFIN_PH_IRQ(9)
296#define IRQ_PH10 BFIN_PH_IRQ(10)
297#define IRQ_PH11 BFIN_PH_IRQ(11)
298#define IRQ_PH12 BFIN_PH_IRQ(12)
299#define IRQ_PH13 BFIN_PH_IRQ(13)
300#define IRQ_PH14 BFIN_PH_IRQ(14) /* N/A */
301#define IRQ_PH15 BFIN_PH_IRQ(15) /* N/A */
302
303#define BFIN_PI_IRQ(x) ((x) + IRQ_PH15 + 1)
304#define IRQ_PI0 BFIN_PI_IRQ(0)
305#define IRQ_PI1 BFIN_PI_IRQ(1)
306#define IRQ_PI2 BFIN_PI_IRQ(2)
307#define IRQ_PI3 BFIN_PI_IRQ(3)
308#define IRQ_PI4 BFIN_PI_IRQ(4)
309#define IRQ_PI5 BFIN_PI_IRQ(5)
310#define IRQ_PI6 BFIN_PI_IRQ(6)
311#define IRQ_PI7 BFIN_PI_IRQ(7)
312#define IRQ_PI8 BFIN_PI_IRQ(8)
313#define IRQ_PI9 BFIN_PI_IRQ(9)
314#define IRQ_PI10 BFIN_PI_IRQ(10)
315#define IRQ_PI11 BFIN_PI_IRQ(11)
316#define IRQ_PI12 BFIN_PI_IRQ(12)
317#define IRQ_PI13 BFIN_PI_IRQ(13)
318#define IRQ_PI14 BFIN_PI_IRQ(14)
319#define IRQ_PI15 BFIN_PI_IRQ(15)
320
321#define BFIN_PJ_IRQ(x) ((x) + IRQ_PI15 + 1)
322#define IRQ_PJ0 BFIN_PJ_IRQ(0)
323#define IRQ_PJ1 BFIN_PJ_IRQ(1)
324#define IRQ_PJ2 BFIN_PJ_IRQ(2)
325#define IRQ_PJ3 BFIN_PJ_IRQ(3)
326#define IRQ_PJ4 BFIN_PJ_IRQ(4)
327#define IRQ_PJ5 BFIN_PJ_IRQ(5)
328#define IRQ_PJ6 BFIN_PJ_IRQ(6)
329#define IRQ_PJ7 BFIN_PJ_IRQ(7)
330#define IRQ_PJ8 BFIN_PJ_IRQ(8)
331#define IRQ_PJ9 BFIN_PJ_IRQ(9)
332#define IRQ_PJ10 BFIN_PJ_IRQ(10)
333#define IRQ_PJ11 BFIN_PJ_IRQ(11)
334#define IRQ_PJ12 BFIN_PJ_IRQ(12)
335#define IRQ_PJ13 BFIN_PJ_IRQ(13)
336#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
337#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
338
339#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
340#define NR_IRQS (IRQ_PJ15+1)
341#else
342#define NR_IRQS (SYS_IRQS+1)
343#endif
344
345#define IVG7 7
346#define IVG8 8
347#define IVG9 9
348#define IVG10 10
349#define IVG11 11
350#define IVG12 12
351#define IVG13 13
352#define IVG14 14
353#define IVG15 15
354
355/* IAR0 BIT FIELDS */
356#define IRQ_PLL_WAKEUP_POS 0
357#define IRQ_DMAC0_ERR_POS 4
358#define IRQ_EPPI0_ERR_POS 8
359#define IRQ_SPORT0_ERR_POS 12
360#define IRQ_SPORT1_ERR_POS 16
361#define IRQ_SPI0_ERR_POS 20
362#define IRQ_UART0_ERR_POS 24
363#define IRQ_RTC_POS 28
364
365/* IAR1 BIT FIELDS */
366#define IRQ_EPPI0_POS 0
367#define IRQ_SPORT0_RX_POS 4
368#define IRQ_SPORT0_TX_POS 8
369#define IRQ_SPORT1_RX_POS 12
370#define IRQ_SPORT1_TX_POS 16
371#define IRQ_SPI0_POS 20
372#define IRQ_UART0_RX_POS 24
373#define IRQ_UART0_TX_POS 28
374
375/* IAR2 BIT FIELDS */
376#define IRQ_TIMER8_POS 0
377#define IRQ_TIMER9_POS 4
378#define IRQ_TIMER10_POS 8
379#define IRQ_PINT0_POS 12
380#define IRQ_PINT1_POS 16
381#define IRQ_MDMAS0_POS 20
382#define IRQ_MDMAS1_POS 24
383#define IRQ_WATCHDOG_POS 28
384
385/* IAR3 BIT FIELDS */
386#define IRQ_DMAC1_ERR_POS 0
387#define IRQ_SPORT2_ERR_POS 4
388#define IRQ_SPORT3_ERR_POS 8
389#define IRQ_MXVR_DATA_POS 12
390#define IRQ_SPI1_ERR_POS 16
391#define IRQ_SPI2_ERR_POS 20
392#define IRQ_UART1_ERR_POS 24
393#define IRQ_UART2_ERR_POS 28
394
395/* IAR4 BIT FILEDS */
396#define IRQ_CAN0_ERR_POS 0
397#define IRQ_SPORT2_RX_POS 4
398#define IRQ_SPORT2_TX_POS 8
399#define IRQ_SPORT3_RX_POS 12
400#define IRQ_SPORT3_TX_POS 16
401#define IRQ_EPPI1_POS 20
402#define IRQ_EPPI2_POS 24
403#define IRQ_SPI1_POS 28
404
405/* IAR5 BIT FIELDS */
406#define IRQ_SPI2_POS 0
407#define IRQ_UART1_RX_POS 4
408#define IRQ_UART1_TX_POS 8
409#define IRQ_ATAPI_RX_POS 12
410#define IRQ_ATAPI_TX_POS 16
411#define IRQ_TWI0_POS 20
412#define IRQ_TWI1_POS 24
413#define IRQ_CAN0_RX_POS 28
414
415/* IAR6 BIT FIELDS */
416#define IRQ_CAN0_TX_POS 0
417#define IRQ_MDMAS2_POS 4
418#define IRQ_MDMAS3_POS 8
419#define IRQ_MXVR_ERR_POS 12
420#define IRQ_MXVR_MSG_POS 16
421#define IRQ_MXVR_PKT_POS 20
422#define IRQ_EPPI1_ERR_POS 24
423#define IRQ_EPPI2_ERR_POS 28
424
425/* IAR7 BIT FIELDS */
426#define IRQ_UART3_ERR_POS 0
427#define IRQ_HOST_ERR_POS 4
428#define IRQ_PIXC_ERR_POS 12
429#define IRQ_NFC_ERR_POS 16
430#define IRQ_ATAPI_ERR_POS 20
431#define IRQ_CAN1_ERR_POS 24
432#define IRQ_HS_DMA_ERR_POS 28
433
434/* IAR8 BIT FIELDS */
435#define IRQ_PIXC_IN0_POS 0
436#define IRQ_PIXC_IN1_POS 4
437#define IRQ_PIXC_OUT_POS 8
438#define IRQ_SDH_POS 12
439#define IRQ_CNT_POS 16
440#define IRQ_KEY_POS 20
441#define IRQ_CAN1_RX_POS 24
442#define IRQ_CAN1_TX_POS 28
443
444/* IAR9 BIT FIELDS */
445#define IRQ_SDH_MASK0_POS 0
446#define IRQ_SDH_MASK1_POS 4
447#define IRQ_USB_INT0_POS 12
448#define IRQ_USB_INT1_POS 16
449#define IRQ_USB_INT2_POS 20
450#define IRQ_USB_DMA_POS 24
451#define IRQ_OTPSEC_POS 28
452
453/* IAR10 BIT FIELDS */
454#define IRQ_TIMER0_POS 24
455#define IRQ_TIMER1_POS 28
456
457/* IAR11 BIT FIELDS */
458#define IRQ_TIMER2_POS 0
459#define IRQ_TIMER3_POS 4
460#define IRQ_TIMER4_POS 8
461#define IRQ_TIMER5_POS 12
462#define IRQ_TIMER6_POS 16
463#define IRQ_TIMER7_POS 20
464#define IRQ_PINT2_POS 24
465#define IRQ_PINT3_POS 28
466
467#endif /* _BF548_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
new file mode 100644
index 000000000000..0cb279e973d7
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -0,0 +1,189 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/mem_init.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 * Copyright 2004-2006 Analog Devices Inc.
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#if (CONFIG_MEM_MT46V32M16)
33
34#if defined CONFIG_CLKIN_HALF
35#define CLKIN_HALF 1
36#else
37#define CLKIN_HALF 0
38#endif
39
40#if defined CONFIG_PLL_BYPASS
41#define PLL_BYPASS 1
42#else
43#define PLL_BYPASS 0
44#endif
45
46/***************************************Currently Not Being Used *********************************/
47#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
48#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
49#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
50#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
51#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
52
53#if (flash_EBIU_AMBCTL_TT > 3)
54#define flash_EBIU_AMBCTL0_TT B0TT_4
55#endif
56#if (flash_EBIU_AMBCTL_TT == 3)
57#define flash_EBIU_AMBCTL0_TT B0TT_3
58#endif
59#if (flash_EBIU_AMBCTL_TT == 2)
60#define flash_EBIU_AMBCTL0_TT B0TT_2
61#endif
62#if (flash_EBIU_AMBCTL_TT < 2)
63#define flash_EBIU_AMBCTL0_TT B0TT_1
64#endif
65
66#if (flash_EBIU_AMBCTL_ST > 3)
67#define flash_EBIU_AMBCTL0_ST B0ST_4
68#endif
69#if (flash_EBIU_AMBCTL_ST == 3)
70#define flash_EBIU_AMBCTL0_ST B0ST_3
71#endif
72#if (flash_EBIU_AMBCTL_ST == 2)
73#define flash_EBIU_AMBCTL0_ST B0ST_2
74#endif
75#if (flash_EBIU_AMBCTL_ST < 2)
76#define flash_EBIU_AMBCTL0_ST B0ST_1
77#endif
78
79#if (flash_EBIU_AMBCTL_HT > 2)
80#define flash_EBIU_AMBCTL0_HT B0HT_3
81#endif
82#if (flash_EBIU_AMBCTL_HT == 2)
83#define flash_EBIU_AMBCTL0_HT B0HT_2
84#endif
85#if (flash_EBIU_AMBCTL_HT == 1)
86#define flash_EBIU_AMBCTL0_HT B0HT_1
87#endif
88#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
89#define flash_EBIU_AMBCTL0_HT B0HT_0
90#endif
91#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
92#define flash_EBIU_AMBCTL0_HT B0HT_1
93#endif
94
95#if (flash_EBIU_AMBCTL_WAT > 14)
96#define flash_EBIU_AMBCTL0_WAT B0WAT_15
97#endif
98#if (flash_EBIU_AMBCTL_WAT == 14)
99#define flash_EBIU_AMBCTL0_WAT B0WAT_14
100#endif
101#if (flash_EBIU_AMBCTL_WAT == 13)
102#define flash_EBIU_AMBCTL0_WAT B0WAT_13
103#endif
104#if (flash_EBIU_AMBCTL_WAT == 12)
105#define flash_EBIU_AMBCTL0_WAT B0WAT_12
106#endif
107#if (flash_EBIU_AMBCTL_WAT == 11)
108#define flash_EBIU_AMBCTL0_WAT B0WAT_11
109#endif
110#if (flash_EBIU_AMBCTL_WAT == 10)
111#define flash_EBIU_AMBCTL0_WAT B0WAT_10
112#endif
113#if (flash_EBIU_AMBCTL_WAT == 9)
114#define flash_EBIU_AMBCTL0_WAT B0WAT_9
115#endif
116#if (flash_EBIU_AMBCTL_WAT == 8)
117#define flash_EBIU_AMBCTL0_WAT B0WAT_8
118#endif
119#if (flash_EBIU_AMBCTL_WAT == 7)
120#define flash_EBIU_AMBCTL0_WAT B0WAT_7
121#endif
122#if (flash_EBIU_AMBCTL_WAT == 6)
123#define flash_EBIU_AMBCTL0_WAT B0WAT_6
124#endif
125#if (flash_EBIU_AMBCTL_WAT == 5)
126#define flash_EBIU_AMBCTL0_WAT B0WAT_5
127#endif
128#if (flash_EBIU_AMBCTL_WAT == 4)
129#define flash_EBIU_AMBCTL0_WAT B0WAT_4
130#endif
131#if (flash_EBIU_AMBCTL_WAT == 3)
132#define flash_EBIU_AMBCTL0_WAT B0WAT_3
133#endif
134#if (flash_EBIU_AMBCTL_WAT == 2)
135#define flash_EBIU_AMBCTL0_WAT B0WAT_2
136#endif
137#if (flash_EBIU_AMBCTL_WAT == 1)
138#define flash_EBIU_AMBCTL0_WAT B0WAT_1
139#endif
140
141#if (flash_EBIU_AMBCTL_RAT > 14)
142#define flash_EBIU_AMBCTL0_RAT B0RAT_15
143#endif
144#if (flash_EBIU_AMBCTL_RAT == 14)
145#define flash_EBIU_AMBCTL0_RAT B0RAT_14
146#endif
147#if (flash_EBIU_AMBCTL_RAT == 13)
148#define flash_EBIU_AMBCTL0_RAT B0RAT_13
149#endif
150#if (flash_EBIU_AMBCTL_RAT == 12)
151#define flash_EBIU_AMBCTL0_RAT B0RAT_12
152#endif
153#if (flash_EBIU_AMBCTL_RAT == 11)
154#define flash_EBIU_AMBCTL0_RAT B0RAT_11
155#endif
156#if (flash_EBIU_AMBCTL_RAT == 10)
157#define flash_EBIU_AMBCTL0_RAT B0RAT_10
158#endif
159#if (flash_EBIU_AMBCTL_RAT == 9)
160#define flash_EBIU_AMBCTL0_RAT B0RAT_9
161#endif
162#if (flash_EBIU_AMBCTL_RAT == 8)
163#define flash_EBIU_AMBCTL0_RAT B0RAT_8
164#endif
165#if (flash_EBIU_AMBCTL_RAT == 7)
166#define flash_EBIU_AMBCTL0_RAT B0RAT_7
167#endif
168#if (flash_EBIU_AMBCTL_RAT == 6)
169#define flash_EBIU_AMBCTL0_RAT B0RAT_6
170#endif
171#if (flash_EBIU_AMBCTL_RAT == 5)
172#define flash_EBIU_AMBCTL0_RAT B0RAT_5
173#endif
174#if (flash_EBIU_AMBCTL_RAT == 4)
175#define flash_EBIU_AMBCTL0_RAT B0RAT_4
176#endif
177#if (flash_EBIU_AMBCTL_RAT == 3)
178#define flash_EBIU_AMBCTL0_RAT B0RAT_3
179#endif
180#if (flash_EBIU_AMBCTL_RAT == 2)
181#define flash_EBIU_AMBCTL0_RAT B0RAT_2
182#endif
183#if (flash_EBIU_AMBCTL_RAT == 1)
184#define flash_EBIU_AMBCTL0_RAT B0RAT_1
185#endif
186
187#define flash_EBIU_AMBCTL0 \
188 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
189 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
new file mode 100644
index 000000000000..72d80e8a6e81
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -0,0 +1,97 @@
1/*
2 * file: include/asm-blackfin/mach-bf548/mem_map.h
3 * based on:
4 * author:
5 *
6 * created:
7 * description:
8 * Memory MAP Common header file for blackfin BF537/6/4 of processors.
9 * rev:
10 *
11 * modified:
12 *
13 * bugs: enter bugs at http://blackfin.uclinux.org/
14 *
15 * this program is free software; you can redistribute it and/or modify
16 * it under the terms of the gnu general public license as published by
17 * the free software foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * this program is distributed in the hope that it will be useful,
21 * but without any warranty; without even the implied warranty of
22 * merchantability or fitness for a particular purpose. see the
23 * gnu general public license for more details.
24 *
25 * you should have received a copy of the gnu general public license
26 * along with this program; see the file copying.
27 * if not, write to the free software foundation,
28 * 59 temple place - suite 330, boston, ma 02111-1307, usa.
29 */
30
31#ifndef _MEM_MAP_548_H_
32#define _MEM_MAP_548_H_
33
34#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
35#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
36
37/* Async Memory Banks */
38#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
39#define ASYNC_BANK3_SIZE 0x04000000 /* 64M */
40#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
41#define ASYNC_BANK2_SIZE 0x04000000 /* 64M */
42#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
43#define ASYNC_BANK1_SIZE 0x04000000 /* 64M */
44#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
45#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
46
47/* Boot ROM Memory */
48
49#define BOOT_ROM_START 0xEF000000
50
51/* Level 1 Memory */
52
53/* Memory Map for ADSP-BF548 processors */
54#ifdef CONFIG_BLKFIN_ICACHE
55#define BLKFIN_ICACHESIZE (16*1024)
56#else
57#define BLKFIN_ICACHESIZE (0*1024)
58#endif
59
60#define L1_CODE_START 0xFFA00000
61#define L1_DATA_A_START 0xFF800000
62#define L1_DATA_B_START 0xFF900000
63
64#define L1_CODE_LENGTH 0xC000
65
66#ifdef CONFIG_BLKFIN_DCACHE
67
68#ifdef CONFIG_BLKFIN_DCACHE_BANKA
69#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
70#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
71#define L1_DATA_B_LENGTH 0x8000
72#define BLKFIN_DCACHESIZE (16*1024)
73#define BLKFIN_DSUPBANKS 1
74#else
75#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
76#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
77#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
78#define BLKFIN_DCACHESIZE (32*1024)
79#define BLKFIN_DSUPBANKS 2
80#endif
81
82#else
83#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
84#define L1_DATA_A_LENGTH 0x8000
85#define L1_DATA_B_LENGTH 0x8000
86#define BLKFIN_DCACHESIZE (0*1024)
87#define BLKFIN_DSUPBANKS 0
88#endif /*CONFIG_BLKFIN_DCACHE*/
89
90/* Scratch Pad Memory */
91
92#if defined(CONFIG_BF54x)
93#define L1_SCRATCH_START 0xFFB00000
94#define L1_SCRATCH_LENGTH 0x1000
95#endif
96
97#endif/* _MEM_MAP_548_H_ */
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
new file mode 100644
index 000000000000..b382deb501a7
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/portmux.h
@@ -0,0 +1,270 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
5#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
6#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
7#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
8#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
9#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
10#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
11#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
12#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
13#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
14#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
15#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
16#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
17#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
18#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
19#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
20#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
21#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
22#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
23#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
24
25#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
26#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
27#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
28#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
29#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
30#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
31#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
32#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
33#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
34#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
35#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
36#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
37#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
38#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
39#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
40#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
41#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
42#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
43#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
44
45#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
46#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
47#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
48#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
49#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
50#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
51#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
52#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
53#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
54#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
55#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
56#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
57#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
58#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
59#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
60#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
61
62#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
63#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
64#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
65#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
66#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
67#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
68#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
69#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
70#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
71#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
72#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
73#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
74#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
75#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
76#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
77#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
78
79#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
80#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
81#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
82#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
83#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
84#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
85#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
86#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
87#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
88#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
89#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
90#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
91#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
92#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
93#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
94#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
95#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
96#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
97#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
98#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
99#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
100#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
101#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
102#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
103#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
104#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
105#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
106#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
107#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
108#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
109#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
110#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
111#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
112#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
113#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
114#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
115#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
116#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
117#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
118#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
119#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
120#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
121#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
122#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
123#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
124#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
125
126#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
127#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
128#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
129#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
130#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
131#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
132#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
133#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
134#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
135#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
136#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
137#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
138#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
139#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
140#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
141#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
142#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
143#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
144#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
145#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
146#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
147#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
148#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
149#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
150
151#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
152#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
153#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
154#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
155#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
156#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
157#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
158#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
159#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
160#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
161#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
162#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
163#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
164#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
165#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
166#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
167#define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
168#define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
169#define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
170#define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
171#define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
172#define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
173#define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
174#define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
175#define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
176#define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
177#define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
178#define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
179#define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
180#define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
181#define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
182#define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
183
184#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
185#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
186#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
187#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
188#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
189#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
190#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
191#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
192#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
193#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
194#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
195#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
196#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
197#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
198#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
199#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
200#define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
201#define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
202#define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
203#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
204#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
205#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
206#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
207#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
208#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
209#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
210#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
211
212#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
213#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
214#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
215#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
216#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
217#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
218#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
219#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
220#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
221#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
222#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
223#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
224#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
225#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
226#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
227#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
228#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
229#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
230#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
231#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
232#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
233#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
234#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
235#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
236
237#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
238#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
239#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
240#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
241#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
242#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
243#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
244#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
245#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
246#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
247#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
248#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
249#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
250#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
251#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
252#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
253#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
254
255#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
256#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
257#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
258#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
259#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
260#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
261#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
262#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
263#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
264#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
265#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
266#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
267#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
268#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
269
270#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
index b14f872e5703..1a8ec9e46922 100644
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -57,12 +57,14 @@
57/* Writing to VR_CTL initiates a PLL relock sequence. */ 57/* Writing to VR_CTL initiates a PLL relock sequence. */
58static __inline__ void bfin_write_VR_CTL(unsigned int val) 58static __inline__ void bfin_write_VR_CTL(unsigned int val)
59{ 59{
60 unsigned long flags, iwr; 60 unsigned long flags, iwr0, iwr1;
61 61
62 /* Enable the PLL Wakeup bit in SIC IWR */ 62 /* Enable the PLL Wakeup bit in SIC IWR */
63 iwr = bfin_read32(SICA_IWR0); 63 iwr0 = bfin_read32(SICA_IWR0);
64 iwr1 = bfin_read32(SICA_IWR1);
64 /* Only allow PPL Wakeup) */ 65 /* Only allow PPL Wakeup) */
65 bfin_write32(SICA_IWR0, IWR_ENABLE(0)); 66 bfin_write32(SICA_IWR0, IWR_ENABLE(0));
67 bfin_write32(SICA_IWR1, 0);
66 68
67 bfin_write16(VR_CTL, val); 69 bfin_write16(VR_CTL, val);
68 __builtin_bfin_ssync(); 70 __builtin_bfin_ssync();
@@ -70,7 +72,8 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
70 local_irq_save(flags); 72 local_irq_save(flags);
71 asm("IDLE;"); 73 asm("IDLE;");
72 local_irq_restore(flags); 74 local_irq_restore(flags);
73 bfin_write32(SICA_IWR0, iwr); 75 bfin_write32(SICA_IWR0, iwr0);
76 bfin_write32(SICA_IWR1, iwr1);
74} 77}
75#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT) 78#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
76#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val) 79#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h
index 21d982003e75..766334b7d8ab 100644
--- a/include/asm-blackfin/mach-bf561/dma.h
+++ b/include/asm-blackfin/mach-bf561/dma.h
@@ -32,4 +32,7 @@
32#define CH_IMEM_STREAM1_SRC 34 32#define CH_IMEM_STREAM1_SRC 34
33#define CH_IMEM_STREAM1_DEST 35 33#define CH_IMEM_STREAM1_DEST 35
34 34
35extern int channel2irq(unsigned int channel);
36extern struct dma_register *base_addr[];
37
35#endif 38#endif
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
new file mode 100644
index 000000000000..10d11d5ffe23
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/portmux.h
@@ -0,0 +1,87 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define P_PPI0_CLK (P_DONTCARE)
5#define P_PPI0_FS1 (P_DONTCARE)
6#define P_PPI0_FS2 (P_DONTCARE)
7#define P_PPI0_FS3 (P_DONTCARE)
8#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
9#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
10#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
11#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
12#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
13#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
14#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
15#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
16#define P_PPI0_D0 (P_DONTCARE)
17#define P_PPI0_D1 (P_DONTCARE)
18#define P_PPI0_D2 (P_DONTCARE)
19#define P_PPI0_D3 (P_DONTCARE)
20#define P_PPI0_D4 (P_DONTCARE)
21#define P_PPI0_D5 (P_DONTCARE)
22#define P_PPI0_D6 (P_DONTCARE)
23#define P_PPI0_D7 (P_DONTCARE)
24#define P_PPI1_CLK (P_DONTCARE)
25#define P_PPI1_FS1 (P_DONTCARE)
26#define P_PPI1_FS2 (P_DONTCARE)
27#define P_PPI1_FS3 (P_DONTCARE)
28#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
29#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
30#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
31#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
32#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
33#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
34#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
35#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
36#define P_PPI1_D0 (P_DONTCARE)
37#define P_PPI1_D1 (P_DONTCARE)
38#define P_PPI1_D2 (P_DONTCARE)
39#define P_PPI1_D3 (P_DONTCARE)
40#define P_PPI1_D4 (P_DONTCARE)
41#define P_PPI1_D5 (P_DONTCARE)
42#define P_PPI1_D6 (P_DONTCARE)
43#define P_PPI1_D7 (P_DONTCARE)
44#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
45#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
46#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
47#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
48#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
49#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
50#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
51#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
52#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
53#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
54#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
55#define P_SPORT1_DRPRI (P_DONTCARE)
56#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
57#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
58#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
59#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
60#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
61#define P_SPORT0_DRPRI (P_DONTCARE)
62#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
63#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
64#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
65#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
66#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
67#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
68#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
69#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
70#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
71#define P_TMR11 (P_DONTCARE)
72#define P_TMR10 (P_DONTCARE)
73#define P_TMR9 (P_DONTCARE)
74#define P_TMR8 (P_DONTCARE)
75#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
76#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
77#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
78#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
79#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
80#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
81#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
82#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
83#define P_SPI0_MOSI (P_DONTCARE)
84#define P_SPI0_MIS0 (P_DONTCARE)
85#define P_SPI0_SCK (P_DONTCARE)
86
87#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
index 58f878947cbc..94ed381e5606 100644
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -40,16 +40,7 @@
40#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val) 40#define bfin_write_SRAM_BASE_ADDRESS(val) bfin_write32(SRAM_BASE_ADDRESS,val)
41#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) 41#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
42#ifdef ANOMALY_05000125 42#ifdef ANOMALY_05000125
43static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val) 43extern void bfin_write_DMEM_CONTROL(unsigned int val);
44{
45 unsigned long flags, iwr;
46
47 local_irq_save(flags);
48 __asm__(".align 8\n");
49 bfin_write32(IMEM_CONTROL, val);
50 __builtin_bfin_ssync();
51 local_irq_restore(flags);
52}
53#else 44#else
54#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val) 45#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
55#endif 46#endif
@@ -139,17 +130,7 @@ static __inline__ void bfin_write_DMEM_CONTROL(unsigned int val)
139*/ 130*/
140#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) 131#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL)
141#ifdef ANOMALY_05000125 132#ifdef ANOMALY_05000125
142static __inline__ void bfin_write_IMEM_CONTROL(unsigned int val) 133extern void bfin_write_IMEM_CONTROL(unsigned int val);
143{
144 unsigned long flags, iwr;
145
146 local_irq_save(flags);
147 __asm__(".align 8\n");
148 bfin_write32(IMEM_CONTROL, val);
149 __builtin_bfin_ssync();
150 local_irq_restore(flags);
151
152}
153#else 134#else
154#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val) 135#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL,val)
155#endif 136#endif
diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h
index 4d504f908c0c..b58f5ad3f024 100644
--- a/include/asm-blackfin/mman.h
+++ b/include/asm-blackfin/mman.h
@@ -22,8 +22,6 @@
22#define MAP_NORESERVE 0x4000 /* don't check for reservations */ 22#define MAP_NORESERVE 0x4000 /* don't check for reservations */
23#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */ 23#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
24#define MAP_NONBLOCK 0x10000 /* do not block on IO */ 24#define MAP_NONBLOCK 0x10000 /* do not block on IO */
25#define MAP_UNINITIALIZE 0x4000000 /* For anonymous mmap, memory could
26 be uninitialized. */
27 25
28#define MS_ASYNC 1 /* sync memory asynchronously */ 26#define MS_ASYNC 1 /* sync memory asynchronously */
29#define MS_INVALIDATE 2 /* invalidate the caches */ 27#define MS_INVALIDATE 2 /* invalidate the caches */
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
index ffad947f1b2a..8bc86717021c 100644
--- a/include/asm-blackfin/page.h
+++ b/include/asm-blackfin/page.h
@@ -4,7 +4,11 @@
4/* PAGE_SHIFT determines the page size */ 4/* PAGE_SHIFT determines the page size */
5 5
6#define PAGE_SHIFT 12 6#define PAGE_SHIFT 12
7#ifdef __ASSEMBLY__
8#define PAGE_SIZE (1 << PAGE_SHIFT)
9#else
7#define PAGE_SIZE (1UL << PAGE_SHIFT) 10#define PAGE_SIZE (1UL << PAGE_SHIFT)
11#endif
8#define PAGE_MASK (~(PAGE_SIZE-1)) 12#define PAGE_MASK (~(PAGE_SIZE-1))
9 13
10#ifdef __KERNEL__ 14#ifdef __KERNEL__
diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h
new file mode 100644
index 000000000000..9d3681e42111
--- /dev/null
+++ b/include/asm-blackfin/portmux.h
@@ -0,0 +1,1133 @@
1/*
2 * Common header file for blackfin family of processors.
3 *
4 */
5
6#ifndef _PORTMUX_H_
7#define _PORTMUX_H_
8
9#define P_IDENT(x) ((x) & 0x1FF)
10#define P_FUNCT(x) (((x) & 0x3) << 9)
11#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3)
12#define P_DEFINED 0x8000
13#define P_UNDEF 0x4000
14#define P_MAYSHARE 0x2000
15#define P_DONTCARE 0x1000
16
17#include <asm/gpio.h>
18#include <asm/mach/portmux.h>
19
20#ifndef P_SPORT2_TFS
21#define P_SPORT2_TFS P_UNDEF
22#endif
23
24#ifndef P_SPORT2_DTSEC
25#define P_SPORT2_DTSEC P_UNDEF
26#endif
27
28#ifndef P_SPORT2_DTPRI
29#define P_SPORT2_DTPRI P_UNDEF
30#endif
31
32#ifndef P_SPORT2_TSCLK
33#define P_SPORT2_TSCLK P_UNDEF
34#endif
35
36#ifndef P_SPORT2_RFS
37#define P_SPORT2_RFS P_UNDEF
38#endif
39
40#ifndef P_SPORT2_DRSEC
41#define P_SPORT2_DRSEC P_UNDEF
42#endif
43
44#ifndef P_SPORT2_DRPRI
45#define P_SPORT2_DRPRI P_UNDEF
46#endif
47
48#ifndef P_SPORT2_RSCLK
49#define P_SPORT2_RSCLK P_UNDEF
50#endif
51
52#ifndef P_SPORT3_TFS
53#define P_SPORT3_TFS P_UNDEF
54#endif
55
56#ifndef P_SPORT3_DTSEC
57#define P_SPORT3_DTSEC P_UNDEF
58#endif
59
60#ifndef P_SPORT3_DTPRI
61#define P_SPORT3_DTPRI P_UNDEF
62#endif
63
64#ifndef P_SPORT3_TSCLK
65#define P_SPORT3_TSCLK P_UNDEF
66#endif
67
68#ifndef P_SPORT3_RFS
69#define P_SPORT3_RFS P_UNDEF
70#endif
71
72#ifndef P_SPORT3_DRSEC
73#define P_SPORT3_DRSEC P_UNDEF
74#endif
75
76#ifndef P_SPORT3_DRPRI
77#define P_SPORT3_DRPRI P_UNDEF
78#endif
79
80#ifndef P_SPORT3_RSCLK
81#define P_SPORT3_RSCLK P_UNDEF
82#endif
83
84#ifndef P_TMR4
85#define P_TMR4 P_UNDEF
86#endif
87
88#ifndef P_TMR5
89#define P_TMR5 P_UNDEF
90#endif
91
92#ifndef P_TMR6
93#define P_TMR6 P_UNDEF
94#endif
95
96#ifndef P_TMR7
97#define P_TMR7 P_UNDEF
98#endif
99
100#ifndef P_TWI1_SCL
101#define P_TWI1_SCL P_UNDEF
102#endif
103
104#ifndef P_TWI1_SDA
105#define P_TWI1_SDA P_UNDEF
106#endif
107
108#ifndef P_UART3_RTS
109#define P_UART3_RTS P_UNDEF
110#endif
111
112#ifndef P_UART3_CTS
113#define P_UART3_CTS P_UNDEF
114#endif
115
116#ifndef P_UART2_TX
117#define P_UART2_TX P_UNDEF
118#endif
119
120#ifndef P_UART2_RX
121#define P_UART2_RX P_UNDEF
122#endif
123
124#ifndef P_UART3_TX
125#define P_UART3_TX P_UNDEF
126#endif
127
128#ifndef P_UART3_RX
129#define P_UART3_RX P_UNDEF
130#endif
131
132#ifndef P_SPI2_SS
133#define P_SPI2_SS P_UNDEF
134#endif
135
136#ifndef P_SPI2_SSEL1
137#define P_SPI2_SSEL1 P_UNDEF
138#endif
139
140#ifndef P_SPI2_SSEL2
141#define P_SPI2_SSEL2 P_UNDEF
142#endif
143
144#ifndef P_SPI2_SSEL3
145#define P_SPI2_SSEL3 P_UNDEF
146#endif
147
148#ifndef P_SPI2_SCK
149#define P_SPI2_SCK P_UNDEF
150#endif
151
152#ifndef P_SPI2_MOSI
153#define P_SPI2_MOSI P_UNDEF
154#endif
155
156#ifndef P_SPI2_MISO
157#define P_SPI2_MISO P_UNDEF
158#endif
159
160#ifndef P_TMR0
161#define P_TMR0 P_UNDEF
162#endif
163
164#ifndef P_TMR1
165#define P_TMR1 P_UNDEF
166#endif
167
168#ifndef P_TMR2
169#define P_TMR2 P_UNDEF
170#endif
171
172#ifndef P_TMR3
173#define P_TMR3 P_UNDEF
174#endif
175
176#ifndef P_SPORT0_TFS
177#define P_SPORT0_TFS P_UNDEF
178#endif
179
180#ifndef P_SPORT0_DTSEC
181#define P_SPORT0_DTSEC P_UNDEF
182#endif
183
184#ifndef P_SPORT0_DTPRI
185#define P_SPORT0_DTPRI P_UNDEF
186#endif
187
188#ifndef P_SPORT0_TSCLK
189#define P_SPORT0_TSCLK P_UNDEF
190#endif
191
192#ifndef P_SPORT0_RFS
193#define P_SPORT0_RFS P_UNDEF
194#endif
195
196#ifndef P_SPORT0_DRSEC
197#define P_SPORT0_DRSEC P_UNDEF
198#endif
199
200#ifndef P_SPORT0_DRPRI
201#define P_SPORT0_DRPRI P_UNDEF
202#endif
203
204#ifndef P_SPORT0_RSCLK
205#define P_SPORT0_RSCLK P_UNDEF
206#endif
207
208#ifndef P_SD_D0
209#define P_SD_D0 P_UNDEF
210#endif
211
212#ifndef P_SD_D1
213#define P_SD_D1 P_UNDEF
214#endif
215
216#ifndef P_SD_D2
217#define P_SD_D2 P_UNDEF
218#endif
219
220#ifndef P_SD_D3
221#define P_SD_D3 P_UNDEF
222#endif
223
224#ifndef P_SD_CLK
225#define P_SD_CLK P_UNDEF
226#endif
227
228#ifndef P_SD_CMD
229#define P_SD_CMD P_UNDEF
230#endif
231
232#ifndef P_MMCLK
233#define P_MMCLK P_UNDEF
234#endif
235
236#ifndef P_MBCLK
237#define P_MBCLK P_UNDEF
238#endif
239
240#ifndef P_PPI1_D0
241#define P_PPI1_D0 P_UNDEF
242#endif
243
244#ifndef P_PPI1_D1
245#define P_PPI1_D1 P_UNDEF
246#endif
247
248#ifndef P_PPI1_D2
249#define P_PPI1_D2 P_UNDEF
250#endif
251
252#ifndef P_PPI1_D3
253#define P_PPI1_D3 P_UNDEF
254#endif
255
256#ifndef P_PPI1_D4
257#define P_PPI1_D4 P_UNDEF
258#endif
259
260#ifndef P_PPI1_D5
261#define P_PPI1_D5 P_UNDEF
262#endif
263
264#ifndef P_PPI1_D6
265#define P_PPI1_D6 P_UNDEF
266#endif
267
268#ifndef P_PPI1_D7
269#define P_PPI1_D7 P_UNDEF
270#endif
271
272#ifndef P_PPI1_D8
273#define P_PPI1_D8 P_UNDEF
274#endif
275
276#ifndef P_PPI1_D9
277#define P_PPI1_D9 P_UNDEF
278#endif
279
280#ifndef P_PPI1_D10
281#define P_PPI1_D10 P_UNDEF
282#endif
283
284#ifndef P_PPI1_D11
285#define P_PPI1_D11 P_UNDEF
286#endif
287
288#ifndef P_PPI1_D12
289#define P_PPI1_D12 P_UNDEF
290#endif
291
292#ifndef P_PPI1_D13
293#define P_PPI1_D13 P_UNDEF
294#endif
295
296#ifndef P_PPI1_D14
297#define P_PPI1_D14 P_UNDEF
298#endif
299
300#ifndef P_PPI1_D15
301#define P_PPI1_D15 P_UNDEF
302#endif
303
304#ifndef P_HOST_D8
305#define P_HOST_D8 P_UNDEF
306#endif
307
308#ifndef P_HOST_D9
309#define P_HOST_D9 P_UNDEF
310#endif
311
312#ifndef P_HOST_D10
313#define P_HOST_D10 P_UNDEF
314#endif
315
316#ifndef P_HOST_D11
317#define P_HOST_D11 P_UNDEF
318#endif
319
320#ifndef P_HOST_D12
321#define P_HOST_D12 P_UNDEF
322#endif
323
324#ifndef P_HOST_D13
325#define P_HOST_D13 P_UNDEF
326#endif
327
328#ifndef P_HOST_D14
329#define P_HOST_D14 P_UNDEF
330#endif
331
332#ifndef P_HOST_D15
333#define P_HOST_D15 P_UNDEF
334#endif
335
336#ifndef P_HOST_D0
337#define P_HOST_D0 P_UNDEF
338#endif
339
340#ifndef P_HOST_D1
341#define P_HOST_D1 P_UNDEF
342#endif
343
344#ifndef P_HOST_D2
345#define P_HOST_D2 P_UNDEF
346#endif
347
348#ifndef P_HOST_D3
349#define P_HOST_D3 P_UNDEF
350#endif
351
352#ifndef P_HOST_D4
353#define P_HOST_D4 P_UNDEF
354#endif
355
356#ifndef P_HOST_D5
357#define P_HOST_D5 P_UNDEF
358#endif
359
360#ifndef P_HOST_D6
361#define P_HOST_D6 P_UNDEF
362#endif
363
364#ifndef P_HOST_D7
365#define P_HOST_D7 P_UNDEF
366#endif
367
368#ifndef P_SPORT1_TFS
369#define P_SPORT1_TFS P_UNDEF
370#endif
371
372#ifndef P_SPORT1_DTSEC
373#define P_SPORT1_DTSEC P_UNDEF
374#endif
375
376#ifndef P_SPORT1_DTPRI
377#define P_SPORT1_DTPRI P_UNDEF
378#endif
379
380#ifndef P_SPORT1_TSCLK
381#define P_SPORT1_TSCLK P_UNDEF
382#endif
383
384#ifndef P_SPORT1_RFS
385#define P_SPORT1_RFS P_UNDEF
386#endif
387
388#ifndef P_SPORT1_DRSEC
389#define P_SPORT1_DRSEC P_UNDEF
390#endif
391
392#ifndef P_SPORT1_DRPRI
393#define P_SPORT1_DRPRI P_UNDEF
394#endif
395
396#ifndef P_SPORT1_RSCLK
397#define P_SPORT1_RSCLK P_UNDEF
398#endif
399
400#ifndef P_PPI2_D0
401#define P_PPI2_D0 P_UNDEF
402#endif
403
404#ifndef P_PPI2_D1
405#define P_PPI2_D1 P_UNDEF
406#endif
407
408#ifndef P_PPI2_D2
409#define P_PPI2_D2 P_UNDEF
410#endif
411
412#ifndef P_PPI2_D3
413#define P_PPI2_D3 P_UNDEF
414#endif
415
416#ifndef P_PPI2_D4
417#define P_PPI2_D4 P_UNDEF
418#endif
419
420#ifndef P_PPI2_D5
421#define P_PPI2_D5 P_UNDEF
422#endif
423
424#ifndef P_PPI2_D6
425#define P_PPI2_D6 P_UNDEF
426#endif
427
428#ifndef P_PPI2_D7
429#define P_PPI2_D7 P_UNDEF
430#endif
431
432#ifndef P_PPI0_D18
433#define P_PPI0_D18 P_UNDEF
434#endif
435
436#ifndef P_PPI0_D19
437#define P_PPI0_D19 P_UNDEF
438#endif
439
440#ifndef P_PPI0_D20
441#define P_PPI0_D20 P_UNDEF
442#endif
443
444#ifndef P_PPI0_D21
445#define P_PPI0_D21 P_UNDEF
446#endif
447
448#ifndef P_PPI0_D22
449#define P_PPI0_D22 P_UNDEF
450#endif
451
452#ifndef P_PPI0_D23
453#define P_PPI0_D23 P_UNDEF
454#endif
455
456#ifndef P_KEY_ROW0
457#define P_KEY_ROW0 P_UNDEF
458#endif
459
460#ifndef P_KEY_ROW1
461#define P_KEY_ROW1 P_UNDEF
462#endif
463
464#ifndef P_KEY_ROW2
465#define P_KEY_ROW2 P_UNDEF
466#endif
467
468#ifndef P_KEY_ROW3
469#define P_KEY_ROW3 P_UNDEF
470#endif
471
472#ifndef P_KEY_COL0
473#define P_KEY_COL0 P_UNDEF
474#endif
475
476#ifndef P_KEY_COL1
477#define P_KEY_COL1 P_UNDEF
478#endif
479
480#ifndef P_KEY_COL2
481#define P_KEY_COL2 P_UNDEF
482#endif
483
484#ifndef P_KEY_COL3
485#define P_KEY_COL3 P_UNDEF
486#endif
487
488#ifndef P_SPI0_SCK
489#define P_SPI0_SCK P_UNDEF
490#endif
491
492#ifndef P_SPI0_MISO
493#define P_SPI0_MISO P_UNDEF
494#endif
495
496#ifndef P_SPI0_MOSI
497#define P_SPI0_MOSI P_UNDEF
498#endif
499
500#ifndef P_SPI0_SS
501#define P_SPI0_SS P_UNDEF
502#endif
503
504#ifndef P_SPI0_SSEL1
505#define P_SPI0_SSEL1 P_UNDEF
506#endif
507
508#ifndef P_SPI0_SSEL2
509#define P_SPI0_SSEL2 P_UNDEF
510#endif
511
512#ifndef P_SPI0_SSEL3
513#define P_SPI0_SSEL3 P_UNDEF
514#endif
515
516#ifndef P_UART0_TX
517#define P_UART0_TX P_UNDEF
518#endif
519
520#ifndef P_UART0_RX
521#define P_UART0_RX P_UNDEF
522#endif
523
524#ifndef P_UART1_RTS
525#define P_UART1_RTS P_UNDEF
526#endif
527
528#ifndef P_UART1_CTS
529#define P_UART1_CTS P_UNDEF
530#endif
531
532#ifndef P_PPI1_CLK
533#define P_PPI1_CLK P_UNDEF
534#endif
535
536#ifndef P_PPI1_FS1
537#define P_PPI1_FS1 P_UNDEF
538#endif
539
540#ifndef P_PPI1_FS2
541#define P_PPI1_FS2 P_UNDEF
542#endif
543
544#ifndef P_TWI0_SCL
545#define P_TWI0_SCL P_UNDEF
546#endif
547
548#ifndef P_TWI0_SDA
549#define P_TWI0_SDA P_UNDEF
550#endif
551
552#ifndef P_KEY_COL7
553#define P_KEY_COL7 P_UNDEF
554#endif
555
556#ifndef P_KEY_ROW6
557#define P_KEY_ROW6 P_UNDEF
558#endif
559
560#ifndef P_KEY_COL6
561#define P_KEY_COL6 P_UNDEF
562#endif
563
564#ifndef P_KEY_ROW5
565#define P_KEY_ROW5 P_UNDEF
566#endif
567
568#ifndef P_KEY_COL5
569#define P_KEY_COL5 P_UNDEF
570#endif
571
572#ifndef P_KEY_ROW4
573#define P_KEY_ROW4 P_UNDEF
574#endif
575
576#ifndef P_KEY_COL4
577#define P_KEY_COL4 P_UNDEF
578#endif
579
580#ifndef P_KEY_ROW7
581#define P_KEY_ROW7 P_UNDEF
582#endif
583
584#ifndef P_PPI0_D0
585#define P_PPI0_D0 P_UNDEF
586#endif
587
588#ifndef P_PPI0_D1
589#define P_PPI0_D1 P_UNDEF
590#endif
591
592#ifndef P_PPI0_D2
593#define P_PPI0_D2 P_UNDEF
594#endif
595
596#ifndef P_PPI0_D3
597#define P_PPI0_D3 P_UNDEF
598#endif
599
600#ifndef P_PPI0_D4
601#define P_PPI0_D4 P_UNDEF
602#endif
603
604#ifndef P_PPI0_D5
605#define P_PPI0_D5 P_UNDEF
606#endif
607
608#ifndef P_PPI0_D6
609#define P_PPI0_D6 P_UNDEF
610#endif
611
612#ifndef P_PPI0_D7
613#define P_PPI0_D7 P_UNDEF
614#endif
615
616#ifndef P_PPI0_D8
617#define P_PPI0_D8 P_UNDEF
618#endif
619
620#ifndef P_PPI0_D9
621#define P_PPI0_D9 P_UNDEF
622#endif
623
624#ifndef P_PPI0_D10
625#define P_PPI0_D10 P_UNDEF
626#endif
627
628#ifndef P_PPI0_D11
629#define P_PPI0_D11 P_UNDEF
630#endif
631
632#ifndef P_PPI0_D12
633#define P_PPI0_D12 P_UNDEF
634#endif
635
636#ifndef P_PPI0_D13
637#define P_PPI0_D13 P_UNDEF
638#endif
639
640#ifndef P_PPI0_D14
641#define P_PPI0_D14 P_UNDEF
642#endif
643
644#ifndef P_PPI0_D15
645#define P_PPI0_D15 P_UNDEF
646#endif
647
648#ifndef P_ATAPI_D0A
649#define P_ATAPI_D0A P_UNDEF
650#endif
651
652#ifndef P_ATAPI_D1A
653#define P_ATAPI_D1A P_UNDEF
654#endif
655
656#ifndef P_ATAPI_D2A
657#define P_ATAPI_D2A P_UNDEF
658#endif
659
660#ifndef P_ATAPI_D3A
661#define P_ATAPI_D3A P_UNDEF
662#endif
663
664#ifndef P_ATAPI_D4A
665#define P_ATAPI_D4A P_UNDEF
666#endif
667
668#ifndef P_ATAPI_D5A
669#define P_ATAPI_D5A P_UNDEF
670#endif
671
672#ifndef P_ATAPI_D6A
673#define P_ATAPI_D6A P_UNDEF
674#endif
675
676#ifndef P_ATAPI_D7A
677#define P_ATAPI_D7A P_UNDEF
678#endif
679
680#ifndef P_ATAPI_D8A
681#define P_ATAPI_D8A P_UNDEF
682#endif
683
684#ifndef P_ATAPI_D9A
685#define P_ATAPI_D9A P_UNDEF
686#endif
687
688#ifndef P_ATAPI_D10A
689#define P_ATAPI_D10A P_UNDEF
690#endif
691
692#ifndef P_ATAPI_D11A
693#define P_ATAPI_D11A P_UNDEF
694#endif
695
696#ifndef P_ATAPI_D12A
697#define P_ATAPI_D12A P_UNDEF
698#endif
699
700#ifndef P_ATAPI_D13A
701#define P_ATAPI_D13A P_UNDEF
702#endif
703
704#ifndef P_ATAPI_D14A
705#define P_ATAPI_D14A P_UNDEF
706#endif
707
708#ifndef P_ATAPI_D15A
709#define P_ATAPI_D15A P_UNDEF
710#endif
711
712#ifndef P_PPI0_CLK
713#define P_PPI0_CLK P_UNDEF
714#endif
715
716#ifndef P_PPI0_FS1
717#define P_PPI0_FS1 P_UNDEF
718#endif
719
720#ifndef P_PPI0_FS2
721#define P_PPI0_FS2 P_UNDEF
722#endif
723
724#ifndef P_PPI0_D16
725#define P_PPI0_D16 P_UNDEF
726#endif
727
728#ifndef P_PPI0_D17
729#define P_PPI0_D17 P_UNDEF
730#endif
731
732#ifndef P_SPI1_SSEL1
733#define P_SPI1_SSEL1 P_UNDEF
734#endif
735
736#ifndef P_SPI1_SSEL2
737#define P_SPI1_SSEL2 P_UNDEF
738#endif
739
740#ifndef P_SPI1_SSEL3
741#define P_SPI1_SSEL3 P_UNDEF
742#endif
743
744#ifndef P_SPI1_SCK
745#define P_SPI1_SCK P_UNDEF
746#endif
747
748#ifndef P_SPI1_MISO
749#define P_SPI1_MISO P_UNDEF
750#endif
751
752#ifndef P_SPI1_MOSI
753#define P_SPI1_MOSI P_UNDEF
754#endif
755
756#ifndef P_SPI1_SS
757#define P_SPI1_SS P_UNDEF
758#endif
759
760#ifndef P_CAN0_TX
761#define P_CAN0_TX P_UNDEF
762#endif
763
764#ifndef P_CAN0_RX
765#define P_CAN0_RX P_UNDEF
766#endif
767
768#ifndef P_CAN1_TX
769#define P_CAN1_TX P_UNDEF
770#endif
771
772#ifndef P_CAN1_RX
773#define P_CAN1_RX P_UNDEF
774#endif
775
776#ifndef P_ATAPI_A0A
777#define P_ATAPI_A0A P_UNDEF
778#endif
779
780#ifndef P_ATAPI_A1A
781#define P_ATAPI_A1A P_UNDEF
782#endif
783
784#ifndef P_ATAPI_A2A
785#define P_ATAPI_A2A P_UNDEF
786#endif
787
788#ifndef P_HOST_CE
789#define P_HOST_CE P_UNDEF
790#endif
791
792#ifndef P_HOST_RD
793#define P_HOST_RD P_UNDEF
794#endif
795
796#ifndef P_HOST_WR
797#define P_HOST_WR P_UNDEF
798#endif
799
800#ifndef P_MTXONB
801#define P_MTXONB P_UNDEF
802#endif
803
804#ifndef P_PPI2_FS2
805#define P_PPI2_FS2 P_UNDEF
806#endif
807
808#ifndef P_PPI2_FS1
809#define P_PPI2_FS1 P_UNDEF
810#endif
811
812#ifndef P_PPI2_CLK
813#define P_PPI2_CLK P_UNDEF
814#endif
815
816#ifndef P_CNT_CZM
817#define P_CNT_CZM P_UNDEF
818#endif
819
820#ifndef P_UART1_TX
821#define P_UART1_TX P_UNDEF
822#endif
823
824#ifndef P_UART1_RX
825#define P_UART1_RX P_UNDEF
826#endif
827
828#ifndef P_ATAPI_RESET
829#define P_ATAPI_RESET P_UNDEF
830#endif
831
832#ifndef P_HOST_ADDR
833#define P_HOST_ADDR P_UNDEF
834#endif
835
836#ifndef P_HOST_ACK
837#define P_HOST_ACK P_UNDEF
838#endif
839
840#ifndef P_MTX
841#define P_MTX P_UNDEF
842#endif
843
844#ifndef P_MRX
845#define P_MRX P_UNDEF
846#endif
847
848#ifndef P_MRXONB
849#define P_MRXONB P_UNDEF
850#endif
851
852#ifndef P_A4
853#define P_A4 P_UNDEF
854#endif
855
856#ifndef P_A5
857#define P_A5 P_UNDEF
858#endif
859
860#ifndef P_A6
861#define P_A6 P_UNDEF
862#endif
863
864#ifndef P_A7
865#define P_A7 P_UNDEF
866#endif
867
868#ifndef P_A8
869#define P_A8 P_UNDEF
870#endif
871
872#ifndef P_A9
873#define P_A9 P_UNDEF
874#endif
875
876#ifndef P_PPI1_FS3
877#define P_PPI1_FS3 P_UNDEF
878#endif
879
880#ifndef P_PPI2_FS3
881#define P_PPI2_FS3 P_UNDEF
882#endif
883
884#ifndef P_TMR8
885#define P_TMR8 P_UNDEF
886#endif
887
888#ifndef P_TMR9
889#define P_TMR9 P_UNDEF
890#endif
891
892#ifndef P_TMR10
893#define P_TMR10 P_UNDEF
894#endif
895#ifndef P_TMR11
896#define P_TMR11 P_UNDEF
897#endif
898
899#ifndef P_DMAR0
900#define P_DMAR0 P_UNDEF
901#endif
902
903#ifndef P_DMAR1
904#define P_DMAR1 P_UNDEF
905#endif
906
907#ifndef P_PPI0_FS3
908#define P_PPI0_FS3 P_UNDEF
909#endif
910
911#ifndef P_CNT_CDG
912#define P_CNT_CDG P_UNDEF
913#endif
914
915#ifndef P_CNT_CUD
916#define P_CNT_CUD P_UNDEF
917#endif
918
919#ifndef P_A10
920#define P_A10 P_UNDEF
921#endif
922
923#ifndef P_A11
924#define P_A11 P_UNDEF
925#endif
926
927#ifndef P_A12
928#define P_A12 P_UNDEF
929#endif
930
931#ifndef P_A13
932#define P_A13 P_UNDEF
933#endif
934
935#ifndef P_A14
936#define P_A14 P_UNDEF
937#endif
938
939#ifndef P_A15
940#define P_A15 P_UNDEF
941#endif
942
943#ifndef P_A16
944#define P_A16 P_UNDEF
945#endif
946
947#ifndef P_A17
948#define P_A17 P_UNDEF
949#endif
950
951#ifndef P_A18
952#define P_A18 P_UNDEF
953#endif
954
955#ifndef P_A19
956#define P_A19 P_UNDEF
957#endif
958
959#ifndef P_A20
960#define P_A20 P_UNDEF
961#endif
962
963#ifndef P_A21
964#define P_A21 P_UNDEF
965#endif
966
967#ifndef P_A22
968#define P_A22 P_UNDEF
969#endif
970
971#ifndef P_A23
972#define P_A23 P_UNDEF
973#endif
974
975#ifndef P_A24
976#define P_A24 P_UNDEF
977#endif
978
979#ifndef P_A25
980#define P_A25 P_UNDEF
981#endif
982
983#ifndef P_NOR_CLK
984#define P_NOR_CLK P_UNDEF
985#endif
986
987#ifndef P_TMRCLK
988#define P_TMRCLK P_UNDEF
989#endif
990
991#ifndef P_AMC_ARDY_NOR_WAIT
992#define P_AMC_ARDY_NOR_WAIT P_UNDEF
993#endif
994
995#ifndef P_NAND_CE
996#define P_NAND_CE P_UNDEF
997#endif
998
999#ifndef P_NAND_RB
1000#define P_NAND_RB P_UNDEF
1001#endif
1002
1003#ifndef P_ATAPI_DIOR
1004#define P_ATAPI_DIOR P_UNDEF
1005#endif
1006
1007#ifndef P_ATAPI_DIOW
1008#define P_ATAPI_DIOW P_UNDEF
1009#endif
1010
1011#ifndef P_ATAPI_CS0
1012#define P_ATAPI_CS0 P_UNDEF
1013#endif
1014
1015#ifndef P_ATAPI_CS1
1016#define P_ATAPI_CS1 P_UNDEF
1017#endif
1018
1019#ifndef P_ATAPI_DMACK
1020#define P_ATAPI_DMACK P_UNDEF
1021#endif
1022
1023#ifndef P_ATAPI_DMARQ
1024#define P_ATAPI_DMARQ P_UNDEF
1025#endif
1026
1027#ifndef P_ATAPI_INTRQ
1028#define P_ATAPI_INTRQ P_UNDEF
1029#endif
1030
1031#ifndef P_ATAPI_IORDY
1032#define P_ATAPI_IORDY P_UNDEF
1033#endif
1034
1035#ifndef P_AMC_BR
1036#define P_AMC_BR P_UNDEF
1037#endif
1038
1039#ifndef P_AMC_BG
1040#define P_AMC_BG P_UNDEF
1041#endif
1042
1043#ifndef P_AMC_BGH
1044#define P_AMC_BGH P_UNDEF
1045#endif
1046
1047/* EMAC */
1048
1049#ifndef P_MII0_ETxD0
1050#define P_MII0_ETxD0 P_UNDEF
1051#endif
1052
1053#ifndef P_MII0_ETxD1
1054#define P_MII0_ETxD1 P_UNDEF
1055#endif
1056
1057#ifndef P_MII0_ETxD2
1058#define P_MII0_ETxD2 P_UNDEF
1059#endif
1060
1061#ifndef P_MII0_ETxD3
1062#define P_MII0_ETxD3 P_UNDEF
1063#endif
1064
1065#ifndef P_MII0_ETxEN
1066#define P_MII0_ETxEN P_UNDEF
1067#endif
1068
1069#ifndef P_MII0_TxCLK
1070#define P_MII0_TxCLK P_UNDEF
1071#endif
1072
1073#ifndef P_MII0_PHYINT
1074#define P_MII0_PHYINT P_UNDEF
1075#endif
1076
1077#ifndef P_MII0_COL
1078#define P_MII0_COL P_UNDEF
1079#endif
1080
1081#ifndef P_MII0_ERxD0
1082#define P_MII0_ERxD0 P_UNDEF
1083#endif
1084
1085#ifndef P_MII0_ERxD1
1086#define P_MII0_ERxD1 P_UNDEF
1087#endif
1088
1089#ifndef P_MII0_ERxD2
1090#define P_MII0_ERxD2 P_UNDEF
1091#endif
1092
1093#ifndef P_MII0_ERxD3
1094#define P_MII0_ERxD3 P_UNDEF
1095#endif
1096
1097#ifndef P_MII0_ERxDV
1098#define P_MII0_ERxDV P_UNDEF
1099#endif
1100
1101#ifndef P_MII0_ERxCLK
1102#define P_MII0_ERxCLK P_UNDEF
1103#endif
1104
1105#ifndef P_MII0_ERxER
1106#define P_MII0_ERxER P_UNDEF
1107#endif
1108
1109#ifndef P_MII0_CRS
1110#define P_MII0_CRS P_UNDEF
1111#endif
1112
1113#ifndef P_RMII0_REF_CLK
1114#define P_RMII0_REF_CLK P_UNDEF
1115#endif
1116
1117#ifndef P_RMII0_MDINT
1118#define P_RMII0_MDINT P_UNDEF
1119#endif
1120
1121#ifndef P_RMII0_CRS_DV
1122#define P_RMII0_CRS_DV P_UNDEF
1123#endif
1124
1125#ifndef P_MDC
1126#define P_MDC P_UNDEF
1127#endif
1128
1129#ifndef P_MDIO
1130#define P_MDIO P_UNDEF
1131#endif
1132
1133#endif /* _PORTMUX_H_ */
diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h
new file mode 100644
index 000000000000..9c2474c9a589
--- /dev/null
+++ b/include/asm-blackfin/trace.h
@@ -0,0 +1,52 @@
1/*
2 * Common header file for blackfin family of processors.
3 *
4 */
5
6#ifndef _BLACKFIN_TRACE_
7#define _BLACKFIN_TRACE_
8
9#ifndef __ASSEMBLY__
10/* Trace Macros for C files */
11
12#define trace_buffer_save(x) \
13 do { \
14 (x) = bfin_read_TBUFCTL(); \
15 bfin_write_TBUFCTL((x) & ~TBUFEN); \
16 } while (0)
17
18#define trace_buffer_restore(x) \
19 do { \
20 bfin_write_TBUFCTL((x)); \
21 } while (0)
22
23#else
24/* Trace Macros for Assembly files */
25
26#define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg)
27#define TRACE_BUFFER_STOP(preg, dreg) trace_buffer_stop(preg, dreg)
28
29#define trace_buffer_stop(preg, dreg) \
30 preg.L = LO(TBUFCTL); \
31 preg.H = HI(TBUFCTL); \
32 dreg = 0x1; \
33 [preg] = dreg;
34
35#define trace_buffer_start(preg, dreg) \
36 preg.L = LO(TBUFCTL); \
37 preg.H = HI(TBUFCTL); \
38 dreg = 0x13; \
39 [preg] = dreg;
40
41#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
42# define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg)
43# define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg)
44
45#else
46# define DEBUG_START_HWTRACE(preg, dreg)
47# define DEBUG_STOP_HWTRACE(preg, dreg)
48#endif
49
50#endif /* __ASSEMBLY__ */
51
52#endif /* _BLACKFIN_TRACE_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 02:49:28 -0500