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authorLucas Stach <l.stach@pengutronix.de>2014-09-26 09:41:02 -0400
committerShawn Guo <shawn.guo@linaro.org>2014-11-23 01:56:20 -0500
commit82a40b54820601aad0facf72050c62ae7fc7d4df (patch)
treeac79a73cbff3ec82b6a41a88b89ca2bf9436e70b
parente0fed5133cc3656319e94c258e4a064dca8ccb27 (diff)
ARM: imx53: clk: add ARM clock
The ARM clock is a virtual clock feeding the ARM partition of the SoC. It controls multiple other clocks to ensure the right sequencing when cpufreq changes the CPU clock rate. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c5
-rw-r--r--include/dt-bindings/clock/imx5-clock.h3
2 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index aafccf4b47c2..0f7e536147cb 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -541,6 +541,11 @@ static void __init mx53_clocks_init(struct device_node *np)
541 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); 541 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
542 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, 542 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
543 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel)); 543 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
544 clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf",
545 clk[IMX5_CLK_CPU_PODF],
546 clk[IMX5_CLK_CPU_PODF_SEL],
547 clk[IMX5_CLK_PLL1_SW],
548 clk[IMX5_CLK_STEP_SEL]);
544 549
545 imx_check_clocks(clk, ARRAY_SIZE(clk)); 550 imx_check_clocks(clk, ARRAY_SIZE(clk));
546 551
diff --git a/include/dt-bindings/clock/imx5-clock.h b/include/dt-bindings/clock/imx5-clock.h
index 1a36ff4ace1e..f4b7478e23c8 100644
--- a/include/dt-bindings/clock/imx5-clock.h
+++ b/include/dt-bindings/clock/imx5-clock.h
@@ -200,6 +200,7 @@
200#define IMX5_CLK_SATA_REF 188 200#define IMX5_CLK_SATA_REF 188
201#define IMX5_CLK_STEP_SEL 189 201#define IMX5_CLK_STEP_SEL 189
202#define IMX5_CLK_CPU_PODF_SEL 190 202#define IMX5_CLK_CPU_PODF_SEL 190
203#define IMX5_CLK_END 191 203#define IMX5_CLK_ARM 191
204#define IMX5_CLK_END 192
204 205
205#endif /* __DT_BINDINGS_CLOCK_IMX5_H */ 206#endif /* __DT_BINDINGS_CLOCK_IMX5_H */