drm/nouveau/fence: make internal hooks part of the context

A step towards being able to provide fences from other engines not
connected to PFIFO.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

8 files changed, 48 insertions, 45 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index b7349a636546..6a7a5b576273 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -61,13 +61,12 @@ nouveau_fence_context_new(struct nouveau_fence_chan *fctx)
 static void
 nouveau_fence_update(struct nouveau_channel *chan)
 {
-        struct nouveau_fence_priv *priv = chan->drm->fence;
         struct nouveau_fence_chan *fctx = chan->fence;
         struct nouveau_fence *fence, *fnext;
 
         spin_lock(&fctx->lock);
         list_for_each_entry_safe(fence, fnext, &fctx->pending, head) {
-                if (priv->read(chan) < fence->sequence)
+                if (fctx->read(chan) < fence->sequence)
                         break;
 
                 if (fence->work)
@@ -82,7 +81,6 @@ nouveau_fence_update(struct nouveau_channel *chan)
 int
 nouveau_fence_emit(struct nouveau_fence *fence, struct nouveau_channel *chan)
 {
-        struct nouveau_fence_priv *priv = chan->drm->fence;
         struct nouveau_fence_chan *fctx = chan->fence;
         int ret;
 
@@ -90,7 +88,7 @@ nouveau_fence_emit(struct nouveau_fence *fence, struct nouveau_channel *chan)
         fence->timeout  = jiffies + (3 * DRM_HZ);
         fence->sequence = ++fctx->sequence;
 
-        ret = priv->emit(fence);
+        ret = fctx->emit(fence);
         if (!ret) {
                 kref_get(&fence->kref);
                 spin_lock(&fctx->lock);
@@ -219,14 +217,14 @@ nouveau_fence_wait(struct nouveau_fence *fence, bool lazy, bool intr)
 int
 nouveau_fence_sync(struct nouveau_fence *fence, struct nouveau_channel *chan)
 {
-        struct nouveau_fence_priv *priv = chan->drm->fence;
+        struct nouveau_fence_chan *fctx = chan->fence;
         struct nouveau_channel *prev;
         int ret = 0;
 
         prev = fence ? fence->channel : NULL;
         if (prev) {
                 if (unlikely(prev != chan && !nouveau_fence_done(fence))) {
-                        ret = priv->sync(fence, prev, chan);
+                        ret = fctx->sync(fence, prev, chan);
                         if (unlikely(ret))
                                 ret = nouveau_fence_wait(fence, true, false);
                 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.h b/drivers/gpu/drm/nouveau/nouveau_fence.h
index fb0993c3dc39..a5c47e348e22 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.h
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.h
@@ -29,6 +29,13 @@ struct nouveau_fence_chan {
         struct list_head pending;
         struct list_head flip;
 
+        int  (*emit)(struct nouveau_fence *);
+        int  (*sync)(struct nouveau_fence *, struct nouveau_channel *,
+                     struct nouveau_channel *);
+        u32  (*read)(struct nouveau_channel *);
+        int  (*emit32)(struct nouveau_channel *, u64, u32);
+        int  (*sync32)(struct nouveau_channel *, u64, u32);
+
         spinlock_t lock;
         u32 sequence;
 };
@@ -39,12 +46,6 @@ struct nouveau_fence_priv {
         void (*resume)(struct nouveau_drm *);
         int  (*context_new)(struct nouveau_channel *);
         void (*context_del)(struct nouveau_channel *);
-        int  (*emit32)(struct nouveau_channel *, u64, u32);
-        int  (*emit)(struct nouveau_fence *);
-        int  (*sync32)(struct nouveau_channel *, u64, u32);
-        int  (*sync)(struct nouveau_fence *, struct nouveau_channel *,
-                     struct nouveau_channel *);
-        u32  (*read)(struct nouveau_channel *);
 
         wait_queue_head_t waiting;
         bool uevent;
diff --git a/drivers/gpu/drm/nouveau/nv04_fence.c b/drivers/gpu/drm/nouveau/nv04_fence.c
index a220b94ba9f2..94eadd1dd10a 100644
--- a/drivers/gpu/drm/nouveau/nv04_fence.c
+++ b/drivers/gpu/drm/nouveau/nv04_fence.c
@@ -78,6 +78,9 @@ nv04_fence_context_new(struct nouveau_channel *chan)
         struct nv04_fence_chan *fctx = kzalloc(sizeof(*fctx), GFP_KERNEL);
         if (fctx) {
                 nouveau_fence_context_new(&fctx->base);
+                fctx->base.emit = nv04_fence_emit;
+                fctx->base.sync = nv04_fence_sync;
+                fctx->base.read = nv04_fence_read;
                 chan->fence = fctx;
                 return 0;
         }
@@ -104,8 +107,5 @@ nv04_fence_create(struct nouveau_drm *drm)
         priv->base.dtor = nv04_fence_destroy;
         priv->base.context_new = nv04_fence_context_new;
         priv->base.context_del = nv04_fence_context_del;
-        priv->base.emit = nv04_fence_emit;
-        priv->base.sync = nv04_fence_sync;
-        priv->base.read = nv04_fence_read;
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c
index e4f124a48d4e..06f434f03fba 100644
--- a/drivers/gpu/drm/nouveau/nv10_fence.c
+++ b/drivers/gpu/drm/nouveau/nv10_fence.c
@@ -75,6 +75,9 @@ nv10_fence_context_new(struct nouveau_channel *chan)
                 return -ENOMEM;
 
         nouveau_fence_context_new(&fctx->base);
+        fctx->base.emit = nv10_fence_emit;
+        fctx->base.read = nv10_fence_read;
+        fctx->base.sync = nv10_fence_sync;
         return 0;
 }
 
@@ -102,9 +105,6 @@ nv10_fence_create(struct nouveau_drm *drm)
         priv->base.dtor = nv10_fence_destroy;
         priv->base.context_new = nv10_fence_context_new;
         priv->base.context_del = nv10_fence_context_del;
-        priv->base.emit = nv10_fence_emit;
-        priv->base.read = nv10_fence_read;
-        priv->base.sync = nv10_fence_sync;
         spin_lock_init(&priv->lock);
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c
index fe194451e0ad..8e47a9bae8c3 100644
--- a/drivers/gpu/drm/nouveau/nv17_fence.c
+++ b/drivers/gpu/drm/nouveau/nv17_fence.c
@@ -84,6 +84,9 @@ nv17_fence_context_new(struct nouveau_channel *chan)
                 return -ENOMEM;
 
         nouveau_fence_context_new(&fctx->base);
+        fctx->base.emit = nv10_fence_emit;
+        fctx->base.read = nv10_fence_read;
+        fctx->base.sync = nv17_fence_sync;
 
         ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
                                  NvSema, 0x0002,
@@ -121,9 +124,6 @@ nv17_fence_create(struct nouveau_drm *drm)
         priv->base.resume = nv17_fence_resume;
         priv->base.context_new = nv17_fence_context_new;
         priv->base.context_del = nv10_fence_context_del;
-        priv->base.emit = nv10_fence_emit;
-        priv->base.read = nv10_fence_read;
-        priv->base.sync = nv17_fence_sync;
         spin_lock_init(&priv->lock);
 
         ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c
index 72791d658b40..f9701e567db8 100644
--- a/drivers/gpu/drm/nouveau/nv50_fence.c
+++ b/drivers/gpu/drm/nouveau/nv50_fence.c
@@ -46,6 +46,9 @@ nv50_fence_context_new(struct nouveau_channel *chan)
                 return -ENOMEM;
 
         nouveau_fence_context_new(&fctx->base);
+        fctx->base.emit = nv10_fence_emit;
+        fctx->base.read = nv10_fence_read;
+        fctx->base.sync = nv17_fence_sync;
 
         ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
                                  NvSema, 0x0002,
@@ -88,11 +91,9 @@ nv50_fence_create(struct nouveau_drm *drm)
                 return -ENOMEM;
 
         priv->base.dtor = nv10_fence_destroy;
+        priv->base.resume = nv17_fence_resume;
         priv->base.context_new = nv50_fence_context_new;
         priv->base.context_del = nv10_fence_context_del;
-        priv->base.emit = nv10_fence_emit;
-        priv->base.read = nv10_fence_read;
-        priv->base.sync = nv17_fence_sync;
         spin_lock_init(&priv->lock);
 
         ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
@@ -108,13 +109,11 @@ nv50_fence_create(struct nouveau_drm *drm)
                         nouveau_bo_ref(NULL, &priv->bo);
         }
 
-        if (ret == 0) {
-                nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
-                priv->base.sync = nv17_fence_sync;
-                priv->base.resume = nv17_fence_resume;
+        if (ret) {
+                nv10_fence_destroy(drm);
+                return ret;
         }
 
-        if (ret)
-                nv10_fence_destroy(drm);
+        nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
         return ret;
 }
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c
index 8a80ad7c0cf5..bc6493c1a1ef 100644
--- a/drivers/gpu/drm/nouveau/nv84_fence.c
+++ b/drivers/gpu/drm/nouveau/nv84_fence.c
@@ -80,22 +80,20 @@ int
 nv84_fence_emit(struct nouveau_fence *fence)
 {
         struct nouveau_channel *chan = fence->channel;
-        struct nv84_fence_priv *priv = chan->drm->fence;
         struct nv84_fence_chan *fctx = chan->fence;
         struct nouveau_fifo_chan *fifo = (void *)chan->object;
         u64 addr = fctx->vma.offset + fifo->chid * 16;
-        return priv->base.emit32(chan, addr, fence->sequence);
+        return fctx->base.emit32(chan, addr, fence->sequence);
 }
 
 int
 nv84_fence_sync(struct nouveau_fence *fence,
                 struct nouveau_channel *prev, struct nouveau_channel *chan)
 {
-        struct nv84_fence_priv *priv = chan->drm->fence;
         struct nv84_fence_chan *fctx = chan->fence;
         struct nouveau_fifo_chan *fifo = (void *)prev->object;
         u64 addr = fctx->vma.offset + fifo->chid * 16;
-        return priv->base.sync32(chan, addr, fence->sequence);
+        return fctx->base.sync32(chan, addr, fence->sequence);
 }
 
 u32
@@ -139,6 +137,11 @@ nv84_fence_context_new(struct nouveau_channel *chan)
                 return -ENOMEM;
 
         nouveau_fence_context_new(&fctx->base);
+        fctx->base.emit = nv84_fence_emit;
+        fctx->base.sync = nv84_fence_sync;
+        fctx->base.read = nv84_fence_read;
+        fctx->base.emit32 = nv84_fence_emit32;
+        fctx->base.sync32 = nv84_fence_sync32;
 
         ret = nouveau_bo_vma_add(priv->bo, client->vm, &fctx->vma);
         if (ret)
@@ -213,11 +216,6 @@ nv84_fence_create(struct nouveau_drm *drm)
         priv->base.resume = nv84_fence_resume;
         priv->base.context_new = nv84_fence_context_new;
         priv->base.context_del = nv84_fence_context_del;
-        priv->base.emit32 = nv84_fence_emit32;
-        priv->base.emit = nv84_fence_emit;
-        priv->base.sync32 = nv84_fence_sync32;
-        priv->base.sync = nv84_fence_sync;
-        priv->base.read = nv84_fence_read;
 
         init_waitqueue_head(&priv->base.waiting);
         priv->base.uevent = true;
diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c
index 8213f7de92fa..b7def390d808 100644
--- a/drivers/gpu/drm/nouveau/nvc0_fence.c
+++ b/drivers/gpu/drm/nouveau/nvc0_fence.c
@@ -66,6 +66,18 @@ nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
         return ret;
 }
 
+static int
+nvc0_fence_context_new(struct nouveau_channel *chan)
+{
+        int ret = nv84_fence_context_new(chan);
+        if (ret == 0) {
+                struct nv84_fence_chan *fctx = chan->fence;
+                fctx->base.emit32 = nvc0_fence_emit32;
+                fctx->base.sync32 = nvc0_fence_sync32;
+        }
+        return ret;
+}
+
 int
 nvc0_fence_create(struct nouveau_drm *drm)
 {
@@ -80,13 +92,8 @@ nvc0_fence_create(struct nouveau_drm *drm)
         priv->base.dtor = nv84_fence_destroy;
         priv->base.suspend = nv84_fence_suspend;
         priv->base.resume = nv84_fence_resume;
-        priv->base.context_new = nv84_fence_context_new;
+        priv->base.context_new = nvc0_fence_context_new;
         priv->base.context_del = nv84_fence_context_del;
-        priv->base.emit32 = nvc0_fence_emit32;
-        priv->base.emit = nv84_fence_emit;
-        priv->base.sync32 = nvc0_fence_sync32;
-        priv->base.sync = nv84_fence_sync;
-        priv->base.read = nv84_fence_read;
 
         init_waitqueue_head(&priv->base.waiting);
         priv->base.uevent = true;