clk: mvebu: Fix ratio register offset on A375 SoC

This commit fixes the ratio register offset which is 0x4,
as per the Armada 375 SoC specification.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index 4da60760be10..4af33ba54a1e 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -213,7 +213,7 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = {
                 .set_rate = clk_corediv_set_rate,
         },
         .ratio_reload = BIT(8),
-        .ratio_offset = 0x8,
+        .ratio_offset = 0x4,
 };
 
 static void __init