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authorHariprasad Shenai <hariprasad@chelsio.com>2014-07-21 11:25:12 -0400
committerDavid S. Miller <davem@davemloft.net>2014-07-21 23:23:59 -0400
commit822dd8a85c27913da7b58e8fed947529c9965e55 (patch)
treea0b19ed904b3618b80699d3ca3b91d55f1b27a57
parentbc3bd3f41480d378b12ba6f1c16fd3310815ad1d (diff)
cxgb4: Add the MC1 registers to read in the interrupt handler
Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_hw.c16
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_regs.h3
2 files changed, 16 insertions, 3 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index eb5a278e8045..e76885236e9d 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -1719,16 +1719,24 @@ static void mps_intr_handler(struct adapter *adapter)
1719 */ 1719 */
1720static void mem_intr_handler(struct adapter *adapter, int idx) 1720static void mem_intr_handler(struct adapter *adapter, int idx)
1721{ 1721{
1722 static const char name[3][5] = { "EDC0", "EDC1", "MC" }; 1722 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
1723 1723
1724 unsigned int addr, cnt_addr, v; 1724 unsigned int addr, cnt_addr, v;
1725 1725
1726 if (idx <= MEM_EDC1) { 1726 if (idx <= MEM_EDC1) {
1727 addr = EDC_REG(EDC_INT_CAUSE, idx); 1727 addr = EDC_REG(EDC_INT_CAUSE, idx);
1728 cnt_addr = EDC_REG(EDC_ECC_STATUS, idx); 1728 cnt_addr = EDC_REG(EDC_ECC_STATUS, idx);
1729 } else if (idx == MEM_MC) {
1730 if (is_t4(adapter->params.chip)) {
1731 addr = MC_INT_CAUSE;
1732 cnt_addr = MC_ECC_STATUS;
1733 } else {
1734 addr = MC_P_INT_CAUSE;
1735 cnt_addr = MC_P_ECC_STATUS;
1736 }
1729 } else { 1737 } else {
1730 addr = MC_INT_CAUSE; 1738 addr = MC_REG(MC_P_INT_CAUSE, 1);
1731 cnt_addr = MC_ECC_STATUS; 1739 cnt_addr = MC_REG(MC_P_ECC_STATUS, 1);
1732 } 1740 }
1733 1741
1734 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; 1742 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
@@ -1892,6 +1900,8 @@ int t4_slow_intr_handler(struct adapter *adapter)
1892 pcie_intr_handler(adapter); 1900 pcie_intr_handler(adapter);
1893 if (cause & MC) 1901 if (cause & MC)
1894 mem_intr_handler(adapter, MEM_MC); 1902 mem_intr_handler(adapter, MEM_MC);
1903 if (!is_t4(adapter->params.chip) && (cause & MC1))
1904 mem_intr_handler(adapter, MEM_MC1);
1895 if (cause & EDC0) 1905 if (cause & EDC0)
1896 mem_intr_handler(adapter, MEM_EDC0); 1906 mem_intr_handler(adapter, MEM_EDC0);
1897 if (cause & EDC1) 1907 if (cause & EDC1)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index 3b244abbf907..e3146e83df20 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -448,11 +448,13 @@
448#define TDUE 0x00010000U 448#define TDUE 0x00010000U
449 449
450#define MC_INT_CAUSE 0x7518 450#define MC_INT_CAUSE 0x7518
451#define MC_P_INT_CAUSE 0x41318
451#define ECC_UE_INT_CAUSE 0x00000004U 452#define ECC_UE_INT_CAUSE 0x00000004U
452#define ECC_CE_INT_CAUSE 0x00000002U 453#define ECC_CE_INT_CAUSE 0x00000002U
453#define PERR_INT_CAUSE 0x00000001U 454#define PERR_INT_CAUSE 0x00000001U
454 455
455#define MC_ECC_STATUS 0x751c 456#define MC_ECC_STATUS 0x751c
457#define MC_P_ECC_STATUS 0x4131c
456#define ECC_CECNT_MASK 0xffff0000U 458#define ECC_CECNT_MASK 0xffff0000U
457#define ECC_CECNT_SHIFT 16 459#define ECC_CECNT_SHIFT 16
458#define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT) 460#define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT)
@@ -1101,6 +1103,7 @@
1101#define I2CM 0x00000002U 1103#define I2CM 0x00000002U
1102#define CIM 0x00000001U 1104#define CIM 0x00000001U
1103 1105
1106#define MC1 0x31
1104#define PL_INT_ENABLE 0x19410 1107#define PL_INT_ENABLE 0x19410
1105#define PL_INT_MAP0 0x19414 1108#define PL_INT_MAP0 0x19414
1106#define PL_RST 0x19428 1109#define PL_RST 0x19428