ARM: vexpress: Remove non-DT code

Now, with the CLCD DT support available, there is no
more reason to keep the non-DT support for V2P-CA9.

Removed, together with "some" supporting code. It was
necessary to make PLAT_VERSATILE_SCHED_CLOCK optional
and selected by the machines still interested in it.

Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

17 files changed, 17 insertions, 943 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 89c4b5ccc68d..6c6fdb8a36e1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -350,6 +350,7 @@ config ARCH_REALVIEW
         select ICST
         select NEED_MACH_MEMORY_H
         select PLAT_VERSATILE
+        select PLAT_VERSATILE_SCHED_CLOCK
         help
           This enables support for ARM Ltd RealView boards.
 
@@ -365,6 +366,7 @@ config ARCH_VERSATILE
         select ICST
         select PLAT_VERSATILE
         select PLAT_VERSATILE_CLOCK
+        select PLAT_VERSATILE_SCHED_CLOCK
         select VERSATILE_FPGA_IRQ
         help
           This enables support for ARM Ltd Versatile board.
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index b2cfba16c4e8..9a96bab12ef3 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -49,9 +49,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
           build a working kernel, you must also enable relevant core
           tile support or Flattened Device Tree based support options.
 
-config ARCH_VEXPRESS_CA9X4
-        bool "Versatile Express Cortex-A9x4 tile"
-
 config ARCH_VEXPRESS_DCSCB
         bool "Dual Cluster System Control Block (DCSCB) support"
         depends on MCPM
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index fc649bc09d0c..f5c1006dd6a1 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -1,11 +1,10 @@
 #
 # Makefile for the linux kernel.
 #
-ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := \
         -I$(srctree)/arch/arm/plat-versatile/include
 
 obj-y                                   := v2m.o
-obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
 obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)       += dcscb.o      dcscb_setup.o
 CFLAGS_dcscb.o                          += -march=armv7-a
 CFLAGS_REMOVE_dcscb.o                   = -pg
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index 152fad91b3ae..2a11d3ac8c68 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,12 +1,5 @@
-/* 2MB large area for motherboard's peripherals static mapping */
-#define V2M_PERIPH 0xf8000000
-
-/* Tile's peripherals static mappings should start here */
-#define V2T_PERIPH 0xf8200000
-
 bool vexpress_smp_init_ops(void);
 
-extern struct smp_operations    vexpress_smp_ops;
 extern struct smp_operations    vexpress_smp_dt_ops;
 
 extern void vexpress_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
deleted file mode 100644
index 27bea049380a..000000000000
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/*
- * Versatile Express Core Tile Cortex A9x4 Support
- */
-#include <linux/init.h>
-#include <linux/gfp.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/clcd.h>
-#include <linux/platform_data/video-clcd-versatile.h>
-#include <linux/clkdev.h>
-#include <linux/vexpress.h>
-#include <linux/irqchip/arm-gic.h>
-
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/smp_scu.h>
-#include <asm/smp_twd.h>
-
-#include <mach/ct-ca9x4.h>
-
-#include <asm/hardware/timer-sp.h>
-
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include "core.h"
-
-#include <mach/motherboard.h>
-#include <mach/irqs.h>
-
-static struct map_desc ct_ca9x4_io_desc[] __initdata = {
-        {
-                .virtual        = V2T_PERIPH,
-                .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
-                .length         = SZ_8K,
-                .type           = MT_DEVICE,
-        },
-};
-
-static void __init ct_ca9x4_map_io(void)
-{
-        iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
-}
-
-static void __init ca9x4_l2_init(void)
-{
-#ifdef CONFIG_CACHE_L2X0
-        void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
-
-        if (l2x0_base) {
-                /* set RAM latencies to 1 cycle for this core tile. */
-                writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
-                writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
-
-                l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
-        } else {
-                pr_err("L2C: unable to map L2 cache controller\n");
-        }
-#endif
-}
-
-#ifdef CONFIG_HAVE_ARM_TWD
-static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
-
-static void __init ca9x4_twd_init(void)
-{
-        int err = twd_local_timer_register(&twd_local_timer);
-        if (err)
-                pr_err("twd_local_timer_register failed %d\n", err);
-}
-#else
-#define ca9x4_twd_init()        do {} while(0)
-#endif
-
-static void __init ct_ca9x4_init_irq(void)
-{
-        gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
-                 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
-        ca9x4_twd_init();
-        ca9x4_l2_init();
-}
-
-static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
-{
-        unsigned long framesize = 1024 * 768 * 2;
-
-        fb->panel = versatile_clcd_get_panel("XVGA");
-        if (!fb->panel)
-                return -EINVAL;
-
-        return versatile_clcd_setup_dma(fb, framesize);
-}
-