aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJames Hogan <james.hogan@imgtec.com>2013-07-29 07:25:01 -0400
committerMike Turquette <mturquette@linaro.org>2013-08-19 15:27:17 -0400
commit819c1de344c5b8350bffd35be9a0fa74541292d3 (patch)
treea7829ac81de6d968cc24516f17c87da98c528d06
parent71472c0c06cf9a3d1540762ea205654c584e3bc4 (diff)
clk: add CLK_SET_RATE_NO_REPARENT flag
Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat
-rw-r--r--arch/arm/mach-imx/clk.h5
-rw-r--r--drivers/clk/mmp/clk-mmp2.c39
-rw-r--r--drivers/clk/mmp/clk-pxa168.c40
-rw-r--r--drivers/clk/mmp/clk-pxa910.c31
-rw-r--r--drivers/clk/mxs/clk.h4
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c6
-rw-r--r--drivers/clk/samsung/clk.h2
-rw-r--r--drivers/clk/spear/spear1310_clock.c179
-rw-r--r--drivers/clk/spear/spear1340_clock.c97
-rw-r--r--drivers/clk/spear/spear3xx_clock.c57
-rw-r--r--drivers/clk/spear/spear6xx_clock.c35
-rw-r--r--drivers/clk/sunxi/clk-sunxi.c3
-rw-r--r--drivers/clk/tegra/clk-tegra114.c36
-rw-r--r--drivers/clk/tegra/clk-tegra20.c6
-rw-r--r--drivers/clk/tegra/clk-tegra30.c33
-rw-r--r--drivers/clk/versatile/clk-vexpress.c4
-rw-r--r--drivers/clk/zynq/clkc.c86
-rw-r--r--include/linux/clk-provider.h1
18 files changed, 388 insertions, 276 deletions
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 0e4e8bb261b9..c8575fb7f717 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -79,7 +79,8 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
79static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, 79static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
80 u8 shift, u8 width, const char **parents, int num_parents) 80 u8 shift, u8 width, const char **parents, int num_parents)
81{ 81{
82 return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift, 82 return clk_register_mux(NULL, name, parents, num_parents,
83 CLK_SET_RATE_NO_REPARENT, reg, shift,
83 width, 0, &imx_ccm_lock); 84 width, 0, &imx_ccm_lock);
84} 85}
85 86
@@ -88,7 +89,7 @@ static inline struct clk *imx_clk_mux_flags(const char *name,
88 int num_parents, unsigned long flags) 89 int num_parents, unsigned long flags)
89{ 90{
90 return clk_register_mux(NULL, name, parents, num_parents, 91 return clk_register_mux(NULL, name, parents, num_parents,
91 flags, reg, shift, width, 0, 92 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
92 &imx_ccm_lock); 93 &imx_ccm_lock);
93} 94}
94 95
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index d1f1a19d4351..b2721cae257a 100644
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -248,7 +248,8 @@ void __init mmp2_clk_init(void)
248 clk_register_clkdev(clk, NULL, "mmp2-pwm.3"); 248 clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
249 249
250 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, 250 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
251 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 251 ARRAY_SIZE(uart_parent),
252 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
252 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); 253 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
253 clk_set_parent(clk, vctcxo); 254 clk_set_parent(clk, vctcxo);
254 clk_register_clkdev(clk, "uart_mux.0", NULL); 255 clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -258,7 +259,8 @@ void __init mmp2_clk_init(void)
258 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); 259 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
259 260
260 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, 261 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
261 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 262 ARRAY_SIZE(uart_parent),
263 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
262 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); 264 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
263 clk_set_parent(clk, vctcxo); 265 clk_set_parent(clk, vctcxo);
264 clk_register_clkdev(clk, "uart_mux.1", NULL); 266 clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -268,7 +270,8 @@ void __init mmp2_clk_init(void)
268 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); 270 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
269 271
270 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, 272 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
271 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 273 ARRAY_SIZE(uart_parent),
274 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
272 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); 275 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
273 clk_set_parent(clk, vctcxo); 276 clk_set_parent(clk, vctcxo);
274 clk_register_clkdev(clk, "uart_mux.2", NULL); 277 clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -278,7 +281,8 @@ void __init mmp2_clk_init(void)
278 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); 281 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
279 282
280 clk = clk_register_mux(NULL, "uart3_mux", uart_parent, 283 clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
281 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 284 ARRAY_SIZE(uart_parent),
285 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
282 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock); 286 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
283 clk_set_parent(clk, vctcxo); 287 clk_set_parent(clk, vctcxo);
284 clk_register_clkdev(clk, "uart_mux.3", NULL); 288 clk_register_clkdev(clk, "uart_mux.3", NULL);
@@ -288,7 +292,8 @@ void __init mmp2_clk_init(void)
288 clk_register_clkdev(clk, NULL, "pxa2xx-uart.3"); 292 clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
289 293
290 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, 294 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
291 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 295 ARRAY_SIZE(ssp_parent),
296 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
292 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); 297 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
293 clk_register_clkdev(clk, "uart_mux.0", NULL); 298 clk_register_clkdev(clk, "uart_mux.0", NULL);
294 299
@@ -297,7 +302,8 @@ void __init mmp2_clk_init(void)
297 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); 302 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
298 303
299 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, 304 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
300 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 305 ARRAY_SIZE(ssp_parent),
306 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
301 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); 307 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
302 clk_register_clkdev(clk, "ssp_mux.1", NULL); 308 clk_register_clkdev(clk, "ssp_mux.1", NULL);
303 309
@@ -306,7 +312,8 @@ void __init mmp2_clk_init(void)
306 clk_register_clkdev(clk, NULL, "mmp-ssp.1"); 312 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
307 313
308 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, 314 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
309 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 315 ARRAY_SIZE(ssp_parent),
316 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
310 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); 317 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
311 clk_register_clkdev(clk, "ssp_mux.2", NULL); 318 clk_register_clkdev(clk, "ssp_mux.2", NULL);
312 319
@@ -315,7 +322,8 @@ void __init mmp2_clk_init(void)
315 clk_register_clkdev(clk, NULL, "mmp-ssp.2"); 322 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
316 323
317 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, 324 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
318 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 325 ARRAY_SIZE(ssp_parent),
326 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
319 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); 327 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
320 clk_register_clkdev(clk, "ssp_mux.3", NULL); 328 clk_register_clkdev(clk, "ssp_mux.3", NULL);
321 329
@@ -324,7 +332,8 @@ void __init mmp2_clk_init(void)
324 clk_register_clkdev(clk, NULL, "mmp-ssp.3"); 332 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
325 333
326 clk = clk_register_mux(NULL, "sdh_mux", sdh_parent, 334 clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
327 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, 335 ARRAY_SIZE(sdh_parent),
336 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
328 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock); 337 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
329 clk_register_clkdev(clk, "sdh_mux", NULL); 338 clk_register_clkdev(clk, "sdh_mux", NULL);
330 339
@@ -354,7 +363,8 @@ void __init mmp2_clk_init(void)
354 clk_register_clkdev(clk, "usb_clk", NULL); 363 clk_register_clkdev(clk, "usb_clk", NULL);
355 364
356 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, 365 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
357 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, 366 ARRAY_SIZE(disp_parent),
367 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
358 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock); 368 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
359 clk_register_clkdev(clk, "disp_mux.0", NULL); 369 clk_register_clkdev(clk, "disp_mux.0", NULL);
360 370
@@ -376,7 +386,8 @@ void __init mmp2_clk_init(void)
376 clk_register_clkdev(clk, "disp_sphy.0", NULL); 386 clk_register_clkdev(clk, "disp_sphy.0", NULL);
377 387
378 clk = clk_register_mux(NULL, "disp1_mux", disp_parent, 388 clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
379 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, 389 ARRAY_SIZE(disp_parent),
390 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
380 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock); 391 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
381 clk_register_clkdev(clk, "disp_mux.1", NULL); 392 clk_register_clkdev(clk, "disp_mux.1", NULL);
382 393
@@ -394,7 +405,8 @@ void __init mmp2_clk_init(void)
394 clk_register_clkdev(clk, "ccic_arbiter", NULL); 405 clk_register_clkdev(clk, "ccic_arbiter", NULL);
395 406
396 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, 407 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
397 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, 408 ARRAY_SIZE(ccic_parent),
409 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
398 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); 410 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
399 clk_register_clkdev(clk, "ccic_mux.0", NULL); 411 clk_register_clkdev(clk, "ccic_mux.0", NULL);
400 412
@@ -421,7 +433,8 @@ void __init mmp2_clk_init(void)
421 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); 433 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
422 434
423 clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent, 435 clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
424 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, 436 ARRAY_SIZE(ccic_parent),
437 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
425 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); 438 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
426 clk_register_clkdev(clk, "ccic_mux.1", NULL); 439 clk_register_clkdev(clk, "ccic_mux.1", NULL);
427 440
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index 28b3b51c794b..014396b028a2 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -199,7 +199,8 @@ void __init pxa168_clk_init(void)
199 clk_register_clkdev(clk, NULL, "pxa168-pwm.3"); 199 clk_register_clkdev(clk, NULL, "pxa168-pwm.3");
200 200
201 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, 201 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
202 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 202 ARRAY_SIZE(uart_parent),
203 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
203 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); 204 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
204 clk_set_parent(clk, uart_pll); 205 clk_set_parent(clk, uart_pll);
205 clk_register_clkdev(clk, "uart_mux.0", NULL); 206 clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -209,7 +210,8 @@ void __init pxa168_clk_init(void)
209 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); 210 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
210 211
211 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, 212 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
212 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 213 ARRAY_SIZE(uart_parent),
214 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
213 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); 215 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
214 clk_set_parent(clk, uart_pll); 216 clk_set_parent(clk, uart_pll);
215 clk_register_clkdev(clk, "uart_mux.1", NULL); 217 clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -219,7 +221,8 @@ void __init pxa168_clk_init(void)
219 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); 221 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
220 222
221 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, 223 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
222 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 224 ARRAY_SIZE(uart_parent),
225 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
223 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock); 226 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
224 clk_set_parent(clk, uart_pll); 227 clk_set_parent(clk, uart_pll);
225 clk_register_clkdev(clk, "uart_mux.2", NULL); 228 clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -229,7 +232,8 @@ void __init pxa168_clk_init(void)
229 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); 232 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
230 233
231 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, 234 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
232 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 235 ARRAY_SIZE(ssp_parent),
236 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
233 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); 237 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
234 clk_register_clkdev(clk, "uart_mux.0", NULL); 238 clk_register_clkdev(clk, "uart_mux.0", NULL);
235 239
@@ -238,7 +242,8 @@ void __init pxa168_clk_init(void)
238 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); 242 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
239 243
240 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, 244 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
241 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 245 ARRAY_SIZE(ssp_parent),
246 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
242 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); 247 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
243 clk_register_clkdev(clk, "ssp_mux.1", NULL); 248 clk_register_clkdev(clk, "ssp_mux.1", NULL);
244 249
@@ -247,7 +252,8 @@ void __init pxa168_clk_init(void)
247 clk_register_clkdev(clk, NULL, "mmp-ssp.1"); 252 clk_register_clkdev(clk, NULL, "mmp-ssp.1");
248 253
249 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, 254 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
250 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 255 ARRAY_SIZE(ssp_parent),
256 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
251 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock); 257 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
252 clk_register_clkdev(clk, "ssp_mux.2", NULL); 258 clk_register_clkdev(clk, "ssp_mux.2", NULL);
253 259
@@ -256,7 +262,8 @@ void __init pxa168_clk_init(void)
256 clk_register_clkdev(clk, NULL, "mmp-ssp.2"); 262 clk_register_clkdev(clk, NULL, "mmp-ssp.2");
257 263
258 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, 264 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
259 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 265 ARRAY_SIZE(ssp_parent),
266 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
260 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock); 267 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
261 clk_register_clkdev(clk, "ssp_mux.3", NULL); 268 clk_register_clkdev(clk, "ssp_mux.3", NULL);
262 269
@@ -265,7 +272,8 @@ void __init pxa168_clk_init(void)
265 clk_register_clkdev(clk, NULL, "mmp-ssp.3"); 272 clk_register_clkdev(clk, NULL, "mmp-ssp.3");
266 273
267 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent, 274 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent,
268 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 275 ARRAY_SIZE(ssp_parent),
276 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
269 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock); 277 apbc_base + APBC_SSP4, 4, 3, 0, &clk_lock);
270 clk_register_clkdev(clk, "ssp_mux.4", NULL); 278 clk_register_clkdev(clk, "ssp_mux.4", NULL);
271 279
@@ -278,7 +286,8 @@ void __init pxa168_clk_init(void)
278 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); 286 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
279 287
280 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, 288 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
281 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, 289 ARRAY_SIZE(sdh_parent),
290 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
282 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); 291 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
283 clk_register_clkdev(clk, "sdh0_mux", NULL); 292 clk_register_clkdev(clk, "sdh0_mux", NULL);
284 293
@@ -287,7 +296,8 @@ void __init pxa168_clk_init(void)
287 clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); 296 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
288 297
289 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, 298 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
290 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, 299 ARRAY_SIZE(sdh_parent),
300 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
291 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); 301 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
292 clk_register_clkdev(clk, "sdh1_mux", NULL); 302 clk_register_clkdev(clk, "sdh1_mux", NULL);
293 303
@@ -304,7 +314,8 @@ void __init pxa168_clk_init(void)
304 clk_register_clkdev(clk, "sph_clk", NULL); 314 clk_register_clkdev(clk, "sph_clk", NULL);
305 315
306 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, 316 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
307 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, 317 ARRAY_SIZE(disp_parent),
318 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
308 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); 319 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
309 clk_register_clkdev(clk, "disp_mux.0", NULL); 320 clk_register_clkdev(clk, "disp_mux.0", NULL);
310 321
@@ -317,7 +328,8 @@ void __init pxa168_clk_init(void)
317 clk_register_clkdev(clk, "hclk", "mmp-disp.0"); 328 clk_register_clkdev(clk, "hclk", "mmp-disp.0");
318 329
319 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, 330 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
320 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, 331 ARRAY_SIZE(ccic_parent),
332 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
321 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); 333 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
322 clk_register_clkdev(clk, "ccic_mux.0", NULL); 334 clk_register_clkdev(clk, "ccic_mux.0", NULL);
323 335
@@ -327,8 +339,8 @@ void __init pxa168_clk_init(void)
327 339
328 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, 340 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
329 ARRAY_SIZE(ccic_phy_parent), 341 ARRAY_SIZE(ccic_phy_parent),
330 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 342 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
331 7, 1, 0, &clk_lock); 343 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
332 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); 344 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
333 345
334 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", 346 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index 6ec05698ed38..9efc6a47535d 100644
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -204,7 +204,8 @@ void __init pxa910_clk_init(void)
204 clk_register_clkdev(clk, NULL, "pxa910-pwm.3"); 204 clk_register_clkdev(clk, NULL, "pxa910-pwm.3");
205 205
206 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, 206 clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
207 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 207 ARRAY_SIZE(uart_parent),
208 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
208 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock); 209 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
209 clk_set_parent(clk, uart_pll); 210 clk_set_parent(clk, uart_pll);
210 clk_register_clkdev(clk, "uart_mux.0", NULL); 211 clk_register_clkdev(clk, "uart_mux.0", NULL);
@@ -214,7 +215,8 @@ void __init pxa910_clk_init(void)
214 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); 215 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
215 216
216 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, 217 clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
217 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 218 ARRAY_SIZE(uart_parent),
219 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
218 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock); 220 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
219 clk_set_parent(clk, uart_pll); 221 clk_set_parent(clk, uart_pll);
220 clk_register_clkdev(clk, "uart_mux.1", NULL); 222 clk_register_clkdev(clk, "uart_mux.1", NULL);
@@ -224,7 +226,8 @@ void __init pxa910_clk_init(void)
224 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); 226 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
225 227
226 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, 228 clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
227 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT, 229 ARRAY_SIZE(uart_parent),
230 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
228 apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock); 231 apbcp_base + APBCP_UART2, 4, 3, 0, &clk_lock);
229 clk_set_parent(clk, uart_pll); 232 clk_set_parent(clk, uart_pll);
230 clk_register_clkdev(clk, "uart_mux.2", NULL); 233 clk_register_clkdev(clk, "uart_mux.2", NULL);
@@ -234,7 +237,8 @@ void __init pxa910_clk_init(void)
234 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); 237 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
235 238
236 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, 239 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
237 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 240 ARRAY_SIZE(ssp_parent),
241 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
238 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock); 242 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
239 clk_register_clkdev(clk, "uart_mux.0", NULL); 243 clk_register_clkdev(clk, "uart_mux.0", NULL);
240 244
@@ -243,7 +247,8 @@ void __init pxa910_clk_init(void)
243 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); 247 clk_register_clkdev(clk, NULL, "mmp-ssp.0");
244 248
245 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, 249 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
246 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT, 250 ARRAY_SIZE(ssp_parent),
251 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
247 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock); 252 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
248 clk_register_clkdev(clk, "ssp_mux.1", NULL); 253 clk_register_clkdev(clk, "ssp_mux.1", NULL);
249 254
@@ -256,7 +261,8 @@ void __init pxa910_clk_init(void)
256 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); 261 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0");
257 262
258 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, 263 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent,
259 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, 264 ARRAY_SIZE(sdh_parent),
265 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
260 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock); 266 apmu_base + APMU_SDH0, 6, 1, 0, &clk_lock);
261 clk_register_clkdev(clk, "sdh0_mux", NULL); 267 clk_register_clkdev(clk, "sdh0_mux", NULL);
262 268
@@ -265,7 +271,8 @@ void __init pxa910_clk_init(void)
265 clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); 271 clk_register_clkdev(clk, NULL, "sdhci-pxa.0");
266 272
267 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, 273 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent,
268 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT, 274 ARRAY_SIZE(sdh_parent),
275 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
269 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock); 276 apmu_base + APMU_SDH1, 6, 1, 0, &clk_lock);
270 clk_register_clkdev(clk, "sdh1_mux", NULL); 277 clk_register_clkdev(clk, "sdh1_mux", NULL);
271 278
@@ -282,7 +289,8 @@ void __init pxa910_clk_init(void)
282 clk_register_clkdev(clk, "sph_clk", NULL); 289 clk_register_clkdev(clk, "sph_clk", NULL);
283 290
284 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, 291 clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
285 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT, 292 ARRAY_SIZE(disp_parent),
293 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
286 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock); 294 apmu_base + APMU_DISP0, 6, 1, 0, &clk_lock);
287 clk_register_clkdev(clk, "disp_mux.0", NULL); 295 clk_register_clkdev(clk, "disp_mux.0", NULL);
288 296
@@ -291,7 +299,8 @@ void __init pxa910_clk_init(void)
291 clk_register_clkdev(clk, NULL, "mmp-disp.0"); 299 clk_register_clkdev(clk, NULL, "mmp-disp.0");
292 300
293 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, 301 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
294 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT, 302 ARRAY_SIZE(ccic_parent),
303 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
295 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); 304 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock);
296 clk_register_clkdev(clk, "ccic_mux.0", NULL); 305 clk_register_clkdev(clk, "ccic_mux.0", NULL);
297 306
@@ -301,8 +310,8 @@ void __init pxa910_clk_init(void)
301 310
302 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, 311 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent,
303 ARRAY_SIZE(ccic_phy_parent), 312 ARRAY_SIZE(ccic_phy_parent),
304 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, 313 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
305 7, 1, 0, &clk_lock); 314 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock);
306 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); 315 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL);
307 316
308 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", 317 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux",
diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h
index 81421e28e69c..ef10ad9b5daa 100644
--- a/drivers/clk/mxs/clk.h
+++ b/drivers/clk/mxs/clk.h
@@ -52,8 +52,8 @@ static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg,
52 u8 shift, u8 width, const char **parent_names, int num_parents) 52 u8 shift, u8 width, const char **parent_names, int num_parents)
53{ 53{
54 return clk_register_mux(NULL, name, parent_names, num_parents, 54 return clk_register_mux(NULL, name, parent_names, num_parents,
55 CLK_SET_RATE_PARENT, reg, shift, width, 55 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
56 0, &mxs_lock); 56 reg, shift, width, 0, &mxs_lock);
57} 57}
58 58
59static inline struct clk *mxs_clk_fixed_factor(const char *name, 59static inline struct clk *mxs_clk_fixed_factor(const char *name,
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 51b48daf5c8a..39b40aaede2b 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -82,11 +82,13 @@ static void __init exynos_audss_clk_init(struct device_node *np)
82 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 82 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
83 83
84 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", 84 clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
85 mout_audss_p, ARRAY_SIZE(mout_audss_p), 0, 85 mout_audss_p, ARRAY_SIZE(mout_audss_p),
86 CLK_SET_RATE_NO_REPARENT,
86 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 87 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
87 88
88 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", 89 clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
89 mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0, 90 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
91 CLK_SET_RATE_NO_REPARENT,
90 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); 92 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
91 93
92 clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp", 94 clk_table[EXYNOS_DOUT_SRP] = clk_register_divider(NULL, "dout_srp",
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index e7dfccb5d981..31b4174e7a5b 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -130,7 +130,7 @@ struct samsung_mux_clock {
130 .name = cname, \ 130 .name = cname, \
131 .parent_names = pnames, \ 131 .parent_names = pnames, \
132 .num_parents = ARRAY_SIZE(pnames), \ 132 .num_parents = ARRAY_SIZE(pnames), \
133 .flags = f, \ 133 .flags = (f) | CLK_SET_RATE_NO_REPARENT, \
134 .offset = o, \ 134 .offset = o, \
135 .shift = s, \ 135 .shift = s, \
136 .width = w, \ 136 .width = w, \
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index aedbbe12f321..65894f7687ed 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -416,9 +416,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
416 /* clock derived from 24 or 25 MHz osc clk */ 416 /* clock derived from 24 or 25 MHz osc clk */
417 /* vco-pll */ 417 /* vco-pll */
418 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, 418 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
419 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 419 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
420 SPEAR1310_PLL1_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 420 SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT,
421 &_lock); 421 SPEAR1310_PLL_CLK_MASK, 0, &_lock);
422 clk_register_clkdev(clk, "vco1_mclk", NULL); 422 clk_register_clkdev(clk, "vco1_mclk", NULL);
423 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 423 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
424 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl, 424 0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
@@ -427,9 +427,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
427 clk_register_clkdev(clk1, "pll1_clk", NULL); 427 clk_register_clkdev(clk1, "pll1_clk", NULL);
428 428
429 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, 429 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
430 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 430 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
431 SPEAR1310_PLL2_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 431 SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT,
432 &_lock); 432 SPEAR1310_PLL_CLK_MASK, 0, &_lock);
433 clk_register_clkdev(clk, "vco2_mclk", NULL); 433 clk_register_clkdev(clk, "vco2_mclk", NULL);
434 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 434 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
435 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl, 435 0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
@@ -438,9 +438,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
438 clk_register_clkdev(clk1, "pll2_clk", NULL); 438 clk_register_clkdev(clk1, "pll2_clk", NULL);
439 439
440 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, 440 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
441 ARRAY_SIZE(vco_parents), 0, SPEAR1310_PLL_CFG, 441 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
442 SPEAR1310_PLL3_CLK_SHIFT, SPEAR1310_PLL_CLK_MASK, 0, 442 SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT,
443 &_lock); 443 SPEAR1310_PLL_CLK_MASK, 0, &_lock);
444 clk_register_clkdev(clk, "vco3_mclk", NULL); 444 clk_register_clkdev(clk, "vco3_mclk", NULL);
445 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 445 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
446 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl, 446 0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
@@ -515,9 +515,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
515 515
516 /* gpt clocks */ 516 /* gpt clocks */
517 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, 517 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
518 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 518 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
519 SPEAR1310_GPT0_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 519 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT,
520 &_lock); 520 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
521 clk_register_clkdev(clk, "gpt0_mclk", NULL); 521 clk_register_clkdev(clk, "gpt0_mclk", NULL);
522 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, 522 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
523 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0, 523 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
@@ -525,9 +525,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
525 clk_register_clkdev(clk, NULL, "gpt0"); 525 clk_register_clkdev(clk, NULL, "gpt0");
526 526
527 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, 527 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
528 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 528 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
529 SPEAR1310_GPT1_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 529 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT,
530 &_lock); 530 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
531 clk_register_clkdev(clk, "gpt1_mclk", NULL); 531 clk_register_clkdev(clk, "gpt1_mclk", NULL);
532 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 532 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
533 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0, 533 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
@@ -535,9 +535,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
535 clk_register_clkdev(clk, NULL, "gpt1"); 535 clk_register_clkdev(clk, NULL, "gpt1");
536 536
537 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, 537 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
538 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 538 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
539 SPEAR1310_GPT2_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 539 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT,
540 &_lock); 540 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
541 clk_register_clkdev(clk, "gpt2_mclk", NULL); 541 clk_register_clkdev(clk, "gpt2_mclk", NULL);
542 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 542 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
543 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0, 543 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
@@ -545,9 +545,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
545 clk_register_clkdev(clk, NULL, "gpt2"); 545 clk_register_clkdev(clk, NULL, "gpt2");
546 546
547 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, 547 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
548 ARRAY_SIZE(gpt_parents), 0, SPEAR1310_PERIP_CLK_CFG, 548 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
549 SPEAR1310_GPT3_CLK_SHIFT, SPEAR1310_GPT_CLK_MASK, 0, 549 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT,
550 &_lock); 550 SPEAR1310_GPT_CLK_MASK, 0, &_lock);
551 clk_register_clkdev(clk, "gpt3_mclk", NULL); 551 clk_register_clkdev(clk, "gpt3_mclk", NULL);
552 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 552 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
553 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0, 553 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
@@ -562,7 +562,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
562 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 562 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
563 563
564 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 564 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
565 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, 565 ARRAY_SIZE(uart0_parents),
566 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
566 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT, 567 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
567 SPEAR1310_UART_CLK_MASK, 0, &_lock); 568 SPEAR1310_UART_CLK_MASK, 0, &_lock);
568 clk_register_clkdev(clk, "uart0_mclk", NULL); 569 clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -602,7 +603,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
602 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 603 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
603 604
604 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 605 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
605 ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT, 606 ARRAY_SIZE(c3_parents),
607 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
606 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT, 608 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
607 SPEAR1310_C3_CLK_MASK, 0, &_lock); 609 SPEAR1310_C3_CLK_MASK, 0, &_lock);
608 clk_register_clkdev(clk, "c3_mclk", NULL); 610 clk_register_clkdev(clk, "c3_mclk", NULL);
@@ -614,8 +616,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
614 616
615 /* gmac */ 617 /* gmac */
616 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 618 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
617 ARRAY_SIZE(gmac_phy_input_parents), 0, 619 ARRAY_SIZE(gmac_phy_input_parents),
618 SPEAR1310_GMAC_CLK_CFG, 620 CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG,
619 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT, 621 SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
620 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 622 SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
621 clk_register_clkdev(clk, "phy_input_mclk", NULL); 623 clk_register_clkdev(clk, "phy_input_mclk", NULL);
@@ -627,15 +629,16 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
627 clk_register_clkdev(clk1, "phy_syn_gclk", NULL); 629 clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
628 630
629 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, 631 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
630 ARRAY_SIZE(gmac_phy_parents), 0, 632 ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
631 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, 633 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
632 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); 634 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
633 clk_register_clkdev(clk, "stmmacphy.0", NULL); 635 clk_register_clkdev(clk, "stmmacphy.0", NULL);
634 636
635 /* clcd */ 637 /* clcd */
636 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 638 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
637 ARRAY_SIZE(clcd_synth_parents), 0, 639 ARRAY_SIZE(clcd_synth_parents),
638 SPEAR1310_CLCD_CLK_SYNT, SPEAR1310_CLCD_SYNT_CLK_SHIFT, 640 CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT,
641 SPEAR1310_CLCD_SYNT_CLK_SHIFT,
639 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock); 642 SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
640 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); 643 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
641 644
@@ -645,7 +648,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
645 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 648 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
646 649
647 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 650 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
648 ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT, 651 ARRAY_SIZE(clcd_pixel_parents),
652 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
649 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, 653 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
650 SPEAR1310_CLCD_CLK_MASK, 0, &_lock); 654 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
651 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); 655 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
@@ -657,9 +661,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
657 661
658 /* i2s */ 662 /* i2s */
659 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 663 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
660 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG, 664 ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
661 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK, 665 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT,
662 0, &_lock); 666 SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock);
663 clk_register_clkdev(clk, "i2s_src_mclk", NULL); 667 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
664 668
665 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, 669 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
@@ -668,7 +672,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
668 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 672 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
669 673
670 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 674 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
671 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, 675 ARRAY_SIZE(i2s_ref_parents),
676 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
672 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT, 677 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
673 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock); 678 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
674 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); 679 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
@@ -806,13 +811,15 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
806 811
807 /* RAS clks */ 812 /* RAS clks */
808 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, 813 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
809 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1310_PLL_CFG, 814 ARRAY_SIZE(gen_synth0_1_parents),
815 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
810 SPEAR1310_RAS_SYNT0_1_CLK_SHIFT, 816 SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
811 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 817 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
812 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); 818 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
813 819
814 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 820 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
815 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1310_PLL_CFG, 821 ARRAY_SIZE(gen_synth2_3_parents),
822 CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
816 SPEAR1310_RAS_SYNT2_3_CLK_SHIFT, 823 SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
817 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock); 824 SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
818 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); 825 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
@@ -929,8 +936,8 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
929 936
930 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", 937 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
931 smii_rgmii_phy_parents, 938 smii_rgmii_phy_parents,
932 ARRAY_SIZE(smii_rgmii_phy_parents), 0, 939 ARRAY_SIZE(smii_rgmii_phy_parents),
933 SPEAR1310_RAS_CTRL_REG1, 940 CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1,
934 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, 941 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
935 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 942 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
936 clk_register_clkdev(clk, "stmmacphy.1", NULL); 943 clk_register_clkdev(clk, "stmmacphy.1", NULL);
@@ -938,15 +945,15 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
938 clk_register_clkdev(clk, "stmmacphy.4", NULL); 945 clk_register_clkdev(clk, "stmmacphy.4", NULL);
939 946
940 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, 947 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
941 ARRAY_SIZE(rmii_phy_parents), 0, 948 ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT,
942 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, 949 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
943 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 950 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
944 clk_register_clkdev(clk, "stmmacphy.3", NULL); 951 clk_register_clkdev(clk, "stmmacphy.3", NULL);
945 952
946 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, 953 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
947 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 954 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
948 SPEAR1310_UART1_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 955 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT,
949 0, &_lock); 956 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
950 clk_register_clkdev(clk, "uart1_mclk", NULL); 957 clk_register_clkdev(clk, "uart1_mclk", NULL);
951 958
952 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, 959 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
@@ -955,9 +962,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
955 clk_register_clkdev(clk, NULL, "5c800000.serial"); 962 clk_register_clkdev(clk, NULL, "5c800000.serial");
956 963
957 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, 964 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
958 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 965 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
959 SPEAR1310_UART2_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 966 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT,
960 0, &_lock); 967 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
961 clk_register_clkdev(clk, "uart2_mclk", NULL); 968 clk_register_clkdev(clk, "uart2_mclk", NULL);
962 969
963 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, 970 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
@@ -966,9 +973,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
966 clk_register_clkdev(clk, NULL, "5c900000.serial"); 973 clk_register_clkdev(clk, NULL, "5c900000.serial");
967 974
968 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, 975 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
969 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 976 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
970 SPEAR1310_UART3_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 977 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT,
971 0, &_lock); 978 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
972 clk_register_clkdev(clk, "uart3_mclk", NULL); 979 clk_register_clkdev(clk, "uart3_mclk", NULL);
973 980
974 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, 981 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
@@ -977,9 +984,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
977 clk_register_clkdev(clk, NULL, "5ca00000.serial"); 984 clk_register_clkdev(clk, NULL, "5ca00000.serial");
978 985
979 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, 986 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
980 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 987 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
981 SPEAR1310_UART4_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 988 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT,
982 0, &_lock); 989 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
983 clk_register_clkdev(clk, "uart4_mclk", NULL); 990 clk_register_clkdev(clk, "uart4_mclk", NULL);
984 991
985 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, 992 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
@@ -988,9 +995,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
988 clk_register_clkdev(clk, NULL, "5cb00000.serial"); 995 clk_register_clkdev(clk, NULL, "5cb00000.serial");
989 996
990 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, 997 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
991 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 998 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
992 SPEAR1310_UART5_CLK_SHIFT, SPEAR1310_RAS_UART_CLK_MASK, 999 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT,
993 0, &_lock); 1000 SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
994 clk_register_clkdev(clk, "uart5_mclk", NULL); 1001 clk_register_clkdev(clk, "uart5_mclk", NULL);
995 1002
996 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, 1003 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
@@ -999,9 +1006,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
999 clk_register_clkdev(clk, NULL, "5cc00000.serial"); 1006 clk_register_clkdev(clk, NULL, "5cc00000.serial");
1000 1007
1001 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, 1008 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
1002 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1009 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1003 SPEAR1310_I2C1_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1010 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT,
1004 &_lock); 1011 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1005 clk_register_clkdev(clk, "i2c1_mclk", NULL); 1012 clk_register_clkdev(clk, "i2c1_mclk", NULL);
1006 1013
1007 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, 1014 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
@@ -1010,9 +1017,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1010 clk_register_clkdev(clk, NULL, "5cd00000.i2c"); 1017 clk_register_clkdev(clk, NULL, "5cd00000.i2c");
1011 1018
1012 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, 1019 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
1013 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1020 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1014 SPEAR1310_I2C2_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1021 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT,
1015 &_lock); 1022 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1016 clk_register_clkdev(clk, "i2c2_mclk", NULL); 1023 clk_register_clkdev(clk, "i2c2_mclk", NULL);
1017 1024
1018 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, 1025 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
@@ -1021,9 +1028,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1021 clk_register_clkdev(clk, NULL, "5ce00000.i2c"); 1028 clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1022 1029
1023 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, 1030 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
1024 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1031 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1025 SPEAR1310_I2C3_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1032 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT,
1026 &_lock); 1033 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1027 clk_register_clkdev(clk, "i2c3_mclk", NULL); 1034 clk_register_clkdev(clk, "i2c3_mclk", NULL);
1028 1035
1029 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, 1036 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
@@ -1032,9 +1039,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1032 clk_register_clkdev(clk, NULL, "5cf00000.i2c"); 1039 clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1033 1040
1034 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, 1041 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
1035 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1042 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1036 SPEAR1310_I2C4_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1043 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT,
1037 &_lock); 1044 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1038 clk_register_clkdev(clk, "i2c4_mclk", NULL); 1045 clk_register_clkdev(clk, "i2c4_mclk", NULL);
1039 1046
1040 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, 1047 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
@@ -1043,9 +1050,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1043 clk_register_clkdev(clk, NULL, "5d000000.i2c"); 1050 clk_register_clkdev(clk, NULL, "5d000000.i2c");
1044 1051
1045 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, 1052 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
1046 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1053 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1047 SPEAR1310_I2C5_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1054 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT,
1048 &_lock); 1055 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1049 clk_register_clkdev(clk, "i2c5_mclk", NULL); 1056 clk_register_clkdev(clk, "i2c5_mclk", NULL);
1050 1057
1051 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, 1058 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
@@ -1054,9 +1061,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1054 clk_register_clkdev(clk, NULL, "5d100000.i2c"); 1061 clk_register_clkdev(clk, NULL, "5d100000.i2c");
1055 1062
1056 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, 1063 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
1057 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1064 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1058 SPEAR1310_I2C6_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1065 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT,
1059 &_lock); 1066 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1060 clk_register_clkdev(clk, "i2c6_mclk", NULL); 1067 clk_register_clkdev(clk, "i2c6_mclk", NULL);
1061 1068
1062 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, 1069 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
@@ -1065,9 +1072,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1065 clk_register_clkdev(clk, NULL, "5d200000.i2c"); 1072 clk_register_clkdev(clk, NULL, "5d200000.i2c");
1066 1073
1067 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, 1074 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
1068 ARRAY_SIZE(i2c_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1075 ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1069 SPEAR1310_I2C7_CLK_SHIFT, SPEAR1310_I2C_CLK_MASK, 0, 1076 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT,
1070 &_lock); 1077 SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1071 clk_register_clkdev(clk, "i2c7_mclk", NULL); 1078 clk_register_clkdev(clk, "i2c7_mclk", NULL);
1072 1079
1073 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, 1080 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
@@ -1076,9 +1083,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1076 clk_register_clkdev(clk, NULL, "5d300000.i2c"); 1083 clk_register_clkdev(clk, NULL, "5d300000.i2c");
1077 1084
1078 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, 1085 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
1079 ARRAY_SIZE(ssp1_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1086 ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT,
1080 SPEAR1310_SSP1_CLK_SHIFT, SPEAR1310_SSP1_CLK_MASK, 0, 1087 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT,
1081 &_lock); 1088 SPEAR1310_SSP1_CLK_MASK, 0, &_lock);
1082 clk_register_clkdev(clk, "ssp1_mclk", NULL); 1089 clk_register_clkdev(clk, "ssp1_mclk", NULL);
1083 1090
1084 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, 1091 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
@@ -1087,9 +1094,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1087 clk_register_clkdev(clk, NULL, "5d400000.spi"); 1094 clk_register_clkdev(clk, NULL, "5d400000.spi");
1088 1095
1089 clk = clk_register_mux(NULL, "pci_mclk", pci_parents, 1096 clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
1090 ARRAY_SIZE(pci_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1097 ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT,
1091 SPEAR1310_PCI_CLK_SHIFT, SPEAR1310_PCI_CLK_MASK, 0, 1098 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT,
1092 &_lock); 1099 SPEAR1310_PCI_CLK_MASK, 0, &_lock);
1093 clk_register_clkdev(clk, "pci_mclk", NULL); 1100 clk_register_clkdev(clk, "pci_mclk", NULL);
1094 1101
1095 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, 1102 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
@@ -1098,9 +1105,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1098 clk_register_clkdev(clk, NULL, "pci"); 1105 clk_register_clkdev(clk, NULL, "pci");
1099 1106
1100 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, 1107 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
1101 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1108 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1102 SPEAR1310_TDM1_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, 1109 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT,
1103 &_lock); 1110 SPEAR1310_TDM_CLK_MASK, 0, &_lock);
1104 clk_register_clkdev(clk, "tdm1_mclk", NULL); 1111 clk_register_clkdev(clk, "tdm1_mclk", NULL);
1105 1112
1106 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, 1113 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
@@ -1109,9 +1116,9 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
1109 clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); 1116 clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1110 1117
1111 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, 1118 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
1112 ARRAY_SIZE(tdm_parents), 0, SPEAR1310_RAS_CTRL_REG0, 1119 ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1113 SPEAR1310_TDM2_CLK_SHIFT, SPEAR1310_TDM_CLK_MASK, 0, 1120 SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT,
1114 &_lock); 1121 SPEAR1310_TDM_CLK_MASK, 0, &_lock);
1115 clk_register_clkdev(clk, "tdm2_mclk", NULL); 1122 clk_register_clkdev(clk, "tdm2_mclk", NULL);
1116 1123
1117 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, 1124 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 9d0b3949db30..fe835c1845fe 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -473,9 +473,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
473 /* clock derived from 24 or 25 MHz osc clk */ 473 /* clock derived from 24 or 25 MHz osc clk */
474 /* vco-pll */ 474 /* vco-pll */
475 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, 475 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
476 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 476 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
477 SPEAR1340_PLL1_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 477 SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT,
478 &_lock); 478 SPEAR1340_PLL_CLK_MASK, 0, &_lock);
479 clk_register_clkdev(clk, "vco1_mclk", NULL); 479 clk_register_clkdev(clk, "vco1_mclk", NULL);
480 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0, 480 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
481 SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl, 481 SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
@@ -484,9 +484,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
484 clk_register_clkdev(clk1, "pll1_clk", NULL); 484 clk_register_clkdev(clk1, "pll1_clk", NULL);
485 485
486 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, 486 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
487 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 487 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
488 SPEAR1340_PLL2_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 488 SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT,
489 &_lock); 489 SPEAR1340_PLL_CLK_MASK, 0, &_lock);
490 clk_register_clkdev(clk, "vco2_mclk", NULL); 490 clk_register_clkdev(clk, "vco2_mclk", NULL);
491 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0, 491 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
492 SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl, 492 SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
@@ -495,9 +495,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
495 clk_register_clkdev(clk1, "pll2_clk", NULL); 495 clk_register_clkdev(clk1, "pll2_clk", NULL);
496 496
497 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, 497 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
498 ARRAY_SIZE(vco_parents), 0, SPEAR1340_PLL_CFG, 498 ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
499 SPEAR1340_PLL3_CLK_SHIFT, SPEAR1340_PLL_CLK_MASK, 0, 499 SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT,
500 &_lock); 500 SPEAR1340_PLL_CLK_MASK, 0, &_lock);
501 clk_register_clkdev(clk, "vco3_mclk", NULL); 501 clk_register_clkdev(clk, "vco3_mclk", NULL);
502 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0, 502 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
503 SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl, 503 SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
@@ -561,8 +561,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
561 clk_register_clkdev(clk, "amba_syn_clk", NULL); 561 clk_register_clkdev(clk, "amba_syn_clk", NULL);
562 562
563 clk = clk_register_mux(NULL, "sys_mclk", sys_parents, 563 clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
564 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL, 564 ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT,
565 SPEAR1340_SCLK_SRC_SEL_SHIFT, 565 SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT,
566 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock); 566 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
567 clk_register_clkdev(clk, "sys_mclk", NULL); 567 clk_register_clkdev(clk, "sys_mclk", NULL);
568 568
@@ -583,8 +583,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
583 clk_register_clkdev(clk, NULL, "smp_twd"); 583 clk_register_clkdev(clk, NULL, "smp_twd");
584 584
585 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents, 585 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
586 ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL, 586 ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT,
587 SPEAR1340_HCLK_SRC_SEL_SHIFT, 587 SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT,
588 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock); 588 SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
589 clk_register_clkdev(clk, "ahb_clk", NULL); 589 clk_register_clkdev(clk, "ahb_clk", NULL);
590 590
@@ -594,9 +594,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
594 594
595 /* gpt clocks */ 595 /* gpt clocks */
596 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, 596 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
597 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 597 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
598 SPEAR1340_GPT0_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 598 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT,
599 &_lock); 599 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
600 clk_register_clkdev(clk, "gpt0_mclk", NULL); 600 clk_register_clkdev(clk, "gpt0_mclk", NULL);
601 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, 601 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
602 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0, 602 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
@@ -604,9 +604,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
604 clk_register_clkdev(clk, NULL, "gpt0"); 604 clk_register_clkdev(clk, NULL, "gpt0");
605 605
606 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, 606 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
607 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 607 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
608 SPEAR1340_GPT1_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 608 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT,
609 &_lock); 609 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
610 clk_register_clkdev(clk, "gpt1_mclk", NULL); 610 clk_register_clkdev(clk, "gpt1_mclk", NULL);
611 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 611 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
612 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0, 612 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
@@ -614,9 +614,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
614 clk_register_clkdev(clk, NULL, "gpt1"); 614 clk_register_clkdev(clk, NULL, "gpt1");
615 615
616 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, 616 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
617 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 617 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
618 SPEAR1340_GPT2_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 618 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT,
619 &_lock); 619 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
620 clk_register_clkdev(clk, "gpt2_mclk", NULL); 620 clk_register_clkdev(clk, "gpt2_mclk", NULL);
621 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 621 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
622 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0, 622 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
@@ -624,9 +624,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
624 clk_register_clkdev(clk, NULL, "gpt2"); 624 clk_register_clkdev(clk, NULL, "gpt2");
625 625
626 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, 626 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
627 ARRAY_SIZE(gpt_parents), 0, SPEAR1340_PERIP_CLK_CFG, 627 ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
628 SPEAR1340_GPT3_CLK_SHIFT, SPEAR1340_GPT_CLK_MASK, 0, 628 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT,
629 &_lock); 629 SPEAR1340_GPT_CLK_MASK, 0, &_lock);
630 clk_register_clkdev(clk, "gpt3_mclk", NULL); 630 clk_register_clkdev(clk, "gpt3_mclk", NULL);
631 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 631 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
632 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0, 632 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
@@ -641,7 +641,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
641 clk_register_clkdev(clk1, "uart0_syn_gclk", NULL); 641 clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
642 642
643 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 643 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
644 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, 644 ARRAY_SIZE(uart0_parents),
645 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
645 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT, 646 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT,
646 SPEAR1340_UART_CLK_MASK, 0, &_lock); 647 SPEAR1340_UART_CLK_MASK, 0, &_lock);
647 clk_register_clkdev(clk, "uart0_mclk", NULL); 648 clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -658,9 +659,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
658 clk_register_clkdev(clk1, "uart1_syn_gclk", NULL); 659 clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
659 660
660 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents, 661 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
661 ARRAY_SIZE(uart1_parents), 0, SPEAR1340_PERIP_CLK_CFG, 662 ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT,
662 SPEAR1340_UART1_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0, 663 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT,
663 &_lock); 664 SPEAR1340_UART_CLK_MASK, 0, &_lock);
664 clk_register_clkdev(clk, "uart1_mclk", NULL); 665 clk_register_clkdev(clk, "uart1_mclk", NULL);
665 666
666 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, 667 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
@@ -698,7 +699,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
698 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 699 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
699 700
700 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 701 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
701 ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT, 702 ARRAY_SIZE(c3_parents),
703 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
702 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT, 704 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT,
703 SPEAR1340_C3_CLK_MASK, 0, &_lock); 705 SPEAR1340_C3_CLK_MASK, 0, &_lock);
704 clk_register_clkdev(clk, "c3_mclk", NULL); 706 clk_register_clkdev(clk, "c3_mclk", NULL);
@@ -710,8 +712,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
710 712
711 /* gmac */ 713 /* gmac */
712 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 714 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
713 ARRAY_SIZE(gmac_phy_input_parents), 0, 715 ARRAY_SIZE(gmac_phy_input_parents),
714 SPEAR1340_GMAC_CLK_CFG, 716 CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG,
715 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT, 717 SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
716 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock); 718 SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
717 clk_register_clkdev(clk, "phy_input_mclk", NULL); 719 clk_register_clkdev(clk, "phy_input_mclk", NULL);
@@ -723,15 +725,16 @@ void __init spear1340_clk_init(void __iomem *misc_base)
723 clk_register_clkdev(clk1, "phy_syn_gclk", NULL); 725 clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
724 726
725 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, 727 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
726 ARRAY_SIZE(gmac_phy_parents), 0, 728 ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
727 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT, 729 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
728 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock); 730 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
729 clk_register_clkdev(clk, "stmmacphy.0", NULL); 731 clk_register_clkdev(clk, "stmmacphy.0", NULL);
730 732
731 /* clcd */ 733 /* clcd */
732 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 734 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
733 ARRAY_SIZE(clcd_synth_parents), 0, 735 ARRAY_SIZE(clcd_synth_parents),
734 SPEAR1340_CLCD_CLK_SYNT, SPEAR1340_CLCD_SYNT_CLK_SHIFT, 736 CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT,
737 SPEAR1340_CLCD_SYNT_CLK_SHIFT,
735 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock); 738 SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
736 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); 739 clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
737 740
@@ -741,7 +744,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
741 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 744 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
742 745
743 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 746 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
744 ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT, 747 ARRAY_SIZE(clcd_pixel_parents),
748 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
745 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT, 749 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
746 SPEAR1340_CLCD_CLK_MASK, 0, &_lock); 750 SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
747 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); 751 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
@@ -753,9 +757,9 @@ void __init spear1340_clk_init(void __iomem *misc_base)
753 757
754 /* i2s */ 758 /* i2s */
755 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 759 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
756 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG, 760 ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
757 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK, 761 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT,
758 0, &_lock); 762 SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock);
759 clk_register_clkdev(clk, "i2s_src_mclk", NULL); 763 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
760 764
761 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 765 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
@@ -765,7 +769,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
765 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 769 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
766 770
767 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 771 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
768 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, 772 ARRAY_SIZE(i2s_ref_parents),
773 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
769 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT, 774 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT,
770 SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock); 775 SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock);
771 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); 776 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
@@ -891,13 +896,15 @@ void __init spear1340_clk_init(void __iomem *misc_base)
891 896
892 /* RAS clks */ 897 /* RAS clks */
893 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, 898 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
894 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1340_PLL_CFG, 899 ARRAY_SIZE(gen_synth0_1_parents),
900 CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
895 SPEAR1340_GEN_SYNT0_1_CLK_SHIFT, 901 SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
896 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 902 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
897 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL); 903 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
898 904
899 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 905 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
900 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1340_PLL_CFG, 906 ARRAY_SIZE(gen_synth2_3_parents),
907 CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
901 SPEAR1340_GEN_SYNT2_3_CLK_SHIFT, 908 SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
902 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 909 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
903 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL); 910 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
@@ -938,7 +945,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
938 clk_register_clkdev(clk, NULL, "spear_cec.1"); 945 clk_register_clkdev(clk, NULL, "spear_cec.1");
939 946
940 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents, 947 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
941 ARRAY_SIZE(spdif_out_parents), CLK_SET_RATE_PARENT, 948 ARRAY_SIZE(spdif_out_parents),
949 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
942 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT, 950 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
943 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 951 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
944 clk_register_clkdev(clk, "spdif_out_mclk", NULL); 952 clk_register_clkdev(clk, "spdif_out_mclk", NULL);
@@ -949,7 +957,8 @@ void __init spear1340_clk_init(void __iomem *misc_base)
949 clk_register_clkdev(clk, NULL, "d0000000.spdif-out"); 957 clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
950 958
951 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents, 959 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
952 ARRAY_SIZE(spdif_in_parents), CLK_SET_RATE_PARENT, 960 ARRAY_SIZE(spdif_in_parents),
961 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
953 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT, 962 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
954 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 963 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
955 clk_register_clkdev(clk, "spdif_in_mclk", NULL); 964 clk_register_clkdev(clk, "spdif_in_mclk", NULL);
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index 080c3c5e33f6..c2d204315546 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -294,7 +294,8 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
294 clk_register_clkdev(clk, NULL, "a9400000.i2s"); 294 clk_register_clkdev(clk, NULL, "a9400000.i2s");
295 295
296 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, 296 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
297 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT, 297 ARRAY_SIZE(i2s_ref_parents),
298 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
298 SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT, 299 SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
299 I2S_REF_PCLK_MASK, 0, &_lock); 300 I2S_REF_PCLK_MASK, 0, &_lock);
300 clk_register_clkdev(clk, "i2s_ref_clk", NULL); 301 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
@@ -313,57 +314,66 @@ static void __init spear320_clk_init(void __iomem *soc_config_base)
313 clk_register_clkdev(clk, "hclk", "ab000000.eth"); 314 clk_register_clkdev(clk, "hclk", "ab000000.eth");
314 315
315 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, 316 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
316 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 317 ARRAY_SIZE(uartx_parents),
318 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
317 SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT, 319 SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
318 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 320 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
319 clk_register_clkdev(clk, NULL, "a9300000.serial"); 321 clk_register_clkdev(clk, NULL, "a9300000.serial");
320 322
321 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, 323 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
322 ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT, 324 ARRAY_SIZE(sdhci_parents),
325 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
323 SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 326 SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
324 0, &_lock); 327 0, &_lock);
325 clk_register_clkdev(clk, NULL, "70000000.sdhci"); 328 clk_register_clkdev(clk, NULL, "70000000.sdhci");
326 329
327 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, 330 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
328 ARRAY_SIZE(smii0_parents), 0, SPEAR320_CONTROL_REG, 331 ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT,
329 SMII_PCLK_SHIFT, SMII_PCLK_MASK, 0, &_lock); 332 SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK,
333 0, &_lock);
330 clk_register_clkdev(clk, NULL, "smii_pclk"); 334 clk_register_clkdev(clk, NULL, "smii_pclk");
331 335
332 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1); 336 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
333 clk_register_clkdev(clk, NULL, "smii"); 337 clk_register_clkdev(clk, NULL, "smii");
334 338
335 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, 339 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
336 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 340 ARRAY_SIZE(uartx_parents),
341 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
337 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK, 342 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
338 0, &_lock); 343 0, &_lock);
339 clk_register_clkdev(clk, NULL, "a3000000.serial"); 344 clk_register_clkdev(clk, NULL, "a3000000.serial");
340 345
341 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, 346 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
342 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 347 ARRAY_SIZE(uartx_parents),
348 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
343 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT, 349 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
344 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 350 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
345 clk_register_clkdev(clk, NULL, "a4000000.serial"); 351 clk_register_clkdev(clk, NULL, "a4000000.serial");
346 352
347 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, 353 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
348 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 354 ARRAY_SIZE(uartx_parents),
355 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
349 SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT, 356 SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
350 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 357 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
351 clk_register_clkdev(clk, NULL, "a9100000.serial"); 358 clk_register_clkdev(clk, NULL, "a9100000.serial");
352 359
353 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, 360 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
354 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 361 ARRAY_SIZE(uartx_parents),
362 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
355 SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT, 363 SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
356 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 364 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
357 clk_register_clkdev(clk, NULL, "a9200000.serial"); 365 clk_register_clkdev(clk, NULL, "a9200000.serial");
358 366
359 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, 367 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
360 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 368 ARRAY_SIZE(uartx_parents),
369 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
361 SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT, 370 SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
362 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 371 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
363 clk_register_clkdev(clk, NULL, "60000000.serial"); 372 clk_register_clkdev(clk, NULL, "60000000.serial");
364 373
365 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, 374 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
366 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT, 375 ARRAY_SIZE(uartx_parents),
376 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
367 SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT, 377 SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
368 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 378 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
369 clk_register_clkdev(clk, NULL, "60100000.serial"); 379 clk_register_clkdev(clk, NULL, "60100000.serial");
@@ -427,7 +437,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
427 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 437 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
428 438
429 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 439 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
430 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT, 440 ARRAY_SIZE(uart0_parents),
441 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
431 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, 442 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
432 &_lock); 443 &_lock);
433 clk_register_clkdev(clk, "uart0_mclk", NULL); 444 clk_register_clkdev(clk, "uart0_mclk", NULL);
@@ -444,7 +455,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
444 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); 455 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
445 456
446 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, 457 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
447 ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT, 458 ARRAY_SIZE(firda_parents),
459 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
448 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, 460 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
449 &_lock); 461 &_lock);
450 clk_register_clkdev(clk, "firda_mclk", NULL); 462 clk_register_clkdev(clk, "firda_mclk", NULL);
@@ -458,14 +470,16 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
458 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, 470 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
459 ARRAY_SIZE(gpt_rtbl), &_lock); 471 ARRAY_SIZE(gpt_rtbl), &_lock);
460 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, 472 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
461 ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT, 473 ARRAY_SIZE(gpt0_parents),
474 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
462 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 475 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
463 clk_register_clkdev(clk, NULL, "gpt0"); 476 clk_register_clkdev(clk, NULL, "gpt0");
464 477
465 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, 478 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
466 ARRAY_SIZE(gpt_rtbl), &_lock); 479 ARRAY_SIZE(gpt_rtbl), &_lock);
467 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, 480 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
468 ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT, 481 ARRAY_SIZE(gpt1_parents),
482 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
469 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 483 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
470 clk_register_clkdev(clk, "gpt1_mclk", NULL); 484 clk_register_clkdev(clk, "gpt1_mclk", NULL);
471 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 485 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
@@ -476,7 +490,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
476 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, 490 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
477 ARRAY_SIZE(gpt_rtbl), &_lock); 491 ARRAY_SIZE(gpt_rtbl), &_lock);
478 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, 492 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
479 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT, 493 ARRAY_SIZE(gpt2_parents),
494 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
480 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 495 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
481 clk_register_clkdev(clk, "gpt2_mclk", NULL); 496 clk_register_clkdev(clk, "gpt2_mclk", NULL);
482 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 497 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
@@ -498,9 +513,9 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
498 clk_register_clkdev(clk1, "gen1_syn_gclk", NULL); 513 clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
499 514
500 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents, 515 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
501 ARRAY_SIZE(gen2_3_parents), 0, CORE_CLK_CFG, 516 ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT,
502 GEN_SYNTH2_3_CLK_SHIFT, GEN_SYNTH2_3_CLK_MASK, 0, 517 CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT,
503 &_lock); 518 GEN_SYNTH2_3_CLK_MASK, 0, &_lock);
504 clk_register_clkdev(clk, "gen2_3_par_clk", NULL); 519 clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
505 520
506 clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk", 521 clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
@@ -540,8 +555,8 @@ void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_
540 clk_register_clkdev(clk, "ahbmult2_clk", NULL); 555 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
541 556
542 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, 557 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
543 ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, 558 ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
544 MCTR_CLK_MASK, 0, &_lock); 559 PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
545 clk_register_clkdev(clk, "ddr_clk", NULL); 560 clk_register_clkdev(clk, "ddr_clk", NULL);
546 561
547 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", 562 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index 9406f2426d64..4f649c9cb094 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -169,8 +169,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
169 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 169 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
170 170
171 clk = clk_register_mux(NULL, "uart_mclk", uart_parents, 171 clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
172 ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG, 172 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
173 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); 173 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
174 &_lock);
174 clk_register_clkdev(clk, "uart_mclk", NULL); 175 clk_register_clkdev(clk, "uart_mclk", NULL);
175 176
176 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB, 177 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
@@ -188,8 +189,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
188 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); 189 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
189 190
190 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, 191 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
191 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, 192 ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
192 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); 193 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
194 &_lock);
193 clk_register_clkdev(clk, "firda_mclk", NULL); 195 clk_register_clkdev(clk, "firda_mclk", NULL);
194 196
195 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, 197 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
@@ -203,8 +205,9 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
203 clk_register_clkdev(clk1, "clcd_syn_gclk", NULL); 205 clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
204 206
205 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents, 207 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
206 ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG, 208 ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
207 CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock); 209 PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
210 &_lock);
208 clk_register_clkdev(clk, "clcd_mclk", NULL); 211 clk_register_clkdev(clk, "clcd_mclk", NULL);
209 212
210 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, 213 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
@@ -217,13 +220,13 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
217 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL); 220 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
218 221
219 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents, 222 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
220 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, 223 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
221 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 224 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
222 clk_register_clkdev(clk, NULL, "gpt0"); 225 clk_register_clkdev(clk, NULL, "gpt0");
223 226
224 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents, 227 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
225 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, 228 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
226 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 229 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
227 clk_register_clkdev(clk, "gpt1_mclk", NULL); 230 clk_register_clkdev(clk, "gpt1_mclk", NULL);
228 231
229 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 232 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
@@ -235,8 +238,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
235 clk_register_clkdev(clk, "gpt2_syn_clk", NULL); 238 clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
236 239
237 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, 240 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
238 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, 241 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
239 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 242 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
240 clk_register_clkdev(clk, "gpt2_mclk", NULL); 243 clk_register_clkdev(clk, "gpt2_mclk", NULL);
241 244
242 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 245 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
@@ -248,8 +251,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
248 clk_register_clkdev(clk, "gpt3_syn_clk", NULL); 251 clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
249 252
250 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents, 253 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
251 ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG, 254 ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
252 GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 255 PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
253 clk_register_clkdev(clk, "gpt3_mclk", NULL); 256 clk_register_clkdev(clk, "gpt3_mclk", NULL);
254 257
255 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 258 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
@@ -277,8 +280,8 @@ void __init spear6xx_clk_init(void __iomem *misc_base)
277 clk_register_clkdev(clk, "ahbmult2_clk", NULL); 280 clk_register_clkdev(clk, "ahbmult2_clk", NULL);
278 281
279 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, 282 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
280 ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, 283 ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
281 MCTR_CLK_MASK, 0, &_lock); 284 PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
282 clk_register_clkdev(clk, "ddr_clk", NULL); 285 clk_register_clkdev(clk, "ddr_clk", NULL);
283 286
284 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", 287 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 02e440beb3d3..323830465d13 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -261,7 +261,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
261 while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL) 261 while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
262 i++; 262 i++;
263 263
264 clk = clk_register_mux(NULL, clk_name, parents, i, 0, reg, 264 clk = clk_register_mux(NULL, clk_name, parents, i,
265 CLK_SET_RATE_NO_REPARENT, reg,
265 data->shift, SUNXI_MUX_GATE_WIDTH, 266 data->shift, SUNXI_MUX_GATE_WIDTH,
266 0, &clk_lock); 267 0, &clk_lock);
267 268
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 2d3b3dc5c1ec..be40856a6fa4 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1558,7 +1558,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1558 1558
1559 /* audio0 */ 1559 /* audio0 */
1560 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1560 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1561 ARRAY_SIZE(mux_audio_sync_clk), 0, 1561 ARRAY_SIZE(mux_audio_sync_clk),
1562 CLK_SET_RATE_NO_REPARENT,
1562 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, 1563 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1563 NULL); 1564 NULL);
1564 clks[audio0_mux] = clk; 1565 clks[audio0_mux] = clk;
@@ -1570,7 +1571,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1570 1571
1571 /* audio1 */ 1572 /* audio1 */
1572 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1573 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1573 ARRAY_SIZE(mux_audio_sync_clk), 0, 1574 ARRAY_SIZE(mux_audio_sync_clk),
1575 CLK_SET_RATE_NO_REPARENT,
1574 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, 1576 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1575 NULL); 1577 NULL);
1576 clks[audio1_mux] = clk; 1578 clks[audio1_mux] = clk;
@@ -1582,7 +1584,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1582 1584
1583 /* audio2 */ 1585 /* audio2 */
1584 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1586 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1585 ARRAY_SIZE(mux_audio_sync_clk), 0, 1587 ARRAY_SIZE(mux_audio_sync_clk),
1588 CLK_SET_RATE_NO_REPARENT,
1586 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, 1589 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1587 NULL); 1590 NULL);
1588 clks[audio2_mux] = clk; 1591 clks[audio2_mux] = clk;
@@ -1594,7 +1597,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1594 1597
1595 /* audio3 */ 1598 /* audio3 */
1596 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1599 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1597 ARRAY_SIZE(mux_audio_sync_clk), 0, 1600 ARRAY_SIZE(mux_audio_sync_clk),
1601 CLK_SET_RATE_NO_REPARENT,
1598 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, 1602 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1599 NULL); 1603 NULL);
1600 clks[audio3_mux] = clk; 1604 clks[audio3_mux] = clk;
@@ -1606,7 +1610,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1606 1610
1607 /* audio4 */ 1611 /* audio4 */
1608 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1612 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1609 ARRAY_SIZE(mux_audio_sync_clk), 0, 1613 ARRAY_SIZE(mux_audio_sync_clk),
1614 CLK_SET_RATE_NO_REPARENT,
1610 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, 1615 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1611 NULL); 1616 NULL);
1612 clks[audio4_mux] = clk; 1617 clks[audio4_mux] = clk;
@@ -1618,7 +1623,8 @@ static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1618 1623
1619 /* spdif */ 1624 /* spdif */
1620 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1625 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1621 ARRAY_SIZE(mux_audio_sync_clk), 0, 1626 ARRAY_SIZE(mux_audio_sync_clk),
1627 CLK_SET_RATE_NO_REPARENT,
1622 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, 1628 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1623 NULL); 1629 NULL);
1624 clks[spdif_mux] = clk; 1630 clks[spdif_mux] = clk;
@@ -1713,7 +1719,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1713 1719
1714 /* clk_out_1 */ 1720 /* clk_out_1 */
1715 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1721 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1716 ARRAY_SIZE(clk_out1_parents), 0, 1722 ARRAY_SIZE(clk_out1_parents),
1723 CLK_SET_RATE_NO_REPARENT,
1717 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1724 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1718 &clk_out_lock); 1725 &clk_out_lock);
1719 clks[clk_out_1_mux] = clk; 1726 clks[clk_out_1_mux] = clk;
@@ -1725,7 +1732,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1725 1732
1726 /* clk_out_2 */ 1733 /* clk_out_2 */
1727 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1734 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1728 ARRAY_SIZE(clk_out2_parents), 0, 1735 ARRAY_SIZE(clk_out2_parents),
1736 CLK_SET_RATE_NO_REPARENT,
1729 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1737 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1730 &clk_out_lock); 1738 &clk_out_lock);
1731 clks[clk_out_2_mux] = clk; 1739 clks[clk_out_2_mux] = clk;
@@ -1737,7 +1745,8 @@ static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1737 1745
1738 /* clk_out_3 */ 1746 /* clk_out_3 */
1739 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1747 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1740 ARRAY_SIZE(clk_out3_parents), 0, 1748 ARRAY_SIZE(clk_out3_parents),
1749 CLK_SET_RATE_NO_REPARENT,
1741 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1750 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1742 &clk_out_lock); 1751 &clk_out_lock);
1743 clks[clk_out_3_mux] = clk; 1752 clks[clk_out_3_mux] = clk;
@@ -2055,7 +2064,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2055 2064
2056 /* dsia */ 2065 /* dsia */
2057 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0, 2066 clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
2058 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 2067 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2068 CLK_SET_RATE_NO_REPARENT,
2059 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); 2069 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock);
2060 clks[dsia_mux] = clk; 2070 clks[dsia_mux] = clk;
2061 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, 2071 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base,
@@ -2065,7 +2075,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2065 2075
2066 /* dsib */ 2076 /* dsib */
2067 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0, 2077 clk = clk_register_mux(NULL, "dsib_mux", mux_plld_out0_plld2_out0,
2068 ARRAY_SIZE(mux_plld_out0_plld2_out0), 0, 2078 ARRAY_SIZE(mux_plld_out0_plld2_out0),
2079 CLK_SET_RATE_NO_REPARENT,
2069 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); 2080 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock);
2070 clks[dsib_mux] = clk; 2081 clks[dsib_mux] = clk;
2071 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, 2082 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base,
@@ -2102,7 +2113,8 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
2102 2113
2103 /* emc */ 2114 /* emc */
2104 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2115 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
2105 ARRAY_SIZE(mux_pllmcp_clkm), 0, 2116 ARRAY_SIZE(mux_pllmcp_clkm),
2117 CLK_SET_RATE_NO_REPARENT,
2106 clk_base + CLK_SOURCE_EMC, 2118 clk_base + CLK_SOURCE_EMC,
2107 29, 3, 0, NULL); 2119 29, 3, 0, NULL);
2108 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 2120 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base,
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index ebe94ce0f647..056f649d0d89 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -778,7 +778,8 @@ static void __init tegra20_audio_clk_init(void)
778 778
779 /* audio */ 779 /* audio */
780 clk = clk_register_mux(NULL, "audio_mux", audio_parents, 780 clk = clk_register_mux(NULL, "audio_mux", audio_parents,
781 ARRAY_SIZE(audio_parents), 0, 781 ARRAY_SIZE(audio_parents),
782 CLK_SET_RATE_NO_REPARENT,
782 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL); 783 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
783 clk = clk_register_gate(NULL, "audio", "audio_mux", 0, 784 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
784 clk_base + AUDIO_SYNC_CLK, 4, 785 clk_base + AUDIO_SYNC_CLK, 4,
@@ -941,7 +942,8 @@ static void __init tegra20_periph_clk_init(void)
941 942
942 /* emc */ 943 /* emc */
943 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 944 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
944 ARRAY_SIZE(mux_pllmcp_clkm), 0, 945 ARRAY_SIZE(mux_pllmcp_clkm),
946 CLK_SET_RATE_NO_REPARENT,
945 clk_base + CLK_SOURCE_EMC, 947 clk_base + CLK_SOURCE_EMC,
946 30, 2, 0, NULL); 948 30, 2, 0, NULL);
947 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 949 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index ab35040231cd..b09ebf64cdc8 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1026,7 +1026,8 @@ static void __init tegra30_pll_init(void)
1026 1026
1027 /* PLLE */ 1027 /* PLLE */
1028 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents, 1028 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
1029 ARRAY_SIZE(pll_e_parents), 0, 1029 ARRAY_SIZE(pll_e_parents),
1030 CLK_SET_RATE_NO_REPARENT,
1030 clk_base + PLLE_AUX, 2, 1, 0, NULL); 1031 clk_base + PLLE_AUX, 2, 1, 0, NULL);
1031 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, 1032 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1032 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params, 1033 CLK_GET_RATE_NOCACHE, 100000000, &pll_e_params,
@@ -1086,7 +1087,8 @@ static void __init tegra30_audio_clk_init(void)
1086 1087
1087 /* audio0 */ 1088 /* audio0 */
1088 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk, 1089 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1089 ARRAY_SIZE(mux_audio_sync_clk), 0, 1090 ARRAY_SIZE(mux_audio_sync_clk),
1091 CLK_SET_RATE_NO_REPARENT,
1090 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL); 1092 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0, NULL);
1091 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0, 1093 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1092 clk_base + AUDIO_SYNC_CLK_I2S0, 4, 1094 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
@@ -1096,7 +1098,8 @@ static void __init tegra30_audio_clk_init(void)
1096 1098
1097 /* audio1 */ 1099 /* audio1 */
1098 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk, 1100 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1099 ARRAY_SIZE(mux_audio_sync_clk), 0, 1101 ARRAY_SIZE(mux_audio_sync_clk),
1102 CLK_SET_RATE_NO_REPARENT,
1100 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL); 1103 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0, NULL);
1101 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0, 1104 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1102 clk_base + AUDIO_SYNC_CLK_I2S1, 4, 1105 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
@@ -1106,7 +1109,8 @@ static void __init tegra30_audio_clk_init(void)
1106 1109
1107 /* audio2 */ 1110 /* audio2 */
1108 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk, 1111 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1109 ARRAY_SIZE(mux_audio_sync_clk), 0, 1112 ARRAY_SIZE(mux_audio_sync_clk),
1113 CLK_SET_RATE_NO_REPARENT,
1110 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL); 1114 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0, NULL);
1111 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0, 1115 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1112 clk_base + AUDIO_SYNC_CLK_I2S2, 4, 1116 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
@@ -1116,7 +1120,8 @@ static void __init tegra30_audio_clk_init(void)
1116 1120
1117 /* audio3 */ 1121 /* audio3 */
1118 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk, 1122 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1119 ARRAY_SIZE(mux_audio_sync_clk), 0, 1123 ARRAY_SIZE(mux_audio_sync_clk),
1124 CLK_SET_RATE_NO_REPARENT,
1120 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL); 1125 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0, NULL);
1121 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0, 1126 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1122 clk_base + AUDIO_SYNC_CLK_I2S3, 4, 1127 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
@@ -1126,7 +1131,8 @@ static void __init tegra30_audio_clk_init(void)
1126 1131
1127 /* audio4 */ 1132 /* audio4 */
1128 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk, 1133 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1129 ARRAY_SIZE(mux_audio_sync_clk), 0, 1134 ARRAY_SIZE(mux_audio_sync_clk),
1135 CLK_SET_RATE_NO_REPARENT,
1130 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL); 1136 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0, NULL);
1131 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0, 1137 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1132 clk_base + AUDIO_SYNC_CLK_I2S4, 4, 1138 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
@@ -1136,7 +1142,8 @@ static void __init tegra30_audio_clk_init(void)
1136 1142
1137 /* spdif */ 1143 /* spdif */
1138 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk, 1144 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1139 ARRAY_SIZE(mux_audio_sync_clk), 0, 1145 ARRAY_SIZE(mux_audio_sync_clk),
1146 CLK_SET_RATE_NO_REPARENT,
1140 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL); 1147 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0, NULL);
1141 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0, 1148 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1142 clk_base + AUDIO_SYNC_CLK_SPDIF, 4, 1149 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
@@ -1229,7 +1236,8 @@ static void __init tegra30_pmc_clk_init(void)
1229 1236
1230 /* clk_out_1 */ 1237 /* clk_out_1 */
1231 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents, 1238 clk = clk_register_mux(NULL, "clk_out_1_mux", clk_out1_parents,
1232 ARRAY_SIZE(clk_out1_parents), 0, 1239 ARRAY_SIZE(clk_out1_parents),
1240 CLK_SET_RATE_NO_REPARENT,
1233 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0, 1241 pmc_base + PMC_CLK_OUT_CNTRL, 6, 3, 0,
1234 &clk_out_lock); 1242 &clk_out_lock);
1235 clks[clk_out_1_mux] = clk; 1243 clks[clk_out_1_mux] = clk;
@@ -1241,7 +1249,8 @@ static void __init tegra30_pmc_clk_init(void)
1241 1249
1242 /* clk_out_2 */ 1250 /* clk_out_2 */
1243 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents, 1251 clk = clk_register_mux(NULL, "clk_out_2_mux", clk_out2_parents,
1244 ARRAY_SIZE(clk_out2_parents), 0, 1252 ARRAY_SIZE(clk_out2_parents),
1253 CLK_SET_RATE_NO_REPARENT,
1245 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0, 1254 pmc_base + PMC_CLK_OUT_CNTRL, 14, 3, 0,
1246 &clk_out_lock); 1255 &clk_out_lock);
1247 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0, 1256 clk = clk_register_gate(NULL, "clk_out_2", "clk_out_2_mux", 0,
@@ -1252,7 +1261,8 @@ static void __init tegra30_pmc_clk_init(void)
1252 1261
1253 /* clk_out_3 */ 1262 /* clk_out_3 */
1254 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents, 1263 clk = clk_register_mux(NULL, "clk_out_3_mux", clk_out3_parents,
1255 ARRAY_SIZE(clk_out3_parents), 0, 1264 ARRAY_SIZE(clk_out3_parents),
1265 CLK_SET_RATE_NO_REPARENT,
1256 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0, 1266 pmc_base + PMC_CLK_OUT_CNTRL, 22, 3, 0,
1257 &clk_out_lock); 1267 &clk_out_lock);
1258 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0, 1268 clk = clk_register_gate(NULL, "clk_out_3", "clk_out_3_mux", 0,
@@ -1679,7 +1689,8 @@ static void __init tegra30_periph_clk_init(void)
1679 1689
1680 /* emc */ 1690 /* emc */
1681 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 1691 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1682 ARRAY_SIZE(mux_pllmcp_clkm), 0, 1692 ARRAY_SIZE(mux_pllmcp_clkm),
1693 CLK_SET_RATE_NO_REPARENT,
1683 clk_base + CLK_SOURCE_EMC, 1694 clk_base + CLK_SOURCE_EMC,
1684 30, 2, 0, NULL); 1695 30, 2, 0, NULL);
1685 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0, 1696 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c
index a4a728d05092..2d5e1b4820e0 100644
--- a/drivers/clk/versatile/clk-vexpress.c
+++ b/drivers/clk/versatile/clk-vexpress.c
@@ -37,8 +37,8 @@ static void __init vexpress_sp810_init(void __iomem *base)
37 snprintf(name, ARRAY_SIZE(name), "timerclken%d", i); 37 snprintf(name, ARRAY_SIZE(name), "timerclken%d", i);
38 38
39 vexpress_sp810_timerclken[i] = clk_register_mux(NULL, name, 39 vexpress_sp810_timerclken[i] = clk_register_mux(NULL, name,
40 parents, 2, 0, base + SCCTRL, 40 parents, 2, CLK_SET_RATE_NO_REPARENT,
41 SCCTRL_TIMERENnSEL_SHIFT(i), 1, 41 base + SCCTRL, SCCTRL_TIMERENnSEL_SHIFT(i), 1,
42 0, &vexpress_sp810_lock); 42 0, &vexpress_sp810_lock);
43 43
44 if (WARN_ON(IS_ERR(vexpress_sp810_timerclken[i]))) 44 if (WARN_ON(IS_ERR(vexpress_sp810_timerclken[i])))
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index 5c205b60a82a..e05c9e3f1385 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -124,8 +124,9 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
124 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); 124 div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
125 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); 125 div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
126 126
127 clk = clk_register_mux(NULL, mux_name, parents, 4, 0, 127 clk = clk_register_mux(NULL, mux_name, parents, 4,
128 fclk_ctrl_reg, 4, 2, 0, fclk_lock); 128 CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
129 fclk_lock);
129 130
130 clk = clk_register_divider(NULL, div0_name, mux_name, 131 clk = clk_register_divider(NULL, div0_name, mux_name,
131 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | 132 0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
@@ -167,8 +168,8 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
167 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); 168 mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
168 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); 169 div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
169 170
170 clk = clk_register_mux(NULL, mux_name, parents, 4, 0, 171 clk = clk_register_mux(NULL, mux_name, parents, 4,
171 clk_ctrl, 4, 2, 0, lock); 172 CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
172 173
173 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, 174 clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
174 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); 175 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
@@ -235,25 +236,26 @@ static void __init zynq_clk_setup(struct device_node *np)
235 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, 236 clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
236 SLCR_PLL_STATUS, 0, &armpll_lock); 237 SLCR_PLL_STATUS, 0, &armpll_lock);
237 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], 238 clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
238 armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0, 239 armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
239 &armpll_lock); 240 SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
240 241
241 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, 242 clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
242 SLCR_PLL_STATUS, 1, &ddrpll_lock); 243 SLCR_PLL_STATUS, 1, &ddrpll_lock);
243 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], 244 clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
244 ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0, 245 ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
245 &ddrpll_lock); 246 SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
246 247
247 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, 248 clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
248 SLCR_PLL_STATUS, 2, &iopll_lock); 249 SLCR_PLL_STATUS, 2, &iopll_lock);
249 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], 250 clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
250 iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0, 251 iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
251 &iopll_lock); 252 SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
252 253
253 /* CPU clocks */ 254 /* CPU clocks */
254 tmp = readl(SLCR_621_TRUE) & 1; 255 tmp = readl(SLCR_621_TRUE) & 1;
255 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0, 256 clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
256 SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock); 257 CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
258 &armclk_lock);
257 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, 259 clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
258 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 260 SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
259 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); 261 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
@@ -292,8 +294,9 @@ static void __init zynq_clk_setup(struct device_node *np)
292 swdt_ext_clk_mux_parents[i + 1] = dummy_nm; 294 swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
293 } 295 }
294 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], 296 clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
295 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT, 297 swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT |
296 SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock); 298 CLK_SET_RATE_NO_REPARENT, SLCR_SWDT_CLK_SEL, 0, 1, 0,
299 &gem0clk_lock);
297 300
298 /* DDR clocks */ 301 /* DDR clocks */
299 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, 302 clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
@@ -355,8 +358,9 @@ static void __init zynq_clk_setup(struct device_node *np)
355 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, 358 gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
356 idx); 359 idx);
357 } 360 }
358 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0, 361 clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
359 SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock); 362 CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
363 &gem0clk_lock);
360 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, 364 clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
361 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 365 SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
362 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); 366 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
@@ -364,8 +368,9 @@ static void __init zynq_clk_setup(struct device_node *np)
364 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, 368 CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
365 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 369 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
366 &gem0clk_lock); 370 &gem0clk_lock);
367 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0, 371 clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
368 SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock); 372 CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 6, 1, 0,
373 &gem0clk_lock);
369 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], 374 clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
370 "gem0_emio_mux", CLK_SET_RATE_PARENT, 375 "gem0_emio_mux", CLK_SET_RATE_PARENT,
371 SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); 376 SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
@@ -377,8 +382,9 @@ static void __init zynq_clk_setup(struct device_node *np)
377 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, 382 gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
378 idx); 383 idx);
379 } 384 }
380 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0, 385 clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
381 SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock); 386 CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
387 &gem1clk_lock);
382 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, 388 clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
383 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 389 SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
384 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); 390 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
@@ -386,8 +392,9 @@ static void __init zynq_clk_setup(struct device_node *np)
386 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, 392 CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
387 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, 393 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
388 &gem1clk_lock); 394 &gem1clk_lock);
389 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0, 395 clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
390 SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock); 396 CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 6, 1, 0,
397 &gem1clk_lock);
391 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], 398 clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
392 "gem1_emio_mux", CLK_SET_RATE_PARENT, 399 "gem1_emio_mux", CLK_SET_RATE_PARENT,
393 SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); 400 SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
@@ -406,8 +413,9 @@ static void __init zynq_clk_setup(struct device_node *np)
406 can_mio_mux_parents[i] = dummy_nm; 413 can_mio_mux_parents[i] = dummy_nm;
407 } 414 }
408 kfree(clk_name); 415 kfree(clk_name);
409 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0, 416 clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
410 SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock); 417 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
418 &canclk_lock);
411 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, 419 clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
412 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 420 SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
413 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); 421 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
@@ -422,17 +430,21 @@ static void __init zynq_clk_setup(struct device_node *np)
422 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, 430 CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
423 &canclk_lock); 431 &canclk_lock);
424 clk = clk_register_mux(NULL, "can0_mio_mux", 432 clk = clk_register_mux(NULL, "can0_mio_mux",
425 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, 433 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
426 SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock); 434 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
435 &canmioclk_lock);
427 clk = clk_register_mux(NULL, "can1_mio_mux", 436 clk = clk_register_mux(NULL, "can1_mio_mux",
428 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, 437 can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
429 SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock); 438 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
439 0, &canmioclk_lock);
430 clks[can0] = clk_register_mux(NULL, clk_output_name[can0], 440 clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
431 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, 441 can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
432 SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock); 442 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 6, 1, 0,
443 &canmioclk_lock);
433 clks[can1] = clk_register_mux(NULL, clk_output_name[can1], 444 clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
434 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, 445 can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT |
435 SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock); 446 CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 22, 1,
447 0, &canmioclk_lock);
436 448
437 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { 449 for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
438 int idx = of_property_match_string(np, "clock-names", 450 int idx = of_property_match_string(np, "clock-names",
@@ -441,13 +453,15 @@ static void __init zynq_clk_setup(struct device_node *np)
441 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, 453 dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
442 idx); 454 idx);
443 } 455 }
444 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0, 456 clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
445 SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock); 457 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
458 &dbgclk_lock);
446 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, 459 clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
447 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | 460 SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
448 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); 461 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
449 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0, 462 clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
450 SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock); 463 CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
464 &dbgclk_lock);
451 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], 465 clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
452 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, 466 "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
453 0, 0, &dbgclk_lock); 467 0, 0, &dbgclk_lock);
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 4f525b37c6fd..5c0bc3904c9b 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -27,6 +27,7 @@
27#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 27#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
28#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ 28#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
29#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ 29#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
30#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
30 31
31struct clk_hw; 32struct clk_hw;
32 33
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-07 22:09:34 -0500