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authorArnd Bergmann <arnd@arndb.de>2012-05-14 10:29:32 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-14 10:29:32 -0400
commit815acebff7ac578970986ca3f0ff406c92a0e243 (patch)
tree651c411bbedeb0500ab9912766e992be3d5a8bab
parent417f381c4568212275f0244500d7d5e1cdb5f99f (diff)
parent72fb92200d6c31b9982c06784e4bcff2f5b7d8b6 (diff)
Merge branch 'ux500/delete-u5500' into next/soc
Conflicts: arch/arm/mach-ux500/cache-l2x0.c arch/arm/mach-ux500/clock.c arch/arm/mach-ux500/cpu.c arch/arm/mach-ux500/mbox-db5500.c arch/arm/mach-ux500/platsmp.c arch/arm/mach-ux500/timer.c Resolve lots of identical conflicts between the removal of u5500 and the addition of u8540. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--arch/arm/mach-ux500/Kconfig25
-rw-r--r--arch/arm/mach-ux500/Makefile5
-rw-r--r--arch/arm/mach-ux500/board-u5500-sdi.c74
-rw-r--r--arch/arm/mach-ux500/board-u5500.c162
-rw-r--r--arch/arm/mach-ux500/cache-l2x0.c4
-rw-r--r--arch/arm/mach-ux500/clock.c12
-rw-r--r--arch/arm/mach-ux500/cpu-db5500.c247
-rw-r--r--arch/arm/mach-ux500/cpu.c8
-rw-r--r--arch/arm/mach-ux500/devices-db5500.h99
-rw-r--r--arch/arm/mach-ux500/dma-db5500.c137
-rw-r--r--arch/arm/mach-ux500/include/mach/db5500-regs.h143
-rw-r--r--arch/arm/mach-ux500/include/mach/debug-macro.S4
-rw-r--r--arch/arm/mach-ux500/include/mach/devices.h1
-rw-r--r--arch/arm/mach-ux500/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-u5500.h21
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-db5500.h113
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs.h5
-rw-r--r--arch/arm/mach-ux500/include/mach/mbox-db5500.h88
-rw-r--r--arch/arm/mach-ux500/include/mach/setup.h6
-rw-r--r--arch/arm/mach-ux500/include/mach/uncompress.h7
-rw-r--r--arch/arm/mach-ux500/mbox-db5500.c565
-rw-r--r--arch/arm/mach-ux500/modem-irq-db5500.c143
-rw-r--r--arch/arm/mach-ux500/pins-db5500.h620
-rw-r--r--arch/arm/mach-ux500/platsmp.c8
-rw-r--r--arch/arm/mach-ux500/ste-dma40-db5500.h135
-rw-r--r--arch/arm/mach-ux500/timer.c13
-rw-r--r--drivers/clocksource/Kconfig2
-rw-r--r--drivers/mfd/Kconfig27
-rw-r--r--drivers/mfd/Makefile3
-rw-r--r--drivers/mfd/ab5500-core.c1439
-rw-r--r--drivers/mfd/ab5500-debugfs.c807
-rw-r--r--drivers/mfd/ab5500-debugfs.h22
-rw-r--r--drivers/mfd/db5500-prcmu.c451
-rw-r--r--include/linux/mfd/abx500.h5
-rw-r--r--include/linux/mfd/abx500/ab5500.h140
-rw-r--r--include/linux/mfd/db5500-prcmu.h105
-rw-r--r--include/linux/mfd/dbx500-prcmu.h242
37 files changed, 56 insertions, 5833 deletions
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index ef7099eea0f2..0e8470a3fbeb 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -10,10 +10,6 @@ config UX500_SOC_COMMON
10 select ARM_ERRATA_764369 10 select ARM_ERRATA_764369
11 select CACHE_L2X0 11 select CACHE_L2X0
12 12
13config UX500_SOC_DB5500
14 bool
15 select MFD_DB5500_PRCMU
16
17config UX500_SOC_DB8500 13config UX500_SOC_DB8500
18 bool 14 bool
19 select MFD_DB8500_PRCMU 15 select MFD_DB8500_PRCMU
@@ -45,15 +41,8 @@ config MACH_SNOWBALL
45 help 41 help
46 Include support for the snowball development platform. 42 Include support for the snowball development platform.
47 43
48config MACH_U5500
49 bool "U5500 Development platform"
50 select UX500_SOC_DB5500
51 help
52 Include support for the U5500 development platform.
53
54config UX500_AUTO_PLATFORM 44config UX500_AUTO_PLATFORM
55 def_bool y 45 def_bool y
56 depends on !MACH_U5500
57 select MACH_MOP500 46 select MACH_MOP500
58 help 47 help
59 At least one platform needs to be selected in order to build 48 At least one platform needs to be selected in order to build
@@ -74,18 +63,4 @@ config UX500_DEBUG_UART
74 Choose the UART on which kernel low-level debug messages should be 63 Choose the UART on which kernel low-level debug messages should be
75 output. 64 output.
76 65
77config U5500_MODEM_IRQ
78 bool "Modem IRQ support"
79 depends on UX500_SOC_DB5500
80 default y
81 help
82 Add support for handling IRQ:s from modem side
83
84config U5500_MBOX
85 bool "Mailbox support"
86 depends on U5500_MODEM_IRQ
87 default y
88 help
89 Add support for U5500 mailbox communication with modem side
90
91endif 66endif
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 465b9ec9510a..fc7db5df970b 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -5,16 +5,11 @@
5obj-y := clock.o cpu.o devices.o devices-common.o \ 5obj-y := clock.o cpu.o devices.o devices-common.o \
6 id.o usb.o timer.o 6 id.o usb.o timer.o
7obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o 7obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
8obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o
9obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o 8obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
10obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \ 9obj-$(CONFIG_MACH_MOP500) += board-mop500.o board-mop500-sdi.o \
11 board-mop500-regulators.o \ 10 board-mop500-regulators.o \
12 board-mop500-uib.o board-mop500-stuib.o \ 11 board-mop500-uib.o board-mop500-stuib.o \
13 board-mop500-u8500uib.o \ 12 board-mop500-u8500uib.o \
14 board-mop500-pins.o 13 board-mop500-pins.o
15obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o
16obj-$(CONFIG_SMP) += platsmp.o headsmp.o 14obj-$(CONFIG_SMP) += platsmp.o headsmp.o
17obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 15obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
18obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o
19obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o
20
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
deleted file mode 100644
index 836112eedde7..000000000000
--- a/arch/arm/mach-ux500/board-u5500-sdi.c
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Hanumath Prasad <ulf.hansson@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/amba/mmci.h>
9#include <linux/mmc/host.h>
10
11#include <plat/pincfg.h>
12#include <plat/gpio-nomadik.h>
13#include <mach/db5500-regs.h>
14#include <plat/ste_dma40.h>
15
16#include "pins-db5500.h"
17#include "devices-db5500.h"
18#include "ste-dma40-db5500.h"
19
20static pin_cfg_t u5500_sdi_pins[] = {
21 /* SDI0 (POP eMMC) */
22 GPIO5_MC0_DAT0 | PIN_DIR_INPUT | PIN_PULL_UP,
23 GPIO6_MC0_DAT1 | PIN_DIR_INPUT | PIN_PULL_UP,
24 GPIO7_MC0_DAT2 | PIN_DIR_INPUT | PIN_PULL_UP,
25 GPIO8_MC0_DAT3 | PIN_DIR_INPUT | PIN_PULL_UP,
26 GPIO9_MC0_DAT4 | PIN_DIR_INPUT | PIN_PULL_UP,
27 GPIO10_MC0_DAT5 | PIN_DIR_INPUT | PIN_PULL_UP,
28 GPIO11_MC0_DAT6 | PIN_DIR_INPUT | PIN_PULL_UP,
29 GPIO12_MC0_DAT7 | PIN_DIR_INPUT | PIN_PULL_UP,
30 GPIO13_MC0_CMD | PIN_DIR_INPUT | PIN_PULL_UP,
31 GPIO14_MC0_CLK | PIN_DIR_OUTPUT | PIN_VAL_LOW,
32};
33
34#ifdef CONFIG_STE_DMA40
35struct stedma40_chan_cfg u5500_sdi0_dma_cfg_rx = {
36 .mode = STEDMA40_MODE_LOGICAL,
37 .dir = STEDMA40_PERIPH_TO_MEM,
38 .src_dev_type = DB5500_DMA_DEV24_SDMMC0_RX,
39 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
40 .src_info.data_width = STEDMA40_WORD_WIDTH,
41 .dst_info.data_width = STEDMA40_WORD_WIDTH,
42};
43
44static struct stedma40_chan_cfg u5500_sdi0_dma_cfg_tx = {
45 .mode = STEDMA40_MODE_LOGICAL,
46 .dir = STEDMA40_MEM_TO_PERIPH,
47 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
48 .dst_dev_type = DB5500_DMA_DEV24_SDMMC0_TX,
49 .src_info.data_width = STEDMA40_WORD_WIDTH,
50 .dst_info.data_width = STEDMA40_WORD_WIDTH,
51};
52#endif
53
54static struct mmci_platform_data u5500_sdi0_data = {
55 .ocr_mask = MMC_VDD_165_195,
56 .f_max = 50000000,
57 .capabilities = MMC_CAP_4_BIT_DATA |
58 MMC_CAP_8_BIT_DATA |
59 MMC_CAP_MMC_HIGHSPEED,
60 .gpio_cd = -1,
61 .gpio_wp = -1,
62#ifdef CONFIG_STE_DMA40
63 .dma_filter = stedma40_filter,
64 .dma_rx_param = &u5500_sdi0_dma_cfg_rx,
65 .dma_tx_param = &u5500_sdi0_dma_cfg_tx,
66#endif
67};
68
69void __init u5500_sdi_init(struct device *parent)
70{
71 nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins));
72
73 db5500_add_sdi0(parent, &u5500_sdi0_data);
74}
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
deleted file mode 100644
index 0ff4be72a809..000000000000
--- a/arch/arm/mach-ux500/board-u5500.c
+++ /dev/null
@@ -1,162 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/amba/bus.h>
11#include <linux/irq.h>
12#include <linux/i2c.h>
13#include <linux/mfd/abx500/ab5500.h>
14
15#include <asm/hardware/gic.h>
16#include <asm/mach/arch.h>
17#include <asm/mach-types.h>
18
19#include <plat/pincfg.h>
20#include <plat/i2c.h>
21#include <plat/gpio-nomadik.h>
22
23#include <mach/hardware.h>
24#include <mach/devices.h>
25#include <mach/setup.h>
26
27#include "pins-db5500.h"
28#include "devices-db5500.h"
29#include <linux/led-lm3530.h>
30
31/*
32 * GPIO
33 */
34
35static pin_cfg_t u5500_pins[] = {
36 /* I2C */
37 GPIO218_I2C2_SCL | PIN_INPUT_PULLUP,
38 GPIO219_I2C2_SDA | PIN_INPUT_PULLUP,
39
40 /* DISPLAY_ENABLE */
41 GPIO226_GPIO | PIN_OUTPUT_LOW,
42
43 /* Backlight Enbale */
44 GPIO224_GPIO | PIN_OUTPUT_HIGH,
45};
46/*
47 * I2C
48 */
49
50#define U5500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
51static struct nmk_i2c_controller u5500_i2c##id##_data = { \
52 /* \
53 * slave data setup time, which is \
54 * 250 ns,100ns,10ns which is 14,6,2 \
55 * respectively for a 48 Mhz \
56 * i2c clock \
57 */ \
58 .slsu = _slsu, \
59 /* Tx FIFO threshold */ \
60 .tft = _tft, \
61 /* Rx FIFO threshold */ \
62 .rft = _rft, \
63 /* std. mode operation */ \
64 .clk_freq = clk, \
65 .sm = _sm, \
66}
67/*
68 * The board uses TODO <3> i2c controllers, initialize all of
69 * them with slave data setup time of 250 ns,
70 * Tx & Rx FIFO threshold values as 1 and standard
71 * mode of operation
72 */
73
74U5500_I2C_CONTROLLER(2, 0xe, 1, 1, 400000, I2C_FREQ_MODE_FAST);
75
76static struct lm3530_platform_data u5500_als_platform_data = {
77 .mode = LM3530_BL_MODE_MANUAL,
78 .als_input_mode = LM3530_INPUT_ALS1,
79 .max_current = LM3530_FS_CURR_26mA,
80 .pwm_pol_hi = true,
81 .als_avrg_time = LM3530_ALS_AVRG_TIME_512ms,
82 .brt_ramp_law = 1, /* Linear */
83 .brt_ramp_fall = LM3530_RAMP_TIME_8s,
84 .brt_ramp_rise = LM3530_RAMP_TIME_8s,
85 .als1_resistor_sel = LM3530_ALS_IMPD_13_53kOhm,
86 .als2_resistor_sel = LM3530_ALS_IMPD_Z,
87 .als_vmin = 730, /* mV */
88 .als_vmax = 1020, /* mV */
89 .brt_val = 0x7F, /* Max brightness */
90};
91
92static struct i2c_board_info __initdata u5500_i2c2_devices[] = {
93 {
94 /* Backlight */
95 I2C_BOARD_INFO("lm3530-led", 0x36),
96 .platform_data = &u5500_als_platform_data,
97 },
98};
99
100static void __init u5500_i2c_init(struct device *parent)
101{
102 db5500_add_i2c2(parent, &u5500_i2c2_data);
103 i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices));
104}
105
106static struct ab5500_platform_data ab5500_plf_data = {
107 .irq = {
108 .base = 0,
109 .count = 0,
110 },
111 .init_settings = NULL,
112 .init_settings_sz = 0,
113 .pm_power_off = false,
114};
115
116static struct platform_device ab5500_device = {
117 .name = "ab5500-core",
118 .id = 0,
119 .dev = {
120 .platform_data = &ab5500_plf_data,
121 },
122 .num_resources = 0,
123};
124
125static struct platform_device *u5500_platform_devices[] __initdata = {
126 &ab5500_device,
127};
128
129static void __init u5500_uart_init(struct device *parent)
130{
131 db5500_add_uart0(parent, NULL);
132 db5500_add_uart1(parent, NULL);
133 db5500_add_uart2(parent, NULL);
134}
135
136static void __init u5500_init_machine(void)
137{
138 struct device *parent = NULL;
139 int i;
140
141 parent = u5500_init_devices();
142 nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins));
143
144 u5500_i2c_init(parent);
145 u5500_sdi_init(parent);
146 u5500_uart_init(parent);
147
148 for (i = 0; i < ARRAY_SIZE(u5500_platform_devices); i++)
149 u5500_platform_devices[i]->dev.parent = parent;
150
151 platform_add_devices(u5500_platform_devices,
152 ARRAY_SIZE(u5500_platform_devices));
153}
154
155MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
156 .atag_offset = 0x100,
157 .map_io = u5500_map_io,
158 .init_irq = ux500_init_irq,
159 .timer = &ux500_timer,
160 .handle_irq = gic_handle_irq,
161 .init_machine = u5500_init_machine,
162MACHINE_END
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 677bb7683c71..dc12394295d5 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -38,9 +38,7 @@ static int __init ux500_l2x0_init(void)
38{ 38{
39 u32 aux_val = 0x3e000000; 39 u32 aux_val = 0x3e000000;
40 40
41 if (cpu_is_u5500()) 41 if (cpu_is_u8500_family())
42 l2x0_base = __io_address(U5500_L2CC_BASE);
43 else if (cpu_is_u8500_family())
44 l2x0_base = __io_address(U8500_L2CC_BASE); 42 l2x0_base = __io_address(U8500_L2CC_BASE);
45 else 43 else
46 ux500_unknown_soc(); 44 ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index cc87f7788ff5..063f3dbd45a9 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -149,9 +149,7 @@ static unsigned long clk_mtu_get_rate(struct clk *clk)
149 unsigned long mturate; 149 unsigned long mturate;
150 unsigned long retclk; 150 unsigned long retclk;
151 151
152 if (cpu_is_u5500()) 152 if (cpu_is_u8500_family())
153 addr = __io_address(U5500_PRCMU_BASE);
154 else if (cpu_is_u8500_family())
155 addr = __io_address(U8500_PRCMU_BASE); 153 addr = __io_address(U8500_PRCMU_BASE);
156 else 154 else
157 ux500_unknown_soc(); 155 ux500_unknown_soc();
@@ -705,14 +703,6 @@ late_initcall(clk_init_smp_twd_cpufreq);
705 703
706int __init clk_init(void) 704int __init clk_init(void)
707{ 705{
708 if (cpu_is_u5500()) {
709 /* Clock tree for U5500 not implemented yet */
710 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
711 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
712 clk_uartclk.rate = 36360000;
713 clk_sdmmcclk.rate = 99900000;
714 }
715
716 clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks)); 706 clkdev_add_table(u8500_clks, ARRAY_SIZE(u8500_clks));
717 clkdev_add(&clk_smp_twd_lookup); 707 clkdev_add(&clk_smp_twd_lookup);
718 708
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
deleted file mode 100644
index bca47f32082f..000000000000
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ /dev/null
@@ -1,247 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/platform_device.h>
9#include <linux/amba/bus.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12
13#include <asm/mach/map.h>
14#include <asm/pmu.h>
15
16#include <plat/gpio-nomadik.h>
17
18#include <mach/hardware.h>
19#include <mach/devices.h>
20#include <mach/setup.h>
21#include <mach/irqs.h>
22#include <mach/usb.h>
23
24#include "devices-db5500.h"
25#include "ste-dma40-db5500.h"
26
27static struct map_desc u5500_uart_io_desc[] __initdata = {
28 __IO_DEV_DESC(U5500_UART0_BASE, SZ_4K),
29 __IO_DEV_DESC(U5500_UART2_BASE, SZ_4K),
30};
31
32static struct map_desc u5500_io_desc[] __initdata = {
33 /* SCU base also covers GIC CPU BASE and TWD with its 4K page */
34 __IO_DEV_DESC(U5500_SCU_BASE, SZ_4K),
35 __IO_DEV_DESC(U5500_GIC_DIST_BASE, SZ_4K),
36 __IO_DEV_DESC(U5500_L2CC_BASE, SZ_4K),
37 __IO_DEV_DESC(U5500_MTU0_BASE, SZ_4K),
38 __IO_DEV_DESC(U5500_BACKUPRAM0_BASE, SZ_8K),
39
40 __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
41 __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K),
42 __IO_DEV_DESC(U5500_GPIO2_BASE, SZ_4K),
43 __IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K),
44 __IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K),
45 __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
46 __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K),
47};
48
49static struct resource mbox0_resources[] = {
50 {
51 .name = "mbox_peer",
52 .start = U5500_MBOX0_PEER_START,
53 .end = U5500_MBOX0_PEER_END,
54 .flags = IORESOURCE_MEM,
55 },
56 {
57 .name = "mbox_local",
58 .start = U5500_MBOX0_LOCAL_START,
59 .end = U5500_MBOX0_LOCAL_END,
60 .flags = IORESOURCE_MEM,
61 },
62 {
63 .name = "mbox_irq",
64 .start = MBOX_PAIR0_VIRT_IRQ,
65 .end = MBOX_PAIR0_VIRT_IRQ,
66 .flags = IORESOURCE_IRQ,
67 }
68};
69
70static struct resource mbox1_resources[] = {
71 {
72 .name = "mbox_peer",
73 .start = U5500_MBOX1_PEER_START,
74 .end = U5500_MBOX1_PEER_END,
75 .flags = IORESOURCE_MEM,
76 },
77 {
78 .name = "mbox_local",
79 .start = U5500_MBOX1_LOCAL_START,
80 .end = U5500_MBOX1_LOCAL_END,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .name = "mbox_irq",
85 .start = MBOX_PAIR1_VIRT_IRQ,
86 .end = MBOX_PAIR1_VIRT_IRQ,
87 .flags = IORESOURCE_IRQ,
88 }
89};
90
91static struct resource mbox2_resources[] = {
92 {
93 .name = "mbox_peer",
94 .start = U5500_MBOX2_PEER_START,
95 .end = U5500_MBOX2_PEER_END,
96 .flags = IORESOURCE_MEM,
97 },
98 {
99 .name = "mbox_local",
100 .start = U5500_MBOX2_LOCAL_START,
101 .end = U5500_MBOX2_LOCAL_END,
102 .flags = IORESOURCE_MEM,
103 },
104 {
105 .name = "mbox_irq",
106 .start = MBOX_PAIR2_VIRT_IRQ,
107 .end = MBOX_PAIR2_VIRT_IRQ,
108 .flags = IORESOURCE_IRQ,
109 }
110};
111
112static struct platform_device mbox0_device = {
113 .id = 0,
114 .name = "mbox",
115 .resource = mbox0_resources,
116 .num_resources = ARRAY_SIZE(mbox0_resources),
117};
118
119static struct platform_device mbox1_device = {
120 .id = 1,
121 .name = "mbox",
122 .resource = mbox1_resources,
123 .num_resources = ARRAY_SIZE(mbox1_resources),
124};
125
126static struct platform_device mbox2_device = {
127 .id = 2,
128 .name = "mbox",
129 .resource = mbox2_resources,
130 .num_resources = ARRAY_SIZE(mbox2_resources),
131};
132
133static struct platform_device *db5500_platform_devs[] __initdata = {
134 &mbox0_device,
135 &mbox1_device,
136 &mbox2_device,
137};
138
139static resource_size_t __initdata db5500_gpio_base[] = {
140 U5500_GPIOBANK0_BASE,
141 U5500_GPIOBANK1_BASE,
142 U5500_GPIOBANK2_BASE,
143 U5500_GPIOBANK3_BASE,
144 U5500_GPIOBANK4_BASE,
145 U5500_GPIOBANK5_BASE,
146 U5500_GPIOBANK6_BASE,
147 U5500_GPIOBANK7_BASE,
148};
149
150static void __init db5500_add_gpios(struct device *parent)
151{
152 struct nmk_gpio_platform_data pdata = {
153 /* No custom data yet */
154 };
155
156 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db5500_gpio_base),
157 IRQ_DB5500_GPIO0, &pdata);
158}
159
160void __init u5500_map_io(void)
161{
162 /*
163 * Map the UARTs early so that the DEBUG_LL stuff continues to work.
164 */
165 iotable_init(u5500_uart_io_desc, ARRAY_SIZE(u5500_uart_io_desc));
166
167 ux500_map_io();
168
169 iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
170
171 _PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
172}
173
174static void __init db5500_pmu_init(void)
175{
176 struct resource res[] = {
177 [0] = {
178 .start = IRQ_DB5500_PMU0,
179 .end = IRQ_DB5500_PMU0,
180 .flags = IORESOURCE_IRQ,
181 },
182 [1] = {
183 .start = IRQ_DB5500_PMU1,
184 .end = IRQ_DB5500_PMU1,
185 .flags = IORESOURCE_IRQ,
186 },
187 };
188
189 platform_device_register_simple("arm-pmu", ARM_PMU_DEVICE_CPU,
190 res, ARRAY_SIZE(res));
191}
192
193static int usb_db5500_rx_dma_cfg[] = {
194 DB5500_DMA_DEV4_USB_OTG_IEP_1_9,
195 DB5500_DMA_DEV5_USB_OTG_IEP_2_10,
196 DB5500_DMA_DEV6_USB_OTG_IEP_3_11,
197 DB5500_DMA_DEV20_USB_OTG_IEP_4_12,
198 DB5500_DMA_DEV21_USB_OTG_IEP_5_13,
199 DB5500_DMA_DEV22_USB_OTG_IEP_6_14,
200 DB5500_DMA_DEV23_USB_OTG_IEP_7_15,
201 DB5500_DMA_DEV38_USB_OTG_IEP_8
202};
203
204static int usb_db5500_tx_dma_cfg[] = {
205 DB5500_DMA_DEV4_USB_OTG_OEP_1_9,
206 DB5500_DMA_DEV5_USB_OTG_OEP_2_10,
207 DB5500_DMA_DEV6_USB_OTG_OEP_3_11,
208 DB5500_DMA_DEV20_USB_OTG_OEP_4_12,
209 DB5500_DMA_DEV21_USB_OTG_OEP_5_13,
210 DB5500_DMA_DEV22_USB_OTG_OEP_6_14,
211 DB5500_DMA_DEV23_USB_OTG_OEP_7_15,
212 DB5500_DMA_DEV38_USB_OTG_OEP_8
213};
214
215static const char *db5500_read_soc_id(void)
216{
217 return kasprintf(GFP_KERNEL, "u5500 currently unsupported\n");
218}
219
220static struct device * __init db5500_soc_device_init(void)
221{
222 const char *soc_id = db5500_read_soc_id();
223
224 return ux500_soc_device_init(soc_id);
225}
226
227struct device * __init u5500_init_devices(void)
228{
229 struct device *parent;
230 int i;
231
232 parent = db5500_soc_device_init();
233
234 db5500_add_gpios(parent);
235 db5500_pmu_init();
236 db5500_dma_init(parent);
237 db5500_add_rtc(parent);
238 db5500_add_usb(parent, usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
239
240 for (i = 0; i < ARRAY_SIZE(db5500_platform_devs); i++)
241 db5500_platform_devs[i]->dev.parent = parent;
242
243 platform_add_devices(db5500_platform_devs,
244 ARRAY_SIZE(db5500_platform_devs));
245
246 return parent;
247}
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 857e48167526..0982279f51f3 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -10,7 +10,6 @@
10#include <linux/io.h> 10#include <linux/io.h>
11#include <linux/clk.h> 11#include <linux/clk.h>
12#include <linux/mfd/db8500-prcmu.h> 12#include <linux/mfd/db8500-prcmu.h>
13#include <linux/mfd/db5500-prcmu.h>
14#include <linux/clksrc-dbx500-prcmu.h> 13#include <linux/clksrc-dbx500-prcmu.h>
15#include <linux/sys_soc.h> 14#include <linux/sys_soc.h>
16#include <linux/err.h> 15#include <linux/err.h>
@@ -40,10 +39,7 @@ void __init ux500_init_irq(void)
40 void __iomem *dist_base; 39 void __iomem *dist_base;
41 void __iomem *cpu_base; 40 void __iomem *cpu_base;
42 41
43 if (cpu_is_u5500()) { 42 if (cpu_is_u8500_family()) {
44 dist_base = __io_address(U5500_GIC_DIST_BASE);
45 cpu_base = __io_address(U5500_GIC_CPU_BASE);
46 } else if (cpu_is_u8500_family()) {
47 dist_base = __io_address(U8500_GIC_DIST_BASE); 43 dist_base = __io_address(U8500_GIC_DIST_BASE);
48 cpu_base = __io_address(U8500_GIC_CPU_BASE); 44 cpu_base = __io_address(U8500_GIC_CPU_BASE);
49 } else 45 } else
@@ -60,8 +56,6 @@ void __init ux500_init_irq(void)
60 * Init clocks here so that they are available for system timer 56 * Init clocks here so that they are available for system timer
61 * initialization. 57 * initialization.
62 */ 58 */
63 if (cpu_is_u5500())
64 db5500_prcmu_early_init();
65 if (cpu_is_u8500_family()) 59 if (cpu_is_u8500_family())
66 db8500_prcmu_early_init(); 60 db8500_prcmu_early_init();
67 clk_init(); 61 clk_init();
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
deleted file mode 100644
index e70955502c35..000000000000
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __DEVICES_DB5500_H
9#define __DEVICES_DB5500_H
10
11#include "devices-common.h"
12
13#define db5500_add_i2c1(parent, pdata) \
14 dbx500_add_i2c(parent, 1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata)
15#define db5500_add_i2c2(parent, pdata) \
16 dbx500_add_i2c(parent, 2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata)
17#define db5500_add_i2c3(parent, pdata) \
18 dbx500_add_i2c(parent, 3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata)
19
20#define db5500_add_msp0_spi(parent, pdata) \
21 dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \
22 IRQ_DB5500_MSP0, pdata)
23#define db5500_add_msp1_spi(parent, pdata) \
24 dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \
25 IRQ_DB5500_MSP1, pdata)
26#define db5500_add_msp2_spi(parent, pdata) \
27 dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \
28 IRQ_DB5500_MSP2, pdata)
29
30#define db5500_add_msp0_spi(parent, pdata) \
31 dbx500_add_msp_spi(parent, "msp0", U5500_MSP0_BASE, \
32 IRQ_DB5500_MSP0, pdata)
33#define db5500_add_msp1_spi(parent, pdata) \
34 dbx500_add_msp_spi(parent, "msp1", U5500_MSP1_BASE, \
35 IRQ_DB5500_MSP1, pdata)
36#define db5500_add_msp2_spi(parent, pdata) \
37 dbx500_add_msp_spi(parent, "msp2", U5500_MSP2_BASE, \
38 IRQ_DB5500_MSP2, pdata)
39
40#define db5500_add_rtc(parent) \
41 dbx500_add_rtc(parent, U5500_RTC_BASE, IRQ_DB5500_RTC);
42
43#define db5500_add_usb(parent, rx_cfg, tx_cfg) \
44 ux500_add_usb(parent, U5500_USBOTG_BASE, \
45 IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
46
47#define db5500_add_sdi0(parent, pdata) \
48 dbx500_add_sdi(parent, "sdi0", U5500_SDI0_BASE, \
49 IRQ_DB5500_SDMMC0, pdata, \
50 0x10480180)
51#define db5500_add_sdi1(parent, pdata) \
52 dbx500_add_sdi(parent, "sdi1", U5500_SDI1_BASE, \
53 IRQ_DB5500_SDMMC1, pdata, \
54 0x10480180)
55#define db5500_add_sdi2(parent, pdata) \
56 dbx500_add_sdi(parent, "sdi2", U5500_SDI2_BASE, \
57 IRQ_DB5500_SDMMC2, pdata \
58 0x10480180)
59#define db5500_add_sdi3(parent, pdata) \
60 dbx500_add_sdi(parent, "sdi3", U5500_SDI3_BASE, \
61 IRQ_DB5500_SDMMC3, pdata \
62 0x10480180)
63#define db5500_add_sdi4(parent, pdata) \
64 dbx500_add_sdi(parent, "sdi4", U5500_SDI4_BASE, \
65 IRQ_DB5500_SDMMC4, pdata \
66 0x10480180)
67
68/* This one has a bad peripheral ID in the U5500 silicon */
69#define db5500_add_spi0(parent, pdata) \
70 dbx500_add_spi(parent, "spi0", U5500_SPI0_BASE, \
71 IRQ_DB5500_SPI0, pdata, \
72 0x10080023)
73#define db5500_add_spi1(parent, pdata) \
74 dbx500_add_spi(parent, "spi1", U5500_SPI1_BASE, \
75 IRQ_DB5500_SPI1, pdata, \
76 0x10080023)
77#define db5500_add_spi2(parent, pdata) \
78 dbx500_add_spi(parent, "spi2", U5500_SPI2_BASE, \
79 IRQ_DB5500_SPI2, pdata \
80 0x10080023)
81#define db5500_add_spi3(parent, pdata) \
82 dbx500_add_spi(parent, "spi3", U5500_SPI3_BASE, \
83 IRQ_DB5500_SPI3, pdata \
84 0x10080023)
85
86#define db5500_add_uart0(parent, plat) \
87 dbx500_add_uart(parent, "uart0", U5500_UART0_BASE, \
88 IRQ_DB5500_UART0, plat)
89#define db5500_add_uart1(parent, plat) \
90 dbx500_add_uart(parent, "uart1", U5500_UART1_BASE, \
91 IRQ_DB5500_UART1, plat)
92#define db5500_add_uart2(parent, plat) \
93 dbx500_add_uart(parent, "uart2", U5500_UART2_BASE, \
94 IRQ_DB5500_UART2, plat)
95#define db5500_add_uart3(parent, plat) \
96 dbx500_add_uart(parent, "uart3", U5500_UART3_BASE, \
97 IRQ_DB5500_UART3, plat)
98
99#endif
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
deleted file mode 100644
index 41e9470fa0e6..000000000000
--- a/arch/arm/mach-ux500/dma-db5500.c
+++ /dev/null
@@ -1,137 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson
7 *
8 * License terms: GNU General Public License (GPL), version 2
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13
14#include <plat/ste_dma40.h>
15#include <mach/setup.h>
16#include <mach/hardware.h>
17
18#include "ste-dma40-db5500.h"
19
20static struct resource dma40_resources[] = {
21 [0] = {
22 .start = U5500_DMA_BASE,
23 .end = U5500_DMA_BASE + SZ_4K - 1,
24 .flags = IORESOURCE_MEM,
25 .name = "base",
26 },
27 [1] = {
28 .start = U5500_DMA_LCPA_BASE,
29 .end = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
30 .flags = IORESOURCE_MEM,
31 .name = "lcpa",
32 },
33 [2] = {
34 .start = IRQ_DB5500_DMA,
35 .end = IRQ_DB5500_DMA,
36 .flags = IORESOURCE_IRQ
37 }
38};
39
40/* Default configuration for physical memcpy */
41static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
42 .mode = STEDMA40_MODE_PHYSICAL,
43 .dir = STEDMA40_MEM_TO_MEM,
44
45 .src_info.data_width = STEDMA40_BYTE_WIDTH,
46 .src_info.psize = STEDMA40_PSIZE_PHY_1,
47 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
48
49 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
50 .dst_info.psize = STEDMA40_PSIZE_PHY_1,
51 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
52};
53
54/* Default configuration for logical memcpy */
55static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
56 .dir = STEDMA40_MEM_TO_MEM,
57
58 .src_info.data_width = STEDMA40_BYTE_WIDTH,
59 .src_info.psize = STEDMA40_PSIZE_LOG_1,
60 .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
61
62 .dst_info.data_width = STEDMA40_BYTE_WIDTH,
63 .dst_info.psize = STEDMA40_PSIZE_LOG_1,
64 .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
65};
66
67/*
68 * Mapping between soruce event lines and physical device address This was
69 * created assuming that the event line is tied to a device and therefore the
70 * address is constant, however this is not true for at least USB, and the
71 * values are just placeholders for USB. This table is preserved and used for
72 * now.
73 */
74static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = {
75 [DB5500_DMA_DEV24_SDMMC0_RX] = -1,
76 [DB5500_DMA_DEV38_USB_OTG_IEP_8] = -1,
77 [DB5500_DMA_DEV23_USB_OTG_IEP_7_15] = -1,
78 [DB5500_DMA_DEV22_USB_OTG_IEP_6_14] = -1,
79 [DB5500_DMA_DEV21_USB_OTG_IEP_5_13] = -1,
80 [DB5500_DMA_DEV20_USB_OTG_IEP_4_12] = -1,
81 [DB5500_DMA_DEV6_USB_OTG_IEP_3_11] = -1,
82 [DB5500_DMA_DEV5_USB_OTG_IEP_2_10] = -1,
83 [DB5500_DMA_DEV4_USB_OTG_IEP_1_9] = -1,
84};
85
86/* Mapping between destination event lines and physical device address */
87static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = {
88 [DB5500_DMA_DEV24_SDMMC0_TX] = -1,
89 [DB5500_DMA_DEV38_USB_OTG_OEP_8] = -1,
90 [DB5500_DMA_DEV23_USB_OTG_OEP_7_15] = -1,
91 [DB5500_DMA_DEV22_USB_OTG_OEP_6_14] = -1,
92 [DB5500_DMA_DEV21_USB_OTG_OEP_5_13] = -1,
93 [DB5500_DMA_DEV20_USB_OTG_OEP_4_12] = -1,
94 [DB5500_DMA_DEV6_USB_OTG_OEP_3_11] = -1,
95 [DB5500_DMA_DEV5_USB_OTG_OEP_2_10] = -1,
96 [DB5500_DMA_DEV4_USB_OTG_OEP_1_9] = -1,
97};
98
99static int dma40_memcpy_event[] = {
100 DB5500_DMA_MEMCPY_TX_1,
101 DB5500_DMA_MEMCPY_TX_2,
102 DB5500_DMA_MEMCPY_TX_3,
103 DB5500_DMA_MEMCPY_TX_4,
104 DB5500_DMA_MEMCPY_TX_5,
105};
106
107static struct stedma40_platform_data dma40_plat_data = {
108 .dev_len = ARRAY_SIZE(dma40_rx_map),
109 .dev_rx = dma40_rx_map,
110 .dev_tx = dma40_tx_map,
111 .memcpy = dma40_memcpy_event,
112 .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
113 .memcpy_conf_phy = &dma40_memcpy_conf_phy,
114 .memcpy_conf_log = &dma40_memcpy_conf_log,
115 .disabled_channels = {-1},
116};
117
118static struct platform_device dma40_device = {
119 .dev = {
120 .platform_data = &dma40_plat_data,
121 },
122 .name = "dma40",
123 .id = 0,
124 .num_resources = ARRAY_SIZE(dma40_resources),
125 .resource = dma40_resources
126};
127
128void __init db5500_dma_init(struct device *parent)
129{
130 int ret;
131
132 dma40_device.dev.parent = parent;
133 ret = platform_device_register(&dma40_device);
134 if (ret)
135 dev_err(&dma40_device.dev, "unable to register device: %d\n", ret);
136
137}
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
deleted file mode 100644
index 8e714bcb099f..000000000000
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_DB5500_REGS_H
8#define __MACH_DB5500_REGS_H
9
10#define U5500_PER1_BASE 0xA0020000
11#define U5500_PER2_BASE 0xA0010000
12#define U5500_PER3_BASE 0x80140000
13#define U5500_PER4_BASE 0x80150000
14#define U5500_PER5_BASE 0x80100000
15#define U5500_PER6_BASE 0x80120000
16
17#define U5500_GIC_DIST_BASE 0xA0411000
18#define U5500_GIC_CPU_BASE 0xA0410100
19#define U5500_DMA_BASE 0x90030000
20#define U5500_STM_BASE 0x90020000
21#define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000)
22#define U5500_MCDE_BASE 0xA0400000
23#define U5500_MODEM_BASE 0xB0000000
24#define U5500_L2CC_BASE 0xA0412000
25#define U5500_SCU_BASE 0xA0410000
26#define U5500_DSI1_BASE 0xA0401000
27#define U5500_DSI2_BASE 0xA0402000
28#define U5500_SIA_BASE 0xA0100000
29#define U5500_SVA_BASE 0x80200000
30#define U5500_HSEM_BASE 0xA0000000
31#define U5500_NAND0_BASE 0x60000000
32#define U5500_NAND1_BASE 0x70000000
33#define U5500_TWD_BASE 0xa0410600
34#define U5500_ICN_BASE 0xA0040000
35#define U5500_B2R2_BASE 0xa0200000
36#define U5500_BOOT_ROM_BASE 0x90000000
37
38#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
39#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
40#define U5500_SDI2_BASE (U5500_PER1_BASE + 0x2000)
41#define U5500_UART0_BASE (U5500_PER1_BASE + 0x3000)
42#define U5500_I2C1_BASE (U5500_PER1_BASE + 0x4000)
43#define U5500_MSP0_BASE (U5500_PER1_BASE + 0x5000)
44#define U5500_GPIO0_BASE (U5500_PER1_BASE + 0xE000)
45#define U5500_CLKRST1_BASE (U5500_PER1_BASE + 0xF000)
46
47#define U5500_USBOTG_BASE (U5500_PER2_BASE + 0x0000)
48#define U5500_GPIO1_BASE (U5500_PER2_BASE + 0xE000)
49#define U5500_CLKRST2_BASE (U5500_PER2_BASE + 0xF000)
50
51#define U5500_KEYPAD_BASE (U5500_PER3_BASE + 0x0000)
52#define U5500_PWM_BASE (U5500_PER3_BASE + 0x1000)
53#define U5500_GPIO3_BASE (U5500_PER3_BASE + 0xE000)
54#define U5500_CLKRST3_BASE (U5500_PER3_BASE + 0xF000)
55
56#define U5500_BACKUPRAM0_BASE (U5500_PER4_BASE + 0x0000)
57#define U5500_BACKUPRAM1_BASE (U5500_PER4_BASE + 0x1000)
58#define U5500_RTT0_BASE (U5500_PER4_BASE + 0x2000)
59#define U5500_RTT1_BASE (U5500_PER4_BASE + 0x3000)
60#define U5500_RTC_BASE (U5500_PER4_BASE + 0x4000)
61#define U5500_SCR_BASE (U5500_PER4_BASE + 0x5000)
62#define U5500_DMC_BASE (U5500_PER4_BASE + 0x6000)
63#define U5500_PRCMU_BASE (U5500_PER4_BASE + 0x7000)
64#define U5500_PRCMU_TIMER_3_BASE (U5500_PER4_BASE + 0x07338)
65#define U5500_PRCMU_TIMER_4_BASE (U5500_PER4_BASE + 0x07450)
66#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
67#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
68#define U5500_MTIMER_BASE (U5500_PER4_BASE + 0xC000)
69#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
70#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000)
71#define U5500_PRCMU_TCPM_BASE (U5500_PER4_BASE + 0x10000)
72#define U5500_TPIU_BASE (U5500_PER4_BASE + 0x50000)
73
74#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
75#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
76#define U5500_SPI2_BASE (U5500_PER5_BASE + 0x2000)
77#define U5500_SPI3_BASE (U5500_PER5_BASE + 0x3000)
78#define U5500_UART1_BASE (U5500_PER5_BASE + 0x4000)
79#define U5500_UART2_BASE (U5500_PER5_BASE + 0x5000)
80#define U5500_UART3_BASE (U5500_PER5_BASE + 0x6000)
81#define U5500_SDI1_BASE (U5500_PER5_BASE + 0x7000)
82#define U5500_SDI3_BASE (U5500_PER5_BASE + 0x8000)
83#define U5500_SDI4_BASE (U5500_PER5_BASE + 0x9000)
84#define U5500_I2C2_BASE (U5500_PER5_BASE + 0xA000)
85#define U5500_I2C3_BASE (U5500_PER5_BASE + 0xB000)
86#define U5500_MSP2_BASE (U5500_PER5_BASE + 0xC000)
87#define U5500_IRDA_BASE (U5500_PER5_BASE + 0xD000)
88#define U5500_IRRC_BASE (U5500_PER5_BASE + 0x10000)
89#define U5500_GPIO4_BASE (U5500_PER5_BASE + 0x1E000)
90#define U5500_CLKRST5_BASE (U5500_PER5_BASE + 0x1F000)
91
92#define U5500_RNG_BASE (U5500_PER6_BASE + 0x0000)
93#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
94#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
95#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
96#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100)
97#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
98#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
99#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
100#define U5500_CRYP0_BASE (U5500_PER6_BASE + 0xA000)
101#define U5500_CRYP1_BASE (U5500_PER6_BASE + 0xB000)
102#define U5500_CLKRST6_BASE (U5500_PER6_BASE + 0xF000)
103
104#define U5500_GPIOBANK0_BASE U5500_GPIO0_BASE
105#define U5500_GPIOBANK1_BASE (U5500_GPIO0_BASE + 0x80)
106#define U5500_GPIOBANK2_BASE U5500_GPIO1_BASE
107#define U5500_GPIOBANK3_BASE U5500_GPIO2_BASE
108#define U5500_GPIOBANK4_BASE U5500_GPIO3_BASE
109#define U5500_GPIOBANK5_BASE U5500_GPIO4_BASE
110#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80)
111#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100)
112
113#define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000)
114#define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40)
115#define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F)
116#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60)
117#define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F)
118#define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80)
119#define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F)
120#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0)
121#define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF)
122#define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00)
123#define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F)
124#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
125#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F)
126
127#define U5500_ACCCON_BASE_SEC (0xBFFF0000)
128#define U5500_ACCCON_BASE (0xBFFF1000)
129#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
130#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
131#define U5500_INTCON_MBOX1_INT_RESET_ADDR (0xBFFD31A4)
132
133#define U5500_ESRAM_BASE 0x40000000
134#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000
135#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
136
137#define U5500_MCDE_SIZE 0x1000
138#define U5500_DSI_LINK_SIZE 0x1000
139#define U5500_DSI_LINK_COUNT 0x2
140#define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE)
141#define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE)
142
143#endif
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index 8d74d927d4e2..67035223334a 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -20,10 +20,6 @@
20 * built, so that there's some hint during the build that something is wrong. 20 * built, so that there's some hint during the build that something is wrong.
21 */ 21 */
22 22
23#ifdef CONFIG_UX500_SOC_DB5500
24#define __UX500_UART(n) U5500_UART##n##_BASE
25#endif
26
27#ifdef CONFIG_UX500_SOC_DB8500 23#ifdef CONFIG_UX500_SOC_DB8500
28#define __UX500_UART(n) U8500_UART##n##_BASE 24#define __UX500_UART(n) U8500_UART##n##_BASE
29#endif 25#endif
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index 5f6cb71fc62d..9b5eb69a0154 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -10,7 +10,6 @@
10struct platform_device; 10struct platform_device;
11struct amba_device; 11struct amba_device;
12 12
13extern struct platform_device u5500_gpio_devs[];
14extern struct platform_device u8500_gpio_devs[]; 13extern struct platform_device u8500_gpio_devs[];
15 14
16extern struct amba_device ux500_pl031_device; 15extern struct amba_device ux500_pl031_device;
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 836165778a2d..808c1d6601c5 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -31,7 +31,6 @@
31#define io_p2v(n) __io_address(n) 31#define io_p2v(n) __io_address(n)
32 32
33#include <mach/db8500-regs.h> 33#include <mach/db8500-regs.h>
34#include <mach/db5500-regs.h>
35 34
36#define MSP_TX_RX_REG_OFFSET 0 35#define MSP_TX_RX_REG_OFFSET 0
37 36
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
deleted file mode 100644
index 29d972c7717b..000000000000
--- a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __MACH_IRQS_BOARD_U5500_H
8#define __MACH_IRQS_BOARD_U5500_H
9
10#define AB5500_NR_IRQS 5
11#define IRQ_AB5500_BASE IRQ_BOARD_START
12#define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS)
13
14#define U5500_IRQ_END IRQ_AB5500_END
15
16#if IRQ_BOARD_END < U5500_IRQ_END
17#undef IRQ_BOARD_END
18#define IRQ_BOARD_END U5500_IRQ_END
19#endif
20
21#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
deleted file mode 100644
index 77239776a6f2..000000000000
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#ifndef __MACH_IRQS_DB5500_H
9#define __MACH_IRQS_DB5500_H
10
11#define IRQ_DB5500_MTU0 (IRQ_SHPI_START + 4)
12#define IRQ_DB5500_SPI2 (IRQ_SHPI_START + 6)
13#define IRQ_DB5500_PMU0 (IRQ_SHPI_START + 7)
14#define IRQ_DB5500_SPI0 (IRQ_SHPI_START + 8)
15#define IRQ_DB5500_RTT (IRQ_SHPI_START + 9)
16#define IRQ_DB5500_PKA (IRQ_SHPI_START + 10)
17#define IRQ_DB5500_UART0 (IRQ_SHPI_START + 11)
18#define IRQ_DB5500_I2C3 (IRQ_SHPI_START + 12)
19#define IRQ_DB5500_L2CC (IRQ_SHPI_START + 13)
20#define IRQ_DB5500_MSP0 (IRQ_SHPI_START + 14)
21#define IRQ_DB5500_CRYP1 (IRQ_SHPI_START + 15)
22#define IRQ_DB5500_PMU1 (IRQ_SHPI_START + 16)
23#define IRQ_DB5500_MTU1 (IRQ_SHPI_START + 17)
24#define IRQ_DB5500_RTC (IRQ_SHPI_START + 18)
25#define IRQ_DB5500_UART1 (IRQ_SHPI_START + 19)
26#define IRQ_DB5500_USB_WAKEUP (IRQ_SHPI_START + 20)
27#define IRQ_DB5500_I2C0 (IRQ_SHPI_START + 21)
28#define IRQ_DB5500_I2C1 (IRQ_SHPI_START + 22)
29#define IRQ_DB5500_USBOTG (IRQ_SHPI_START + 23)
30#define IRQ_DB5500_DMA_SECURE (IRQ_SHPI_START + 24)
31#define IRQ_DB5500_DMA (IRQ_SHPI_START + 25)
32#define IRQ_DB5500_UART2 (IRQ_SHPI_START + 26)
33#define IRQ_DB5500_ICN_PMU1 (IRQ_SHPI_START + 27)
34#define IRQ_DB5500_ICN_PMU2 (IRQ_SHPI_START + 28)
35#define IRQ_DB5500_UART3 (IRQ_SHPI_START + 29)
36#define IRQ_DB5500_SPI3 (IRQ_SHPI_START + 30)
37#define IRQ_DB5500_SDMMC4 (IRQ_SHPI_START + 31)
38#define IRQ_DB5500_IRRC (IRQ_SHPI_START + 33)
39#define IRQ_DB5500_IRDA_FT (IRQ_SHPI_START + 34)
40#define IRQ_DB5500_IRDA_SD (IRQ_SHPI_START + 35)
41#define IRQ_DB5500_IRDA_FI (IRQ_SHPI_START + 36)
42#define IRQ_DB5500_IRDA_FD (IRQ_SHPI_START + 37)
43#define IRQ_DB5500_FSMC_CODEREADY (IRQ_SHPI_START + 38)
44#define IRQ_DB5500_FSMC_NANDWAIT (IRQ_SHPI_START + 39)
45#define IRQ_DB5500_AB5500 (IRQ_SHPI_START + 40)
46#define IRQ_DB5500_SDMMC2 (IRQ_SHPI_START + 41)
47#define IRQ_DB5500_SIA (IRQ_SHPI_START + 42)
48#define IRQ_DB5500_SIA2 (IRQ_SHPI_START + 43)
49#define IRQ_DB5500_HVA (IRQ_SHPI_START + 44)
50#define IRQ_DB5500_HVA2 (IRQ_SHPI_START + 45)
51#define IRQ_DB5500_PRCMU0 (IRQ_SHPI_START + 46)
52#define IRQ_DB5500_PRCMU1 (IRQ_SHPI_START + 47)
53#define IRQ_DB5500_DISP (IRQ_SHPI_START + 48)
54#define IRQ_DB5500_SDMMC1 (IRQ_SHPI_START + 50)
55#define IRQ_DB5500_MSP1 (IRQ_SHPI_START + 52)
56#define IRQ_DB5500_KBD (IRQ_SHPI_START + 53)
57#define IRQ_DB5500_I2C2 (IRQ_SHPI_START + 55)
58#define IRQ_DB5500_B2R2 (IRQ_SHPI_START + 56)
59#define IRQ_DB5500_CRYP0 (IRQ_SHPI_START + 57)
60#define IRQ_DB5500_SDMMC3 (IRQ_SHPI_START + 59)
61#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60)
62#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61)
63#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63)
64#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65)
65#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96)
66#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98)
67#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101)
68#define IRQ_DB5500_CTI0 (IRQ_SHPI_START + 108)
69#define IRQ_DB5500_CTI1 (IRQ_SHPI_START + 109)
70#define IRQ_DB5500_ICN_ERR (IRQ_SHPI_START + 110)
71#define IRQ_DB5500_MALI_PPMMU (IRQ_SHPI_START + 112)
72#define IRQ_DB5500_MALI_PP (IRQ_SHPI_START + 113)
73#define IRQ_DB5500_MALI_GPMMU (IRQ_SHPI_START + 114)
74#define IRQ_DB5500_MALI_GP (IRQ_SHPI_START + 115)
75#define IRQ_DB5500_MALI (IRQ_SHPI_START + 116)
76#define IRQ_DB5500_PRCMU_SEM (IRQ_SHPI_START + 118)
77#define IRQ_DB5500_GPIO0 (IRQ_SHPI_START + 119)
78#define IRQ_DB5500_GPIO1 (IRQ_SHPI_START + 120)
79#define IRQ_DB5500_GPIO2 (IRQ_SHPI_START + 121)
80#define IRQ_DB5500_GPIO3 (IRQ_SHPI_START + 122)
81#define IRQ_DB5500_GPIO4 (IRQ_SHPI_START + 123)
82#define IRQ_DB5500_GPIO5 (IRQ_SHPI_START + 124)
83#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125)
84#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126)
85
86#ifdef CONFIG_UX500_SOC_DB5500
87
88/*
89 * After the GPIO ones we reserve a range of IRQ:s in which virtual
90 * IRQ:s representing modem IRQ:s can be allocated
91 */
92#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START
93#define IRQ_MODEM_EVENTS_NBR 72
94#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
95
96/* List of virtual IRQ:s that are allocated from the range above */
97#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
98#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
99#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
100
101/*
102 * We may have several SoCs, but only one will run at a
103 * time, so the one with most IRQs will bump this ahead,
104 * but the IRQ_SOC_START remains the same for either SoC.
105 */
106#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END
107#undef IRQ_SOC_END
108#define IRQ_SOC_END IRQ_MODEM_EVENTS_END
109#endif
110
111#endif /* CONFIG_UX500_SOC_DB5500 */
112
113#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 7da9ec58a531..e8928548b6a3 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -36,7 +36,6 @@
36/* This will be overridden by SoC-specific irq headers */ 36/* This will be overridden by SoC-specific irq headers */
37#define IRQ_SOC_END IRQ_SOC_START 37#define IRQ_SOC_END IRQ_SOC_START
38 38
39#include <mach/irqs-db5500.h>
40#include <mach/irqs-db8500.h> 39#include <mach/irqs-db8500.h>
41 40
42#define IRQ_BOARD_START IRQ_SOC_END 41#define IRQ_BOARD_START IRQ_SOC_END
@@ -47,10 +46,6 @@
47#include <mach/irqs-board-mop500.h> 46#include <mach/irqs-board-mop500.h>
48#endif 47#endif
49 48
50#ifdef CONFIG_MACH_U5500
51#include <mach/irqs-board-u5500.h>
52#endif
53
54#define NR_IRQS IRQ_BOARD_END 49#define NR_IRQS IRQ_BOARD_END
55 50
56#endif /* ASM_ARCH_IRQS_H */ 51#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/mbox-db5500.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
deleted file mode 100644
index 7f9da4d2fbda..000000000000
--- a/arch/arm/mach-ux500/include/mach/mbox-db5500.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __INC_STE_MBOX_H
9#define __INC_STE_MBOX_H
10
11#define MBOX_BUF_SIZE 16
12#define MBOX_NAME_SIZE 8
13
14/**
15 * mbox_recv_cb_t - Definition of the mailbox callback.
16 * @mbox_msg: The mailbox message.
17 * @priv: The clients private data as specified in the call to mbox_setup.
18 *
19 * This function will be called upon reception of new mailbox messages.
20 */
21typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv);
22
23/**
24 * struct mbox - Mailbox instance struct
25 * @list: Linked list head.
26 * @pdev: Pointer to device struct.
27 * @cb: Callback function. Will be called
28 * when new data is received.
29 * @client_data: Clients private data. Will be sent back
30 * in the callback function.
31 * @virtbase_peer: Virtual address for outgoing mailbox.
32 * @virtbase_local: Virtual address for incoming mailbox.
33 * @buffer: Then internal queue for outgoing messages.
34 * @name: Name of this mailbox.
35 * @buffer_available: Completion variable to achieve "blocking send".
36 * This variable will be signaled when there is
37 * internal buffer space available.
38 * @client_blocked: To keep track if any client is currently
39 * blocked.
40 * @lock: Spinlock to protect this mailbox instance.
41 * @write_index: Index in internal buffer to write to.
42 * @read_index: Index in internal buffer to read from.
43 * @allocated: Indicates whether this particular mailbox
44 * id has been allocated by someone.
45 */
46struct mbox {
47 struct list_head list;
48 struct platform_device *pdev;
49 mbox_recv_cb_t *cb;
50 void *client_data;
51 void __iomem *virtbase_peer;
52 void __iomem *virtbase_local;
53 u32 buffer[MBOX_BUF_SIZE];
54 char name[MBOX_NAME_SIZE];
55 struct completion buffer_available;
56 u8 client_blocked;
57 spinlock_t lock;
58 u8 write_index;
59 u8 read_index;
60 bool allocated;
61};
62
63/**
64 * mbox_setup - Set up a mailbox and return its instance.
65 * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU,
66 * 2 for modem DSP.
67 * @mbox_cb: Pointer to the callback function to be called when a new message
68 * is received.
69 * @priv: Client user data which will be returned in the callback.
70 *
71 * Returns a mailbox instance to be specified in subsequent calls to mbox_send.
72 */
73struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv);
74
75/**
76 * mbox_send - Send a mailbox message.
77 * @mbox: Mailbox instance (returned by mbox_setup)
78 * @mbox_msg: The mailbox message to send.
79 * @block: Specifies whether this call will block until send is possible,
80 * or return an error if the mailbox buffer is full.
81 *
82 * Returns 0 on success or a negative error code on error. -ENOMEM indicates
83 * that the internal buffer is full and you have to try again later (or
84 * specify "block" in order to block until send is possible).
85 */
86int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block);
87
88#endif /*INC_STE_MBOX_H*/
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 3dc00ffa7bfa..4e369f1645ec 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -15,18 +15,12 @@
15#include <linux/init.h> 15#include <linux/init.h>
16 16
17void __init ux500_map_io(void); 17void __init ux500_map_io(void);
18extern void __init u5500_map_io(void);
19extern void __init u8500_map_io(void); 18extern void __init u8500_map_io(void);
20 19
21extern struct device * __init u5500_init_devices(void);
22extern struct device * __init u8500_init_devices(void); 20extern struct device * __init u8500_init_devices(void);
23 21
24extern void __init ux500_init_irq(void); 22extern void __init ux500_init_irq(void);
25 23
26extern void __init u5500_sdi_init(struct device *parent);
27
28extern void __init db5500_dma_init(struct device *parent);
29
30extern struct device *ux500_soc_device_init(const char *soc_id); 24extern struct device *ux500_soc_device_init(const char *soc_id);
31 25
32struct amba_device; 26struct amba_device;
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 6fb3c4b0105d..34775baadaea 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -50,11 +50,8 @@ static void flush(void)
50 50
51static inline void arch_decomp_setup(void) 51static inline void arch_decomp_setup(void)
52{ 52{
53 /* Check in run time if we run on an U8500 or U5500 */ 53 /* Use machine_is_foo() macro if you need to switch base someday */
54 if (machine_is_u5500()) 54 ux500_uart_base = U8500_UART2_BASE;
55 ux500_uart_base = U5500_UART0_BASE;
56 else
57 ux500_uart_base = U8500_UART2_BASE;
58} 55}
59 56
60#define arch_decomp_wdog() /* nothing to do here */ 57#define arch_decomp_wdog() /* nothing to do here */
diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c
deleted file mode 100644
index 0127490218cd..000000000000
--- a/arch/arm/mach-ux500/mbox-db5500.c
+++ /dev/null
@@ -1,565 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8/*
9 * Mailbox nomenclature:
10 *
11 * APE MODEM
12 * mbox pairX
13 * ..........................
14 * . .
15 * . peer .
16 * . send ---- .
17 * . --> | | .
18 * . | | .
19 * . ---- .
20 * . .
21 * . local .
22 * . rec ---- .
23 * . | | <-- .
24 * . | | .
25 * . ---- .
26 * .........................
27 */
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/spinlock.h>
34#include <linux/errno.h>
35#include <linux/io.h>
36#include <linux/irq.h>
37#include <linux/platform_device.h>
38#include <linux/debugfs.h>
39#include <linux/seq_file.h>
40#include <linux/completion.h>
41#include <mach/mbox-db5500.h>
42
43#define MBOX_NAME "mbox"
44
45#define MBOX_FIFO_DATA 0x000
46#define MBOX_FIFO_ADD 0x004
47#define MBOX_FIFO_REMOVE 0x008
48#define MBOX_FIFO_THRES_FREE 0x00C
49#define MBOX_FIFO_THRES_OCCUP 0x010
50#define MBOX_FIFO_STATUS 0x014
51
52#define MBOX_DISABLE_IRQ 0x4
53#define MBOX_ENABLE_IRQ 0x0
54#define MBOX_LATCH 1
55
56/* Global list of all mailboxes */
57static struct list_head mboxs = LIST_HEAD_INIT(mboxs);
58
59static struct mbox *get_mbox_with_id(u8 id)
60{
61 u8 i;
62 struct list_head *pos = &mboxs;
63 for (i = 0; i <= id; i++)
64 pos = pos->next;
65
66 return (struct mbox *) list_entry(pos, struct mbox, list);
67}
68
69int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block)
70{
71 int res = 0;
72
73 spin_lock(&mbox->lock);
74
75 dev_dbg(&(mbox->pdev->dev),
76 "About to buffer 0x%X to mailbox 0x%X."
77 " ri = %d, wi = %d\n",
78 mbox_msg, (u32)mbox, mbox->read_index,
79 mbox->write_index);
80
81 /* Check if write buffer is full */
82 while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) {
83 if (!block) {
84 dev_dbg(&(mbox->pdev->dev),
85 "Buffer full in non-blocking call! "
86 "Returning -ENOMEM!\n");
87 res = -ENOMEM;
88 goto exit;
89 }
90 spin_unlock(&mbox->lock);
91 dev_dbg(&(mbox->pdev->dev),
92 "Buffer full in blocking call! Sleeping...\n");
93 mbox->client_blocked = 1;
94 wait_for_completion(&mbox->buffer_available);
95 dev_dbg(&(mbox->pdev->dev),
96 "Blocking send was woken up! Trying again...\n");
97 spin_lock(&mbox->lock);
98 }
99
100 mbox->buffer[mbox->write_index] = mbox_msg;
101 mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE;
102
103 /*
104 * Indicate that we want an IRQ as soon as there is a slot
105 * in the FIFO
106 */
107 writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
108
109exit:
110 spin_unlock(&mbox->lock);
111 return res;
112}
113EXPORT_SYMBOL(mbox_send);
114
115#if defined(CONFIG_DEBUG_FS)
116/*
117 * Expected input: <value> <nbr sends>
118 * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times
119 */
120static ssize_t mbox_write_fifo(struct device *dev,
121 struct device_attribute *attr,
122 const char *buf,
123 size_t count)
124{
125 unsigned long mbox_mess;
126 unsigned long nbr_sends;
127 unsigned long i;
128 char int_buf[16];
129 char *token;
130 char *val;
131
132 struct mbox *mbox = (struct mbox *) dev->platform_data;
133
134 strncpy((char *) &int_buf, buf, sizeof(int_buf));
135 token = (char *) &int_buf;
136
137 /* Parse message */
138 val = strsep(&token, " ");
139 if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0))
140 mbox_mess = 0xDEADBEEF;
141
142 val = strsep(&token, " ");
143 if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0))
144 nbr_sends = 1;
145
146 dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n",
147 mbox_mess, nbr_sends, (u32) mbox);
148
149 for (i = 0; i < nbr_sends; i++)
150 mbox_send(mbox, mbox_mess, true);
151
152 return count;
153}
154
155static ssize_t mbox_read_fifo(struct device *dev,
156 struct device_attribute *attr,
157 char *buf)
158{
159 int mbox_value;
160 struct mbox *mbox = (struct mbox *) dev->platform_data;
161
162 if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0)
163 return sprintf(buf, "Mailbox is empty\n");
164
165 mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
166 writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
167
168 return sprintf(buf, "0x%X\n", mbox_value);
169}
170
171static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
172
173static int mbox_show(struct seq_file *s, void *data)
174{
175 struct list_head *pos;
176 u8 mbox_index = 0;
177
178 list_for_each(pos, &mboxs) {
179 struct mbox *m =
180 (struct mbox *) list_entry(pos, struct mbox, list);
181 if (m == NULL) {
182 seq_printf(s,
183 "Unable to retrieve mailbox %d\n",
184 mbox_index);
185 continue;
186 }
187
188 spin_lock(&m->lock);
189 if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) {
190 seq_printf(s, "MAILBOX %d not setup or corrupt\n",
191 mbox_index);
192 spin_unlock(&m->lock);
193 continue;
194 }
195
196 seq_printf(s,
197 "===========================\n"
198 " MAILBOX %d\n"
199 " PEER MAILBOX DUMP\n"
200 "---------------------------\n"
201 "FIFO: 0x%X (%d)\n"
202 "Free Threshold: 0x%.2X (%d)\n"
203 "Occupied Threshold: 0x%.2X (%d)\n"
204 "Status: 0x%.2X (%d)\n"
205 " Free spaces (ot): %d (%d)\n"
206 " Occup spaces (ot): %d (%d)\n"
207 "===========================\n"
208 " LOCAL MAILBOX DUMP\n"
209 "---------------------------\n"
210 "FIFO: 0x%.X (%d)\n"
211 "Free Threshold: 0x%.2X (%d)\n"
212 "Occupied Threshold: 0x%.2X (%d)\n"
213 "Status: 0x%.2X (%d)\n"
214 " Free spaces (ot): %d (%d)\n"
215 " Occup spaces (ot): %d (%d)\n"
216 "===========================\n"
217 "write_index: %d\n"
218 "read_index : %d\n"
219 "===========================\n"
220 "\n",
221 mbox_index,
222 readl(m->virtbase_peer + MBOX_FIFO_DATA),
223 readl(m->virtbase_peer + MBOX_FIFO_DATA),
224 readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
225 readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
226 readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
227 readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
228 readl(m->virtbase_peer + MBOX_FIFO_STATUS),
229 readl(m->virtbase_peer + MBOX_FIFO_STATUS),
230 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7,
231 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1,
232 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7,
233 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1,
234 readl(m->virtbase_local + MBOX_FIFO_DATA),
235 readl(m->virtbase_local + MBOX_FIFO_DATA),
236 readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
237 readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
238 readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
239 readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
240 readl(m->virtbase_local + MBOX_FIFO_STATUS),
241 readl(m->virtbase_local + MBOX_FIFO_STATUS),
242 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7,
243 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1,
244 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7,
245 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1,
246 m->write_index, m->read_index);
247 mbox_index++;
248 spin_unlock(&m->lock);
249 }
250
251 return 0;
252}
253
254static int mbox_open(struct inode *inode, struct file *file)
255{
256 return single_open(file, mbox_show, NULL);
257}
258
259static const struct file_operations mbox_operations = {
260 .owner = THIS_MODULE,
261 .open = mbox_open,
262 .read = seq_read,
263 .llseek = seq_lseek,
264 .release = single_release,
265};
266#endif
267
268static irqreturn_t mbox_irq(int irq, void *arg)
269{
270 u32 mbox_value;
271 int nbr_occup;
272 int nbr_free;
273 struct mbox *mbox = (struct mbox *) arg;
274
275 spin_lock(&mbox->lock);
276
277 dev_dbg(&(mbox->pdev->dev),
278 "mbox IRQ [%d] received. ri = %d, wi = %d\n",
279 irq, mbox->read_index, mbox->write_index);
280
281 /*
282 * Check if we have any outgoing messages, and if there is space for
283 * them in the FIFO.
284 */
285 if (mbox->read_index != mbox->write_index) {
286 /*
287 * Check by reading FREE for LOCAL since that indicates
288 * OCCUP for PEER
289 */
290 nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS)
291 >> 4) & 0x7;
292 dev_dbg(&(mbox->pdev->dev),
293 "Status indicates %d empty spaces in the FIFO!\n",
294 nbr_free);
295
296 while ((nbr_free > 0) &&
297 (mbox->read_index != mbox->write_index)) {
298 /* Write the message and latch it into the FIFO */
299 writel(mbox->buffer[mbox->read_index],
300 (mbox->virtbase_peer + MBOX_FIFO_DATA));
301 writel(MBOX_LATCH,
302 (mbox->virtbase_peer + MBOX_FIFO_ADD));
303 dev_dbg(&(mbox->pdev->dev),
304 "Wrote message 0x%X to addr 0x%X\n",
305 mbox->buffer[mbox->read_index],
306 (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA));
307
308 nbr_free--;
309 mbox->read_index =
310 (mbox->read_index + 1) % MBOX_BUF_SIZE;
311 }
312
313 /*
314 * Check if we still want IRQ:s when there is free
315 * space to send
316 */
317 if (mbox->read_index != mbox->write_index) {
318 dev_dbg(&(mbox->pdev->dev),
319 "Still have messages to send, but FIFO full. "
320 "Request IRQ again!\n");
321 writel(MBOX_ENABLE_IRQ,
322 mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
323 } else {
324 dev_dbg(&(mbox->pdev->dev),
325 "No more messages to send. "
326 "Do not request IRQ again!\n");
327 writel(MBOX_DISABLE_IRQ,
328 mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
329 }
330
331 /*
332 * Check if we can signal any blocked clients that it is OK to
333 * start buffering again
334 */
335 if (mbox->client_blocked &&
336 (((mbox->write_index + 1) % MBOX_BUF_SIZE)
337 != mbox->read_index)) {
338 dev_dbg(&(mbox->pdev->dev),
339 "Waking up blocked client\n");
340 complete(&mbox->buffer_available);
341 mbox->client_blocked = 0;
342 }
343 }
344
345 /* Check if we have any incoming messages */
346 nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7;
347 if (nbr_occup == 0)
348 goto exit;
349
350 if (mbox->cb == NULL) {
351 dev_dbg(&(mbox->pdev->dev), "No receive callback registered, "
352 "leaving %d incoming messages in fifo!\n", nbr_occup);
353 goto exit;
354 }
355
356 /* Read and acknowledge the message */
357 mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
358 writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
359
360 /* Notify consumer of new mailbox message */
361 dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n",
362 mbox_value);
363 mbox->cb(mbox_value, mbox->client_data);
364
365exit:
366 dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n",
367 mbox->read_index, mbox->write_index);
368 spin_unlock(&mbox->lock);
369
370 return IRQ_HANDLED;
371}
372
373/* Setup is executed once for each mbox pair */
374struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv)
375{
376 struct resource *resource;
377 int irq;
378 int res;
379 struct mbox *mbox;
380
381 mbox = get_mbox_with_id(mbox_id);
382 if (mbox == NULL) {
383 dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n",
384 mbox_id);
385 goto exit;
386 }
387
388 /*
389 * Check if mailbox has been allocated to someone else,
390 * otherwise allocate it
391 */
392 if (mbox->allocated) {
393 dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n",
394 mbox_id);
395 mbox = NULL;
396 goto exit;
397 }
398 mbox->allocated = true;
399
400 dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n",
401 mbox_id, (u32)mbox);
402
403 mbox->client_data = priv;
404 mbox->cb = mbox_cb;
405
406 /* Get addr for peer mailbox and ioremap it */
407 resource = platform_get_resource_byname(mbox->pdev,
408 IORESOURCE_MEM,
409 "mbox_peer");
410 if (resource == NULL) {
411 dev_err(&(mbox->pdev->dev),
412 "Unable to retrieve mbox peer resource\n");
413 mbox = NULL;
414 goto exit;
415 }
416 dev_dbg(&(mbox->pdev->dev),
417 "Resource name: %s start: 0x%X, end: 0x%X\n",
418 resource->name, resource->start, resource->end);
419 mbox->virtbase_peer = ioremap(resource->start, resource_size(resource));
420 if (!mbox->virtbase_peer) {
421 dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n");
422 mbox = NULL;
423 goto exit;
424 }
425 dev_dbg(&(mbox->pdev->dev),
426 "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n",
427 resource->start, resource->end, (u32) mbox->virtbase_peer);
428
429 /* Get addr for local mailbox and ioremap it */
430 resource = platform_get_resource_byname(mbox->pdev,
431 IORESOURCE_MEM,
432 "mbox_local");
433 if (resource == NULL) {
434 dev_err(&(mbox->pdev->dev),
435 "Unable to retrieve mbox local resource\n");
436 mbox = NULL;
437 goto exit;
438 }
439 dev_dbg(&(mbox->pdev->dev),
440 "Resource name: %s start: 0x%X, end: 0x%X\n",
441 resource->name, resource->start, resource->end);
442 mbox->virtbase_local = ioremap(resource->start, resource_size(resource));
443 if (!mbox->virtbase_local) {
444 dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n");
445 mbox = NULL;
446 goto exit;
447 }
448 dev_dbg(&(mbox->pdev->dev),
449 "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n",
450 resource->start, resource->end, (u32) mbox->virtbase_peer);
451
452 init_completion(&mbox->buffer_available);
453 mbox->client_blocked = 0;
454
455 /* Get IRQ for mailbox and allocate it */
456 irq = platform_get_irq_byname(mbox->pdev, "mbox_irq");
457 if (irq < 0) {
458 dev_err(&(mbox->pdev->dev),
459 "Unable to retrieve mbox irq resource\n");
460 mbox = NULL;
461 goto exit;
462 }
463
464 dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq);
465 res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox);
466 if (res < 0) {
467 dev_err(&(mbox->pdev->dev),
468 "Unable to allocate mbox irq %d\n", irq);
469 mbox = NULL;
470 goto exit;
471 }
472
473 /* Set up mailbox to not launch IRQ on free space in mailbox */
474 writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
475
476 /*
477 * Set up mailbox to launch IRQ on new message if we have
478 * a callback set. If not, do not raise IRQ, but keep message
479 * in FIFO for manual retrieval
480 */
481 if (mbox_cb != NULL)
482 writel(MBOX_ENABLE_IRQ,
483 mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
484 else
485 writel(MBOX_DISABLE_IRQ,
486 mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
487
488#if defined(CONFIG_DEBUG_FS)
489 res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo);
490 if (res != 0)
491 dev_warn(&(mbox->pdev->dev),
492 "Unable to create mbox sysfs entry");
493
494 (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL,
495 NULL, &mbox_operations);
496#endif
497
498 dev_info(&(mbox->pdev->dev),
499 "Mailbox driver with index %d initiated!\n", mbox_id);
500
501exit:
502 return mbox;
503}
504EXPORT_SYMBOL(mbox_setup);
505
506
507int __init mbox_probe(struct platform_device *pdev)
508{
509 struct mbox local_mbox;
510 struct mbox *mbox;
511 int res = 0;
512 dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev);
513
514 memset(&local_mbox, 0x0, sizeof(struct mbox));
515
516 /* Associate our mbox data with the platform device */
517 res = platform_device_add_data(pdev,
518 (void *) &local_mbox,
519 sizeof(struct mbox));
520 if (res != 0) {
521 dev_err(&(pdev->dev),
522 "Unable to allocate driver platform data!\n");
523 goto exit;
524 }
525
526 mbox = (struct mbox *) pdev->dev.platform_data;
527 mbox->pdev = pdev;
528 mbox->write_index = 0;
529 mbox->read_index = 0;
530
531 INIT_LIST_HEAD(&(mbox->list));
532 list_add_tail(&(mbox->list), &mboxs);
533
534 sprintf(mbox->name, "%s", MBOX_NAME);
535 spin_lock_init(&mbox->lock);
536
537 dev_info(&(pdev->dev), "Mailbox driver loaded\n");
538
539exit:
540 return res;
541}
542
543static struct platform_driver mbox_driver = {
544 .driver = {
545 .name = MBOX_NAME,
546 .owner = THIS_MODULE,
547 },
548};
549
550static int __init mbox_init(void)
551{
552 return platform_driver_probe(&mbox_driver, mbox_probe);
553}
554
555module_init(mbox_init);
556
557void __exit mbox_exit(void)
558{
559 platform_driver_unregister(&mbox_driver);
560}
561
562module_exit(mbox_exit);
563
564MODULE_LICENSE("GPL");
565MODULE_DESCRIPTION("MBOX driver");
diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c
deleted file mode 100644
index 6b86416c94c9..000000000000
--- a/arch/arm/mach-ux500/modem-irq-db5500.c
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/irq.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/slab.h>
14
15#include <mach/id.h>
16
17#define MODEM_INTCON_BASE_ADDR 0xBFFD3000
18#define MODEM_INTCON_SIZE 0xFFF
19
20#define DEST_IRQ41_OFFSET 0x2A4
21#define DEST_IRQ43_OFFSET 0x2AC
22#define DEST_IRQ45_OFFSET 0x2B4
23
24#define PRIO_IRQ41_OFFSET 0x6A4
25#define PRIO_IRQ43_OFFSET 0x6AC
26#define PRIO_IRQ45_OFFSET 0x6B4
27
28#define ALLOW_IRQ_OFFSET 0x104
29
30#define MODEM_INTCON_CPU_NBR 0x1
31#define MODEM_INTCON_PRIO_HIGH 0x0
32
33#define MODEM_INTCON_ALLOW_IRQ41 0x0200
34#define MODEM_INTCON_ALLOW_IRQ43 0x0800
35#define MODEM_INTCON_ALLOW_IRQ45 0x2000
36
37#define MODEM_IRQ_REG_OFFSET 0x4
38
39struct modem_irq {
40 void __iomem *modem_intcon_base;
41};
42
43
44static void setup_modem_intcon(void __iomem *modem_intcon_base)
45{
46 /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */
47 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET);
48 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET);
49 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET);
50
51 /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */
52 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET);
53 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET);
54 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET);
55
56 /* IC_ALLOW_ARRAY - IRQ enable */
57 writel(MODEM_INTCON_ALLOW_IRQ41 |
58 MODEM_INTCON_ALLOW_IRQ43 |
59 MODEM_INTCON_ALLOW_IRQ45,
60 modem_intcon_base + ALLOW_IRQ_OFFSET);
61}
62
63static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
64{
65 int real_irq;
66 int virt_irq;
67 struct modem_irq *mi = (struct modem_irq *)data;
68
69 /* Read modem side IRQ number from modem IRQ controller */
70 real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF;
71 virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq;
72
73 pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X "
74 "which will be 0x%X (%d) which translates to "
75 "virtual IRQ 0x%X (%d)!\n",
76 (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET,
77 real_irq,
78 real_irq & 0xFF,
79 real_irq & 0xFF,
80 virt_irq,
81 virt_irq);
82
83 if (virt_irq != 0)
84 generic_handle_irq(virt_irq);
85
86 pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq);
87
88 return IRQ_HANDLED;
89}
90
91static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
92{
93 irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq);
94 set_irq_flags(irq, IRQF_VALID);
95
96 pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
97}
98
99static int modem_irq_init(void)
100{
101 int err;
102 static struct irq_chip modem_irq_chip;
103 struct modem_irq *mi;
104
105 if (!cpu_is_u5500())
106 return -ENODEV;
107
108 pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n",
109 IRQ_DB5500_MODEM);
110
111 mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL);
112 if (!mi) {
113 pr_err("modem_irq: Could not allocate device\n");
114 return -ENOMEM;
115 }
116
117 mi->modem_intcon_base =
118 ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE);
119 pr_debug("modem_irq: ioremapped modem_intcon_base from "
120 "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR,
121 (u32)mi->modem_intcon_base);
122
123 setup_modem_intcon(mi->modem_intcon_base);
124
125 modem_irq_chip = dummy_irq_chip;
126 modem_irq_chip.name = "modem_irq";
127
128 /* Create the virtual IRQ:s needed */
129 create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip);
130 create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip);
131 create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip);
132
133 err = request_threaded_irq(IRQ_DB5500_MODEM, NULL,
134 modem_cpu_irq_handler, IRQF_ONESHOT,
135 "modem_irq", mi);
136 if (err)
137 pr_err("modem_irq: Could not register IRQ %d\n",
138 IRQ_DB5500_MODEM);
139
140 return 0;
141}
142
143arch_initcall(modem_irq_init);
diff --git a/arch/arm/mach-ux500/pins-db5500.h b/arch/arm/mach-ux500/pins-db5500.h
deleted file mode 100644
index bf50c21fe69d..000000000000
--- a/arch/arm/mach-ux500/pins-db5500.h
+++ /dev/null
@@ -1,620 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
6 */
7
8#ifndef __MACH_DB5500_PINS_H
9#define __MACH_DB5500_PINS_H
10
11#define GPIO0_GPIO PIN_CFG(0, GPIO)
12#define GPIO0_SM_CS3n PIN_CFG(0, ALT_A)
13
14#define GPIO1_GPIO PIN_CFG(1, GPIO)
15#define GPIO1_SM_A3 PIN_CFG(1, ALT_A)
16
17#define GPIO2_GPIO PIN_CFG(2, GPIO)
18#define GPIO2_SM_A4 PIN_CFG(2, ALT_A)
19#define GPIO2_SM_AVD PIN_CFG(2, ALT_B)
20
21#define GPIO3_GPIO PIN_CFG(3, GPIO)
22#define GPIO3_I2C1_SCL PIN_CFG(3, ALT_A)
23
24#define GPIO4_GPIO PIN_CFG(4, GPIO)
25#define GPIO4_I2C1_SDA PIN_CFG(4, ALT_A)
26
27#define GPIO5_GPIO PIN_CFG(5, GPIO)
28#define GPIO5_MC0_DAT0 PIN_CFG(5, ALT_A)
29#define GPIO5_SM_ADQ8 PIN_CFG(5, ALT_B)
30
31#define GPIO6_GPIO PIN_CFG(6, GPIO)
32#define GPIO6_MC0_DAT1 PIN_CFG(6, ALT_A)
33#define GPIO6_SM_ADQ0 PIN_CFG(6, ALT_B)
34
35#define GPIO7_GPIO PIN_CFG(7, GPIO)
36#define GPIO7_MC0_DAT2 PIN_CFG(7, ALT_A)
37#define GPIO7_SM_ADQ9 PIN_CFG(7, ALT_B)
38
39#define GPIO8_GPIO PIN_CFG(8, GPIO)
40#define GPIO8_MC0_DAT3 PIN_CFG(8, ALT_A)
41#define GPIO8_SM_ADQ1 PIN_CFG(8, ALT_B)
42
43#define GPIO9_GPIO PIN_CFG(9, GPIO)
44#define GPIO9_MC0_DAT4 PIN_CFG(9, ALT_A)
45#define GPIO9_SM_ADQ10 PIN_CFG(9, ALT_B)
46
47#define GPIO10_GPIO PIN_CFG(10, GPIO)
48#define GPIO10_MC0_DAT5 PIN_CFG(10, ALT_A)
49#define GPIO10_SM_ADQ2 PIN_CFG(10, ALT_B)
50
51#define GPIO11_GPIO PIN_CFG(11, GPIO)
52#define GPIO11_MC0_DAT6 PIN_CFG(11, ALT_A)
53#define GPIO11_SM_ADQ11 PIN_CFG(11, ALT_B)
54
55#define GPIO12_GPIO PIN_CFG(12, GPIO)
56#define GPIO12_MC0_DAT7 PIN_CFG(12, ALT_A)
57#define GPIO12_SM_ADQ3 PIN_CFG(12, ALT_B)
58
59#define GPIO13_GPIO PIN_CFG(13, GPIO)
60#define GPIO13_MC0_CMD PIN_CFG(13, ALT_A)
61#define GPIO13_SM_BUSY0n PIN_CFG(13, ALT_B)
62#define GPIO13_SM_WAIT0n PIN_CFG(13, ALT_C)
63
64#define GPIO14_GPIO PIN_CFG(14, GPIO)
65#define GPIO14_MC0_CLK PIN_CFG(14, ALT_A)
66#define GPIO14_SM_CS1n PIN_CFG(14, ALT_B)
67#define GPIO14_SM_CKO PIN_CFG(14, ALT_C)
68
69#define GPIO15_GPIO PIN_CFG(15, GPIO)
70#define GPIO15_SM_A5 PIN_CFG(15, ALT_A)
71#define GPIO15_SM_CLE PIN_CFG(15, ALT_B)
72
73#define GPIO16_GPIO PIN_CFG(16, GPIO)
74#define GPIO16_MC2_CMD PIN_CFG(16, ALT_A)
75#define GPIO16_SM_OEn PIN_CFG(16, ALT_B)
76
77#define GPIO17_GPIO PIN_CFG(17, GPIO)
78#define GPIO17_MC2_CLK PIN_CFG(17, ALT_A)
79#define GPIO17_SM_WEn PIN_CFG(17, ALT_B)
80
81#define GPIO18_GPIO PIN_CFG(18, GPIO)
82#define GPIO18_SM_A6 PIN_CFG(18, ALT_A)
83#define GPIO18_SM_ALE PIN_CFG(18, ALT_B)
84#define GPIO18_SM_AVDn PIN_CFG(18, ALT_C)
85
86#define GPIO19_GPIO PIN_CFG(19, GPIO)
87#define GPIO19_MC2_DAT1 PIN_CFG(19, ALT_A)
88#define GPIO19_SM_ADQ4 PIN_CFG(19, ALT_B)
89
90#define GPIO20_GPIO PIN_CFG(20, GPIO)
91#define GPIO20_MC2_DAT3 PIN_CFG(20, ALT_A)
92#define GPIO20_SM_ADQ5 PIN_CFG(20, ALT_B)
93
94#define GPIO21_GPIO PIN_CFG(21, GPIO)
95#define GPIO21_MC2_DAT5 PIN_CFG(21, ALT_A)
96#define GPIO21_SM_ADQ6 PIN_CFG(21, ALT_B)
97
98#define GPIO22_GPIO PIN_CFG(22, GPIO)
99#define GPIO22_MC2_DAT7 PIN_CFG(22, ALT_A)
100#define GPIO22_SM_ADQ7 PIN_CFG(22, ALT_B)
101
102#define GPIO23_GPIO PIN_CFG(23, GPIO)
103#define GPIO23_MC2_DAT0 PIN_CFG(23, ALT_A)
104#define GPIO23_SM_ADQ12 PIN_CFG(23, ALT_B)
105#define GPIO23_MC0_DAT1 PIN_CFG(23, ALT_C)
106
107#define GPIO24_GPIO PIN_CFG(24, GPIO)
108#define GPIO24_MC2_DAT2 PIN_CFG(24, ALT_A)
109#define GPIO24_SM_ADQ13 PIN_CFG(24, ALT_B)
110#define GPIO24_MC0_DAT3 PIN_CFG(24, ALT_C)
111
112#define GPIO25_GPIO PIN_CFG(25, GPIO)
113#define GPIO25_MC2_DAT4 PIN_CFG(25, ALT_A)
114#define GPIO25_SM_ADQ14 PIN_CFG(25, ALT_B)
115#define GPIO25_MC0_CMD PIN_CFG(25, ALT_C)
116
117#define GPIO26_GPIO PIN_CFG(26, GPIO)
118#define GPIO26_MC2_DAT6 PIN_CFG(26, ALT_A)
119#define GPIO26_SM_ADQ15 PIN_CFG(26, ALT_B)
120
121#define GPIO27_GPIO PIN_CFG(27, GPIO)
122#define GPIO27_SM_CS0n PIN_CFG(27, ALT_A)
123#define GPIO27_SM_PS0n PIN_CFG(27, ALT_B)
124
125#define GPIO28_GPIO PIN_CFG(28, GPIO)
126#define GPIO28_U0_TXD PIN_CFG(28, ALT_A)
127#define GPIO28_SM_A0 PIN_CFG(28, ALT_B)
128
129#define GPIO29_GPIO PIN_CFG(29, GPIO)
130#define GPIO29_U0_RXD PIN_CFG(29, ALT_A)
131#define GPIO29_SM_A1 PIN_CFG(29, ALT_B)
132#define GPIO29_PWM_0 PIN_CFG(29, ALT_C)
133
134#define GPIO30_GPIO PIN_CFG(30, GPIO)
135#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
136#define GPIO30_SM_A2 PIN_CFG(30, ALT_B)
137#define GPIO30_PWM_1 PIN_CFG(30, ALT_C)
138
139#define GPIO31_GPIO PIN_CFG(31, GPIO)
140#define GPIO31_MC0_DAT7 PIN_CFG(31, ALT_A)
141#define GPIO31_SM_CS2n PIN_CFG(31, ALT_B)
142#define GPIO31_PWM_2 PIN_CFG(31, ALT_C)
143
144#define GPIO32_GPIO PIN_CFG(32, GPIO)
145#define GPIO32_MSP0_TCK PIN_CFG(32, ALT_A)
146#define GPIO32_ACCI2S0_SCK PIN_CFG(32, ALT_B)
147
148#define GPIO33_GPIO PIN_CFG(33, GPIO)
149#define GPIO33_MSP0_TFS PIN_CFG(33, ALT_A)
150#define GPIO33_ACCI2S0_WS PIN_CFG(33, ALT_B)
151
152#define GPIO34_GPIO PIN_CFG(34, GPIO)
153#define GPIO34_MSP0_TXD PIN_CFG(34, ALT_A)
154#define GPIO34_ACCI2S0_DLD PIN_CFG(34, ALT_B)
155
156#define GPIO35_GPIO PIN_CFG(35, GPIO)
157#define GPIO35_MSP0_RXD PIN_CFG(35, ALT_A)
158#define GPIO35_ACCI2S0_ULD PIN_CFG(35, ALT_B)
159
160#define GPIO64_GPIO PIN_CFG(64, GPIO)
161#define GPIO64_USB_DAT0 PIN_CFG(64, ALT_A)
162#define GPIO64_U0_TXD PIN_CFG(64, ALT_B)
163
164#define GPIO65_GPIO PIN_CFG(65, GPIO)
165#define GPIO65_USB_DAT1 PIN_CFG(65, ALT_A)
166#define GPIO65_U0_RXD PIN_CFG(65, ALT_B)
167
168#define GPIO66_GPIO PIN_CFG(66, GPIO)
169#define GPIO66_USB_DAT2 PIN_CFG(66, ALT_A)
170
171#define GPIO67_GPIO PIN_CFG(67, GPIO)
172#define GPIO67_USB_DAT3 PIN_CFG(67, ALT_A)
173
174#define GPIO68_GPIO PIN_CFG(68, GPIO)
175#define GPIO68_USB_DAT4 PIN_CFG(68, ALT_A)
176
177#define GPIO69_GPIO PIN_CFG(69, GPIO)
178#define GPIO69_USB_DAT5 PIN_CFG(69, ALT_A)
179
180#define GPIO70_GPIO PIN_CFG(70, GPIO)
181#define GPIO70_USB_DAT6 PIN_CFG(70, ALT_A)
182
183#define GPIO71_GPIO PIN_CFG(71, GPIO)
184#define GPIO71_USB_DAT7 PIN_CFG(71, ALT_A)
185
186#define GPIO72_GPIO PIN_CFG(72, GPIO)
187#define GPIO72_USB_STP PIN_CFG(72, ALT_A)
188
189#define GPIO73_GPIO PIN_CFG(73, GPIO)
190#define GPIO73_USB_DIR PIN_CFG(73, ALT_A)
191
192#define GPIO74_GPIO PIN_CFG(74, GPIO)
193#define GPIO74_USB_NXT PIN_CFG(74, ALT_A)
194
195#define GPIO75_GPIO PIN_CFG(75, GPIO)
196#define GPIO75_USB_XCLK PIN_CFG(75, ALT_A)
197
198#define GPIO76_GPIO PIN_CFG(76, GPIO)
199
200#define GPIO77_GPIO PIN_CFG(77, GPIO)
201#define GPIO77_ACCTX_ON PIN_CFG(77, ALT_A)
202
203#define GPIO78_GPIO PIN_CFG(78, GPIO)
204#define GPIO78_IRQn PIN_CFG(78, ALT_A)
205
206#define GPIO79_GPIO PIN_CFG(79, GPIO)
207#define GPIO79_ACCSIM_Clk PIN_CFG(79, ALT_A)
208
209#define GPIO80_GPIO PIN_CFG(80, GPIO)
210#define GPIO80_ACCSIM_Da PIN_CFG(80, ALT_A)
211
212#define GPIO81_GPIO PIN_CFG(81, GPIO)
213#define GPIO81_ACCSIM_Reset PIN_CFG(81, ALT_A)
214
215#define GPIO82_GPIO PIN_CFG(82, GPIO)
216#define GPIO82_ACCSIM_DDir PIN_CFG(82, ALT_A)
217
218#define GPIO96_GPIO PIN_CFG(96, GPIO)
219#define GPIO96_MSP1_TCK PIN_CFG(96, ALT_A)
220#define GPIO96_PRCMU_DEBUG3 PIN_CFG(96, ALT_B)
221#define GPIO96_PRCMU_DEBUG7 PIN_CFG(96, ALT_C)
222
223#define GPIO97_GPIO PIN_CFG(97, GPIO)
224#define GPIO97_MSP1_TFS PIN_CFG(97, ALT_A)
225#define GPIO97_PRCMU_DEBUG2 PIN_CFG(97, ALT_B)
226#define GPIO97_PRCMU_DEBUG6 PIN_CFG(97, ALT_C)
227
228#define GPIO98_GPIO PIN_CFG(98, GPIO)
229#define GPIO98_MSP1_TXD PIN_CFG(98, ALT_A)
230#define GPIO98_PRCMU_DEBUG1 PIN_CFG(98, ALT_B)
231#define GPIO98_PRCMU_DEBUG5 PIN_CFG(98, ALT_C)
232
233#define GPIO99_GPIO PIN_CFG(99, GPIO)
234#define GPIO99_MSP1_RXD PIN_CFG(99, ALT_A)
235#define GPIO99_PRCMU_DEBUG0 PIN_CFG(99, ALT_B)
236#define GPIO99_PRCMU_DEBUG4 PIN_CFG(99, ALT_C)
237
238#define GPIO100_GPIO PIN_CFG(100, GPIO)
239#define GPIO100_I2C0_SCL PIN_CFG(100, ALT_A)
240
241#define GPIO101_GPIO PIN_CFG(101, GPIO)
242#define GPIO101_I2C0_SDA PIN_CFG(101, ALT_A)
243
244#define GPIO128_GPIO PIN_CFG(128, GPIO)
245#define GPIO128_KP_I0 PIN_CFG(128, ALT_A)
246#define GPIO128_BUSMON_D0 PIN_CFG(128, ALT_B)
247
248#define GPIO129_GPIO PIN_CFG(129, GPIO)
249#define GPIO129_KP_O0 PIN_CFG(129, ALT_A)
250#define GPIO129_BUSMON_D1 PIN_CFG(129, ALT_B)
251
252#define GPIO130_GPIO PIN_CFG(130, GPIO)
253#define GPIO130_KP_I1 PIN_CFG(130, ALT_A)
254#define GPIO130_BUSMON_D2 PIN_CFG(130, ALT_B)
255
256#define GPIO131_GPIO PIN_CFG(131, GPIO)
257#define GPIO131_KP_O1 PIN_CFG(131, ALT_A)
258#define GPIO131_BUSMON_D3 PIN_CFG(131, ALT_B)
259
260#define GPIO132_GPIO PIN_CFG(132, GPIO)
261#define GPIO132_KP_I2 PIN_CFG(132, ALT_A)
262#define GPIO132_ETM_D15 PIN_CFG(132, ALT_B)
263#define GPIO132_STMAPE_CLK PIN_CFG(132, ALT_C)
264
265#define GPIO133_GPIO PIN_CFG(133, GPIO)
266#define GPIO133_KP_O2 PIN_CFG(133, ALT_A)
267#define GPIO133_ETM_D14 PIN_CFG(133, ALT_B)
268#define GPIO133_U0_RXD PIN_CFG(133, ALT_C)
269
270#define GPIO134_GPIO PIN_CFG(134, GPIO)
271#define GPIO134_KP_I3 PIN_CFG(134, ALT_A)
272#define GPIO134_ETM_D13 PIN_CFG(134, ALT_B)
273#define GPIO134_STMAPE_DAT0 PIN_CFG(134, ALT_C)
274
275#define GPIO135_GPIO PIN_CFG(135, GPIO)
276#define GPIO135_KP_O3 PIN_CFG(135, ALT_A)
277#define GPIO135_ETM_D12 PIN_CFG(135, ALT_B)
278#define GPIO135_STMAPE_DAT1 PIN_CFG(135, ALT_C)
279
280#define GPIO136_GPIO PIN_CFG(136, GPIO)
281#define GPIO136_KP_I4 PIN_CFG(136, ALT_A)
282#define GPIO136_ETM_D11 PIN_CFG(136, ALT_B)
283#define GPIO136_STMAPE_DAT2 PIN_CFG(136, ALT_C)
284
285#define GPIO137_GPIO PIN_CFG(137, GPIO)
286#define GPIO137_KP_O4 PIN_CFG(137, ALT_A)
287#define GPIO137_ETM_D10 PIN_CFG(137, ALT_B)
288#define GPIO137_STMAPE_DAT3 PIN_CFG(137, ALT_C)
289
290#define GPIO138_GPIO PIN_CFG(138, GPIO)
291#define GPIO138_KP_I5 PIN_CFG(138, ALT_A)
292#define GPIO138_ETM_D9 PIN_CFG(138, ALT_B)
293#define GPIO138_U0_TXD PIN_CFG(138, ALT_C)
294
295#define GPIO139_GPIO PIN_CFG(139, GPIO)
296#define GPIO139_KP_O5 PIN_CFG(139, ALT_A)
297#define GPIO139_ETM_D8 PIN_CFG(139, ALT_B)
298#define GPIO139_BUSMON_D11 PIN_CFG(139, ALT_C)
299
300#define GPIO140_GPIO PIN_CFG(140, GPIO)
301#define GPIO140_KP_I6 PIN_CFG(140, ALT_A)
302#define GPIO140_ETM_D7 PIN_CFG(140, ALT_B)
303#define GPIO140_STMAPE_CLK PIN_CFG(140, ALT_C)
304
305#define GPIO141_GPIO PIN_CFG(141, GPIO)
306#define GPIO141_KP_O6 PIN_CFG(141, ALT_A)
307#define GPIO141_ETM_D6 PIN_CFG(141, ALT_B)
308#define GPIO141_U0_RXD PIN_CFG(141, ALT_C)
309
310#define GPIO142_GPIO PIN_CFG(142, GPIO)
311#define GPIO142_KP_I7 PIN_CFG(142, ALT_A)
312#define GPIO142_ETM_D5 PIN_CFG(142, ALT_B)
313#define GPIO142_STMAPE_DAT0 PIN_CFG(142, ALT_C)
314
315#define GPIO143_GPIO PIN_CFG(143, GPIO)
316#define GPIO143_KP_O7 PIN_CFG(143, ALT_A)
317#define GPIO143_ETM_D4 PIN_CFG(143, ALT_B)
318#define GPIO143_STMAPE_DAT1 PIN_CFG(143, ALT_C)
319
320#define GPIO144_GPIO PIN_CFG(144, GPIO)
321#define GPIO144_I2C3_SCL PIN_CFG(144, ALT_A)
322#define GPIO144_ETM_D3 PIN_CFG(144, ALT_B)
323#define GPIO144_STMAPE_DAT2 PIN_CFG(144, ALT_C)
324
325#define GPIO145_GPIO PIN_CFG(145, GPIO)
326#define GPIO145_I2C3_SDA PIN_CFG(145, ALT_A)
327#define GPIO145_ETM_D2 PIN_CFG(145, ALT_B)
328#define GPIO145_STMAPE_DAT3 PIN_CFG(145, ALT_C)
329
330#define GPIO146_GPIO PIN_CFG(146, GPIO)
331#define GPIO146_PWM_0 PIN_CFG(146, ALT_A)
332#define GPIO146_ETM_D1 PIN_CFG(146, ALT_B)
333
334#define GPIO147_GPIO PIN_CFG(147, GPIO)
335#define GPIO147_PWM_1 PIN_CFG(147, ALT_A)
336#define GPIO147_ETM_D0 PIN_CFG(147, ALT_B)
337
338#define GPIO148_GPIO PIN_CFG(148, GPIO)
339#define GPIO148_PWM_2 PIN_CFG(148, ALT_A)
340#define GPIO148_ETM_CLK PIN_CFG(148, ALT_B)
341
342#define GPIO160_GPIO PIN_CFG(160, GPIO)
343#define GPIO160_CLKOUT_REQn PIN_CFG(160, ALT_A)
344
345#define GPIO161_GPIO PIN_CFG(161, GPIO)
346#define GPIO161_CLKOUT_0 PIN_CFG(161, ALT_A)
347
348#define GPIO162_GPIO PIN_CFG(162, GPIO)
349#define GPIO162_CLKOUT_1 PIN_CFG(162, ALT_A)
350
351#define GPIO163_GPIO PIN_CFG(163, GPIO)
352
353#define GPIO164_GPIO PIN_CFG(164, GPIO)
354#define GPIO164_GPS_START PIN_CFG(164, ALT_A)
355
356#define GPIO165_GPIO PIN_CFG(165, GPIO)
357#define GPIO165_SPI1_CS2n PIN_CFG(165, ALT_A)
358#define GPIO165_U3_RXD PIN_CFG(165, ALT_B)
359#define GPIO165_BUSMON_D20 PIN_CFG(165, ALT_C)
360
361#define GPIO166_GPIO PIN_CFG(166, GPIO)
362#define GPIO166_SPI1_CS1n PIN_CFG(166, ALT_A)
363#define GPIO166_U3_TXD PIN_CFG(166, ALT_B)
364#define GPIO166_BUSMON_D21 PIN_CFG(166, ALT_C)
365
366#define GPIO167_GPIO PIN_CFG(167, GPIO)
367#define GPIO167_SPI1_CS0n PIN_CFG(167, ALT_A)
368#define GPIO167_U3_RTSn PIN_CFG(167, ALT_B)
369#define GPIO167_BUSMON_D22 PIN_CFG(167, ALT_C)
370
371#define GPIO168_GPIO PIN_CFG(168, GPIO)
372#define GPIO168_SPI1_RXD PIN_CFG(168, ALT_A)
373#define GPIO168_U3_CTSn PIN_CFG(168, ALT_B)
374#define GPIO168_BUSMON_D23 PIN_CFG(168, ALT_C)
375
376#define GPIO169_GPIO PIN_CFG(169, GPIO)
377#define GPIO169_SPI1_TXD PIN_CFG(169, ALT_A)
378#define GPIO169_DDR_RC PIN_CFG(169, ALT_B)
379#define GPIO169_BUSMON_D24 PIN_CFG(169, ALT_C)
380
381#define GPIO170_GPIO PIN_CFG(170, GPIO)
382#define GPIO170_SPI1_CLK PIN_CFG(170, ALT_A)
383
384#define GPIO171_GPIO PIN_CFG(171, GPIO)
385#define GPIO171_MC3_DAT0 PIN_CFG(171, ALT_A)
386#define GPIO171_SPI3_RXD PIN_CFG(171, ALT_B)
387#define GPIO171_BUSMON_D25 PIN_CFG(171, ALT_C)
388
389#define GPIO172_GPIO PIN_CFG(172, GPIO)
390#define GPIO172_MC3_DAT1 PIN_CFG(172, ALT_A)
391#define GPIO172_SPI3_CS1n PIN_CFG(172, ALT_B)
392#define GPIO172_BUSMON_D26 PIN_CFG(172, ALT_C)
393
394#define GPIO173_GPIO PIN_CFG(173, GPIO)
395#define GPIO173_MC3_DAT2 PIN_CFG(173, ALT_A)
396#define GPIO173_SPI3_CS2n PIN_CFG(173, ALT_B)
397#define GPIO173_BUSMON_D27 PIN_CFG(173, ALT_C)
398
399#define GPIO174_GPIO PIN_CFG(174, GPIO)
400#define GPIO174_MC3_DAT3 PIN_CFG(174, ALT_A)
401#define GPIO174_SPI3_CS0n PIN_CFG(174, ALT_B)
402#define GPIO174_BUSMON_D28 PIN_CFG(174, ALT_C)
403
404#define GPIO175_GPIO PIN_CFG(175, GPIO)
405#define GPIO175_MC3_CMD PIN_CFG(175, ALT_A)
406#define GPIO175_SPI3_TXD PIN_CFG(175, ALT_B)
407#define GPIO175_BUSMON_D29 PIN_CFG(175, ALT_C)
408
409#define GPIO176_GPIO PIN_CFG(176, GPIO)
410#define GPIO176_MC3_CLK PIN_CFG(176, ALT_A)
411#define GPIO176_SPI3_CLK PIN_CFG(176, ALT_B)
412
413#define GPIO177_GPIO PIN_CFG(177, GPIO)
414#define GPIO177_U2_RXD PIN_CFG(177, ALT_A)
415#define GPIO177_I2C3_SCL PIN_CFG(177, ALT_B)
416#define GPIO177_BUSMON_D30 PIN_CFG(177, ALT_C)
417
418#define GPIO178_GPIO PIN_CFG(178, GPIO)
419#define GPIO178_U2_TXD PIN_CFG(178, ALT_A)
420#define GPIO178_I2C3_SDA PIN_CFG(178, ALT_B)
421#define GPIO178_BUSMON_D31 PIN_CFG(178, ALT_C)
422
423#define GPIO179_GPIO PIN_CFG(179, GPIO)
424#define GPIO179_U2_CTSn PIN_CFG(179, ALT_A)
425#define GPIO179_U3_RXD PIN_CFG(179, ALT_B)
426#define GPIO179_BUSMON_D32 PIN_CFG(179, ALT_C)
427
428#define GPIO180_GPIO PIN_CFG(180, GPIO)
429#define GPIO180_U2_RTSn PIN_CFG(180, ALT_A)
430#define GPIO180_U3_TXD PIN_CFG(180, ALT_B)
431#define GPIO180_BUSMON_D33 PIN_CFG(180, ALT_C)
432
433#define GPIO185_GPIO PIN_CFG(185, GPIO)
434#define GPIO185_SPI3_CS2n PIN_CFG(185, ALT_A)
435#define GPIO185_MC4_DAT0 PIN_CFG(185, ALT_B)
436
437#define GPIO186_GPIO PIN_CFG(186, GPIO)
438#define GPIO186_SPI3_CS1n PIN_CFG(186, ALT_A)
439#define GPIO186_MC4_DAT1 PIN_CFG(186, ALT_B)
440
441#define GPIO187_GPIO PIN_CFG(187, GPIO)
442#define GPIO187_SPI3_CS0n PIN_CFG(187, ALT_A)
443#define GPIO187_MC4_DAT2 PIN_CFG(187, ALT_B)
444
445#define GPIO188_GPIO PIN_CFG(188, GPIO)
446#define GPIO188_SPI3_RXD PIN_CFG(188, ALT_A)
447#define GPIO188_MC4_DAT3 PIN_CFG(188, ALT_B)
448
449#define GPIO189_GPIO PIN_CFG(189, GPIO)
450#define GPIO189_SPI3_TXD PIN_CFG(189, ALT_A)
451#define GPIO189_MC4_CMD PIN_CFG(189, ALT_B)
452
453#define GPIO190_GPIO PIN_CFG(190, GPIO)
454#define GPIO190_SPI3_CLK PIN_CFG(190, ALT_A)
455#define GPIO190_MC4_CLK PIN_CFG(190, ALT_B)
456
457#define GPIO191_GPIO PIN_CFG(191, GPIO)
458#define GPIO191_MC1_DAT0 PIN_CFG(191, ALT_A)
459#define GPIO191_MC4_DAT4 PIN_CFG(191, ALT_B)
460#define GPIO191_STMAPE_DAT0 PIN_CFG(191, ALT_C)
461
462#define GPIO192_GPIO PIN_CFG(192, GPIO)
463#define GPIO192_MC1_DAT1 PIN_CFG(192, ALT_A)
464#define GPIO192_MC4_DAT5 PIN_CFG(192, ALT_B)
465#define GPIO192_STMAPE_DAT1 PIN_CFG(192, ALT_C)
466
467#define GPIO193_GPIO PIN_CFG(193, GPIO)
468#define GPIO193_MC1_DAT2 PIN_CFG(193, ALT_A)
469#define GPIO193_MC4_DAT6 PIN_CFG(193, ALT_B)
470#define GPIO193_STMAPE_DAT2 PIN_CFG(193, ALT_C)
471
472#define GPIO194_GPIO PIN_CFG(194, GPIO)
473#define GPIO194_MC1_DAT3 PIN_CFG(194, ALT_A)
474#define GPIO194_MC4_DAT7 PIN_CFG(194, ALT_B)
475#define GPIO194_STMAPE_DAT3 PIN_CFG(194, ALT_C)
476
477#define GPIO195_GPIO PIN_CFG(195, GPIO)
478#define GPIO195_MC1_CLK PIN_CFG(195, ALT_A)
479#define GPIO195_STMAPE_CLK PIN_CFG(195, ALT_B)
480#define GPIO195_BUSMON_CLK PIN_CFG(195, ALT_C)
481
482#define GPIO196_GPIO PIN_CFG(196, GPIO)
483#define GPIO196_MC1_CMD PIN_CFG(196, ALT_A)
484#define GPIO196_U0_RXD PIN_CFG(196, ALT_B)
485#define GPIO196_BUSMON_D38 PIN_CFG(196, ALT_C)
486
487#define GPIO197_GPIO PIN_CFG(197, GPIO)
488#define GPIO197_MC1_CMDDIR PIN_CFG(197, ALT_A)
489#define GPIO197_BUSMON_D39 PIN_CFG(197, ALT_B)
490
491#define GPIO198_GPIO PIN_CFG(198, GPIO)
492#define GPIO198_MC1_FBCLK PIN_CFG(198, ALT_A)
493
494#define GPIO199_GPIO PIN_CFG(199, GPIO)
495#define GPIO199_MC1_DAT0DIR PIN_CFG(199, ALT_A)
496#define GPIO199_BUSMON_D40 PIN_CFG(199, ALT_B)
497
498#define GPIO200_GPIO PIN_CFG(200, GPIO)
499#define GPIO200_U1_TXD PIN_CFG(200, ALT_A)
500#define GPIO200_ACCU0_RTSn PIN_CFG(200, ALT_B)
501
502#define GPIO201_GPIO PIN_CFG(201, GPIO)
503#define GPIO201_U1_RXD PIN_CFG(201, ALT_A)
504#define GPIO201_ACCU0_CTSn PIN_CFG(201, ALT_B)
505
506#define GPIO202_GPIO PIN_CFG(202, GPIO)
507#define GPIO202_U1_CTSn PIN_CFG(202, ALT_A)
508#define GPIO202_ACCU0_RXD PIN_CFG(202, ALT_B)
509
510#define GPIO203_GPIO PIN_CFG(203, GPIO)
511#define GPIO203_U1_RTSn PIN_CFG(203, ALT_A)
512#define GPIO203_ACCU0_TXD PIN_CFG(203, ALT_B)
513
514#define GPIO204_GPIO PIN_CFG(204, GPIO)
515#define GPIO204_SPI0_CS2n PIN_CFG(204, ALT_A)
516#define GPIO204_ACCGPIO_000 PIN_CFG(204, ALT_B)
517#define GPIO204_LCD_VSI1 PIN_CFG(204, ALT_C)
518
519#define GPIO205_GPIO PIN_CFG(205, GPIO)
520#define GPIO205_SPI0_CS1n PIN_CFG(205, ALT_A)
521#define GPIO205_ACCGPIO_001 PIN_CFG(205, ALT_B)
522#define GPIO205_LCD_D3 PIN_CFG(205, ALT_C)
523
524#define GPIO206_GPIO PIN_CFG(206, GPIO)
525#define GPIO206_SPI0_CS0n PIN_CFG(206, ALT_A)
526#define GPIO206_ACCGPIO_002 PIN_CFG(206, ALT_B)
527#define GPIO206_LCD_D2 PIN_CFG(206, ALT_C)
528
529#define GPIO207_GPIO PIN_CFG(207, GPIO)
530#define GPIO207_SPI0_RXD PIN_CFG(207, ALT_A)
531#define GPIO207_ACCGPIO_003 PIN_CFG(207, ALT_B)
532#define GPIO207_LCD_D1 PIN_CFG(207, ALT_C)
533
534#define GPIO208_GPIO PIN_CFG(208, GPIO)
535#define GPIO208_SPI0_TXD PIN_CFG(208, ALT_A)
536#define GPIO208_ACCGPIO_004 PIN_CFG(208, ALT_B)
537#define GPIO208_LCD_D0 PIN_CFG(208, ALT_C)
538
539#define GPIO209_GPIO PIN_CFG(209, GPIO)
540#define GPIO209_SPI0_CLK PIN_CFG(209, ALT_A)
541#define GPIO209_ACCGPIO_005 PIN_CFG(209, ALT_B)
542#define GPIO209_LCD_CLK PIN_CFG(209, ALT_C)
543
544#define GPIO210_GPIO PIN_CFG(210, GPIO)
545#define GPIO210_LCD_VSO PIN_CFG(210, ALT_A)
546#define GPIO210_PRCMU_PWRCTRL1 PIN_CFG(210, ALT_B)
547
548#define GPIO211_GPIO PIN_CFG(211, GPIO)
549#define GPIO211_LCD_VSI0 PIN_CFG(211, ALT_A)
550#define GPIO211_PRCMU_PWRCTRL2 PIN_CFG(211, ALT_B)
551
552#define GPIO212_GPIO PIN_CFG(212, GPIO)
553#define GPIO212_SPI2_CS2n PIN_CFG(212, ALT_A)
554#define GPIO212_LCD_HSO PIN_CFG(212, ALT_B)
555
556#define GPIO213_GPIO PIN_CFG(213, GPIO)
557#define GPIO213_SPI2_CS1n PIN_CFG(213, ALT_A)
558#define GPIO213_LCD_DE PIN_CFG(213, ALT_B)
559#define GPIO213_BUSMON_D16 PIN_CFG(213, ALT_C)
560
561#define GPIO214_GPIO PIN_CFG(214, GPIO)
562#define GPIO214_SPI2_CS0n PIN_CFG(214, ALT_A)
563#define GPIO214_LCD_D7 PIN_CFG(214, ALT_B)
564#define GPIO214_BUSMON_D17 PIN_CFG(214, ALT_C)
565
566#define GPIO215_GPIO PIN_CFG(215, GPIO)
567#define GPIO215_SPI2_RXD PIN_CFG(215, ALT_A)
568#define GPIO215_LCD_D6 PIN_CFG(215, ALT_B)
569#define GPIO215_BUSMON_D18 PIN_CFG(215, ALT_C)
570
571#define GPIO216_GPIO PIN_CFG(216, GPIO)
572#define GPIO216_SPI2_CLK PIN_CFG(216, ALT_A)
573#define GPIO216_LCD_D5 PIN_CFG(216, ALT_B)
574
575#define GPIO217_GPIO PIN_CFG(217, GPIO)
576#define GPIO217_SPI2_TXD PIN_CFG(217, ALT_A)
577#define GPIO217_LCD_D4 PIN_CFG(217, ALT_B)
578#define GPIO217_BUSMON_D19 PIN_CFG(217, ALT_C)
579
580#define GPIO218_GPIO PIN_CFG(218, GPIO)
581#define GPIO218_I2C2_SCL PIN_CFG(218, ALT_A)
582#define GPIO218_LCD_VSO PIN_CFG(218, ALT_B)
583
584#define GPIO219_GPIO PIN_CFG(219, GPIO)
585#define GPIO219_I2C2_SDA PIN_CFG(219, ALT_A)
586#define GPIO219_LCD_D3 PIN_CFG(219, ALT_B)
587
588#define GPIO220_GPIO PIN_CFG(220, GPIO)
589#define GPIO220_MSP2_TCK PIN_CFG(220, ALT_A)
590#define GPIO220_LCD_D2 PIN_CFG(220, ALT_B)
591
592#define GPIO221_GPIO PIN_CFG(221, GPIO)
593#define GPIO221_MSP2_TFS PIN_CFG(221, ALT_A)
594#define GPIO221_LCD_D1 PIN_CFG(221, ALT_B)
595
596#define GPIO222_GPIO PIN_CFG(222, GPIO)
597#define GPIO222_MSP2_TXD PIN_CFG(222, ALT_A)
598#define GPIO222_LCD_D0 PIN_CFG(222, ALT_B)
599
600#define GPIO223_GPIO PIN_CFG(223, GPIO)
601#define GPIO223_MSP2_RXD PIN_CFG(223, ALT_A)
602#define GPIO223_LCD_CLK PIN_CFG(223, ALT_B)
603
604#define GPIO224_GPIO PIN_CFG(224, GPIO)
605#define GPIO224_PRCMU_PWRCTRL0 PIN_CFG(224, ALT_A)
606#define GPIO224_LCD_VSI1 PIN_CFG(224, ALT_B)
607
608#define GPIO225_GPIO PIN_CFG(225, GPIO)
609#define GPIO225_PRCMU_PWRCTRL1 PIN_CFG(225, ALT_A)
610#define GPIO225_IRDA_RXD PIN_CFG(225, ALT_B)
611
612#define GPIO226_GPIO PIN_CFG(226, GPIO)
613#define GPIO226_PRCMU_PWRCTRL2 PIN_CFG(226, ALT_A)
614#define GPIO226_IRRC_DAT PIN_CFG(226, ALT_B)
615
616#define GPIO227_GPIO PIN_CFG(227, GPIO)
617#define GPIO227_IRRC_DAT PIN_CFG(227, ALT_A)
618#define GPIO227_IRDA_TXD PIN_CFG(227, ALT_B)
619
620#endif
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index f499a0703928..da1d5ad5bd45 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -48,9 +48,7 @@ static void write_pen_release(int val)
48 48
49static void __iomem *scu_base_addr(void) 49static void __iomem *scu_base_addr(void)
50{ 50{
51 if (cpu_is_u5500()) 51 if (cpu_is_u8500_family())
52 return __io_address(U5500_SCU_BASE);
53 else if (cpu_is_u8500_family())
54 return __io_address(U8500_SCU_BASE); 52 return __io_address(U8500_SCU_BASE);
55 else 53 else
56 ux500_unknown_soc(); 54 ux500_unknown_soc();
@@ -120,9 +118,7 @@ static void __init wakeup_secondary(void)
120{ 118{
121 void __iomem *backupram; 119 void __iomem *backupram;
122 120
123 if (cpu_is_u5500()) 121 if (cpu_is_u8500_family())
124 backupram = __io_address(U5500_BACKUPRAM0_BASE);
125 else if (cpu_is_u8500_family())
126 backupram = __io_address(U8500_BACKUPRAM0_BASE); 122 backupram = __io_address(U8500_BACKUPRAM0_BASE);
127 else 123 else
128 ux500_unknown_soc(); 124 ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h
deleted file mode 100644
index cb2110c32858..000000000000
--- a/arch/arm/mach-ux500/ste-dma40-db5500.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * DB5500-SoC-specific configuration for DMA40
8 */
9
10#ifndef STE_DMA40_DB5500_H
11#define STE_DMA40_DB5500_H
12
13#define DB5500_DMA_NR_DEV 64
14
15enum dma_src_dev_type {
16 DB5500_DMA_DEV0_SPI0_RX = 0,
17 DB5500_DMA_DEV1_SPI1_RX = 1,
18 DB5500_DMA_DEV2_SPI2_RX = 2,
19 DB5500_DMA_DEV3_SPI3_RX = 3,
20 DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4,
21 DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5,
22 DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6,
23 DB5500_DMA_DEV7_IRDA_RFS = 7,
24 DB5500_DMA_DEV8_IRDA_FIFO_RX = 8,
25 DB5500_DMA_DEV9_MSP0_RX = 9,
26 DB5500_DMA_DEV10_MSP1_RX = 10,
27 DB5500_DMA_DEV11_MSP2_RX = 11,
28 DB5500_DMA_DEV12_UART0_RX = 12,
29 DB5500_DMA_DEV13_UART1_RX = 13,
30 DB5500_DMA_DEV14_UART2_RX = 14,
31 DB5500_DMA_DEV15_UART3_RX = 15,
32 DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16,
33 DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17,
34 DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18,
35 DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19,
36 DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20,
37 DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21,
38 DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22,
39 DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23,
40 DB5500_DMA_DEV24_SDMMC0_RX = 24,
41 DB5500_DMA_DEV25_SDMMC1_RX = 25,
42 DB5500_DMA_DEV26_SDMMC2_RX = 26,
43 DB5500_DMA_DEV27_SDMMC3_RX = 27,
44 DB5500_DMA_DEV28_SDMMC4_RX = 28,
45 /* 29 - 32 not used */
46 DB5500_DMA_DEV33_SDMMC0_RX = 33,
47 DB5500_DMA_DEV34_SDMMC1_RX = 34,
48 DB5500_DMA_DEV35_SDMMC2_RX = 35,
49 DB5500_DMA_DEV36_SDMMC3_RX = 36,
50 DB5500_DMA_DEV37_SDMMC4_RX = 37,
51 DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38,
52 DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39,
53 DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40,
54 DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41,
55 DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42,
56 DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43,
57 DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44,
58 DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45,
59 /* 46 not used */
60 DB5500_DMA_DEV47_MCDE_RX = 47,
61 DB5500_DMA_DEV48_CRYPTO1_RX = 48,
62 /* 49, 50 not used */
63 DB5500_DMA_DEV49_I2C1_RX = 51,
64 DB5500_DMA_DEV50_I2C3_RX = 52,
65 DB5500_DMA_DEV51_I2C2_RX = 53,
66 /* 54 - 60 not used */
67 DB5500_DMA_DEV61_CRYPTO0_RX = 61,
68 /* 62, 63 not used */
69};
70
71enum dma_dest_dev_type {
72 DB5500_DMA_DEV0_SPI0_TX = 0,
73 DB5500_DMA_DEV1_SPI1_TX = 1,
74 DB5500_DMA_DEV2_SPI2_TX = 2,
75 DB5500_DMA_DEV3_SPI3_TX = 3,
76 DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4,
77 DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5,
78 DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6,
79 DB5500_DMA_DEV7_IRRC_TX = 7,
80 DB5500_DMA_DEV8_IRDA_FIFO_TX = 8,
81 DB5500_DMA_DEV9_MSP0_TX = 9,
82 DB5500_DMA_DEV10_MSP1_TX = 10,
83 DB5500_DMA_DEV11_MSP2_TX = 11,
84 DB5500_DMA_DEV12_UART0_TX = 12,
85 DB5500_DMA_DEV13_UART1_TX = 13,
86 DB5500_DMA_DEV14_UART2_TX = 14,
87 DB5500_DMA_DEV15_UART3_TX = 15,
88 DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16,
89 DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17,
90 DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18,
91 DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19,
92 DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20,
93 DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21,
94 DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22,
95 DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23,
96 DB5500_DMA_DEV24_SDMMC0_TX = 24,
97 DB5500_DMA_DEV25_SDMMC1_TX = 25,
98 DB5500_DMA_DEV26_SDMMC2_TX = 26,
99 DB5500_DMA_DEV27_SDMMC3_TX = 27,
100 DB5500_DMA_DEV28_SDMMC4_TX = 28,
101 /* 29 - 31 not used */
102 DB5500_DMA_DEV32_FSMC_TX = 32,
103 DB5500_DMA_DEV33_SDMMC0_TX = 33,
104 DB5500_DMA_DEV34_SDMMC1_TX = 34,
105 DB5500_DMA_DEV35_SDMMC2_TX = 35,
106 DB5500_DMA_DEV36_SDMMC3_TX = 36,
107 DB5500_DMA_DEV37_SDMMC4_TX = 37,
108 DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38,
109 DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39,
110 DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40,
111 DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41,
112 DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42,
113 DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43,
114 DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44,
115 DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45,
116 /* 46 not used */
117 DB5500_DMA_DEV47_STM_TX = 47,
118 DB5500_DMA_DEV48_CRYPTO1_TX = 48,
119 DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49,
120 DB5500_DMA_DEV50_HASH1_TX = 50,
121 DB5500_DMA_DEV51_I2C1_TX = 51,
122 DB5500_DMA_DEV52_I2C3_TX = 52,
123 DB5500_DMA_DEV53_I2C2_TX = 53,
124 /* 54, 55 not used */
125 DB5500_DMA_MEMCPY_TX_1 = 56,
126 DB5500_DMA_MEMCPY_TX_2 = 57,
127 DB5500_DMA_MEMCPY_TX_3 = 58,
128 DB5500_DMA_MEMCPY_TX_4 = 59,
129 DB5500_DMA_MEMCPY_TX_5 = 60,
130 DB5500_DMA_DEV61_CRYPTO0_TX = 61,
131 DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62,
132 DB5500_DMA_DEV63_HASH0_TX = 63,
133};
134
135#endif
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 3bfbfdf833c6..e263076bb119 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -18,8 +18,6 @@
18#include <mach/irqs.h> 18#include <mach/irqs.h>
19 19
20#ifdef CONFIG_HAVE_ARM_TWD 20#ifdef CONFIG_HAVE_ARM_TWD
21static DEFINE_TWD_LOCAL_TIMER(u5500_twd_local_timer,
22 U5500_TWD_BASE, IRQ_LOCALTIMER);
23static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer, 21static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
24 U8500_TWD_BASE, IRQ_LOCALTIMER); 22 U8500_TWD_BASE, IRQ_LOCALTIMER);
25 23
@@ -28,8 +26,8 @@ static void __init ux500_twd_init(void)
28 struct twd_local_timer *twd_local_timer; 26 struct twd_local_timer *twd_local_timer;
29 int err; 27 int err;
30 28
31 twd_local_timer = cpu_is_u5500() ? &u5500_twd_local_timer : 29 /* Use this to switch local timer base if changed in new ASICs */
32 &u8500_twd_local_timer; 30 twd_local_timer = &u8500_twd_local_timer;
33 31
34 if (of_have_populated_dt()) 32 if (of_have_populated_dt())
35 twd_local_timer_of_register(); 33 twd_local_timer_of_register();
@@ -48,10 +46,7 @@ static void __init ux500_timer_init(void)
48 void __iomem *mtu_timer_base; 46 void __iomem *mtu_timer_base;
49 void __iomem *prcmu_timer_base; 47 void __iomem *prcmu_timer_base;
50 48
51 if (cpu_is_u5500()) { 49 if (cpu_is_u8500_family()) {
52 mtu_timer_base = __io_address(U5500_MTU0_BASE);
53 prcmu_timer_base = __io_address(U5500_PRCMU_TIMER_3_BASE);
54 } else if (cpu_is_u8500_family()) {
55 mtu_timer_base = __io_address(U8500_MTU0_BASE); 50 mtu_timer_base = __io_address(U8500_MTU0_BASE);
56 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE); 51 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
57 } else { 52 } else {
@@ -70,7 +65,7 @@ static void __init ux500_timer_init(void)
70 * depending on delay which is not yet calibrated. RTC-RTT is in the 65 * depending on delay which is not yet calibrated. RTC-RTT is in the
71 * always-on powerdomain and is used as clockevent instead of twd when 66 * always-on powerdomain and is used as clockevent instead of twd when
72 * sleeping. 67 * sleeping.
73 * The PRCMU timer 4(3 for DB5500) register a clocksource and 68 * The PRCMU timer 4 register a clocksource and
74 * sched_clock with higher rating then MTU since is always-on. 69 * sched_clock with higher rating then MTU since is always-on.
75 * 70 *
76 */ 71 */
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 5138927a416c..99c6b203e6cd 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -18,7 +18,7 @@ config DW_APB_TIMER
18 18
19config CLKSRC_DBX500_PRCMU 19config CLKSRC_DBX500_PRCMU
20 bool "Clocksource PRCMU Timer" 20 bool "Clocksource PRCMU Timer"
21 depends on UX500_SOC_DB5500 || UX500_SOC_DB8500 21 depends on UX500_SOC_DB8500
22 default y 22 default y
23 help 23 help
24 Use the always on PRCMU Timer as clocksource 24 Use the always on PRCMU Timer as clocksource
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 11e44386fa9b..d875bfa56ad5 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -648,23 +648,6 @@ config EZX_PCAP
648 This enables the PCAP ASIC present on EZX Phones. This is 648 This enables the PCAP ASIC present on EZX Phones. This is
649 needed for MMC, TouchScreen, Sound, USB, etc.. 649 needed for MMC, TouchScreen, Sound, USB, etc..
650 650
651config AB5500_CORE
652 bool "ST-Ericsson AB5500 Mixed Signal Power Management chip"
653 depends on ABX500_CORE && MFD_DB5500_PRCMU
654 select MFD_CORE
655 help
656 Select this option to enable access to AB5500 power management
657 chip. This connects to the db5500 chip via the I2C bus via PRCMU.
658 This chip embeds various other multimedia funtionalities as well.
659
660config AB5500_DEBUG
661 bool "Enable debug info via debugfs"
662 depends on AB5500_CORE && DEBUG_FS
663 default y if DEBUG_FS
664 help
665 Select this option if you want debug information from the AB5500
666 using the debug filesystem, debugfs.
667
668config AB8500_CORE 651config AB8500_CORE
669 bool "ST-Ericsson AB8500 Mixed Signal Power Management chip" 652 bool "ST-Ericsson AB8500 Mixed Signal Power Management chip"
670 depends on GENERIC_HARDIRQS && ABX500_CORE 653 depends on GENERIC_HARDIRQS && ABX500_CORE
@@ -711,16 +694,6 @@ config MFD_DB8500_PRCMU
711 system controller running an XP70 microprocessor, which is accessed 694 system controller running an XP70 microprocessor, which is accessed
712 through a register map. 695 through a register map.
713 696
714config MFD_DB5500_PRCMU
715 bool "ST-Ericsson DB5500 Power Reset Control Management Unit"
716 depends on UX500_SOC_DB5500
717 select MFD_CORE
718 help
719 Select this option to enable support for the DB5500 Power Reset
720 and Control Management Unit. This is basically an autonomous
721 system controller running an XP70 microprocessor, which is accessed
722 through a register map.
723
724config MFD_CS5535 697config MFD_CS5535
725 tristate "Support for CS5535 and CS5536 southbridge core functions" 698 tristate "Support for CS5535 and CS5536 southbridge core functions"
726 select MFD_CORE 699 select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 05fa538c5efe..669ba7d85a36 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -87,15 +87,12 @@ obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
87obj-$(CONFIG_ABX500_CORE) += abx500-core.o 87obj-$(CONFIG_ABX500_CORE) += abx500-core.o
88obj-$(CONFIG_AB3100_CORE) += ab3100-core.o 88obj-$(CONFIG_AB3100_CORE) += ab3100-core.o
89obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o 89obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o
90obj-$(CONFIG_AB5500_CORE) += ab5500-core.o
91obj-$(CONFIG_AB5500_DEBUG) += ab5500-debugfs.o
92obj-$(CONFIG_AB8500_CORE) += ab8500-core.o ab8500-sysctrl.o 90obj-$(CONFIG_AB8500_CORE) += ab8500-core.o ab8500-sysctrl.o
93obj-$(CONFIG_AB8500_DEBUG) += ab8500-debugfs.o 91obj-$(CONFIG_AB8500_DEBUG) += ab8500-debugfs.o
94obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o 92obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o
95obj-$(CONFIG_MFD_DB8500_PRCMU) += db8500-prcmu.o 93obj-$(CONFIG_MFD_DB8500_PRCMU) += db8500-prcmu.o
96# ab8500-i2c need to come after db8500-prcmu (which provides the channel) 94# ab8500-i2c need to come after db8500-prcmu (which provides the channel)
97obj-$(CONFIG_AB8500_I2C_CORE) += ab8500-i2c.o 95obj-$(CONFIG_AB8500_I2C_CORE) += ab8500-i2c.o
98obj-$(CONFIG_MFD_DB5500_PRCMU) += db5500-prcmu.o
99obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o 96obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o
100obj-$(CONFIG_PMIC_ADP5520) += adp5520.o 97obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
101obj-$(CONFIG_LPC_SCH) += lpc_sch.o 98obj-$(CONFIG_LPC_SCH) += lpc_sch.o
diff --git a/drivers/mfd/ab5500-core.c b/drivers/mfd/ab5500-core.c
deleted file mode 100644
index 54d0fe40845f..000000000000
--- a/drivers/mfd/ab5500-core.c
+++ /dev/null
@@ -1,1439 +0,0 @@
1/*
2 * Copyright (C) 2007-2011 ST-Ericsson
3 * License terms: GNU General Public License (GPL) version 2
4 * Low-level core for exclusive access to the AB5500 IC on the I2C bus
5 * and some basic chip-configuration.
6 * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
7 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
8 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
9 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
10 * Author: Karl Komierowski <karl.komierowski@stericsson.com>
11 * Author: Bibek Basu <bibek.basu@stericsson.com>
12 *
13 * TODO: Event handling with irq_chip. Waiting for PRCMU fw support.
14 */
15
16#include <linux/module.h>
17#include <linux/mutex.h>
18#include <linux/err.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/device.h>
22#include <linux/irq.h>
23#include <linux/interrupt.h>
24#include <linux/random.h>
25#include <linux/mfd/abx500.h>
26#include <linux/mfd/abx500/ab5500.h>
27#include <linux/list.h>
28#include <linux/bitops.h>
29#include <linux/spinlock.h>
30#include <linux/mfd/core.h>
31#include <linux/mfd/db5500-prcmu.h>
32
33#include "ab5500-core.h"
34#include "ab5500-debugfs.h"
35
36#define AB5500_NUM_EVENT_REG 23
37#define AB5500_IT_LATCH0_REG 0x40
38#define AB5500_IT_MASK0_REG 0x60
39
40/*
41 * Permissible register ranges for reading and writing per device and bank.
42 *
43 * The ranges must be listed in increasing address order, and no overlaps are
44 * allowed. It is assumed that write permission implies read permission
45 * (i.e. only RO and RW permissions should be used). Ranges with write
46 * permission must not be split up.
47 */
48
49#define NO_RANGE {.count = 0, .range = NULL,}
50static struct ab5500_i2c_banks ab5500_bank_ranges[AB5500_NUM_DEVICES] = {
51 [AB5500_DEVID_USB] = {
52 .nbanks = 1,
53 .bank = (struct ab5500_i2c_ranges []) {
54 {
55 .bankid = AB5500_BANK_USB,
56 .nranges = 12,
57 .range = (struct ab5500_reg_range[]) {
58 {
59 .first = 0x01,
60 .last = 0x01,
61 .perm = AB5500_PERM_RW,
62 },
63 {
64 .first = 0x80,
65 .last = 0x83,
66 .perm = AB5500_PERM_RW,
67 },
68 {
69 .first = 0x87,
70 .last = 0x8A,
71 .perm = AB5500_PERM_RW,
72 },
73 {
74 .first = 0x8B,
75 .last = 0x8B,
76 .perm = AB5500_PERM_RO,
77 },
78 {
79 .first = 0x91,
80 .last = 0x92,
81 .perm = AB5500_PERM_RO,
82 },
83 {
84 .first = 0x93,
85 .last = 0x93,
86 .perm = AB5500_PERM_RW,
87 },
88 {
89 .first = 0x94,
90 .last = 0x94,
91 .perm = AB5500_PERM_RO,
92 },
93 {
94 .first = 0xA8,
95 .last = 0xB0,
96 .perm = AB5500_PERM_RO,
97 },
98 {
99 .first = 0xB2,
100 .last = 0xB2,
101 .perm = AB5500_PERM_RO,
102 },
103 {
104 .first = 0xB4,
105 .last = 0xBC,
106 .perm = AB5500_PERM_RO,
107 },
108 {
109 .first = 0xBF,
110 .last = 0xBF,
111 .perm = AB5500_PERM_RO,
112 },
113 {
114 .first = 0xC1,
115 .last = 0xC5,
116 .perm = AB5500_PERM_RO,
117 },
118 },
119 },
120 },
121 },
122 [AB5500_DEVID_ADC] = {
123 .nbanks = 1,
124 .bank = (struct ab5500_i2c_ranges []) {
125 {
126 .bankid = AB5500_BANK_ADC,
127 .nranges = 6,
128 .range = (struct ab5500_reg_range[]) {
129 {
130 .first = 0x1F,
131 .last = 0x22,
132 .perm = AB5500_PERM_RO,
133 },
134 {
135 .first = 0x23,
136 .last = 0x24,
137 .perm = AB5500_PERM_RW,
138 },
139 {
140 .first = 0x26,
141 .last = 0x2D,
142 .perm = AB5500_PERM_RO,
143 },
144 {
145 .first = 0x2F,
146 .last = 0x34,
147 .perm = AB5500_PERM_RW,
148 },
149 {
150 .first = 0x37,
151 .last = 0x57,
152 .perm = AB5500_PERM_RW,
153 },
154 {
155 .first = 0x58,
156 .last = 0x58,
157 .perm = AB5500_PERM_RO,
158 },
159 },
160 },
161 },
162 },
163 [AB5500_DEVID_LEDS] = {
164 .nbanks = 1,
165 .bank = (struct ab5500_i2c_ranges []) {
166 {
167 .bankid = AB5500_BANK_LED,
168 .nranges = 1,
169 .range = (struct ab5500_reg_range[]) {
170 {
171 .first = 0x00,
172 .last = 0x0C,
173 .perm = AB5500_PERM_RW,
174 },
175 },
176 },
177 },
178 },
179 [AB5500_DEVID_VIDEO] = {
180 .nbanks = 1,
181 .bank = (struct ab5500_i2c_ranges []) {
182 {
183 .bankid = AB5500_BANK_VDENC,
184 .nranges = 12,
185 .range = (struct ab5500_reg_range[]) {
186 {
187 .first = 0x00,
188 .last = 0x08,
189 .perm = AB5500_PERM_RW,
190 },
191 {
192 .first = 0x09,
193 .last = 0x09,
194 .perm = AB5500_PERM_RO,
195 },
196 {
197 .first = 0x0A,
198 .last = 0x12,
199 .perm = AB5500_PERM_RW,
200 },
201 {
202 .first = 0x15,
203 .last = 0x19,
204 .perm = AB5500_PERM_RW,
205 },
206 {
207 .first = 0x1B,
208 .last = 0x21,
209 .perm = AB5500_PERM_RW,
210 },
211 {
212 .first = 0x27,
213 .last = 0x2C,
214 .perm = AB5500_PERM_RW,
215 },
216 {
217 .first = 0x41,
218 .last = 0x41,
219 .perm = AB5500_PERM_RW,
220 },
221 {
222 .first = 0x45,
223 .last = 0x5B,
224 .perm = AB5500_PERM_RW,
225 },
226 {
227 .first = 0x5D,
228 .last = 0x5D,
229 .perm = AB5500_PERM_RW,
230 },
231 {
232 .first = 0x69,
233 .last = 0x69,
234 .perm = AB5500_PERM_RW,
235 },
236 {
237 .first = 0x6C,
238 .last = 0x6D,
239 .perm = AB5500_PERM_RW,
240 },
241 {
242 .first = 0x80,
243 .last = 0x81,
244 .perm = AB5500_PERM_RW,
245 },
246 },
247 },
248 },
249 },
250 [AB5500_DEVID_REGULATORS] = {
251 .nbanks = 2,
252 .bank = (struct ab5500_i2c_ranges []) {
253 {
254 .bankid = AB5500_BANK_STARTUP,
255 .nranges = 12,
256 .range = (struct ab5500_reg_range[]) {
257 {
258 .first = 0x00,
259 .last = 0x01,
260 .perm = AB5500_PERM_RW,
261 },
262 {
263 .first = 0x1F,
264 .last = 0x1F,
265 .perm = AB5500_PERM_RW,
266 },
267 {
268 .first = 0x2E,
269 .last = 0x2E,
270 .perm = AB5500_PERM_RO,
271 },
272 {
273 .first = 0x2F,
274 .last = 0x30,
275 .perm = AB5500_PERM_RW,
276 },
277 {
278 .first = 0x50,
279 .last = 0x51,
280 .perm = AB5500_PERM_RW,
281 },
282 {
283 .first = 0x60,
284 .last = 0x61,
285 .perm = AB5500_PERM_RW,
286 },
287 {
288 .first = 0x66,
289 .last = 0x8A,
290 .perm = AB5500_PERM_RW,
291 },
292 {
293 .first = 0x8C,
294 .last = 0x96,
295 .perm = AB5500_PERM_RW,
296 },
297 {
298 .first = 0xAA,
299 .last = 0xB4,
300 .perm = AB5500_PERM_RW,
301 },
302 {
303 .first = 0xB7,
304 .last = 0xBF,
305 .perm = AB5500_PERM_RW,
306 },
307 {
308 .first = 0xC1,
309 .last = 0xCA,
310 .perm = AB5500_PERM_RW,
311 },
312 {
313 .first = 0xD3,
314 .last = 0xE0,
315 .perm = AB5500_PERM_RW,
316 },
317 },
318 },
319 {
320 .bankid = AB5500_BANK_SIM_USBSIM,
321 .nranges = 1,
322 .range = (struct ab5500_reg_range[]) {
323 {
324 .first = 0x13,
325 .last = 0x19,
326 .perm = AB5500_PERM_RW,
327 },
328 },
329 },
330 },
331 },
332 [AB5500_DEVID_SIM] = {
333 .nbanks = 1,
334 .bank = (struct ab5500_i2c_ranges []) {
335 {
336 .bankid = AB5500_BANK_SIM_USBSIM,
337 .nranges = 1,
338 .range = (struct ab5500_reg_range[]) {
339 {
340 .first = 0x13,
341 .last = 0x19,
342 .perm = AB5500_PERM_RW,
343 },
344 },
345 },
346 },
347 },
348 [AB5500_DEVID_RTC] = {
349 .nbanks = 1,
350 .bank = (struct ab5500_i2c_ranges []) {
351 {
352 .bankid = AB5500_BANK_RTC,
353 .nranges = 2,
354 .range = (struct ab5500_reg_range[]) {
355 {
356 .first = 0x00,
357 .last = 0x04,
358 .perm = AB5500_PERM_RW,
359 },
360 {
361 .first = 0x06,
362 .last = 0x0C,
363 .perm = AB5500_PERM_RW,
364 },
365 },
366 },
367 },
368 },
369 [AB5500_DEVID_CHARGER] = {
370 .nbanks = 1,
371 .bank = (struct ab5500_i2c_ranges []) {
372 {
373 .bankid = AB5500_BANK_CHG,
374 .nranges = 2,
375 .range = (struct ab5500_reg_range[]) {
376 {
377 .first = 0x11,
378 .last = 0x11,
379 .perm = AB5500_PERM_RO,
380 },
381 {
382 .first = 0x12,
383 .last = 0x1B,
384 .perm = AB5500_PERM_RW,
385 },
386 },
387 },
388 },
389 },
390 [AB5500_DEVID_FUELGAUGE] = {
391 .nbanks = 1,
392 .bank = (struct ab5500_i2c_ranges []) {
393 {
394 .bankid = AB5500_BANK_FG_BATTCOM_ACC,
395 .nranges = 2,
396 .range = (struct ab5500_reg_range[]) {
397 {
398 .first = 0x00,
399 .last = 0x0B,
400 .perm = AB5500_PERM_RO,
401 },
402 {
403 .first = 0x0C,
404 .last = 0x10,
405 .perm = AB5500_PERM_RW,
406 },
407 },
408 },
409 },
410 },
411 [AB5500_DEVID_VIBRATOR] = {
412 .nbanks = 1,
413 .bank = (struct ab5500_i2c_ranges []) {
414 {
415 .bankid = AB5500_BANK_VIBRA,
416 .nranges = 2,
417 .range = (struct ab5500_reg_range[]) {
418 {
419 .first = 0x10,
420 .last = 0x13,
421 .perm = AB5500_PERM_RW,
422 },
423 {
424 .first = 0xFE,
425 .last = 0xFE,
426 .perm = AB5500_PERM_RW,
427 },
428 },
429 },
430 },
431 },
432 [AB5500_DEVID_CODEC] = {
433 .nbanks = 1,
434 .bank = (struct ab5500_i2c_ranges []) {
435 {
436 .bankid = AB5500_BANK_AUDIO_HEADSETUSB,
437 .nranges = 2,
438 .range = (struct ab5500_reg_range[]) {
439 {
440 .first = 0x00,
441 .last = 0x48,
442 .perm = AB5500_PERM_RW,
443 },
444 {
445 .first = 0xEB,
446 .last = 0xFB,
447 .perm = AB5500_PERM_RW,
448 },
449 },
450 },
451 },
452 },
453 [AB5500_DEVID_POWER] = {
454 .nbanks = 2,
455 .bank = (struct ab5500_i2c_ranges []) {
456 {
457 .bankid = AB5500_BANK_STARTUP,
458 .nranges = 1,
459 .range = (struct ab5500_reg_range[]) {
460 {
461 .first = 0x30,
462 .last = 0x30,
463 .perm = AB5500_PERM_RW,
464 },
465 },
466 },
467 {
468 .bankid = AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP,
469 .nranges = 1,
470 .range = (struct ab5500_reg_range[]) {
471 {
472 .first = 0x01,
473 .last = 0x01,
474 .perm = AB5500_PERM_RW,
475 },
476 },
477 },
478 },
479 },
480};
481
482#define AB5500_IRQ(bank, bit) ((bank) * 8 + (bit))
483
484/* I appologize for the resource names beeing a mix of upper case
485 * and lower case but I want them to be exact as the documentation */
486static struct mfd_cell ab5500_devs[AB5500_NUM_DEVICES] = {
487 [AB5500_DEVID_LEDS] = {
488 .name = "ab5500-leds",
489 .id = AB5500_DEVID_LEDS,
490 },
491 [AB5500_DEVID_POWER] = {
492 .name = "ab5500-power",
493 .id = AB5500_DEVID_POWER,
494 },
495 [AB5500_DEVID_REGULATORS] = {
496 .name = "ab5500-regulator",
497 .id = AB5500_DEVID_REGULATORS,
498 },
499 [AB5500_DEVID_SIM] = {
500 .name = "ab5500-sim",
501 .id = AB5500_DEVID_SIM,
502 .num_resources = 1,
503 .resources = (struct resource[]) {
504 {
505 .name = "SIMOFF",
506 .flags = IORESOURCE_IRQ,
507 .start = AB5500_IRQ(2, 0), /*rising*/
508 .end = AB5500_IRQ(2, 1), /*falling*/
509 },
510 },
511 },
512 [AB5500_DEVID_RTC] = {
513 .name = "ab5500-rtc",
514 .id = AB5500_DEVID_RTC,
515 .num_resources = 1,
516 .resources = (struct resource[]) {
517 {
518 .name = "RTC_Alarm",
519 .flags = IORESOURCE_IRQ,
520 .start = AB5500_IRQ(1, 7),
521 .end = AB5500_IRQ(1, 7),
522 }
523 },
524 },
525 [AB5500_DEVID_CHARGER] = {
526 .name = "ab5500-charger",
527 .id = AB5500_DEVID_CHARGER,
528 },
529 [AB5500_DEVID_ADC] = {
530 .name = "ab5500-adc",
531 .id = AB5500_DEVID_ADC,
532 .num_resources = 10,
533 .resources = (struct resource[]) {
534 {
535 .name = "TRIGGER-0",
536 .flags = IORESOURCE_IRQ,
537 .start = AB5500_IRQ(0, 0),
538 .end = AB5500_IRQ(0, 0),
539 },
540 {
541 .name = "TRIGGER-1",
542 .flags = IORESOURCE_IRQ,
543 .start = AB5500_IRQ(0, 1),
544 .end = AB5500_IRQ(0, 1),
545 },
546 {
547 .name = "TRIGGER-2",
548 .flags = IORESOURCE_IRQ,
549 .start = AB5500_IRQ(0, 2),
550 .end = AB5500_IRQ(0, 2),
551 },
552 {
553 .name = "TRIGGER-3",
554 .flags = IORESOURCE_IRQ,
555 .start = AB5500_IRQ(0, 3),
556 .end = AB5500_IRQ(0, 3),
557 },
558 {
559 .name = "TRIGGER-4",
560 .flags = IORESOURCE_IRQ,
561 .start = AB5500_IRQ(0, 4),
562 .end = AB5500_IRQ(0, 4),
563 },
564 {
565 .name = "TRIGGER-5",
566 .flags = IORESOURCE_IRQ,
567 .start = AB5500_IRQ(0, 5),
568 .end = AB5500_IRQ(0, 5),
569 },
570 {
571 .name = "TRIGGER-6",
572 .flags = IORESOURCE_IRQ,
573 .start = AB5500_IRQ(0, 6),
574 .end = AB5500_IRQ(0, 6),
575 },
576 {
577 .name = "TRIGGER-7",
578 .flags = IORESOURCE_IRQ,
579 .start = AB5500_IRQ(0, 7),
580 .end = AB5500_IRQ(0, 7),
581 },
582 {
583 .name = "TRIGGER-VBAT",
584 .flags = IORESOURCE_IRQ,
585 .start = AB5500_IRQ(0, 8),
586 .end = AB5500_IRQ(0, 8),
587 },
588 {
589 .name = "TRIGGER-VBAT-TXON",
590 .flags = IORESOURCE_IRQ,
591 .start = AB5500_IRQ(0, 9),
592 .end = AB5500_IRQ(0, 9),
593 },
594 },
595 },
596 [AB5500_DEVID_FUELGAUGE] = {
597 .name = "ab5500-fuelgauge",
598 .id = AB5500_DEVID_FUELGAUGE,
599 .num_resources = 6,
600 .resources = (struct resource[]) {
601 {
602 .name = "Batt_attach",
603 .flags = IORESOURCE_IRQ,
604 .start = AB5500_IRQ(7, 5),
605 .end = AB5500_IRQ(7, 5),
606 },
607 {
608 .name = "Batt_removal",
609 .flags = IORESOURCE_IRQ,
610 .start = AB5500_IRQ(7, 6),
611 .end = AB5500_IRQ(7, 6),
612 },
613 {
614 .name = "UART_framing",
615 .flags = IORESOURCE_IRQ,
616 .start = AB5500_IRQ(7, 7),
617 .end = AB5500_IRQ(7, 7),
618 },
619 {
620 .name = "UART_overrun",
621 .flags = IORESOURCE_IRQ,
622 .start = AB5500_IRQ(8, 0),
623 .end = AB5500_IRQ(8, 0),
624 },
625 {
626 .name = "UART_Rdy_RX",
627 .flags = IORESOURCE_IRQ,
628 .start = AB5500_IRQ(8, 1),
629 .end = AB5500_IRQ(8, 1),
630 },
631 {
632 .name = "UART_Rdy_TX",
633 .flags = IORESOURCE_IRQ,
634 .start = AB5500_IRQ(8, 2),
635 .end = AB5500_IRQ(8, 2),
636 },
637 },
638 },
639 [AB5500_DEVID_VIBRATOR] = {
640 .name = "ab5500-vibrator",
641 .id = AB5500_DEVID_VIBRATOR,
642 },
643 [AB5500_DEVID_CODEC] = {
644 .name = "ab5500-codec",
645 .id = AB5500_DEVID_CODEC,
646 .num_resources = 3,
647 .resources = (struct resource[]) {
648 {
649 .name = "audio_spkr1_ovc",
650 .flags = IORESOURCE_IRQ,
651 .start = AB5500_IRQ(9, 5),
652 .end = AB5500_IRQ(9, 5),
653 },
654 {
655 .name = "audio_plllocked",
656 .flags = IORESOURCE_IRQ,
657 .start = AB5500_IRQ(9, 6),
658 .end = AB5500_IRQ(9, 6),
659 },
660 {
661 .name = "audio_spkr2_ovc",
662 .flags = IORESOURCE_IRQ,
663 .start = AB5500_IRQ(17, 4),
664 .end = AB5500_IRQ(17, 4),
665 },
666 },
667 },
668 [AB5500_DEVID_USB] = {
669 .name = "ab5500-usb",
670 .id = AB5500_DEVID_USB,
671 .num_resources = 36,
672 .resources = (struct resource[]) {
673 {
674 .name = "Link_Update",
675 .flags = IORESOURCE_IRQ,
676 .start = AB5500_IRQ(22, 1),
677 .end = AB5500_IRQ(22, 1),
678 },
679 {
680 .name = "DCIO",
681 .flags = IORESOURCE_IRQ,
682 .start = AB5500_IRQ(8, 3),
683 .end = AB5500_IRQ(8, 4),
684 },
685 {
686 .name = "VBUS_R",
687 .flags = IORESOURCE_IRQ,
688 .start = AB5500_IRQ(8, 5),
689 .end = AB5500_IRQ(8, 5),
690 },
691 {
692 .name = "VBUS_F",
693 .flags = IORESOURCE_IRQ,
694 .start = AB5500_IRQ(8, 6),
695 .end = AB5500_IRQ(8, 6),
696 },
697 {
698 .name = "CHGstate_10_PCVBUSchg",
699 .flags = IORESOURCE_IRQ,
700 .start = AB5500_IRQ(8, 7),
701 .end = AB5500_IRQ(8, 7),
702 },
703 {
704 .name = "DCIOreverse_ovc",
705 .flags = IORESOURCE_IRQ,
706 .start = AB5500_IRQ(9, 0),
707 .end = AB5500_IRQ(9, 0),
708 },
709 {
710 .name = "USBCharDetDone",
711 .flags = IORESOURCE_IRQ,
712 .start = AB5500_IRQ(9, 1),
713 .end = AB5500_IRQ(9, 1),
714 },
715 {
716 .name = "DCIO_no_limit",
717 .flags = IORESOURCE_IRQ,
718 .start = AB5500_IRQ(9, 2),
719 .end = AB5500_IRQ(9, 2),
720 },
721 {
722 .name = "USB_suspend",
723 .flags = IORESOURCE_IRQ,
724 .start = AB5500_IRQ(9, 3),
725 .end = AB5500_IRQ(9, 3),
726 },
727 {
728 .name = "DCIOreverse_fwdcurrent",
729 .flags = IORESOURCE_IRQ,
730 .start = AB5500_IRQ(9, 4),
731 .end = AB5500_IRQ(9, 4),
732 },
733 {
734 .name = "Vbus_Imeasmax_change",
735 .flags = IORESOURCE_IRQ,
736 .start = AB5500_IRQ(9, 5),
737 .end = AB5500_IRQ(9, 6),
738 },
739 {
740 .name = "OVV",
741 .flags = IORESOURCE_IRQ,
742 .start = AB5500_IRQ(14, 5),
743 .end = AB5500_IRQ(14, 5),
744 },
745 {
746 .name = "USBcharging_NOTok",
747 .flags = IORESOURCE_IRQ,
748 .start = AB5500_IRQ(15, 3),
749 .end = AB5500_IRQ(15, 3),
750 },
751 {
752 .name = "usb_adp_sensoroff",
753 .flags = IORESOURCE_IRQ,
754 .start = AB5500_IRQ(15, 6),
755 .end = AB5500_IRQ(15, 6),
756 },
757 {
758 .name = "usb_adp_probeplug",
759 .flags = IORESOURCE_IRQ,
760 .start = AB5500_IRQ(15, 7),
761 .end = AB5500_IRQ(15, 7),
762 },
763 {
764 .name = "usb_adp_sinkerror",
765 .flags = IORESOURCE_IRQ,
766 .start = AB5500_IRQ(16, 0),
767 .end = AB5500_IRQ(16, 6),
768 },
769 {
770 .name = "usb_adp_sourceerror",
771 .flags = IORESOURCE_IRQ,
772 .start = AB5500_IRQ(16, 1),
773 .end = AB5500_IRQ(16, 1),
774 },
775 {
776 .name = "usb_idgnd_r",
777 .flags = IORESOURCE_IRQ,
778 .start = AB5500_IRQ(16, 2),
779 .end = AB5500_IRQ(16, 2),
780 },
781 {
782 .name = "usb_idgnd_f",
783 .flags = IORESOURCE_IRQ,
784 .start = AB5500_IRQ(16, 3),
785 .end = AB5500_IRQ(16, 3),
786 },
787 {
788 .name = "usb_iddetR1",
789 .flags = IORESOURCE_IRQ,
790 .start = AB5500_IRQ(16, 4),
791 .end = AB5500_IRQ(16, 5),
792 },
793 {
794 .name = "usb_iddetR2",
795 .flags = IORESOURCE_IRQ,
796 .start = AB5500_IRQ(16, 6),
797 .end = AB5500_IRQ(16, 7),
798 },
799 {
800 .name = "usb_iddetR3",
801 .flags = IORESOURCE_IRQ,
802 .start = AB5500_IRQ(17, 0),
803 .end = AB5500_IRQ(17, 1),
804 },
805 {
806 .name = "usb_iddetR4",
807 .flags = IORESOURCE_IRQ,
808 .start = AB5500_IRQ(17, 2),
809 .end = AB5500_IRQ(17, 3),
810 },
811 {
812 .name = "CharTempWindowOk",
813 .flags = IORESOURCE_IRQ,
814 .start = AB5500_IRQ(17, 7),
815 .end = AB5500_IRQ(18, 0),
816 },
817 {
818 .name = "USB_SprDetect",
819 .flags = IORESOURCE_IRQ,
820 .start = AB5500_IRQ(18, 1),
821 .end = AB5500_IRQ(18, 1),
822 },
823 {
824 .name = "usb_adp_probe_unplug",
825 .flags = IORESOURCE_IRQ,
826 .start = AB5500_IRQ(18, 2),
827 .end = AB5500_IRQ(18, 2),
828 },
829 {
830 .name = "VBUSChDrop",
831 .flags = IORESOURCE_IRQ,
832 .start = AB5500_IRQ(18, 3),
833 .end = AB5500_IRQ(18, 4),
834 },
835 {
836 .name = "dcio_char_rec_done",
837 .flags = IORESOURCE_IRQ,
838 .start = AB5500_IRQ(18, 5),
839 .end = AB5500_IRQ(18, 5),
840 },
841 {
842 .name = "Charging_stopped_by_temp",
843 .flags = IORESOURCE_IRQ,
844 .start = AB5500_IRQ(18, 6),
845 .end = AB5500_IRQ(18, 6),
846 },
847 {
848 .name = "CHGstate_11_SafeModeVBUS",
849 .flags = IORESOURCE_IRQ,
850 .start = AB5500_IRQ(21, 1),
851 .end = AB5500_IRQ(21, 2),
852 },
853 {
854 .name = "CHGstate_12_comletedVBUS",
855 .flags = IORESOURCE_IRQ,
856 .start = AB5500_IRQ(21, 2),
857 .end = AB5500_IRQ(21, 2),
858 },
859 {
860 .name = "CHGstate_13_completedVBUS",
861 .flags = IORESOURCE_IRQ,
862 .start = AB5500_IRQ(21, 3),
863 .end = AB5500_IRQ(21, 3),
864 },
865 {
866 .name = "CHGstate_14_FullChgDCIO",
867 .flags = IORESOURCE_IRQ,
868 .start = AB5500_IRQ(21, 4),
869 .end = AB5500_IRQ(21, 4),
870 },
871 {
872 .name = "CHGstate_15_SafeModeDCIO",
873 .flags = IORESOURCE_IRQ,
874 .start = AB5500_IRQ(21, 5),
875 .end = AB5500_IRQ(21, 5),
876 },
877 {
878 .name = "CHGstate_16_OFFsuspendDCIO",
879 .flags = IORESOURCE_IRQ,
880 .start = AB5500_IRQ(21, 6),
881 .end = AB5500_IRQ(21, 6),
882 },
883 {
884 .name = "CHGstate_17_completedDCIO",
885 .flags = IORESOURCE_IRQ,
886 .start = AB5500_IRQ(21, 7),
887 .end = AB5500_IRQ(21, 7),
888 },
889 },
890 },
891 [AB5500_DEVID_OTP] = {
892 .name = "ab5500-otp",
893 .id = AB5500_DEVID_OTP,
894 },
895 [AB5500_DEVID_VIDEO] = {
896 .name = "ab5500-video",
897 .id = AB5500_DEVID_VIDEO,
898 .num_resources = 1,
899 .resources = (struct resource[]) {
900 {
901 .name = "plugTVdet",
902 .flags = IORESOURCE_IRQ,
903 .start = AB5500_IRQ(22, 2),
904 .end = AB5500_IRQ(22, 2),
905 },
906 },
907 },
908 [AB5500_DEVID_DBIECI] = {
909 .name = "ab5500-dbieci",
910 .id = AB5500_DEVID_DBIECI,
911 .num_resources = 10,
912 .resources = (struct resource[]) {
913 {
914 .name = "COLL",
915 .flags = IORESOURCE_IRQ,
916 .start = AB5500_IRQ(14, 0),
917 .end = AB5500_IRQ(14, 0),
918 },
919 {
920 .name = "RESERR",
921 .flags = IORESOURCE_IRQ,
922 .start = AB5500_IRQ(14, 1),
923 .end = AB5500_IRQ(14, 1),
924 },
925 {
926 .name = "FRAERR",
927 .flags = IORESOURCE_IRQ,
928 .start = AB5500_IRQ(14, 2),
929 .end = AB5500_IRQ(14, 2),
930 },
931 {
932 .name = "COMERR",
933 .flags = IORESOURCE_IRQ,
934 .start = AB5500_IRQ(14, 3),
935 .end = AB5500_IRQ(14, 3),
936 },
937 {
938 .name = "BSI_indicator",
939 .flags = IORESOURCE_IRQ,
940 .start = AB5500_IRQ(14, 4),
941 .end = AB5500_IRQ(14, 4),
942 },
943 {
944 .name = "SPDSET",
945 .flags = IORESOURCE_IRQ,
946 .start = AB5500_IRQ(14, 6),
947 .end = AB5500_IRQ(14, 6),
948 },
949 {
950 .name = "DSENT",
951 .flags = IORESOURCE_IRQ,
952 .start = AB5500_IRQ(14, 7),
953 .end = AB5500_IRQ(14, 7),
954 },
955 {
956 .name = "DREC",
957 .flags = IORESOURCE_IRQ,
958 .start = AB5500_IRQ(15, 0),
959 .end = AB5500_IRQ(15, 0),
960 },
961 {
962 .name = "ACCINT",
963 .flags = IORESOURCE_IRQ,
964 .start = AB5500_IRQ(15, 1),
965 .end = AB5500_IRQ(15, 1),
966 },
967 {
968 .name = "NOPINT",
969 .flags = IORESOURCE_IRQ,
970 .start = AB5500_IRQ(15, 2),
971 .end = AB5500_IRQ(15, 2),
972 },
973 },
974 },
975 [AB5500_DEVID_ONSWA] = {
976 .name = "ab5500-onswa",
977 .id = AB5500_DEVID_ONSWA,
978 .num_resources = 2,
979 .resources = (struct resource[]) {
980 {
981 .name = "ONSWAn_rising",
982 .flags = IORESOURCE_IRQ,
983 .start = AB5500_IRQ(1, 3),
984 .end = AB5500_IRQ(1, 3),
985 },
986 {
987 .name = "ONSWAn_falling",
988 .flags = IORESOURCE_IRQ,
989 .start = AB5500_IRQ(1, 4),
990 .end = AB5500_IRQ(1, 4),
991 },
992 },
993 },
994};
995
996/*
997 * Functionality for getting/setting register values.
998 */
999int ab5500_get_register_interruptible_raw(struct ab5500 *ab,
1000 u8 bank, u8 reg,
1001 u8 *value)
1002{
1003 int err;
1004
1005 if (bank >= AB5500_NUM_BANKS)
1006 return -EINVAL;
1007
1008 err = mutex_lock_interruptible(&ab->access_mutex);
1009 if (err)
1010 return err;
1011 err = db5500_prcmu_abb_read(bankinfo[bank].slave_addr, reg, value, 1);
1012
1013 mutex_unlock(&ab->access_mutex);
1014 return err;
1015}
1016
1017static int get_register_page_interruptible(struct ab5500 *ab, u8 bank,
1018 u8 first_reg, u8 *regvals, u8 numregs)
1019{
1020 int err;
1021
1022 if (bank >= AB5500_NUM_BANKS)
1023 return -EINVAL;
1024
1025 err = mutex_lock_interruptible(&ab->access_mutex);
1026 if (err)
1027 return err;
1028
1029 while (numregs) {
1030 /* The hardware limit for get page is 4 */
1031 u8 curnum = min_t(u8, numregs, 4u);
1032
1033 err = db5500_prcmu_abb_read(bankinfo[bank].slave_addr,
1034 first_reg, regvals, curnum);
1035 if (err)
1036 goto out;
1037
1038 numregs -= curnum;
1039 first_reg += curnum;
1040 regvals += curnum;
1041 }
1042
1043out:
1044 mutex_unlock(&ab->access_mutex);
1045 return err;
1046}
1047
1048int ab5500_mask_and_set_register_interruptible_raw(struct ab5500 *ab, u8 bank,
1049 u8 reg, u8 bitmask, u8 bitvalues)
1050{
1051 int err = 0;
1052
1053 if (bank >= AB5500_NUM_BANKS)
1054 return -EINVAL;
1055
1056 if (bitmask) {
1057 u8 buf;
1058
1059 err = mutex_lock_interruptible(&ab->access_mutex);
1060 if (err)
1061 return err;
1062
1063 if (bitmask == 0xFF) /* No need to read in this case. */
1064 buf = bitvalues;
1065 else { /* Read and modify the register value. */
1066 err = db5500_prcmu_abb_read(bankinfo[bank].slave_addr,
1067 reg, &buf, 1);
1068 if (err)
1069 return err;
1070
1071 buf = ((~bitmask & buf) | (bitmask & bitvalues));
1072 }
1073 /* Write the new value. */
1074 err = db5500_prcmu_abb_write(bankinfo[bank].slave_addr, reg,
1075 &buf, 1);
1076
1077 mutex_unlock(&ab->access_mutex);
1078 }
1079 return err;
1080}
1081
1082static int
1083set_register_interruptible(struct ab5500 *ab, u8 bank, u8 reg, u8 value)
1084{
1085 return ab5500_mask_and_set_register_interruptible_raw(ab, bank, reg,
1086 0xff, value);
1087}
1088
1089/*
1090 * Read/write permission checking functions.
1091 */
1092static const struct ab5500_i2c_ranges *get_bankref(u8 devid, u8 bank)
1093{
1094 u8 i;
1095
1096 if (devid < AB5500_NUM_DEVICES) {
1097 for (i = 0; i < ab5500_bank_ranges[devid].nbanks; i++) {
1098 if (ab5500_bank_ranges[devid].bank[i].bankid == bank)
1099 return &ab5500_bank_ranges[devid].bank[i];
1100 }
1101 }
1102 return NULL;
1103}
1104
1105static bool page_write_allowed(u8 devid, u8 bank, u8 first_reg, u8 last_reg)
1106{
1107 u8 i; /* range loop index */
1108 const struct ab5500_i2c_ranges *bankref;
1109
1110 bankref = get_bankref(devid, bank);
1111 if (bankref == NULL || last_reg < first_reg)
1112 return false;
1113
1114 for (i = 0; i < bankref->nranges; i++) {
1115 if (first_reg < bankref->range[i].first)
1116 break;
1117 if ((last_reg <= bankref->range[i].last) &&
1118 (bankref->range[i].perm & AB5500_PERM_WR))
1119 return true;
1120 }
1121 return false;
1122}
1123
1124static bool reg_write_allowed(u8 devid, u8 bank, u8 reg)
1125{
1126 return page_write_allowed(devid, bank, reg, reg);
1127}
1128
1129static bool page_read_allowed(u8 devid, u8 bank, u8 first_reg, u8 last_reg)
1130{
1131 u8 i;
1132 const struct ab5500_i2c_ranges *bankref;
1133
1134 bankref = get_bankref(devid, bank);
1135 if (bankref == NULL || last_reg < first_reg)
1136 return false;
1137
1138
1139 /* Find the range (if it exists in the list) that includes first_reg. */
1140 for (i = 0; i < bankref->nranges; i++) {
1141 if (first_reg < bankref->range[i].first)
1142 return false;
1143 if (first_reg <= bankref->range[i].last)
1144 break;
1145 }
1146 /* Make sure that the entire range up to and including last_reg is
1147 * readable. This may span several of the ranges in the list.
1148 */
1149 while ((i < bankref->nranges) &&
1150 (bankref->range[i].perm & AB5500_PERM_RD)) {
1151 if (last_reg <= bankref->range[i].last)
1152 return true;
1153 if ((++i >= bankref->nranges) ||
1154 (bankref->range[i].first !=
1155 (bankref->range[i - 1].last + 1))) {
1156 break;
1157 }
1158 }
1159 return false;
1160}
1161
1162static bool reg_read_allowed(u8 devid, u8 bank, u8 reg)
1163{
1164 return page_read_allowed(devid, bank, reg, reg);
1165}
1166
1167
1168/*
1169 * The exported register access functionality.
1170 */
1171static int ab5500_get_chip_id(struct device *dev)
1172{
1173 struct ab5500 *ab = dev_get_drvdata(dev->parent);
1174
1175 return (int)ab->chip_id;
1176}
1177
1178static int ab5500_mask_and_set_register_interruptible(struct device *dev,
1179 u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
1180{
1181 struct ab5500 *ab;
1182 struct platform_device *pdev = to_platform_device(dev);
1183
1184 if ((AB5500_NUM_BANKS <= bank) ||
1185 !reg_write_allowed(pdev->id, bank, reg))
1186 return -EINVAL;
1187
1188 ab = dev_get_drvdata(dev->parent);
1189 return ab5500_mask_and_set_register_interruptible_raw(ab, bank, reg,
1190 bitmask, bitvalues);
1191}
1192
1193static int ab5500_set_register_interruptible(struct device *dev, u8 bank,
1194 u8 reg, u8 value)
1195{
1196 return ab5500_mask_and_set_register_interruptible(dev, bank, reg, 0xFF,
1197 value);
1198}
1199
1200static int ab5500_get_register_interruptible(struct device *dev, u8 bank,
1201 u8 reg, u8 *value)
1202{
1203 struct ab5500 *ab;
1204 struct platform_device *pdev = to_platform_device(dev);
1205
1206 if ((AB5500_NUM_BANKS <= bank) ||
1207 !reg_read_allowed(pdev->id, bank, reg))
1208 return -EINVAL;
1209
1210 ab = dev_get_drvdata(dev->parent);
1211 return ab5500_get_register_interruptible_raw(ab, bank, reg, value);
1212}
1213
1214static int ab5500_get_register_page_interruptible(struct device *dev, u8 bank,
1215 u8 first_reg, u8 *regvals, u8 numregs)
1216{
1217 struct ab5500 *ab;
1218 struct platform_device *pdev = to_platform_device(dev);
1219
1220 if ((AB5500_NUM_BANKS <= bank) ||
1221 !page_read_allowed(pdev->id, bank,
1222 first_reg, (first_reg + numregs - 1)))
1223 return -EINVAL;
1224
1225 ab = dev_get_drvdata(dev->parent);
1226 return get_register_page_interruptible(ab, bank, first_reg, regvals,
1227 numregs);
1228}
1229
1230static int
1231ab5500_event_registers_startup_state_get(struct device *dev, u8 *event)
1232{
1233 struct ab5500 *ab;
1234
1235 ab = dev_get_drvdata(dev->parent);
1236 if (!ab->startup_events_read)
1237 return -EAGAIN; /* Try again later */
1238
1239 memcpy(event, ab->startup_events, AB5500_NUM_EVENT_REG);
1240 return 0;
1241}
1242
1243static struct abx500_ops ab5500_ops = {
1244 .get_chip_id = ab5500_get_chip_id,
1245 .get_register = ab5500_get_register_interruptible,
1246 .set_register = ab5500_set_register_interruptible,
1247 .get_register_page = ab5500_get_register_page_interruptible,
1248 .set_register_page = NULL,
1249 .mask_and_set_register = ab5500_mask_and_set_register_interruptible,
1250 .event_registers_startup_state_get =
1251 ab5500_event_registers_startup_state_get,
1252 .startup_irq_enabled = NULL,
1253};
1254
1255/*
1256 * ab5500_setup : Basic set-up, datastructure creation/destruction
1257 * and I2C interface.This sets up a default config
1258 * in the AB5500 chip so that it will work as expected.
1259 * @ab : Pointer to ab5500 structure
1260 * @settings : Pointer to struct abx500_init_settings
1261 * @size : Size of init data
1262 */
1263static int __init ab5500_setup(struct ab5500 *ab,
1264 struct abx500_init_settings *settings, unsigned int size)
1265{
1266 int err = 0;
1267 int i;
1268
1269 for (i = 0; i < size; i++) {
1270 err = ab5500_mask_and_set_register_interruptible_raw(ab,
1271 settings[i].bank,
1272 settings[i].reg,
1273 0xFF, settings[i].setting);
1274 if (err)
1275 goto exit_no_setup;
1276
1277 /* If event mask register update the event mask in ab5500 */
1278 if ((settings[i].bank == AB5500_BANK_IT) &&
1279 (AB5500_MASK_BASE <= settings[i].reg) &&
1280 (settings[i].reg <= AB5500_MASK_END)) {
1281 ab->mask[settings[i].reg - AB5500_MASK_BASE] =
1282 settings[i].setting;
1283 }
1284 }
1285exit_no_setup:
1286 return err;
1287}
1288
1289struct ab_family_id {
1290 u8 id;
1291 char *name;
1292};
1293
1294static const struct ab_family_id ids[] __initdata = {
1295 /* AB5500 */
1296 {
1297 .id = AB5500_1_0,
1298 .name = "1.0"
1299 },
1300 {
1301 .id = AB5500_1_1,
1302 .name = "1.1"
1303 },
1304 /* Terminator */
1305 {
1306 .id = 0x00,
1307 }
1308};
1309
1310static int __init ab5500_probe(struct platform_device *pdev)
1311{
1312 struct ab5500 *ab;
1313 struct ab5500_platform_data *ab5500_plf_data =
1314 pdev->dev.platform_data;
1315 int err;
1316 int i;
1317
1318 ab = kzalloc(sizeof(struct ab5500), GFP_KERNEL);
1319 if (!ab) {
1320 dev_err(&pdev->dev,
1321 "could not allocate ab5500 device\n");
1322 return -ENOMEM;
1323 }
1324
1325 /* Initialize data structure */
1326 mutex_init(&ab->access_mutex);
1327 mutex_init(&ab->irq_lock);
1328 ab->dev = &pdev->dev;
1329
1330 platform_set_drvdata(pdev, ab);
1331
1332 /* Read chip ID register */
1333 err = ab5500_get_register_interruptible_raw(ab,
1334 AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP,
1335 AB5500_CHIP_ID, &ab->chip_id);
1336 if (err) {
1337 dev_err(&pdev->dev, "could not communicate with the analog "
1338 "baseband chip\n");
1339 goto exit_no_detect;
1340 }
1341
1342 for (i = 0; ids[i].id != 0x0; i++) {
1343 if (ids[i].id == ab->chip_id) {
1344 snprintf(&ab->chip_name[0], sizeof(ab->chip_name) - 1,
1345 "AB5500 %s", ids[i].name);
1346 break;
1347 }
1348 }
1349 if (ids[i].id == 0x0) {
1350 dev_err(&pdev->dev, "unknown analog baseband chip id: 0x%x\n",
1351 ab->chip_id);
1352 dev_err(&pdev->dev, "driver not started!\n");
1353 goto exit_no_detect;
1354 }
1355
1356 /* Clear and mask all interrupts */
1357 for (i = 0; i < AB5500_NUM_IRQ_REGS; i++) {
1358 u8 latchreg = AB5500_IT_LATCH0_REG + i;
1359 u8 maskreg = AB5500_IT_MASK0_REG + i;
1360 u8 val;
1361
1362 ab5500_get_register_interruptible_raw(ab, AB5500_BANK_IT,
1363 latchreg, &val);
1364 set_register_interruptible(ab, AB5500_BANK_IT, maskreg, 0xff);
1365 ab->mask[i] = ab->oldmask[i] = 0xff;
1366 }
1367
1368 err = abx500_register_ops(&pdev->dev, &ab5500_ops);
1369 if (err) {
1370 dev_err(&pdev->dev, "ab5500_register ops error\n");
1371 goto exit_no_detect;
1372 }
1373
1374 /* Set up and register the platform devices. */
1375 for (i = 0; i < AB5500_NUM_DEVICES; i++) {
1376 ab5500_devs[i].platform_data = ab5500_plf_data->dev_data[i];
1377 ab5500_devs[i].pdata_size =
1378 sizeof(ab5500_plf_data->dev_data[i]);
1379 }
1380
1381 err = mfd_add_devices(&pdev->dev, 0, ab5500_devs,
1382 ARRAY_SIZE(ab5500_devs), NULL,
1383 ab5500_plf_data->irq.base);
1384 if (err) {
1385 dev_err(&pdev->dev, "ab5500_mfd_add_device error\n");
1386 goto exit_no_detect;
1387 }
1388
1389 err = ab5500_setup(ab, ab5500_plf_data->init_settings,
1390 ab5500_plf_data->init_settings_sz);
1391 if (err) {
1392 dev_err(&pdev->dev, "ab5500_setup error\n");
1393 goto exit_no_detect;
1394 }
1395
1396 ab5500_setup_debugfs(ab);
1397
1398 dev_info(&pdev->dev, "detected AB chip: %s\n", &ab->chip_name[0]);
1399 return 0;
1400
1401exit_no_detect:
1402 kfree(ab);
1403 return err;
1404}
1405
1406static int __exit ab5500_remove(struct platform_device *pdev)
1407{
1408 struct ab5500 *ab = platform_get_drvdata(pdev);
1409
1410 ab5500_remove_debugfs();
1411 mfd_remove_devices(&pdev->dev);
1412 kfree(ab);
1413 return 0;
1414}
1415
1416static struct platform_driver ab5500_driver = {
1417 .driver = {
1418 .name = "ab5500-core",
1419 .owner = THIS_MODULE,
1420 },
1421 .remove = __exit_p(ab5500_remove),
1422};
1423
1424static int __init ab5500_core_init(void)
1425{
1426 return platform_driver_probe(&ab5500_driver, ab5500_probe);
1427}
1428
1429static void __exit ab5500_core_exit(void)
1430{
1431 platform_driver_unregister(&ab5500_driver);
1432}
1433
1434subsys_initcall(ab5500_core_init);
1435module_exit(ab5500_core_exit);
1436
1437MODULE_AUTHOR("Mattias Wallin <mattias.wallin@stericsson.com>");
1438MODULE_DESCRIPTION("AB5500 core driver");
1439MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/ab5500-debugfs.c b/drivers/mfd/ab5500-debugfs.c
deleted file mode 100644
index 72006940937a..000000000000
--- a/drivers/mfd/ab5500-debugfs.c
+++ /dev/null
@@ -1,807 +0,0 @@
1/*
2 * Copyright (C) 2011 ST-Ericsson
3 * License terms: GNU General Public License (GPL) version 2
4 * Debugfs support for the AB5500 MFD driver
5 */
6
7#include <linux/module.h>
8#include <linux/debugfs.h>
9#include <linux/seq_file.h>
10#include <linux/mfd/abx500.h>
11#include <linux/mfd/abx500/ab5500.h>
12#include <linux/uaccess.h>
13
14#include "ab5500-core.h"
15#include "ab5500-debugfs.h"
16
17static struct ab5500_i2c_ranges ab5500_reg_ranges[AB5500_NUM_BANKS] = {
18 [AB5500_BANK_LED] = {
19 .bankid = AB5500_BANK_LED,
20 .nranges = 1,
21 .range = (struct ab5500_reg_range[]) {
22 {
23 .first = 0x00,
24 .last = 0x0C,
25 .perm = AB5500_PERM_RW,
26 },
27 },
28 },
29 [AB5500_BANK_ADC] = {
30 .bankid = AB5500_BANK_ADC,
31 .nranges = 6,
32 .range = (struct ab5500_reg_range[]) {
33 {
34 .first = 0x1F,
35 .last = 0x22,
36 .perm = AB5500_PERM_RO,
37 },
38 {
39 .first = 0x23,
40 .last = 0x24,
41 .perm = AB5500_PERM_RW,
42 },
43 {
44 .first = 0x26,
45 .last = 0x2D,
46 .perm = AB5500_PERM_RO,
47 },
48 {
49 .first = 0x2F,
50 .last = 0x34,
51 .perm = AB5500_PERM_RW,
52 },
53 {
54 .first = 0x37,
55 .last = 0x57,
56 .perm = AB5500_PERM_RW,
57 },
58 {
59 .first = 0x58,
60 .last = 0x58,
61 .perm = AB5500_PERM_RO,
62 },
63 },
64 },
65 [AB5500_BANK_RTC] = {
66 .bankid = AB5500_BANK_RTC,
67 .nranges = 2,
68 .range = (struct ab5500_reg_range[]) {
69 {
70 .first = 0x00,
71 .last = 0x04,
72 .perm = AB5500_PERM_RW,
73 },
74 {
75 .first = 0x06,
76 .last = 0x0C,
77 .perm = AB5500_PERM_RW,
78 },
79 },
80 },
81 [AB5500_BANK_STARTUP] = {
82 .bankid = AB5500_BANK_STARTUP,
83 .nranges = 12,
84 .range = (struct ab5500_reg_range[]) {
85 {
86 .first = 0x00,
87 .last = 0x01,
88 .perm = AB5500_PERM_RW,
89 },
90 {
91 .first = 0x1F,
92 .last = 0x1F,
93 .perm = AB5500_PERM_RW,
94 },
95 {
96 .first = 0x2E,
97 .last = 0x2E,
98 .perm = AB5500_PERM_RO,
99 },
100 {
101 .first = 0x2F,
102 .last = 0x30,
103 .perm = AB5500_PERM_RW,
104 },
105 {
106 .first = 0x50,
107 .last = 0x51,
108 .perm = AB5500_PERM_RW,
109 },
110 {
111 .first = 0x60,
112 .last = 0x61,
113 .perm = AB5500_PERM_RW,
114 },
115 {
116 .first = 0x66,
117 .last = 0x8A,
118 .perm = AB5500_PERM_RW,
119 },
120 {
121 .first = 0x8C,
122 .last = 0x96,
123 .perm = AB5500_PERM_RW,
124 },
125 {
126 .first = 0xAA,
127 .last = 0xB4,
128 .perm = AB5500_PERM_RW,
129 },
130 {
131 .first = 0xB7,
132 .last = 0xBF,
133 .perm = AB5500_PERM_RW,
134 },
135 {
136 .first = 0xC1,
137 .last = 0xCA,
138 .perm = AB5500_PERM_RW,
139 },
140 {
141 .first = 0xD3,
142 .last = 0xE0,
143 .perm = AB5500_PERM_RW,
144 },
145 },
146 },
147 [AB5500_BANK_DBI_ECI] = {
148 .bankid = AB5500_BANK_DBI_ECI,
149 .nranges = 3,
150 .range = (struct ab5500_reg_range[]) {
151 {
152 .first = 0x00,
153 .last = 0x07,
154 .perm = AB5500_PERM_RW,
155 },
156 {
157 .first = 0x10,
158 .last = 0x10,
159 .perm = AB5500_PERM_RW,
160 },
161 {
162 .first = 0x13,
163 .last = 0x13,
164 .perm = AB5500_PERM_RW,
165 },
166 },
167 },
168 [AB5500_BANK_CHG] = {
169 .bankid = AB5500_BANK_CHG,
170 .nranges = 2,
171 .range = (struct ab5500_reg_range[]) {
172 {
173 .first = 0x11,
174 .last = 0x11,
175 .perm = AB5500_PERM_RO,
176 },
177 {
178 .first = 0x12,
179 .last = 0x1B,
180 .perm = AB5500_PERM_RW,
181 },
182 },
183 },
184 [AB5500_BANK_FG_BATTCOM_ACC] = {
185 .bankid = AB5500_BANK_FG_BATTCOM_ACC,
186 .nranges = 2,
187 .range = (struct ab5500_reg_range[]) {
188 {
189 .first = 0x00,
190 .last = 0x0B,
191 .perm = AB5500_PERM_RO,
192 },
193 {
194 .first = 0x0C,
195 .last = 0x10,
196 .perm = AB5500_PERM_RW,
197 },
198 },
199 },
200 [AB5500_BANK_USB] = {
201 .bankid = AB5500_BANK_USB,
202 .nranges = 12,
203 .range = (struct ab5500_reg_range[]) {
204 {
205 .first = 0x01,
206 .last = 0x01,
207 .perm = AB5500_PERM_RW,
208 },
209 {
210 .first = 0x80,
211 .last = 0x83,
212 .perm = AB5500_PERM_RW,
213 },
214 {
215 .first = 0x87,
216 .last = 0x8A,
217 .perm = AB5500_PERM_RW,
218 },
219 {
220 .first = 0x8B,
221 .last = 0x8B,
222 .perm = AB5500_PERM_RO,
223 },
224 {
225 .first = 0x91,
226 .last = 0x92,
227 .perm = AB5500_PERM_RO,
228 },
229 {
230 .first = 0x93,
231 .last = 0x93,
232 .perm = AB5500_PERM_RW,
233 },
234 {
235 .first = 0x94,
236 .last = 0x94,
237 .perm = AB5500_PERM_RO,
238 },
239 {
240 .first = 0xA8,
241 .last = 0xB0,
242 .perm = AB5500_PERM_RO,
243 },
244 {
245 .first = 0xB2,
246 .last = 0xB2,
247 .perm = AB5500_PERM_RO,
248 },
249 {
250 .first = 0xB4,
251 .last = 0xBC,
252 .perm = AB5500_PERM_RO,
253 },
254 {
255 .first = 0xBF,
256 .last = 0xBF,
257 .perm = AB5500_PERM_RO,
258 },
259 {
260 .first = 0xC1,
261 .last = 0xC5,
262 .perm = AB5500_PERM_RO,
263 },
264 },
265 },
266 [AB5500_BANK_IT] = {
267 .bankid = AB5500_BANK_IT,
268 .nranges = 4,
269 .range = (struct ab5500_reg_range[]) {
270 {
271 .first = 0x00,
272 .last = 0x02,
273 .perm = AB5500_PERM_RO,
274 },
275 {
276 .first = 0x20,
277 .last = 0x36,
278 .perm = AB5500_PERM_RO,
279 },
280 {
281 .first = 0x40,
282 .last = 0x56,
283 .perm = AB5500_PERM_RO,
284 },
285 {
286 .first = 0x60,
287 .last = 0x76,
288 .perm = AB5500_PERM_RO,
289 },
290 },
291 },
292 [AB5500_BANK_VDDDIG_IO_I2C_CLK_TST] = {
293 .bankid = AB5500_BANK_VDDDIG_IO_I2C_CLK_TST,
294 .nranges = 7,
295 .range = (struct ab5500_reg_range[]) {
296 {
297 .first = 0x02,
298 .last = 0x02,
299 .perm = AB5500_PERM_RW,
300 },
301 {
302 .first = 0x12,
303 .last = 0x12,
304 .perm = AB5500_PERM_RW,
305 },
306 {
307 .first = 0x30,
308 .last = 0x34,
309 .perm = AB5500_PERM_RW,
310 },
311 {
312 .first = 0x40,
313 .last = 0x44,
314 .perm = AB5500_PERM_RW,
315 },
316 {
317 .first = 0x50,
318 .last = 0x54,
319 .perm = AB5500_PERM_RW,
320 },
321 {
322 .first = 0x60,
323 .last = 0x64,
324 .perm = AB5500_PERM_RW,
325 },
326 {
327 .first = 0x70,
328 .last = 0x74,
329 .perm = AB5500_PERM_RW,
330 },
331 },
332 },
333 [AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP] = {
334 .bankid = AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP,
335 .nranges = 13,
336 .range = (struct ab5500_reg_range[]) {
337 {
338 .first = 0x01,
339 .last = 0x01,
340 .perm = AB5500_PERM_RW,
341 },
342 {
343 .first = 0x02,
344 .last = 0x02,
345 .perm = AB5500_PERM_RO,
346 },
347 {
348 .first = 0x0D,
349 .last = 0x0F,
350 .perm = AB5500_PERM_RW,
351 },
352 {
353 .first = 0x1C,
354 .last = 0x1C,
355 .perm = AB5500_PERM_RW,
356 },
357 {
358 .first = 0x1E,
359 .last = 0x1E,
360 .perm = AB5500_PERM_RW,
361 },
362 {
363 .first = 0x20,
364 .last = 0x21,
365 .perm = AB5500_PERM_RW,
366 },
367 {
368 .first = 0x25,
369 .last = 0x25,
370 .perm = AB5500_PERM_RW,
371 },
372 {
373 .first = 0x28,
374 .last = 0x2A,
375 .perm = AB5500_PERM_RW,
376 },
377 {
378 .first = 0x30,
379 .last = 0x33,
380 .perm = AB5500_PERM_RW,
381 },
382 {
383 .first = 0x40,
384 .last = 0x43,
385 .perm = AB5500_PERM_RW,
386 },
387 {
388 .first = 0x50,
389 .last = 0x53,
390 .perm = AB5500_PERM_RW,
391 },
392 {
393 .first = 0x60,
394 .last = 0x63,
395 .perm = AB5500_PERM_RW,
396 },
397 {
398 .first = 0x70,
399 .last = 0x73,
400 .perm = AB5500_PERM_RW,
401 },
402 },
403 },
404 [AB5500_BANK_VIBRA] = {
405 .bankid = AB5500_BANK_VIBRA,
406 .nranges = 2,
407 .range = (struct ab5500_reg_range[]) {
408 {
409 .first = 0x10,
410 .last = 0x13,
411 .perm = AB5500_PERM_RW,
412 },
413 {
414 .first = 0xFE,
415 .last = 0xFE,
416 .perm = AB5500_PERM_RW,
417 },
418 },
419 },
420 [AB5500_BANK_AUDIO_HEADSETUSB] = {
421 .bankid = AB5500_BANK_AUDIO_HEADSETUSB,
422 .nranges = 2,
423 .range = (struct ab5500_reg_range[]) {
424 {
425 .first = 0x00,
426 .last = 0x48,
427 .perm = AB5500_PERM_RW,
428 },
429 {
430 .first = 0xEB,
431 .last = 0xFB,
432 .perm = AB5500_PERM_RW,
433 },
434 },
435 },
436 [AB5500_BANK_SIM_USBSIM] = {
437 .bankid = AB5500_BANK_SIM_USBSIM,
438 .nranges = 1,
439 .range = (struct ab5500_reg_range[]) {
440 {
441 .first = 0x13,
442 .last = 0x19,
443 .perm = AB5500_PERM_RW,
444 },
445 },
446 },
447 [AB5500_BANK_VDENC] = {
448 .bankid = AB5500_BANK_VDENC,
449 .nranges = 12,
450 .range = (struct ab5500_reg_range[]) {
451 {
452 .first = 0x00,
453 .last = 0x08,
454 .perm = AB5500_PERM_RW,
455 },
456 {
457 .first = 0x09,
458 .last = 0x09,
459 .perm = AB5500_PERM_RO,
460 },
461 {
462 .first = 0x0A,
463 .last = 0x12,
464 .perm = AB5500_PERM_RW,
465 },
466 {
467 .first = 0x15,
468 .last = 0x19,
469 .perm = AB5500_PERM_RW,
470 },
471 {
472 .first = 0x1B,
473 .last = 0x21,
474 .perm = AB5500_PERM_RW,
475 },
476 {
477 .first = 0x27,
478 .last = 0x2C,
479 .perm = AB5500_PERM_RW,
480 },
481 {
482 .first = 0x41,
483 .last = 0x41,
484 .perm = AB5500_PERM_RW,
485 },
486 {
487 .first = 0x45,
488 .last = 0x5B,
489 .perm = AB5500_PERM_RW,
490 },
491 {
492 .first = 0x5D,
493 .last = 0x5D,
494 .perm = AB5500_PERM_RW,
495 },
496 {
497 .first = 0x69,
498 .last = 0x69,
499 .perm = AB5500_PERM_RW,
500 },
501 {
502 .first = 0x6C,
503 .last = 0x6D,
504 .perm = AB5500_PERM_RW,
505 },
506 {
507 .first = 0x80,
508 .last = 0x81,
509 .perm = AB5500_PERM_RW,
510 },
511 },
512 },
513};
514
515static int ab5500_registers_print(struct seq_file *s, void *p)
516{
517 struct ab5500 *ab = s->private;
518 unsigned int i;
519 u8 bank = (u8)ab->debug_bank;
520
521 seq_printf(s, "ab5500 register values:\n");
522 for (bank = 0; bank < AB5500_NUM_BANKS; bank++) {
523 seq_printf(s, " bank %u, %s (0x%x):\n", bank,
524 bankinfo[bank].name,
525 bankinfo[bank].slave_addr);
526 for (i = 0; i < ab5500_reg_ranges[bank].nranges; i++) {
527 u8 reg;
528 int err;
529
530 for (reg = ab5500_reg_ranges[bank].range[i].first;
531 reg <= ab5500_reg_ranges[bank].range[i].last;
532 reg++) {
533 u8 value;
534
535 err = ab5500_get_register_interruptible_raw(ab,
536 bank, reg,
537 &value);
538 if (err < 0) {
539 dev_err(ab->dev, "get_reg failed %d"
540 "bank 0x%x reg 0x%x\n",
541 err, bank, reg);
542 return err;
543 }
544
545 err = seq_printf(s, "[%d/0x%02X]: 0x%02X\n",
546 bank, reg, value);
547 if (err < 0) {
548 dev_err(ab->dev,
549 "seq_printf overflow\n");
550 /*
551 * Error is not returned here since
552 * the output is wanted in any case
553 */
554 return 0;
555 }
556 }
557 }
558 }
559 return 0;
560}
561
562static int ab5500_registers_open(struct inode *inode, struct file *file)
563{
564 return single_open(file, ab5500_registers_print, inode->i_private);
565}
566
567static const struct file_operations ab5500_registers_fops = {
568 .open = ab5500_registers_open,
569 .read = seq_read,
570 .llseek = seq_lseek,
571 .release = single_release,
572 .owner = THIS_MODULE,
573};
574
575static int ab5500_bank_print(struct seq_file *s, void *p)
576{
577 struct ab5500 *ab = s->private;
578
579 seq_printf(s, "%d\n", ab->debug_bank);
580 return 0;
581}
582
583static int ab5500_bank_open(struct inode *inode, struct file *file)
584{
585 return single_open(file, ab5500_bank_print, inode->i_private);
586}
587
588static ssize_t ab5500_bank_write(struct file *file,
589 const char __user *user_buf,
590 size_t count, loff_t *ppos)
591{
592 struct ab5500 *ab = ((struct seq_file *)(file->private_data))->private;
593 char buf[32];
594 int buf_size;
595 unsigned long user_bank;
596 int err;
597
598 /* Get userspace string and assure termination */
599 buf_size = min(count, (sizeof(buf) - 1));
600 if (copy_from_user(buf, user_buf, buf_size))
601 return -EFAULT;
602 buf[buf_size] = 0;
603
604 err = strict_strtoul(buf, 0, &user_bank);
605 if (err)
606 return -EINVAL;
607
608 if (user_bank >= AB5500_NUM_BANKS) {
609 dev_err(ab->dev,
610 "debugfs error input > number of banks\n");
611 return -EINVAL;
612 }
613
614 ab->debug_bank = user_bank;
615
616 return buf_size;
617}
618
619static int ab5500_address_print(struct seq_file *s, void *p)
620{
621 struct ab5500 *ab = s->private;
622
623 seq_printf(s, "0x%02X\n", ab->debug_address);
624 return 0;
625}
626
627static int ab5500_address_open(struct inode *inode, struct file *file)
628{
629 return single_open(file, ab5500_address_print, inode->i_private);
630}
631
632static ssize_t ab5500_address_write(struct file *file,
633 const char __user *user_buf,
634 size_t count, loff_t *ppos)
635{
636 struct ab5500 *ab = ((struct seq_file *)(file->private_data))->private;
637 char buf[32];
638 int buf_size;
639 unsigned long user_address;
640 int err;
641
642 /* Get userspace string and assure termination */
643 buf_size = min(count, (sizeof(buf) - 1));
644 if (copy_from_user(buf, user_buf, buf_size))
645 return -EFAULT;
646 buf[buf_size] = 0;
647
648 err = strict_strtoul(buf, 0, &user_address);
649 if (err)
650 return -EINVAL;
651 if (user_address > 0xff) {
652 dev_err(ab->dev,
653 "debugfs error input > 0xff\n");
654 return -EINVAL;
655 }
656 ab->debug_address = user_address;
657 return buf_size;
658}
659
660static int ab5500_val_print(struct seq_file *s, void *p)
661{
662 struct ab5500 *ab = s->private;
663 int err;
664 u8 regvalue;
665
666 err = ab5500_get_register_interruptible_raw(ab, (u8)ab->debug_bank,
667 (u8)ab->debug_address, &regvalue);
668 if (err) {
669 dev_err(ab->dev, "get_reg failed %d, bank 0x%x"
670 ", reg 0x%x\n", err, ab->debug_bank,
671 ab->debug_address);
672 return -EINVAL;
673 }
674 seq_printf(s, "0x%02X\n", regvalue);
675
676 return 0;
677}
678
679static int ab5500_val_open(struct inode *inode, struct file *file)
680{
681 return single_open(file, ab5500_val_print, inode->i_private);
682}
683
684static ssize_t ab5500_val_write(struct file *file,
685 const char __user *user_buf,
686 size_t count, loff_t *ppos)
687{
688 struct ab5500 *ab = ((struct seq_file *)(file->private_data))->private;
689 char buf[32];
690 int buf_size;
691 unsigned long user_val;
692 int err;
693 u8 regvalue;
694
695 /* Get userspace string and assure termination */
696 buf_size = min(count, (sizeof(buf)-1));
697 if (copy_from_user(buf, user_buf, buf_size))
698 return -EFAULT;
699 buf[buf_size] = 0;
700
701 err = strict_strtoul(buf, 0, &user_val);
702 if (err)
703 return -EINVAL;
704 if (user_val > 0xff) {
705 dev_err(ab->dev,
706 "debugfs error input > 0xff\n");
707 return -EINVAL;
708 }
709 err = ab5500_mask_and_set_register_interruptible_raw(
710 ab, (u8)ab->debug_bank,
711 (u8)ab->debug_address, 0xFF, (u8)user_val);
712 if (err)
713 return -EINVAL;
714
715 ab5500_get_register_interruptible_raw(ab, (u8)ab->debug_bank,
716 (u8)ab->debug_address, &regvalue);
717 if (err)
718 return -EINVAL;
719
720 return buf_size;
721}
722
723static const struct file_operations ab5500_bank_fops = {
724 .open = ab5500_bank_open,
725 .write = ab5500_bank_write,
726 .read = seq_read,
727 .llseek = seq_lseek,
728 .release = single_release,
729 .owner = THIS_MODULE,
730};
731
732static const struct file_operations ab5500_address_fops = {
733 .open = ab5500_address_open,
734 .write = ab5500_address_write,
735 .read = seq_read,
736 .llseek = seq_lseek,
737 .release = single_release,
738 .owner = THIS_MODULE,
739};
740
741static const struct file_operations ab5500_val_fops = {
742 .open = ab5500_val_open,
743 .write = ab5500_val_write,
744 .read = seq_read,
745 .llseek = seq_lseek,
746 .release = single_release,
747 .owner = THIS_MODULE,
748};
749
750static struct dentry *ab5500_dir;
751static struct dentry *ab5500_reg_file;
752static struct dentry *ab5500_bank_file;
753static struct dentry *ab5500_address_file;
754static struct dentry *ab5500_val_file;
755
756void __init ab5500_setup_debugfs(struct ab5500 *ab)
757{
758 ab->debug_bank = AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP;
759 ab->debug_address = AB5500_CHIP_ID;
760
761 ab5500_dir = debugfs_create_dir("ab5500", NULL);
762 if (!ab5500_dir)
763 goto exit_no_debugfs;
764
765 ab5500_reg_file = debugfs_create_file("all-bank-registers",
766 S_IRUGO, ab5500_dir, ab, &ab5500_registers_fops);
767 if (!ab5500_reg_file)
768 goto exit_destroy_dir;
769
770 ab5500_bank_file = debugfs_create_file("register-bank",
771 (S_IRUGO | S_IWUGO), ab5500_dir, ab, &ab5500_bank_fops);
772 if (!ab5500_bank_file)
773 goto exit_destroy_reg;
774
775 ab5500_address_file = debugfs_create_file("register-address",
776 (S_IRUGO | S_IWUGO), ab5500_dir, ab, &ab5500_address_fops);
777 if (!ab5500_address_file)
778 goto exit_destroy_bank;
779
780 ab5500_val_file = debugfs_create_file("register-value",
781 (S_IRUGO | S_IWUGO), ab5500_dir, ab, &ab5500_val_fops);
782 if (!ab5500_val_file)
783 goto exit_destroy_address;
784
785 return;
786
787exit_destroy_address:
788 debugfs_remove(ab5500_address_file);
789exit_destroy_bank:
790 debugfs_remove(ab5500_bank_file);
791exit_destroy_reg:
792 debugfs_remove(ab5500_reg_file);
793exit_destroy_dir:
794 debugfs_remove(ab5500_dir);
795exit_no_debugfs:
796 dev_err(ab->dev, "failed to create debugfs entries.\n");
797 return;
798}
799
800void __exit ab5500_remove_debugfs(void)
801{
802 debugfs_remove(ab5500_val_file);
803 debugfs_remove(ab5500_address_file);
804 debugfs_remove(ab5500_bank_file);
805 debugfs_remove(ab5500_reg_file);
806 debugfs_remove(ab5500_dir);
807}
diff --git a/drivers/mfd/ab5500-debugfs.h b/drivers/mfd/ab5500-debugfs.h
deleted file mode 100644
index 7330a9b6afa6..000000000000
--- a/drivers/mfd/ab5500-debugfs.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright (C) 2011 ST-Ericsson
3 * License terms: GNU General Public License (GPL) version 2
4 * Debugfs interface to the AB5500 core driver
5 */
6
7#ifdef CONFIG_DEBUG_FS
8
9void ab5500_setup_debugfs(struct ab5500 *ab);
10void ab5500_remove_debugfs(void);
11
12#else /* !CONFIG_DEBUG_FS */
13
14static inline void ab5500_setup_debugfs(struct ab5500 *ab)
15{
16}
17
18static inline void ab5500_remove_debugfs(void)
19{
20}
21
22#endif
diff --git a/drivers/mfd/db5500-prcmu.c b/drivers/mfd/db5500-prcmu.c
deleted file mode 100644
index bb115b2f04e9..000000000000
--- a/drivers/mfd/db5500-prcmu.c
+++ /dev/null
@@ -1,451 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
6 *
7 * U5500 PRCM Unit interface driver
8 */
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/spinlock.h>
15#include <linux/io.h>
16#include <linux/slab.h>
17#include <linux/mutex.h>
18#include <linux/completion.h>
19#include <linux/irq.h>
20#include <linux/jiffies.h>
21#include <linux/bitops.h>
22#include <linux/interrupt.h>
23#include <linux/mfd/dbx500-prcmu.h>
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26#include <mach/db5500-regs.h>
27#include "dbx500-prcmu-regs.h"
28
29#define _PRCM_MB_HEADER (tcdm_base + 0xFE8)
30#define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0)
31#define PRCM_REQ_MB1_HEADER (_PRCM_MB_HEADER + 0x1)
32#define PRCM_REQ_MB2_HEADER (_PRCM_MB_HEADER + 0x2)
33#define PRCM_REQ_MB3_HEADER (_PRCM_MB_HEADER + 0x3)
34#define PRCM_REQ_MB4_HEADER (_PRCM_MB_HEADER + 0x4)
35#define PRCM_REQ_MB5_HEADER (_PRCM_MB_HEADER + 0x5)
36#define PRCM_REQ_MB6_HEADER (_PRCM_MB_HEADER + 0x6)
37#define PRCM_REQ_MB7_HEADER (_PRCM_MB_HEADER + 0x7)
38#define PRCM_ACK_MB0_HEADER (_PRCM_MB_HEADER + 0x8)
39#define PRCM_ACK_MB1_HEADER (_PRCM_MB_HEADER + 0x9)
40#define PRCM_ACK_MB2_HEADER (_PRCM_MB_HEADER + 0xa)
41#define PRCM_ACK_MB3_HEADER (_PRCM_MB_HEADER + 0xb)
42#define PRCM_ACK_MB4_HEADER (_PRCM_MB_HEADER + 0xc)
43#define PRCM_ACK_MB5_HEADER (_PRCM_MB_HEADER + 0xd)
44#define PRCM_ACK_MB6_HEADER (_PRCM_MB_HEADER + 0xe)
45#define PRCM_ACK_MB7_HEADER (_PRCM_MB_HEADER + 0xf)
46
47/* Req Mailboxes */
48#define PRCM_REQ_MB0 (tcdm_base + 0xFD8)
49#define PRCM_REQ_MB1 (tcdm_base + 0xFCC)
50#define PRCM_REQ_MB2 (tcdm_base + 0xFC4)
51#define PRCM_REQ_MB3 (tcdm_base + 0xFC0)
52#define PRCM_REQ_MB4 (tcdm_base + 0xF98)
53#define PRCM_REQ_MB5 (tcdm_base + 0xF90)
54#define PRCM_REQ_MB6 (tcdm_base + 0xF8C)
55#define PRCM_REQ_MB7 (tcdm_base + 0xF84)
56
57/* Ack Mailboxes */
58#define PRCM_ACK_MB0 (tcdm_base + 0xF38)
59#define PRCM_ACK_MB1 (tcdm_base + 0xF30)
60#define PRCM_ACK_MB2 (tcdm_base + 0xF24)
61#define PRCM_ACK_MB3 (tcdm_base + 0xF20)
62#define PRCM_ACK_MB4 (tcdm_base + 0xF1C)
63#define PRCM_ACK_MB5 (tcdm_base + 0xF14)
64#define PRCM_ACK_MB6 (tcdm_base + 0xF0C)
65#define PRCM_ACK_MB7 (tcdm_base + 0xF08)
66
67enum mb_return_code {
68 RC_SUCCESS,
69 RC_FAIL,
70};
71
72/* Mailbox 0 headers. */
73enum mb0_header {
74 /* request */
75 RMB0H_PWR_STATE_TRANS = 1,
76 RMB0H_WAKE_UP_CFG,
77 RMB0H_RD_WAKE_UP_ACK,
78 /* acknowledge */
79 AMB0H_WAKE_UP = 1,
80};
81
82/* Mailbox 5 headers. */
83enum mb5_header {
84 MB5H_I2C_WRITE = 1,
85 MB5H_I2C_READ,
86};
87
88/* Request mailbox 5 fields. */
89#define PRCM_REQ_MB5_I2C_SLAVE (PRCM_REQ_MB5 + 0)
90#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 1)
91#define PRCM_REQ_MB5_I2C_SIZE (PRCM_REQ_MB5 + 2)
92#define PRCM_REQ_MB5_I2C_DATA (PRCM_REQ_MB5 + 4)
93
94/* Acknowledge mailbox 5 fields. */
95#define PRCM_ACK_MB5_RETURN_CODE (PRCM_ACK_MB5 + 0)
96#define PRCM_ACK_MB5_I2C_DATA (PRCM_ACK_MB5 + 4)
97
98#define NUM_MB 8
99#define MBOX_BIT BIT
100#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
101
102/*
103* Used by MCDE to setup all necessary PRCMU registers
104*/
105#define PRCMU_RESET_DSIPLL 0x00004000
106#define PRCMU_UNCLAMP_DSIPLL 0x00400800
107
108/* HDMI CLK MGT PLLSW=001 (PLLSOC0), PLLDIV=0x8, = 50 Mhz*/
109#define PRCMU_DSI_CLOCK_SETTING 0x00000128
110/* TVCLK_MGT PLLSW=001 (PLLSOC0) PLLDIV=0x13, = 19.05 MHZ */
111#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000135
112#define PRCMU_PLLDSI_FREQ_SETTING 0x00020121
113#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000002
114#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x03000201
115#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00000101
116
117#define PRCMU_ENABLE_PLLDSI 0x00000001
118#define PRCMU_DISABLE_PLLDSI 0x00000000
119
120#define PRCMU_DSI_RESET_SW 0x00000003
121#define PRCMU_RESOUTN0_PIN 0x00000001
122#define PRCMU_RESOUTN1_PIN 0x00000002
123#define PRCMU_RESOUTN2_PIN 0x00000004
124
125#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
126
127/*
128 * mb0_transfer - state needed for mailbox 0 communication.
129 * @lock: The transaction lock.
130 */
131static struct {
132 spinlock_t lock;
133} mb0_transfer;
134
135/*
136 * mb5_transfer - state needed for mailbox 5 communication.
137 * @lock: The transaction lock.
138 * @work: The transaction completion structure.
139 * @ack: Reply ("acknowledge") data.
140 */
141static struct {
142 struct mutex lock;
143 struct completion work;
144 struct {
145 u8 header;
146 u8 status;
147 u8 value[4];
148 } ack;
149} mb5_transfer;
150
151/* PRCMU TCDM base IO address. */
152static __iomem void *tcdm_base;
153
154/**
155 * db5500_prcmu_abb_read() - Read register value(s) from the ABB.
156 * @slave: The I2C slave address.
157 * @reg: The (start) register address.
158 * @value: The read out value(s).
159 * @size: The number of registers to read.
160 *
161 * Reads register value(s) from the ABB.
162 * @size has to be <= 4.
163 */
164int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
165{
166 int r;
167
168 if ((size < 1) || (4 < size))
169 return -EINVAL;
170
171 mutex_lock(&mb5_transfer.lock);
172
173 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
174 cpu_relax();
175 writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
176 writeb(reg, PRCM_REQ_MB5_I2C_REG);
177 writeb(size, PRCM_REQ_MB5_I2C_SIZE);
178 writeb(MB5H_I2C_READ, PRCM_REQ_MB5_HEADER);
179
180 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
181 wait_for_completion(&mb5_transfer.work);
182
183 r = 0;
184 if ((mb5_transfer.ack.header == MB5H_I2C_READ) &&
185 (mb5_transfer.ack.status == RC_SUCCESS))
186 memcpy(value, mb5_transfer.ack.value, (size_t)size);
187 else
188 r = -EIO;
189
190 mutex_unlock(&mb5_transfer.lock);
191
192 return r;
193}
194
195/**
196 * db5500_prcmu_abb_write() - Write register value(s) to the ABB.
197 * @slave: The I2C slave address.
198 * @reg: The (start) register address.
199 * @value: The value(s) to write.
200 * @size: The number of registers to write.
201 *
202 * Writes register value(s) to the ABB.
203 * @size has to be <= 4.
204 */
205int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
206{
207 int r;
208
209 if ((size < 1) || (4 < size))
210 return -EINVAL;
211
212 mutex_lock(&mb5_transfer.lock);
213
214 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
215 cpu_relax();
216 writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
217 writeb(reg, PRCM_REQ_MB5_I2C_REG);
218 writeb(size, PRCM_REQ_MB5_I2C_SIZE);
219 memcpy_toio(PRCM_REQ_MB5_I2C_DATA, value, size);
220 writeb(MB5H_I2C_WRITE, PRCM_REQ_MB5_HEADER);
221
222 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
223 wait_for_completion(&mb5_transfer.work);
224
225 if ((mb5_transfer.ack.header == MB5H_I2C_WRITE) &&
226 (mb5_transfer.ack.status == RC_SUCCESS))
227 r = 0;
228 else
229 r = -EIO;
230
231 mutex_unlock(&mb5_transfer.lock);
232
233 return r;
234}
235
236int db5500_prcmu_enable_dsipll(void)
237{
238 int i;
239
240 /* Enable DSIPLL_RESETN resets */
241 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
242 /* Unclamp DSIPLL in/out */
243 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
244 /* Set DSI PLL FREQ */
245 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
246 writel(PRCMU_DSI_PLLOUT_SEL_SETTING,
247 PRCM_DSI_PLLOUT_SEL);
248 /* Enable Escape clocks */
249 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
250
251 /* Start DSI PLL */
252 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
253 /* Reset DSI PLL */
254 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
255 for (i = 0; i < 10; i++) {
256 if ((readl(PRCM_PLLDSI_LOCKP) &
257 PRCMU_PLLDSI_LOCKP_LOCKED) == PRCMU_PLLDSI_LOCKP_LOCKED)
258 break;
259 udelay(100);
260 }
261 /* Release DSIPLL_RESETN */
262 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
263 return 0;
264}
265
266int db5500_prcmu_disable_dsipll(void)
267{
268 /* Disable dsi pll */
269 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
270 /* Disable escapeclock */
271 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
272 return 0;
273}
274
275int db5500_prcmu_set_display_clocks(void)
276{
277 /* HDMI and TVCLK Should be handled somewhere else */
278 /* PLLDIV=8, PLLSW=2, CLKEN=1 */
279 writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
280 /* PLLDIV=14, PLLSW=2, CLKEN=1 */
281 writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
282 return 0;
283}
284
285static void ack_dbb_wakeup(void)
286{
287 unsigned long flags;
288
289 spin_lock_irqsave(&mb0_transfer.lock, flags);
290
291 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
292 cpu_relax();
293
294 writeb(RMB0H_RD_WAKE_UP_ACK, PRCM_REQ_MB0_HEADER);
295 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
296
297 spin_unlock_irqrestore(&mb0_transfer.lock, flags);
298}
299
300static inline void print_unknown_header_warning(u8 n, u8 header)
301{
302 pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
303 header, n);
304}
305
306static bool read_mailbox_0(void)
307{
308 bool r;
309 u8 header;
310
311 header = readb(PRCM_ACK_MB0_HEADER);
312 switch (header) {
313 case AMB0H_WAKE_UP:
314 r = true;
315 break;
316 default:
317 print_unknown_header_warning(0, header);
318 r = false;
319 break;
320 }
321 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
322 return r;
323}
324
325static bool read_mailbox_1(void)
326{
327 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
328 return false;
329}
330
331static bool read_mailbox_2(void)
332{
333 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
334 return false;
335}
336
337static bool read_mailbox_3(void)
338{
339 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
340 return false;
341}
342
343static bool read_mailbox_4(void)
344{
345 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
346 return false;
347}
348
349static bool read_mailbox_5(void)
350{
351 u8 header;
352
353 header = readb(PRCM_ACK_MB5_HEADER);
354 switch (header) {
355 case MB5H_I2C_READ:
356 memcpy_fromio(mb5_transfer.ack.value, PRCM_ACK_MB5_I2C_DATA, 4);
357 case MB5H_I2C_WRITE:
358 mb5_transfer.ack.header = header;
359 mb5_transfer.ack.status = readb(PRCM_ACK_MB5_RETURN_CODE);
360 complete(&mb5_transfer.work);
361 break;
362 default:
363 print_unknown_header_warning(5, header);
364 break;
365 }
366 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
367 return false;
368}
369
370static bool read_mailbox_6(void)
371{
372 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
373 return false;
374}
375
376static bool read_mailbox_7(void)
377{
378 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
379 return false;
380}
381
382static bool (* const read_mailbox[NUM_MB])(void) = {
383 read_mailbox_0,
384 read_mailbox_1,
385 read_mailbox_2,
386 read_mailbox_3,
387 read_mailbox_4,
388 read_mailbox_5,
389 read_mailbox_6,
390 read_mailbox_7
391};
392
393static irqreturn_t prcmu_irq_handler(int irq, void *data)
394{
395 u32 bits;
396 u8 n;
397 irqreturn_t r;
398
399 bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
400 if (unlikely(!bits))
401 return IRQ_NONE;
402
403 r = IRQ_HANDLED;
404 for (n = 0; bits; n++) {
405 if (bits & MBOX_BIT(n)) {
406 bits -= MBOX_BIT(n);
407 if (read_mailbox[n]())
408 r = IRQ_WAKE_THREAD;
409 }
410 }
411 return r;
412}
413
414static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
415{
416 ack_dbb_wakeup();
417 return IRQ_HANDLED;
418}
419
420void __init db5500_prcmu_early_init(void)
421{
422 tcdm_base = __io_address(U5500_PRCMU_TCDM_BASE);
423 spin_lock_init(&mb0_transfer.lock);
424 mutex_init(&mb5_transfer.lock);
425 init_completion(&mb5_transfer.work);
426}
427
428/**
429 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
430 *
431 */
432int __init db5500_prcmu_init(void)
433{
434 int r = 0;
435
436 if (ux500_is_svp() || !cpu_is_u5500())
437 return -ENODEV;
438
439 /* Clean up the mailbox interrupts after pre-kernel code. */
440 writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
441
442 r = request_threaded_irq(IRQ_DB5500_PRCMU1, prcmu_irq_handler,
443 prcmu_irq_thread_fn, 0, "prcmu", NULL);
444 if (r < 0) {
445 pr_err("prcmu: Failed to allocate IRQ_DB5500_PRCMU1.\n");
446 return -EBUSY;
447 }
448 return 0;
449}
450
451arch_initcall(db5500_prcmu_init);
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index ee96cd51d8b2..1318ca622633 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -6,7 +6,7 @@
6 * 6 *
7 * ABX500 core access functions. 7 * ABX500 core access functions.
8 * The abx500 interface is used for the Analog Baseband chip 8 * The abx500 interface is used for the Analog Baseband chip
9 * ab3100, ab5500, and ab8500. 9 * ab3100 and ab8500.
10 * 10 *
11 * Author: Mattias Wallin <mattias.wallin@stericsson.com> 11 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
12 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 12 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
@@ -30,9 +30,6 @@ struct device;
30#define AB3100_P1G 0xc6 30#define AB3100_P1G 0xc6
31#define AB3100_R2A 0xc7 31#define AB3100_R2A 0xc7
32#define AB3100_R2B 0xc8 32#define AB3100_R2B 0xc8
33#define AB5500_1_0 0x20
34#define AB5500_1_1 0x21
35#define AB5500_2_0 0x24
36 33
37/* 34/*
38 * AB3100, EVENTA1, A2 and A3 event register flags 35 * AB3100, EVENTA1, A2 and A3 event register flags
diff --git a/include/linux/mfd/abx500/ab5500.h b/include/linux/mfd/abx500/ab5500.h
deleted file mode 100644
index 54f820ed73bb..000000000000
--- a/include/linux/mfd/abx500/ab5500.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson 2011
3 *
4 * License Terms: GNU General Public License v2
5 */
6#ifndef MFD_AB5500_H
7#define MFD_AB5500_H
8
9struct device;
10
11enum ab5500_devid {
12 AB5500_DEVID_ADC,
13 AB5500_DEVID_LEDS,
14 AB5500_DEVID_POWER,
15 AB5500_DEVID_REGULATORS,
16 AB5500_DEVID_SIM,
17 AB5500_DEVID_RTC,
18 AB5500_DEVID_CHARGER,
19 AB5500_DEVID_FUELGAUGE,
20 AB5500_DEVID_VIBRATOR,
21 AB5500_DEVID_CODEC,
22 AB5500_DEVID_USB,
23 AB5500_DEVID_OTP,
24 AB5500_DEVID_VIDEO,
25 AB5500_DEVID_DBIECI,
26 AB5500_DEVID_ONSWA,
27 AB5500_NUM_DEVICES,
28};
29
30enum ab5500_banks {
31 AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP = 0,
32 AB5500_BANK_VDDDIG_IO_I2C_CLK_TST = 1,
33 AB5500_BANK_VDENC = 2,
34 AB5500_BANK_SIM_USBSIM = 3,
35 AB5500_BANK_LED = 4,
36 AB5500_BANK_ADC = 5,
37 AB5500_BANK_RTC = 6,
38 AB5500_BANK_STARTUP = 7,
39 AB5500_BANK_DBI_ECI = 8,
40 AB5500_BANK_CHG = 9,
41 AB5500_BANK_FG_BATTCOM_ACC = 10,
42 AB5500_BANK_USB = 11,
43 AB5500_BANK_IT = 12,
44 AB5500_BANK_VIBRA = 13,
45 AB5500_BANK_AUDIO_HEADSETUSB = 14,
46 AB5500_NUM_BANKS = 15,
47};
48
49enum ab5500_banks_addr {
50 AB5500_ADDR_VIT_IO_I2C_CLK_TST_OTP = 0x4A,
51 AB5500_ADDR_VDDDIG_IO_I2C_CLK_TST = 0x4B,
52 AB5500_ADDR_VDENC = 0x06,
53 AB5500_ADDR_SIM_USBSIM = 0x04,
54 AB5500_ADDR_LED = 0x10,
55 AB5500_ADDR_ADC = 0x0A,
56 AB5500_ADDR_RTC = 0x0F,
57 AB5500_ADDR_STARTUP = 0x03,
58 AB5500_ADDR_DBI_ECI = 0x07,
59 AB5500_ADDR_CHG = 0x0B,
60 AB5500_ADDR_FG_BATTCOM_ACC = 0x0C,
61 AB5500_ADDR_USB = 0x05,
62 AB5500_ADDR_IT = 0x0E,
63 AB5500_ADDR_VIBRA = 0x02,
64 AB5500_ADDR_AUDIO_HEADSETUSB = 0x0D,
65};
66
67/*
68 * Interrupt register offsets
69 * Bank : 0x0E
70 */
71#define AB5500_IT_SOURCE0_REG 0x20
72#define AB5500_IT_SOURCE1_REG 0x21
73#define AB5500_IT_SOURCE2_REG 0x22
74#define AB5500_IT_SOURCE3_REG 0x23
75#define AB5500_IT_SOURCE4_REG 0x24
76#define AB5500_IT_SOURCE5_REG 0x25
77#define AB5500_IT_SOURCE6_REG 0x26
78#define AB5500_IT_SOURCE7_REG 0x27
79#define AB5500_IT_SOURCE8_REG 0x28
80#define AB5500_IT_SOURCE9_REG 0x29
81#define AB5500_IT_SOURCE10_REG 0x2A
82#define AB5500_IT_SOURCE11_REG 0x2B
83#define AB5500_IT_SOURCE12_REG 0x2C
84#define AB5500_IT_SOURCE13_REG 0x2D
85#define AB5500_IT_SOURCE14_REG 0x2E
86#define AB5500_IT_SOURCE15_REG 0x2F
87#define AB5500_IT_SOURCE16_REG 0x30
88#define AB5500_IT_SOURCE17_REG 0x31
89#define AB5500_IT_SOURCE18_REG 0x32
90#define AB5500_IT_SOURCE19_REG 0x33
91#define AB5500_IT_SOURCE20_REG 0x34
92#define AB5500_IT_SOURCE21_REG 0x35
93#define AB5500_IT_SOURCE22_REG 0x36
94#define AB5500_IT_SOURCE23_REG 0x37
95
96#define AB5500_NUM_IRQ_REGS 23
97
98/**
99 * struct ab5500
100 * @access_mutex: lock out concurrent accesses to the AB registers
101 * @dev: a pointer to the device struct for this chip driver
102 * @ab5500_irq: the analog baseband irq
103 * @irq_base: the platform configuration irq base for subdevices
104 * @chip_name: name of this chip variant
105 * @chip_id: 8 bit chip ID for this chip variant
106 * @irq_lock: a lock to protect the mask
107 * @abb_events: a local bit mask of the prcmu wakeup events
108 * @event_mask: a local copy of the mask event registers
109 * @last_event_mask: a copy of the last event_mask written to hardware
110 * @startup_events: a copy of the first reading of the event registers
111 * @startup_events_read: whether the first events have been read
112 */
113struct ab5500 {
114 struct mutex access_mutex;
115 struct device *dev;
116 unsigned int ab5500_irq;
117 unsigned int irq_base;
118 char chip_name[32];
119 u8 chip_id;
120 struct mutex irq_lock;
121 u32 abb_events;
122 u8 mask[AB5500_NUM_IRQ_REGS];
123 u8 oldmask[AB5500_NUM_IRQ_REGS];
124 u8 startup_events[AB5500_NUM_IRQ_REGS];
125 bool startup_events_read;
126#ifdef CONFIG_DEBUG_FS
127 unsigned int debug_bank;
128 unsigned int debug_address;
129#endif
130};
131
132struct ab5500_platform_data {
133 struct {unsigned int base; unsigned int count; } irq;
134 void *dev_data[AB5500_NUM_DEVICES];
135 struct abx500_init_settings *init_settings;
136 unsigned int init_settings_sz;
137 bool pm_power_off;
138};
139
140#endif /* MFD_AB5500_H */
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
deleted file mode 100644
index 5a049dfaf153..000000000000
--- a/include/linux/mfd/db5500-prcmu.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * U5500 PRCMU API.
7 */
8#ifndef __MFD_DB5500_PRCMU_H
9#define __MFD_DB5500_PRCMU_H
10
11static inline int prcmu_resetout(u8 resoutn, u8 state)
12{
13 return 0;
14}
15
16static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state)
17{
18 return 0;
19}
20
21static inline int db5500_prcmu_request_clock(u8 clock, bool enable)
22{
23 return 0;
24}
25
26static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
27 bool keep_ap_pll)
28{
29 return 0;
30}
31
32static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state)
33{
34 return 0;
35}
36
37static inline u16 db5500_prcmu_get_reset_code(void)
38{
39 return 0;
40}
41
42static inline bool db5500_prcmu_is_ac_wake_requested(void)
43{
44 return 0;
45}
46
47static inline int db5500_prcmu_set_arm_opp(u8 opp)
48{
49 return 0;
50}
51
52static inline int db5500_prcmu_get_arm_opp(void)
53{
54 return 0;
55}
56
57static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {}
58
59static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
60
61static inline void db5500_prcmu_system_reset(u16 reset_code) {}
62
63static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {}
64
65#ifdef CONFIG_MFD_DB5500_PRCMU
66
67void db5500_prcmu_early_init(void);
68int db5500_prcmu_set_display_clocks(void);
69int db5500_prcmu_disable_dsipll(void);
70int db5500_prcmu_enable_dsipll(void);
71int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
72int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
73
74#else /* !CONFIG_UX500_SOC_DB5500 */
75
76static inline void db5500_prcmu_early_init(void) {}
77
78static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
79{
80 return -ENOSYS;
81}
82
83static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
84{
85 return -ENOSYS;
86}
87
88static inline int db5500_prcmu_set_display_clocks(void)
89{
90 return 0;
91}
92
93static inline int db5500_prcmu_disable_dsipll(void)
94{
95 return 0;
96}
97
98static inline int db5500_prcmu_enable_dsipll(void)
99{
100 return 0;
101}
102
103#endif /* CONFIG_MFD_DB5500_PRCMU */
104
105#endif /* __MFD_DB5500_PRCMU_H */
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index d7674eb7305f..5a13f93d8f1c 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -55,17 +55,6 @@ enum prcmu_wakeup_index {
55#define NUM_EPOD_ID 8 55#define NUM_EPOD_ID 8
56 56
57/* 57/*
58 * DB5500 EPODs
59 */
60#define DB5500_EPOD_ID_BASE 0x0100
61#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
62#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
63#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
64#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
65#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
66#define DB5500_NUM_EPOD_ID 7
67
68/*
69 * state definition for EPOD (power domain) 58 * state definition for EPOD (power domain)
70 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged 59 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
71 * - EPOD_STATE_OFF: The EPOD is switched off 60 * - EPOD_STATE_OFF: The EPOD is switched off
@@ -80,29 +69,6 @@ enum prcmu_wakeup_index {
80#define EPOD_STATE_ON_CLK_OFF 0x03 69#define EPOD_STATE_ON_CLK_OFF 0x03
81#define EPOD_STATE_ON 0x04 70#define EPOD_STATE_ON 0x04
82 71
83/* DB5500 CLKOUT IDs */
84enum {
85 DB5500_CLKOUT0 = 0,
86 DB5500_CLKOUT1,
87};
88
89/* DB5500 CLKOUTx sources */
90enum {
91 DB5500_CLKOUT_REF_CLK_SEL0,
92 DB5500_CLKOUT_RTC_CLK0_SEL0,
93 DB5500_CLKOUT_ULP_CLK_SEL0,
94 DB5500_CLKOUT_STATIC0,
95 DB5500_CLKOUT_REFCLK,
96 DB5500_CLKOUT_ULPCLK,
97 DB5500_CLKOUT_ARMCLK,
98 DB5500_CLKOUT_SYSACC0CLK,
99 DB5500_CLKOUT_SOC0PLLCLK,
100 DB5500_CLKOUT_SOC1PLLCLK,
101 DB5500_CLKOUT_DDRPLLCLK,
102 DB5500_CLKOUT_TVCLK,
103 DB5500_CLKOUT_IRDACLK,
104};
105
106/* 72/*
107 * CLKOUT sources 73 * CLKOUT sources
108 */ 74 */
@@ -248,101 +214,66 @@ enum ddr_pwrst {
248}; 214};
249 215
250#include <linux/mfd/db8500-prcmu.h> 216#include <linux/mfd/db8500-prcmu.h>
251#include <linux/mfd/db5500-prcmu.h>
252 217
253#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) 218#if defined(CONFIG_UX500_SOC_DB8500)
254 219
255#include <mach/id.h> 220#include <mach/id.h>
256 221
257static inline void __init prcmu_early_init(void) 222static inline void __init prcmu_early_init(void)
258{ 223{
259 if (cpu_is_u5500()) 224 return db8500_prcmu_early_init();
260 return db5500_prcmu_early_init();
261 else
262 return db8500_prcmu_early_init();
263} 225}
264 226
265static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 227static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
266 bool keep_ap_pll) 228 bool keep_ap_pll)
267{ 229{
268 if (cpu_is_u5500()) 230 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
269 return db5500_prcmu_set_power_state(state, keep_ulp_clk, 231 keep_ap_pll);
270 keep_ap_pll);
271 else
272 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
273 keep_ap_pll);
274} 232}
275 233
276static inline u8 prcmu_get_power_state_result(void) 234static inline u8 prcmu_get_power_state_result(void)
277{ 235{
278 if (cpu_is_u5500()) 236 return db8500_prcmu_get_power_state_result();
279 return -EINVAL;
280 else
281 return db8500_prcmu_get_power_state_result();
282} 237}
283 238
284static inline int prcmu_gic_decouple(void) 239static inline int prcmu_gic_decouple(void)
285{ 240{
286 if (cpu_is_u5500()) 241 return db8500_prcmu_gic_decouple();
287 return -EINVAL;
288 else
289 return db8500_prcmu_gic_decouple();
290} 242}
291 243
292static inline int prcmu_gic_recouple(void) 244static inline int prcmu_gic_recouple(void)
293{ 245{
294 if (cpu_is_u5500()) 246 return db8500_prcmu_gic_recouple();
295 return -EINVAL;
296 else
297 return db8500_prcmu_gic_recouple();
298} 247}
299 248
300static inline bool prcmu_gic_pending_irq(void) 249static inline bool prcmu_gic_pending_irq(void)
301{ 250{
302 if (cpu_is_u5500()) 251 return db8500_prcmu_gic_pending_irq();
303 return -EINVAL;
304 else
305 return db8500_prcmu_gic_pending_irq();
306} 252}
307 253
308static inline bool prcmu_is_cpu_in_wfi(int cpu) 254static inline bool prcmu_is_cpu_in_wfi(int cpu)
309{ 255{
310 if (cpu_is_u5500()) 256 return db8500_prcmu_is_cpu_in_wfi(cpu);
311 return -EINVAL;
312 else
313 return db8500_prcmu_is_cpu_in_wfi(cpu);
314} 257}
315 258
316static inline int prcmu_copy_gic_settings(void) 259static inline int prcmu_copy_gic_settings(void)
317{ 260{
318 if (cpu_is_u5500()) 261 return db8500_prcmu_copy_gic_settings();
319 return -EINVAL;
320 else
321 return db8500_prcmu_copy_gic_settings();
322} 262}
323 263
324static inline bool prcmu_pending_irq(void) 264static inline bool prcmu_pending_irq(void)
325{ 265{
326 if (cpu_is_u5500()) 266 return db8500_prcmu_pending_irq();
327 return -EINVAL;
328 else
329 return db8500_prcmu_pending_irq();
330} 267}
331 268
332static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 269static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
333{ 270{
334 if (cpu_is_u5500()) 271 return db8500_prcmu_set_epod(epod_id, epod_state);
335 return -EINVAL;
336 else
337 return db8500_prcmu_set_epod(epod_id, epod_state);
338} 272}
339 273
340static inline void prcmu_enable_wakeups(u32 wakeups) 274static inline void prcmu_enable_wakeups(u32 wakeups)
341{ 275{
342 if (cpu_is_u5500()) 276 db8500_prcmu_enable_wakeups(wakeups);
343 db5500_prcmu_enable_wakeups(wakeups);
344 else
345 db8500_prcmu_enable_wakeups(wakeups);
346} 277}
347 278
348static inline void prcmu_disable_wakeups(void) 279static inline void prcmu_disable_wakeups(void)
@@ -352,18 +283,12 @@ static inline void prcmu_disable_wakeups(void)
352 283
353static inline void prcmu_config_abb_event_readout(u32 abb_events) 284static inline void prcmu_config_abb_event_readout(u32 abb_events)
354{ 285{
355 if (cpu_is_u5500()) 286 db8500_prcmu_config_abb_event_readout(abb_events);
356 db5500_prcmu_config_abb_event_readout(abb_events);
357 else
358 db8500_prcmu_config_abb_event_readout(abb_events);
359} 287}
360 288
361static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 289static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
362{ 290{
363 if (cpu_is_u5500()) 291 db8500_prcmu_get_abb_event_buffer(buf);
364 db5500_prcmu_get_abb_event_buffer(buf);
365 else
366 db8500_prcmu_get_abb_event_buffer(buf);
367} 292}
368 293
369int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 294int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
@@ -374,10 +299,7 @@ int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
374 299
375static inline int prcmu_request_clock(u8 clock, bool enable) 300static inline int prcmu_request_clock(u8 clock, bool enable)
376{ 301{
377 if (cpu_is_u5500()) 302 return db8500_prcmu_request_clock(clock, enable);
378 return db5500_prcmu_request_clock(clock, enable);
379 else
380 return db8500_prcmu_request_clock(clock, enable);
381} 303}
382 304
383unsigned long prcmu_clock_rate(u8 clock); 305unsigned long prcmu_clock_rate(u8 clock);
@@ -386,211 +308,133 @@ int prcmu_set_clock_rate(u8 clock, unsigned long rate);
386 308
387static inline int prcmu_set_ddr_opp(u8 opp) 309static inline int prcmu_set_ddr_opp(u8 opp)
388{ 310{
389 if (cpu_is_u5500()) 311 return db8500_prcmu_set_ddr_opp(opp);
390 return -EINVAL;
391 else
392 return db8500_prcmu_set_ddr_opp(opp);
393} 312}
394static inline int prcmu_get_ddr_opp(void) 313static inline int prcmu_get_ddr_opp(void)
395{ 314{
396 if (cpu_is_u5500()) 315 return db8500_prcmu_get_ddr_opp();
397 return -EINVAL;
398 else
399 return db8500_prcmu_get_ddr_opp();
400} 316}
401 317
402static inline int prcmu_set_arm_opp(u8 opp) 318static inline int prcmu_set_arm_opp(u8 opp)
403{ 319{
404 if (cpu_is_u5500()) 320 return db8500_prcmu_set_arm_opp(opp);
405 return -EINVAL;
406 else
407 return db8500_prcmu_set_arm_opp(opp);
408} 321}
409 322
410static inline int prcmu_get_arm_opp(void) 323static inline int prcmu_get_arm_opp(void)
411{ 324{
412 if (cpu_is_u5500()) 325 return db8500_prcmu_get_arm_opp();
413 return -EINVAL;
414 else
415 return db8500_prcmu_get_arm_opp();
416} 326}
417 327
418static inline int prcmu_set_ape_opp(u8 opp) 328static inline int prcmu_set_ape_opp(u8 opp)
419{ 329{
420 if (cpu_is_u5500()) 330 return db8500_prcmu_set_ape_opp(opp);
421 return -EINVAL;
422 else
423 return db8500_prcmu_set_ape_opp(opp);
424} 331}
425 332
426static inline int prcmu_get_ape_opp(void) 333static inline int prcmu_get_ape_opp(void)
427{ 334{
428 if (cpu_is_u5500()) 335 return db8500_prcmu_get_ape_opp();
429 return -EINVAL;
430 else
431 return db8500_prcmu_get_ape_opp();
432} 336}
433 337
434static inline void prcmu_system_reset(u16 reset_code) 338static inline void prcmu_system_reset(u16 reset_code)
435{ 339{
436 if (cpu_is_u5500()) 340 return db8500_prcmu_system_reset(reset_code);
437 return db5500_prcmu_system_reset(reset_code);
438 else
439 return db8500_prcmu_system_reset(reset_code);
440} 341}
441 342
442static inline u16 prcmu_get_reset_code(void) 343static inline u16 prcmu_get_reset_code(void)
443{ 344{
444 if (cpu_is_u5500()) 345 return db8500_prcmu_get_reset_code();
445 return db5500_prcmu_get_reset_code();
446 else
447 return db8500_prcmu_get_reset_code();
448} 346}
449 347
450void prcmu_ac_wake_req(void); 348void prcmu_ac_wake_req(void);
451void prcmu_ac_sleep_req(void); 349void prcmu_ac_sleep_req(void);
452static inline void prcmu_modem_reset(void) 350static inline void prcmu_modem_reset(void)
453{ 351{
454 if (cpu_is_u5500()) 352 return db8500_prcmu_modem_reset();
455 return;
456 else
457 return db8500_prcmu_modem_reset();
458} 353}
459 354
460static inline bool prcmu_is_ac_wake_requested(void) 355static inline bool prcmu_is_ac_wake_requested(void)
461{ 356{
462 if (cpu_is_u5500()) 357 return db8500_prcmu_is_ac_wake_requested();
463 return db5500_prcmu_is_ac_wake_requested();
464 else
465 return db8500_prcmu_is_ac_wake_requested();
466} 358}
467 359
468static inline int prcmu_set_display_clocks(void) 360static inline int prcmu_set_display_clocks(void)
469{ 361{
470 if (cpu_is_u5500()) 362 return db8500_prcmu_set_display_clocks();
471 return db5500_prcmu_set_display_clocks();
472 else
473 return db8500_prcmu_set_display_clocks();
474} 363}
475 364
476static inline int prcmu_disable_dsipll(void) 365static inline int prcmu_disable_dsipll(void)
477{ 366{
478 if (cpu_is_u5500()) 367 return db8500_prcmu_disable_dsipll();
479 return db5500_prcmu_disable_dsipll();
480 else
481 return db8500_prcmu_disable_dsipll();
482} 368}
483 369
484static inline int prcmu_enable_dsipll(void) 370static inline int prcmu_enable_dsipll(void)
485{ 371{
486 if (cpu_is_u5500()) 372 return db8500_prcmu_enable_dsipll();
487 return db5500_prcmu_enable_dsipll();
488 else
489 return db8500_prcmu_enable_dsipll();
490} 373}
491 374
492static inline int prcmu_config_esram0_deep_sleep(u8 state) 375static inline int prcmu_config_esram0_deep_sleep(u8 state)
493{ 376{
494 if (cpu_is_u5500()) 377 return db8500_prcmu_config_esram0_deep_sleep(state);
495 return -EINVAL;
496 else
497 return db8500_prcmu_config_esram0_deep_sleep(state);
498} 378}
499 379
500static inline int prcmu_config_hotdog(u8 threshold) 380static inline int prcmu_config_hotdog(u8 threshold)
501{ 381{
502 if (cpu_is_u5500()) 382 return db8500_prcmu_config_hotdog(threshold);
503 return -EINVAL;
504 else
505 return db8500_prcmu_config_hotdog(threshold);
506} 383}
507 384
508static inline int prcmu_config_hotmon(u8 low, u8 high) 385static inline int prcmu_config_hotmon(u8 low, u8 high)
509{ 386{
510 if (cpu_is_u5500()) 387 return db8500_prcmu_config_hotmon(low, high);
511 return -EINVAL;
512 else
513 return db8500_prcmu_config_hotmon(low, high);
514} 388}
515 389
516static inline int prcmu_start_temp_sense(u16 cycles32k) 390static inline int prcmu_start_temp_sense(u16 cycles32k)
517{ 391{
518 if (cpu_is_u5500()) 392 return db8500_prcmu_start_temp_sense(cycles32k);
519 return -EINVAL;
520 else
521 return db8500_prcmu_start_temp_sense(cycles32k);
522} 393}
523 394
524static inline int prcmu_stop_temp_sense(void) 395static inline int prcmu_stop_temp_sense(void)
525{ 396{
526 if (cpu_is_u5500()) 397 return db8500_prcmu_stop_temp_sense();
527 return -EINVAL;
528 else
529 return db8500_prcmu_stop_temp_sense();
530} 398}
531 399
532static inline u32 prcmu_read(unsigned int reg) 400static inline u32 prcmu_read(unsigned int reg)
533{ 401{
534 if (cpu_is_u5500()) 402 return db8500_prcmu_read(reg);
535 return -EINVAL;
536 else
537 return db8500_prcmu_read(reg);
538} 403}
539 404
540static inline void prcmu_write(unsigned int reg, u32 value) 405static inline void prcmu_write(unsigned int reg, u32 value)
541{ 406{
542 if (cpu_is_u5500()) 407 db8500_prcmu_write(reg, value);
543 return;
544 else
545 db8500_prcmu_write(reg, value);
546} 408}
547 409
548static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 410static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
549{ 411{
550 if (cpu_is_u5500()) 412 db8500_prcmu_write_masked(reg, mask, value);
551 return;
552 else
553 db8500_prcmu_write_masked(reg, mask, value);
554} 413}
555 414
556static inline int prcmu_enable_a9wdog(u8 id) 415static inline int prcmu_enable_a9wdog(u8 id)
557{ 416{
558 if (cpu_is_u5500()) 417 return db8500_prcmu_enable_a9wdog(id);
559 return -EINVAL;
560 else
561 return db8500_prcmu_enable_a9wdog(id);
562} 418}
563 419
564static inline int prcmu_disable_a9wdog(u8 id) 420static inline int prcmu_disable_a9wdog(u8 id)
565{ 421{
566 if (cpu_is_u5500()) 422 return db8500_prcmu_disable_a9wdog(id);
567 return -EINVAL;
568 else
569 return db8500_prcmu_disable_a9wdog(id);
570} 423}
571 424
572static inline int prcmu_kick_a9wdog(u8 id) 425static inline int prcmu_kick_a9wdog(u8 id)
573{ 426{
574 if (cpu_is_u5500()) 427 return db8500_prcmu_kick_a9wdog(id);
575 return -EINVAL;
576 else
577 return db8500_prcmu_kick_a9wdog(id);
578} 428}
579 429
580static inline int prcmu_load_a9wdog(u8 id, u32 timeout) 430static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
581{ 431{
582 if (cpu_is_u5500()) 432 return db8500_prcmu_load_a9wdog(id, timeout);
583 return -EINVAL;
584 else
585 return db8500_prcmu_load_a9wdog(id, timeout);
586} 433}
587 434
588static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 435static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
589{ 436{
590 if (cpu_is_u5500()) 437 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
591 return -EINVAL;
592 else
593 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
594} 438}
595#else 439#else
596 440
@@ -768,7 +612,7 @@ static inline void prcmu_clear(unsigned int reg, u32 bits)
768 prcmu_write_masked(reg, bits, 0); 612 prcmu_write_masked(reg, bits, 0);
769} 613}
770 614
771#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) 615#if defined(CONFIG_UX500_SOC_DB8500)
772 616
773/** 617/**
774 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. 618 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 12:45:04 -0400