drm/radeon: Use write-combined CPU mappings of IBs on >= CIK

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 16 insertions, 4 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 7cfea7e4583f..20b0e4faf7ae 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -201,10 +201,22 @@ int radeon_ib_pool_init(struct radeon_device *rdev)
         if (rdev->ib_pool_ready) {
                 return 0;
         }
-        r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
-                                      RADEON_IB_POOL_SIZE*64*1024,
-                                      RADEON_GPU_PAGE_SIZE,
-                                      RADEON_GEM_DOMAIN_GTT, 0);
+
+        if (rdev->family >= CHIP_BONAIRE) {
+                r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
+                                              RADEON_IB_POOL_SIZE*64*1024,
+                                              RADEON_GPU_PAGE_SIZE,
+                                              RADEON_GEM_DOMAIN_GTT,
+                                              RADEON_GEM_GTT_WC);
+        } else {
+                /* Before CIK, it's better to stick to cacheable GTT due
+                 * to the command stream checking
+                 */
+                r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
+                                              RADEON_IB_POOL_SIZE*64*1024,
+                                              RADEON_GPU_PAGE_SIZE,
+                                              RADEON_GEM_DOMAIN_GTT, 0);
+        }
         if (r) {
                 return r;
         }