diff options
author | Rasesh Mody <rmody@brocade.com> | 2011-08-02 08:36:05 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-08-03 06:24:39 -0400 |
commit | 80a3809db18b859dfd1eb9045e684d8123415709 (patch) | |
tree | 500dc31feffd9b25f34aa14d8b440a17af14ac55 | |
parent | 12004ae99c009a4ff3c8ea0843f1980aa5bcb4ea (diff) |
bna: Remove get_regs Ethtool Support
Change details:
- This patch contains removal of get_regs support in bnad_ethtool.c. Thus
BNA will have minimal register definitions necessary for MBOX and
interrupt operations
Signed-off-by: Rasesh Mody <rmody@brocade.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/bna/bnad_ethtool.c | 319 |
1 files changed, 0 insertions, 319 deletions
diff --git a/drivers/net/bna/bnad_ethtool.c b/drivers/net/bna/bnad_ethtool.c index fea07f19a5db..49174f87f4d1 100644 --- a/drivers/net/bna/bnad_ethtool.c +++ b/drivers/net/bna/bnad_ethtool.c | |||
@@ -288,323 +288,6 @@ bnad_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) | |||
288 | strncpy(drvinfo->bus_info, pci_name(bnad->pcidev), ETHTOOL_BUSINFO_LEN); | 288 | strncpy(drvinfo->bus_info, pci_name(bnad->pcidev), ETHTOOL_BUSINFO_LEN); |
289 | } | 289 | } |
290 | 290 | ||
291 | static int | ||
292 | get_regs(struct bnad *bnad, u32 * regs) | ||
293 | { | ||
294 | int num = 0, i; | ||
295 | u32 reg_addr; | ||
296 | unsigned long flags; | ||
297 | |||
298 | #define BNAD_GET_REG(addr) \ | ||
299 | do { \ | ||
300 | if (regs) \ | ||
301 | regs[num++] = readl(bnad->bar0 + (addr)); \ | ||
302 | else \ | ||
303 | num++; \ | ||
304 | } while (0) | ||
305 | |||
306 | spin_lock_irqsave(&bnad->bna_lock, flags); | ||
307 | |||
308 | /* DMA Block Internal Registers */ | ||
309 | BNAD_GET_REG(DMA_CTRL_REG0); | ||
310 | BNAD_GET_REG(DMA_CTRL_REG1); | ||
311 | BNAD_GET_REG(DMA_ERR_INT_STATUS); | ||
312 | BNAD_GET_REG(DMA_ERR_INT_ENABLE); | ||
313 | BNAD_GET_REG(DMA_ERR_INT_STATUS_SET); | ||
314 | |||
315 | /* APP Block Register Address Offset from BAR0 */ | ||
316 | BNAD_GET_REG(HOSTFN0_INT_STATUS); | ||
317 | BNAD_GET_REG(HOSTFN0_INT_MASK); | ||
318 | BNAD_GET_REG(HOST_PAGE_NUM_FN0); | ||
319 | BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN0); | ||
320 | BNAD_GET_REG(FN0_PCIE_ERR_REG); | ||
321 | BNAD_GET_REG(FN0_ERR_TYPE_STATUS_REG); | ||
322 | BNAD_GET_REG(FN0_ERR_TYPE_MSK_STATUS_REG); | ||
323 | |||
324 | BNAD_GET_REG(HOSTFN1_INT_STATUS); | ||
325 | BNAD_GET_REG(HOSTFN1_INT_MASK); | ||
326 | BNAD_GET_REG(HOST_PAGE_NUM_FN1); | ||
327 | BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN1); | ||
328 | BNAD_GET_REG(FN1_PCIE_ERR_REG); | ||
329 | BNAD_GET_REG(FN1_ERR_TYPE_STATUS_REG); | ||
330 | BNAD_GET_REG(FN1_ERR_TYPE_MSK_STATUS_REG); | ||
331 | |||
332 | BNAD_GET_REG(PCIE_MISC_REG); | ||
333 | |||
334 | BNAD_GET_REG(HOST_SEM0_INFO_REG); | ||
335 | BNAD_GET_REG(HOST_SEM1_INFO_REG); | ||
336 | BNAD_GET_REG(HOST_SEM2_INFO_REG); | ||
337 | BNAD_GET_REG(HOST_SEM3_INFO_REG); | ||
338 | |||
339 | BNAD_GET_REG(TEMPSENSE_CNTL_REG); | ||
340 | BNAD_GET_REG(TEMPSENSE_STAT_REG); | ||
341 | |||
342 | BNAD_GET_REG(APP_LOCAL_ERR_STAT); | ||
343 | BNAD_GET_REG(APP_LOCAL_ERR_MSK); | ||
344 | |||
345 | BNAD_GET_REG(PCIE_LNK_ERR_STAT); | ||
346 | BNAD_GET_REG(PCIE_LNK_ERR_MSK); | ||
347 | |||
348 | BNAD_GET_REG(FCOE_FIP_ETH_TYPE); | ||
349 | BNAD_GET_REG(RESV_ETH_TYPE); | ||
350 | |||
351 | BNAD_GET_REG(HOSTFN2_INT_STATUS); | ||
352 | BNAD_GET_REG(HOSTFN2_INT_MASK); | ||
353 | BNAD_GET_REG(HOST_PAGE_NUM_FN2); | ||
354 | BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN2); | ||
355 | BNAD_GET_REG(FN2_PCIE_ERR_REG); | ||
356 | BNAD_GET_REG(FN2_ERR_TYPE_STATUS_REG); | ||
357 | BNAD_GET_REG(FN2_ERR_TYPE_MSK_STATUS_REG); | ||
358 | |||
359 | BNAD_GET_REG(HOSTFN3_INT_STATUS); | ||
360 | BNAD_GET_REG(HOSTFN3_INT_MASK); | ||
361 | BNAD_GET_REG(HOST_PAGE_NUM_FN3); | ||
362 | BNAD_GET_REG(HOST_MSIX_ERR_INDEX_FN3); | ||
363 | BNAD_GET_REG(FN3_PCIE_ERR_REG); | ||
364 | BNAD_GET_REG(FN3_ERR_TYPE_STATUS_REG); | ||
365 | BNAD_GET_REG(FN3_ERR_TYPE_MSK_STATUS_REG); | ||
366 | |||
367 | /* Host Command Status Registers */ | ||
368 | reg_addr = HOST_CMDSTS0_CLR_REG; | ||
369 | for (i = 0; i < 16; i++) { | ||
370 | BNAD_GET_REG(reg_addr); | ||
371 | BNAD_GET_REG(reg_addr + 4); | ||
372 | BNAD_GET_REG(reg_addr + 8); | ||
373 | reg_addr += 0x10; | ||
374 | } | ||
375 | |||
376 | /* Function ID register */ | ||
377 | BNAD_GET_REG(FNC_ID_REG); | ||
378 | |||
379 | /* Function personality register */ | ||
380 | BNAD_GET_REG(FNC_PERS_REG); | ||
381 | |||
382 | /* Operation mode register */ | ||
383 | BNAD_GET_REG(OP_MODE); | ||
384 | |||
385 | /* LPU0 Registers */ | ||
386 | BNAD_GET_REG(LPU0_MBOX_CTL_REG); | ||
387 | BNAD_GET_REG(LPU0_MBOX_CMD_REG); | ||
388 | BNAD_GET_REG(LPU0_MBOX_LINK_0REG); | ||
389 | BNAD_GET_REG(LPU1_MBOX_LINK_0REG); | ||
390 | BNAD_GET_REG(LPU0_MBOX_STATUS_0REG); | ||
391 | BNAD_GET_REG(LPU1_MBOX_STATUS_0REG); | ||
392 | BNAD_GET_REG(LPU0_ERR_STATUS_REG); | ||
393 | BNAD_GET_REG(LPU0_ERR_SET_REG); | ||
394 | |||
395 | /* LPU1 Registers */ | ||
396 | BNAD_GET_REG(LPU1_MBOX_CTL_REG); | ||
397 | BNAD_GET_REG(LPU1_MBOX_CMD_REG); | ||
398 | BNAD_GET_REG(LPU0_MBOX_LINK_1REG); | ||
399 | BNAD_GET_REG(LPU1_MBOX_LINK_1REG); | ||
400 | BNAD_GET_REG(LPU0_MBOX_STATUS_1REG); | ||
401 | BNAD_GET_REG(LPU1_MBOX_STATUS_1REG); | ||
402 | BNAD_GET_REG(LPU1_ERR_STATUS_REG); | ||
403 | BNAD_GET_REG(LPU1_ERR_SET_REG); | ||
404 | |||
405 | /* PSS Registers */ | ||
406 | BNAD_GET_REG(PSS_CTL_REG); | ||
407 | BNAD_GET_REG(PSS_ERR_STATUS_REG); | ||
408 | BNAD_GET_REG(ERR_STATUS_SET); | ||
409 | BNAD_GET_REG(PSS_RAM_ERR_STATUS_REG); | ||
410 | |||
411 | /* Catapult CPQ Registers */ | ||
412 | BNAD_GET_REG(HOSTFN0_LPU0_MBOX0_CMD_STAT); | ||
413 | BNAD_GET_REG(HOSTFN0_LPU1_MBOX0_CMD_STAT); | ||
414 | BNAD_GET_REG(LPU0_HOSTFN0_MBOX0_CMD_STAT); | ||
415 | BNAD_GET_REG(LPU1_HOSTFN0_MBOX0_CMD_STAT); | ||
416 | |||
417 | BNAD_GET_REG(HOSTFN0_LPU0_MBOX1_CMD_STAT); | ||
418 | BNAD_GET_REG(HOSTFN0_LPU1_MBOX1_CMD_STAT); | ||
419 | BNAD_GET_REG(LPU0_HOSTFN0_MBOX1_CMD_STAT); | ||
420 | BNAD_GET_REG(LPU1_HOSTFN0_MBOX1_CMD_STAT); | ||
421 | |||
422 | BNAD_GET_REG(HOSTFN1_LPU0_MBOX0_CMD_STAT); | ||
423 | BNAD_GET_REG(HOSTFN1_LPU1_MBOX0_CMD_STAT); | ||
424 | BNAD_GET_REG(LPU0_HOSTFN1_MBOX0_CMD_STAT); | ||
425 | BNAD_GET_REG(LPU1_HOSTFN1_MBOX0_CMD_STAT); | ||
426 | |||
427 | BNAD_GET_REG(HOSTFN1_LPU0_MBOX1_CMD_STAT); | ||
428 | BNAD_GET_REG(HOSTFN1_LPU1_MBOX1_CMD_STAT); | ||
429 | BNAD_GET_REG(LPU0_HOSTFN1_MBOX1_CMD_STAT); | ||
430 | BNAD_GET_REG(LPU1_HOSTFN1_MBOX1_CMD_STAT); | ||
431 | |||
432 | BNAD_GET_REG(HOSTFN2_LPU0_MBOX0_CMD_STAT); | ||
433 | BNAD_GET_REG(HOSTFN2_LPU1_MBOX0_CMD_STAT); | ||
434 | BNAD_GET_REG(LPU0_HOSTFN2_MBOX0_CMD_STAT); | ||
435 | BNAD_GET_REG(LPU1_HOSTFN2_MBOX0_CMD_STAT); | ||
436 | |||
437 | BNAD_GET_REG(HOSTFN2_LPU0_MBOX1_CMD_STAT); | ||
438 | BNAD_GET_REG(HOSTFN2_LPU1_MBOX1_CMD_STAT); | ||
439 | BNAD_GET_REG(LPU0_HOSTFN2_MBOX1_CMD_STAT); | ||
440 | BNAD_GET_REG(LPU1_HOSTFN2_MBOX1_CMD_STAT); | ||
441 | |||
442 | BNAD_GET_REG(HOSTFN3_LPU0_MBOX0_CMD_STAT); | ||
443 | BNAD_GET_REG(HOSTFN3_LPU1_MBOX0_CMD_STAT); | ||
444 | BNAD_GET_REG(LPU0_HOSTFN3_MBOX0_CMD_STAT); | ||
445 | BNAD_GET_REG(LPU1_HOSTFN3_MBOX0_CMD_STAT); | ||
446 | |||
447 | BNAD_GET_REG(HOSTFN3_LPU0_MBOX1_CMD_STAT); | ||
448 | BNAD_GET_REG(HOSTFN3_LPU1_MBOX1_CMD_STAT); | ||
449 | BNAD_GET_REG(LPU0_HOSTFN3_MBOX1_CMD_STAT); | ||
450 | BNAD_GET_REG(LPU1_HOSTFN3_MBOX1_CMD_STAT); | ||
451 | |||
452 | /* Host Function Force Parity Error Registers */ | ||
453 | BNAD_GET_REG(HOSTFN0_LPU_FORCE_PERR); | ||
454 | BNAD_GET_REG(HOSTFN1_LPU_FORCE_PERR); | ||
455 | BNAD_GET_REG(HOSTFN2_LPU_FORCE_PERR); | ||
456 | BNAD_GET_REG(HOSTFN3_LPU_FORCE_PERR); | ||
457 | |||
458 | /* LL Port[0|1] Halt Mask Registers */ | ||
459 | BNAD_GET_REG(LL_HALT_MSK_P0); | ||
460 | BNAD_GET_REG(LL_HALT_MSK_P1); | ||
461 | |||
462 | /* LL Port[0|1] Error Mask Registers */ | ||
463 | BNAD_GET_REG(LL_ERR_MSK_P0); | ||
464 | BNAD_GET_REG(LL_ERR_MSK_P1); | ||
465 | |||
466 | /* EMC FLI Registers */ | ||
467 | BNAD_GET_REG(FLI_CMD_REG); | ||
468 | BNAD_GET_REG(FLI_ADDR_REG); | ||
469 | BNAD_GET_REG(FLI_CTL_REG); | ||
470 | BNAD_GET_REG(FLI_WRDATA_REG); | ||
471 | BNAD_GET_REG(FLI_RDDATA_REG); | ||
472 | BNAD_GET_REG(FLI_DEV_STATUS_REG); | ||
473 | BNAD_GET_REG(FLI_SIG_WD_REG); | ||
474 | |||
475 | BNAD_GET_REG(FLI_DEV_VENDOR_REG); | ||
476 | BNAD_GET_REG(FLI_ERR_STATUS_REG); | ||
477 | |||
478 | /* RxAdm 0 Registers */ | ||
479 | BNAD_GET_REG(RAD0_CTL_REG); | ||
480 | BNAD_GET_REG(RAD0_PE_PARM_REG); | ||
481 | BNAD_GET_REG(RAD0_BCN_REG); | ||
482 | BNAD_GET_REG(RAD0_DEFAULT_REG); | ||
483 | BNAD_GET_REG(RAD0_PROMISC_REG); | ||
484 | BNAD_GET_REG(RAD0_BCNQ_REG); | ||
485 | BNAD_GET_REG(RAD0_DEFAULTQ_REG); | ||
486 | |||
487 | BNAD_GET_REG(RAD0_ERR_STS); | ||
488 | BNAD_GET_REG(RAD0_SET_ERR_STS); | ||
489 | BNAD_GET_REG(RAD0_ERR_INT_EN); | ||
490 | BNAD_GET_REG(RAD0_FIRST_ERR); | ||
491 | BNAD_GET_REG(RAD0_FORCE_ERR); | ||
492 | |||
493 | BNAD_GET_REG(RAD0_MAC_MAN_1H); | ||
494 | BNAD_GET_REG(RAD0_MAC_MAN_1L); | ||
495 | BNAD_GET_REG(RAD0_MAC_MAN_2H); | ||
496 | BNAD_GET_REG(RAD0_MAC_MAN_2L); | ||
497 | BNAD_GET_REG(RAD0_MAC_MAN_3H); | ||
498 | BNAD_GET_REG(RAD0_MAC_MAN_3L); | ||
499 | BNAD_GET_REG(RAD0_MAC_MAN_4H); | ||
500 | BNAD_GET_REG(RAD0_MAC_MAN_4L); | ||
501 | |||
502 | BNAD_GET_REG(RAD0_LAST4_IP); | ||
503 | |||
504 | /* RxAdm 1 Registers */ | ||
505 | BNAD_GET_REG(RAD1_CTL_REG); | ||
506 | BNAD_GET_REG(RAD1_PE_PARM_REG); | ||
507 | BNAD_GET_REG(RAD1_BCN_REG); | ||
508 | BNAD_GET_REG(RAD1_DEFAULT_REG); | ||
509 | BNAD_GET_REG(RAD1_PROMISC_REG); | ||
510 | BNAD_GET_REG(RAD1_BCNQ_REG); | ||
511 | BNAD_GET_REG(RAD1_DEFAULTQ_REG); | ||
512 | |||
513 | BNAD_GET_REG(RAD1_ERR_STS); | ||
514 | BNAD_GET_REG(RAD1_SET_ERR_STS); | ||
515 | BNAD_GET_REG(RAD1_ERR_INT_EN); | ||
516 | |||
517 | /* TxA0 Registers */ | ||
518 | BNAD_GET_REG(TXA0_CTRL_REG); | ||
519 | /* TxA0 TSO Sequence # Registers (RO) */ | ||
520 | for (i = 0; i < 8; i++) { | ||
521 | BNAD_GET_REG(TXA0_TSO_TCP_SEQ_REG(i)); | ||
522 | BNAD_GET_REG(TXA0_TSO_IP_INFO_REG(i)); | ||
523 | } | ||
524 | |||
525 | /* TxA1 Registers */ | ||
526 | BNAD_GET_REG(TXA1_CTRL_REG); | ||
527 | /* TxA1 TSO Sequence # Registers (RO) */ | ||
528 | for (i = 0; i < 8; i++) { | ||
529 | BNAD_GET_REG(TXA1_TSO_TCP_SEQ_REG(i)); | ||
530 | BNAD_GET_REG(TXA1_TSO_IP_INFO_REG(i)); | ||
531 | } | ||
532 | |||
533 | /* RxA Registers */ | ||
534 | BNAD_GET_REG(RXA0_CTL_REG); | ||
535 | BNAD_GET_REG(RXA1_CTL_REG); | ||
536 | |||
537 | /* PLB0 Registers */ | ||
538 | BNAD_GET_REG(PLB0_ECM_TIMER_REG); | ||
539 | BNAD_GET_REG(PLB0_RL_CTL); | ||
540 | for (i = 0; i < 8; i++) | ||
541 | BNAD_GET_REG(PLB0_RL_MAX_BC(i)); | ||
542 | BNAD_GET_REG(PLB0_RL_TU_PRIO); | ||
543 | for (i = 0; i < 8; i++) | ||
544 | BNAD_GET_REG(PLB0_RL_BYTE_CNT(i)); | ||
545 | BNAD_GET_REG(PLB0_RL_MIN_REG); | ||
546 | BNAD_GET_REG(PLB0_RL_MAX_REG); | ||
547 | BNAD_GET_REG(PLB0_EMS_ADD_REG); | ||
548 | |||
549 | /* PLB1 Registers */ | ||
550 | BNAD_GET_REG(PLB1_ECM_TIMER_REG); | ||
551 | BNAD_GET_REG(PLB1_RL_CTL); | ||
552 | for (i = 0; i < 8; i++) | ||
553 | BNAD_GET_REG(PLB1_RL_MAX_BC(i)); | ||
554 | BNAD_GET_REG(PLB1_RL_TU_PRIO); | ||
555 | for (i = 0; i < 8; i++) | ||
556 | BNAD_GET_REG(PLB1_RL_BYTE_CNT(i)); | ||
557 | BNAD_GET_REG(PLB1_RL_MIN_REG); | ||
558 | BNAD_GET_REG(PLB1_RL_MAX_REG); | ||
559 | BNAD_GET_REG(PLB1_EMS_ADD_REG); | ||
560 | |||
561 | /* HQM Control Register */ | ||
562 | BNAD_GET_REG(HQM0_CTL_REG); | ||
563 | BNAD_GET_REG(HQM0_RXQ_STOP_SEM); | ||
564 | BNAD_GET_REG(HQM0_TXQ_STOP_SEM); | ||
565 | BNAD_GET_REG(HQM1_CTL_REG); | ||
566 | BNAD_GET_REG(HQM1_RXQ_STOP_SEM); | ||
567 | BNAD_GET_REG(HQM1_TXQ_STOP_SEM); | ||
568 | |||
569 | /* LUT Registers */ | ||
570 | BNAD_GET_REG(LUT0_ERR_STS); | ||
571 | BNAD_GET_REG(LUT0_SET_ERR_STS); | ||
572 | BNAD_GET_REG(LUT1_ERR_STS); | ||
573 | BNAD_GET_REG(LUT1_SET_ERR_STS); | ||
574 | |||
575 | /* TRC Registers */ | ||
576 | BNAD_GET_REG(TRC_CTL_REG); | ||
577 | BNAD_GET_REG(TRC_MODS_REG); | ||
578 | BNAD_GET_REG(TRC_TRGC_REG); | ||
579 | BNAD_GET_REG(TRC_CNT1_REG); | ||
580 | BNAD_GET_REG(TRC_CNT2_REG); | ||
581 | BNAD_GET_REG(TRC_NXTS_REG); | ||
582 | BNAD_GET_REG(TRC_DIRR_REG); | ||
583 | for (i = 0; i < 10; i++) | ||
584 | BNAD_GET_REG(TRC_TRGM_REG(i)); | ||
585 | for (i = 0; i < 10; i++) | ||
586 | BNAD_GET_REG(TRC_NXTM_REG(i)); | ||
587 | for (i = 0; i < 10; i++) | ||
588 | BNAD_GET_REG(TRC_STRM_REG(i)); | ||
589 | |||
590 | spin_unlock_irqrestore(&bnad->bna_lock, flags); | ||
591 | #undef BNAD_GET_REG | ||
592 | return num; | ||
593 | } | ||
594 | static int | ||
595 | bnad_get_regs_len(struct net_device *netdev) | ||
596 | { | ||
597 | int ret = get_regs(netdev_priv(netdev), NULL) * sizeof(u32); | ||
598 | return ret; | ||
599 | } | ||
600 | |||
601 | static void | ||
602 | bnad_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *buf) | ||
603 | { | ||
604 | memset(buf, 0, bnad_get_regs_len(netdev)); | ||
605 | get_regs(netdev_priv(netdev), buf); | ||
606 | } | ||
607 | |||
608 | static void | 291 | static void |
609 | bnad_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wolinfo) | 292 | bnad_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wolinfo) |
610 | { | 293 | { |
@@ -1192,8 +875,6 @@ static struct ethtool_ops bnad_ethtool_ops = { | |||
1192 | .get_settings = bnad_get_settings, | 875 | .get_settings = bnad_get_settings, |
1193 | .set_settings = bnad_set_settings, | 876 | .set_settings = bnad_set_settings, |
1194 | .get_drvinfo = bnad_get_drvinfo, | 877 | .get_drvinfo = bnad_get_drvinfo, |
1195 | .get_regs_len = bnad_get_regs_len, | ||
1196 | .get_regs = bnad_get_regs, | ||
1197 | .get_wol = bnad_get_wol, | 878 | .get_wol = bnad_get_wol, |
1198 | .get_link = ethtool_op_get_link, | 879 | .get_link = ethtool_op_get_link, |
1199 | .get_coalesce = bnad_get_coalesce, | 880 | .get_coalesce = bnad_get_coalesce, |