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authorImre Deak <imre.deak@intel.com>2014-03-04 12:23:01 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-03-07 16:36:53 -0500
commit7f9e192f1b504ff377f836a14176f38c5717361f (patch)
tree054536a61156d2ebe36f7d2c3cd659a163587b6e
parentb5482bd0ffefadf314098d7fae445aac9f3a0411 (diff)
drm/i915: vlv: keep first level vblank IRQs masked
This is a left-over from commit b7e634cc8dcd320123199a18bae0937b40dc28b8 Author: Imre Deak <imre.deak@intel.com> Date: Tue Feb 4 21:35:45 2014 +0200 drm/i915: vlv: don't unmask IIR[DISPLAY_PIPE_A/B_VBLANK] interrupt where we stopped unmasking the vblank IRQs, but left them enabled in the IER register. Disable them in IER too. v2: - remove comment becoming stale after this change (Ville) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c12
1 files changed, 2 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 939139bc70b1..4a19306b2d73 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3035,17 +3035,9 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
3035 3035
3036 enable_mask = I915_DISPLAY_PORT_INTERRUPT; 3036 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
3037 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3037 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3038 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 3038 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3039 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3040 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
3041 3039
3042 /* 3040 dev_priv->irq_mask = ~enable_mask;
3043 *Leave vblank interrupts masked initially. enable/disable will
3044 * toggle them based on usage.
3045 */
3046 dev_priv->irq_mask = (~enable_mask) |
3047 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
3048 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
3049 3041
3050 I915_WRITE(PORT_HOTPLUG_EN, 0); 3042 I915_WRITE(PORT_HOTPLUG_EN, 0);
3051 POSTING_READ(PORT_HOTPLUG_EN); 3043 POSTING_READ(PORT_HOTPLUG_EN);