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authorBen Skeggs <bskeggs@redhat.com>2013-12-02 22:09:34 -0500
committerBen Skeggs <bskeggs@redhat.com>2014-01-22 22:39:04 -0500
commit7f39e597726774cb3fee71f4b605a5499f7c3a8a (patch)
treef016778a69c94874590bc6a1ed70eac0d1062e05
parent12642e36e0ac29ab7a97e91648ab8ad55c52862e (diff)
drm/nve0/fb/gddr5: more 10f200 stuff
Seen on Titan. NFI what the condition to switch this on is yet, and, hardcoding it to on currently causes master to report unknown intr with a mask of 0x08002000. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
index c0bc7a916249..9a79da908d72 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c
@@ -348,7 +348,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
348 348
349 if (ram->from == 2 && ram->mode != 2) { 349 if (ram->from == 2 && ram->mode != 2) {
350 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000); 350 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
351 ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000); 351 ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
352 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004); 352 ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
353 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010); 353 ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
354 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); 354 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
@@ -377,6 +377,8 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
377 } 377 }
378 378
379 if (ram->from != 2 && ram->mode == 2) { 379 if (ram->from != 2 && ram->mode == 2) {
380 if (0 /*XXX: Titan */)
381 ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
380 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); 382 ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
381 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002); 383 ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
382 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010); 384 ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
@@ -603,7 +605,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
603 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ 605 ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
604 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); 606 ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
605 ram_nsec(fuc, 1000); 607 ram_nsec(fuc, 1000);
606 ram_nuts(ram, 0x10f200, 0x00808800, 0x00000000, 0x00808800); 608 ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
607 609
608 data = ram_rd32(fuc, 0x10f978); 610 data = ram_rd32(fuc, 0x10f978);
609 data &= ~0x00046144; 611 data &= ~0x00046144;
@@ -659,7 +661,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq)
659 else 661 else
660 data = 0x00000000; 662 data = 0x00000000;
661 ram_mask(fuc, 0x10f200, 0x00000800, data); 663 ram_mask(fuc, 0x10f200, 0x00000800, data);
662 ram_nuts(ram, 0x10f200, 0x00808800, data, 0x00808800); 664 ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
663 return 0; 665 return 0;
664} 666}
665 667