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authorTomi Valkeinen <tomi.valkeinen@ti.com>2014-10-09 10:03:17 -0400
committerPaul Walmsley <paul@pwsan.com>2014-11-19 18:41:52 -0500
commit7ede8561614afcc82f0e17bb70ae64fd620b94b0 (patch)
tree7d2279d85601b2634dfd4a4a0b3f75244ce7f214
parent543b2847d4bdb07eb1b50003095bc65cf2a1e2c0 (diff)
ARM: OMAP4: hwmod: use MODULEMODE properly
Instead of using a hacky "dss_fck" clock (which toggles the MODULEMODE bit) as DSS L3 interface clock, set the .modulemode field in the omap44xx_dss_hwmod. This works now that the DSS core hwmod is enabled during DSS submodule resets. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Archit Taneja <archit.taneja@gmail.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index df8dc0f6530f..8126f178d57e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -589,6 +589,7 @@ static struct omap_hwmod omap44xx_dss_hwmod = {
589 .omap4 = { 589 .omap4 = {
590 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, 590 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
591 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, 591 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
592 .modulemode = MODULEMODE_SWCTRL,
592 }, 593 },
593 }, 594 },
594 .opt_clks = dss_opt_clks, 595 .opt_clks = dss_opt_clks,
@@ -3677,7 +3678,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3677static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { 3678static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3678 .master = &omap44xx_l3_main_2_hwmod, 3679 .master = &omap44xx_l3_main_2_hwmod,
3679 .slave = &omap44xx_dss_hwmod, 3680 .slave = &omap44xx_dss_hwmod,
3680 .clk = "dss_fck", 3681 .clk = "l3_div_ck",
3681 .addr = omap44xx_dss_dma_addrs, 3682 .addr = omap44xx_dss_dma_addrs,
3682 .user = OCP_USER_SDMA, 3683 .user = OCP_USER_SDMA,
3683}; 3684};
@@ -3713,7 +3714,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3713static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { 3714static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3714 .master = &omap44xx_l3_main_2_hwmod, 3715 .master = &omap44xx_l3_main_2_hwmod,
3715 .slave = &omap44xx_dss_dispc_hwmod, 3716 .slave = &omap44xx_dss_dispc_hwmod,
3716 .clk = "dss_fck", 3717 .clk = "l3_div_ck",
3717 .addr = omap44xx_dss_dispc_dma_addrs, 3718 .addr = omap44xx_dss_dispc_dma_addrs,
3718 .user = OCP_USER_SDMA, 3719 .user = OCP_USER_SDMA,
3719}; 3720};
@@ -3749,7 +3750,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3749static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { 3750static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3750 .master = &omap44xx_l3_main_2_hwmod, 3751 .master = &omap44xx_l3_main_2_hwmod,
3751 .slave = &omap44xx_dss_dsi1_hwmod, 3752 .slave = &omap44xx_dss_dsi1_hwmod,
3752 .clk = "dss_fck", 3753 .clk = "l3_div_ck",
3753 .addr = omap44xx_dss_dsi1_dma_addrs, 3754 .addr = omap44xx_dss_dsi1_dma_addrs,
3754 .user = OCP_USER_SDMA, 3755 .user = OCP_USER_SDMA,
3755}; 3756};
@@ -3785,7 +3786,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3785static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { 3786static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3786 .master = &omap44xx_l3_main_2_hwmod, 3787 .master = &omap44xx_l3_main_2_hwmod,
3787 .slave = &omap44xx_dss_dsi2_hwmod, 3788 .slave = &omap44xx_dss_dsi2_hwmod,
3788 .clk = "dss_fck", 3789 .clk = "l3_div_ck",
3789 .addr = omap44xx_dss_dsi2_dma_addrs, 3790 .addr = omap44xx_dss_dsi2_dma_addrs,
3790 .user = OCP_USER_SDMA, 3791 .user = OCP_USER_SDMA,
3791}; 3792};
@@ -3821,7 +3822,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3821static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { 3822static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3822 .master = &omap44xx_l3_main_2_hwmod, 3823 .master = &omap44xx_l3_main_2_hwmod,
3823 .slave = &omap44xx_dss_hdmi_hwmod, 3824 .slave = &omap44xx_dss_hdmi_hwmod,
3824 .clk = "dss_fck", 3825 .clk = "l3_div_ck",
3825 .addr = omap44xx_dss_hdmi_dma_addrs, 3826 .addr = omap44xx_dss_hdmi_dma_addrs,
3826 .user = OCP_USER_SDMA, 3827 .user = OCP_USER_SDMA,
3827}; 3828};
@@ -3857,7 +3858,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3857static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { 3858static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3858 .master = &omap44xx_l3_main_2_hwmod, 3859 .master = &omap44xx_l3_main_2_hwmod,
3859 .slave = &omap44xx_dss_rfbi_hwmod, 3860 .slave = &omap44xx_dss_rfbi_hwmod,
3860 .clk = "dss_fck", 3861 .clk = "l3_div_ck",
3861 .addr = omap44xx_dss_rfbi_dma_addrs, 3862 .addr = omap44xx_dss_rfbi_dma_addrs,
3862 .user = OCP_USER_SDMA, 3863 .user = OCP_USER_SDMA,
3863}; 3864};
@@ -3893,7 +3894,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3893static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { 3894static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3894 .master = &omap44xx_l3_main_2_hwmod, 3895 .master = &omap44xx_l3_main_2_hwmod,
3895 .slave = &omap44xx_dss_venc_hwmod, 3896 .slave = &omap44xx_dss_venc_hwmod,
3896 .clk = "dss_fck", 3897 .clk = "l3_div_ck",
3897 .addr = omap44xx_dss_venc_dma_addrs, 3898 .addr = omap44xx_dss_venc_dma_addrs,
3898 .user = OCP_USER_SDMA, 3899 .user = OCP_USER_SDMA,
3899}; 3900};