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authorGiuseppe CAVALLARO <peppe.cavallaro@st.com>2010-01-06 18:07:19 -0500
committerDavid S. Miller <davem@davemloft.net>2010-01-07 20:06:09 -0500
commit7e848ae113ca7442ba6b44168fa2238224f37e8a (patch)
treea5d1a2f0a57a174038afa763682a9bc14e12ef43
parentaec7ff278145280c2c78377aeb98feed02c8b636 (diff)
stmmac: rename mac100 as dwmac100 and fix spare coding style
This patch renames the mac100.[ch] as dwmac100.[ch]; this looks more specific and appropriate for these chip series. The patch also fixes some spare coding style issues. Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/stmmac/Makefile2
-rw-r--r--drivers/net/stmmac/common.h2
-rw-r--r--drivers/net/stmmac/dwmac100.c (renamed from drivers/net/stmmac/mac100.c)179
-rw-r--r--drivers/net/stmmac/dwmac100.h (renamed from drivers/net/stmmac/mac100.h)0
-rw-r--r--drivers/net/stmmac/stmmac_main.c2
5 files changed, 95 insertions, 90 deletions
diff --git a/drivers/net/stmmac/Makefile b/drivers/net/stmmac/Makefile
index c8f499a71251..2ed83859fd59 100644
--- a/drivers/net/stmmac/Makefile
+++ b/drivers/net/stmmac/Makefile
@@ -1,4 +1,4 @@
1obj-$(CONFIG_STMMAC_ETH) += stmmac.o 1obj-$(CONFIG_STMMAC_ETH) += stmmac.o
2stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o 2stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o
3stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o dwmac_lib.o \ 3stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o dwmac_lib.o \
4 mac100.o gmac.o $(stmmac-y) 4 dwmac100.o gmac.o $(stmmac-y)
diff --git a/drivers/net/stmmac/common.h b/drivers/net/stmmac/common.h
index 6f8fe64dd226..987faaaa1920 100644
--- a/drivers/net/stmmac/common.h
+++ b/drivers/net/stmmac/common.h
@@ -225,7 +225,7 @@ struct mac_device_info {
225}; 225};
226 226
227struct mac_device_info *gmac_setup(unsigned long addr); 227struct mac_device_info *gmac_setup(unsigned long addr);
228struct mac_device_info *mac100_setup(unsigned long addr); 228struct mac_device_info *dwmac100_setup(unsigned long addr);
229 229
230extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], 230extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
231 unsigned int high, unsigned int low); 231 unsigned int high, unsigned int low);
diff --git a/drivers/net/stmmac/mac100.c b/drivers/net/stmmac/dwmac100.c
index b675f7c67f6e..010c8b206359 100644
--- a/drivers/net/stmmac/mac100.c
+++ b/drivers/net/stmmac/dwmac100.c
@@ -32,18 +32,18 @@
32#include <linux/phy.h> 32#include <linux/phy.h>
33 33
34#include "common.h" 34#include "common.h"
35#include "mac100.h" 35#include "dwmac100.h"
36#include "dwmac_dma.h" 36#include "dwmac_dma.h"
37 37
38#undef MAC100_DEBUG 38#undef DWMAC100_DEBUG
39/*#define MAC100_DEBUG*/ 39/*#define DWMAC100_DEBUG*/
40#ifdef MAC100_DEBUG 40#ifdef DWMAC100_DEBUG
41#define DBG(fmt, args...) printk(fmt, ## args) 41#define DBG(fmt, args...) printk(fmt, ## args)
42#else 42#else
43#define DBG(fmt, args...) do { } while (0) 43#define DBG(fmt, args...) do { } while (0)
44#endif 44#endif
45 45
46static void mac100_core_init(unsigned long ioaddr) 46static void dwmac100_core_init(unsigned long ioaddr)
47{ 47{
48 u32 value = readl(ioaddr + MAC_CONTROL); 48 u32 value = readl(ioaddr + MAC_CONTROL);
49 49
@@ -55,43 +55,43 @@ static void mac100_core_init(unsigned long ioaddr)
55 return; 55 return;
56} 56}
57 57
58static void mac100_dump_mac_regs(unsigned long ioaddr) 58static void dwmac100_dump_mac_regs(unsigned long ioaddr)
59{ 59{
60 pr_info("\t----------------------------------------------\n" 60 pr_info("\t----------------------------------------------\n"
61 "\t MAC100 CSR (base addr = 0x%8x)\n" 61 "\t DWMAC 100 CSR (base addr = 0x%8x)\n"
62 "\t----------------------------------------------\n", 62 "\t----------------------------------------------\n",
63 (unsigned int)ioaddr); 63 (unsigned int)ioaddr);
64 pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL, 64 pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
65 readl(ioaddr + MAC_CONTROL)); 65 readl(ioaddr + MAC_CONTROL));
66 pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH, 66 pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
67 readl(ioaddr + MAC_ADDR_HIGH)); 67 readl(ioaddr + MAC_ADDR_HIGH));
68 pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW, 68 pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
69 readl(ioaddr + MAC_ADDR_LOW)); 69 readl(ioaddr + MAC_ADDR_LOW));
70 pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n", 70 pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
71 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH)); 71 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
72 pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n", 72 pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
73 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW)); 73 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
74 pr_info("\tflow control (offset 0x%x): 0x%08x\n", 74 pr_info("\tflow control (offset 0x%x): 0x%08x\n",
75 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL)); 75 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
76 pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1, 76 pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
77 readl(ioaddr + MAC_VLAN1)); 77 readl(ioaddr + MAC_VLAN1));
78 pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2, 78 pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
79 readl(ioaddr + MAC_VLAN2)); 79 readl(ioaddr + MAC_VLAN2));
80 pr_info("\n\tMAC management counter registers\n"); 80 pr_info("\n\tMAC management counter registers\n");
81 pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n", 81 pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
82 MMC_CONTROL, readl(ioaddr + MMC_CONTROL)); 82 MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
83 pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n", 83 pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
84 MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR)); 84 MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
85 pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n", 85 pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
86 MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR)); 86 MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
87 pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n", 87 pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
88 MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK)); 88 MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
89 pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n", 89 pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
90 MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK)); 90 MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
91 return; 91 return;
92} 92}
93 93
94static int mac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, 94static int dwmac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
95 u32 dma_rx) 95 u32 dma_rx)
96{ 96{
97 u32 value = readl(ioaddr + DMA_BUS_MODE); 97 u32 value = readl(ioaddr + DMA_BUS_MODE);
@@ -118,7 +118,7 @@ static int mac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
118/* Store and Forward capability is not used at all.. 118/* Store and Forward capability is not used at all..
119 * The transmit threshold can be programmed by 119 * The transmit threshold can be programmed by
120 * setting the TTC bits in the DMA control register.*/ 120 * setting the TTC bits in the DMA control register.*/
121static void mac100_dma_operation_mode(unsigned long ioaddr, int txmode, 121static void dwmac100_dma_operation_mode(unsigned long ioaddr, int txmode,
122 int rxmode) 122 int rxmode)
123{ 123{
124 u32 csr6 = readl(ioaddr + DMA_CONTROL); 124 u32 csr6 = readl(ioaddr + DMA_CONTROL);
@@ -135,11 +135,11 @@ static void mac100_dma_operation_mode(unsigned long ioaddr, int txmode,
135 return; 135 return;
136} 136}
137 137
138static void mac100_dump_dma_regs(unsigned long ioaddr) 138static void dwmac100_dump_dma_regs(unsigned long ioaddr)
139{ 139{
140 int i; 140 int i;
141 141
142 DBG(KERN_DEBUG "MAC100 DMA CSR \n"); 142 DBG(KERN_DEBUG "DWMAC 100 DMA CSR \n");
143 for (i = 0; i < 9; i++) 143 for (i = 0; i < 9; i++)
144 pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i, 144 pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
145 (DMA_BUS_MODE + i * 4), 145 (DMA_BUS_MODE + i * 4),
@@ -152,8 +152,9 @@ static void mac100_dump_dma_regs(unsigned long ioaddr)
152} 152}
153 153
154/* DMA controller has two counters to track the number of 154/* DMA controller has two counters to track the number of
155 the receive missed frames. */ 155 * the receive missed frames. */
156static void mac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, 156static void dwmac100_dma_diagnostic_fr(void *data,
157 struct stmmac_extra_stats *x,
157 unsigned long ioaddr) 158 unsigned long ioaddr)
158{ 159{
159 struct net_device_stats *stats = (struct net_device_stats *)data; 160 struct net_device_stats *stats = (struct net_device_stats *)data;
@@ -182,7 +183,8 @@ static void mac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
182 return; 183 return;
183} 184}
184 185
185static int mac100_get_tx_frame_status(void *data, struct stmmac_extra_stats *x, 186static int dwmac100_get_tx_frame_status(void *data,
187 struct stmmac_extra_stats *x,
186 struct dma_desc *p, unsigned long ioaddr) 188 struct dma_desc *p, unsigned long ioaddr)
187{ 189{
188 int ret = 0; 190 int ret = 0;
@@ -218,7 +220,7 @@ static int mac100_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
218 return ret; 220 return ret;
219} 221}
220 222
221static int mac100_get_tx_len(struct dma_desc *p) 223static int dwmac100_get_tx_len(struct dma_desc *p)
222{ 224{
223 return p->des01.tx.buffer1_size; 225 return p->des01.tx.buffer1_size;
224} 226}
@@ -227,14 +229,15 @@ static int mac100_get_tx_len(struct dma_desc *p)
227 * and, if required, updates the multicast statistics. 229 * and, if required, updates the multicast statistics.
228 * In case of success, it returns csum_none becasue the device 230 * In case of success, it returns csum_none becasue the device
229 * is not able to compute the csum in HW. */ 231 * is not able to compute the csum in HW. */
230static int mac100_get_rx_frame_status(void *data, struct stmmac_extra_stats *x, 232static int dwmac100_get_rx_frame_status(void *data,
233 struct stmmac_extra_stats *x,
231 struct dma_desc *p) 234 struct dma_desc *p)
232{ 235{
233 int ret = csum_none; 236 int ret = csum_none;
234 struct net_device_stats *stats = (struct net_device_stats *)data; 237 struct net_device_stats *stats = (struct net_device_stats *)data;
235 238
236 if (unlikely(p->des01.rx.last_descriptor == 0)) { 239 if (unlikely(p->des01.rx.last_descriptor == 0)) {
237 pr_warning("mac100 Error: Oversized Ethernet " 240 pr_warning("dwmac100 Error: Oversized Ethernet "
238 "frame spanned multiple buffers\n"); 241 "frame spanned multiple buffers\n");
239 stats->rx_length_errors++; 242 stats->rx_length_errors++;
240 return discard_frame; 243 return discard_frame;
@@ -277,24 +280,24 @@ static int mac100_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
277 return ret; 280 return ret;
278} 281}
279 282
280static void mac100_irq_status(unsigned long ioaddr) 283static void dwmac100_irq_status(unsigned long ioaddr)
281{ 284{
282 return; 285 return;
283} 286}
284 287
285static void mac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr, 288static void dwmac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
286 unsigned int reg_n) 289 unsigned int reg_n)
287{ 290{
288 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); 291 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
289} 292}
290 293
291static void mac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr, 294static void dwmac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
292 unsigned int reg_n) 295 unsigned int reg_n)
293{ 296{
294 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); 297 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
295} 298}
296 299
297static void mac100_set_filter(struct net_device *dev) 300static void dwmac100_set_filter(struct net_device *dev)
298{ 301{
299 unsigned long ioaddr = dev->base_addr; 302 unsigned long ioaddr = dev->base_addr;
300 u32 value = readl(ioaddr + MAC_CONTROL); 303 u32 value = readl(ioaddr + MAC_CONTROL);
@@ -320,8 +323,8 @@ static void mac100_set_filter(struct net_device *dev)
320 /* Perfect filter mode for physical address and Hash 323 /* Perfect filter mode for physical address and Hash
321 filter for multicast */ 324 filter for multicast */
322 value |= MAC_CONTROL_HP; 325 value |= MAC_CONTROL_HP;
323 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF 326 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
324 | MAC_CONTROL_HO); 327 MAC_CONTROL_IF | MAC_CONTROL_HO);
325 328
326 memset(mc_filter, 0, sizeof(mc_filter)); 329 memset(mc_filter, 0, sizeof(mc_filter));
327 for (i = 0, mclist = dev->mc_list; 330 for (i = 0, mclist = dev->mc_list;
@@ -348,7 +351,7 @@ static void mac100_set_filter(struct net_device *dev)
348 return; 351 return;
349} 352}
350 353
351static void mac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex, 354static void dwmac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
352 unsigned int fc, unsigned int pause_time) 355 unsigned int fc, unsigned int pause_time)
353{ 356{
354 unsigned int flow = MAC_FLOW_CTRL_ENABLE; 357 unsigned int flow = MAC_FLOW_CTRL_ENABLE;
@@ -360,13 +363,15 @@ static void mac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
360 return; 363 return;
361} 364}
362 365
363/* No PMT module supported in our SoC for the Ethernet Controller. */ 366/* No PMT module supported for this Ethernet Controller.
364static void mac100_pmt(unsigned long ioaddr, unsigned long mode) 367 * Tested on ST platforms only.
368 */
369static void dwmac100_pmt(unsigned long ioaddr, unsigned long mode)
365{ 370{
366 return; 371 return;
367} 372}
368 373
369static void mac100_init_rx_desc(struct dma_desc *p, unsigned int ring_size, 374static void dwmac100_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
370 int disable_rx_ic) 375 int disable_rx_ic)
371{ 376{
372 int i; 377 int i;
@@ -382,7 +387,7 @@ static void mac100_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
382 return; 387 return;
383} 388}
384 389
385static void mac100_init_tx_desc(struct dma_desc *p, unsigned int ring_size) 390static void dwmac100_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
386{ 391{
387 int i; 392 int i;
388 for (i = 0; i < ring_size; i++) { 393 for (i = 0; i < ring_size; i++) {
@@ -394,32 +399,32 @@ static void mac100_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
394 return; 399 return;
395} 400}
396 401
397static int mac100_get_tx_owner(struct dma_desc *p) 402static int dwmac100_get_tx_owner(struct dma_desc *p)
398{ 403{
399 return p->des01.tx.own; 404 return p->des01.tx.own;
400} 405}
401 406
402static int mac100_get_rx_owner(struct dma_desc *p) 407static int dwmac100_get_rx_owner(struct dma_desc *p)
403{ 408{
404 return p->des01.rx.own; 409 return p->des01.rx.own;
405} 410}
406 411
407static void mac100_set_tx_owner(struct dma_desc *p) 412static void dwmac100_set_tx_owner(struct dma_desc *p)
408{ 413{
409 p->des01.tx.own = 1; 414 p->des01.tx.own = 1;
410} 415}
411 416
412static void mac100_set_rx_owner(struct dma_desc *p) 417static void dwmac100_set_rx_owner(struct dma_desc *p)
413{ 418{
414 p->des01.rx.own = 1; 419 p->des01.rx.own = 1;
415} 420}
416 421
417static int mac100_get_tx_ls(struct dma_desc *p) 422static int dwmac100_get_tx_ls(struct dma_desc *p)
418{ 423{
419 return p->des01.tx.last_segment; 424 return p->des01.tx.last_segment;
420} 425}
421 426
422static void mac100_release_tx_desc(struct dma_desc *p) 427static void dwmac100_release_tx_desc(struct dma_desc *p)
423{ 428{
424 int ter = p->des01.tx.end_ring; 429 int ter = p->des01.tx.end_ring;
425 430
@@ -445,45 +450,45 @@ static void mac100_release_tx_desc(struct dma_desc *p)
445 return; 450 return;
446} 451}
447 452
448static void mac100_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, 453static void dwmac100_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
449 int csum_flag) 454 int csum_flag)
450{ 455{
451 p->des01.tx.first_segment = is_fs; 456 p->des01.tx.first_segment = is_fs;
452 p->des01.tx.buffer1_size = len; 457 p->des01.tx.buffer1_size = len;
453} 458}
454 459
455static void mac100_clear_tx_ic(struct dma_desc *p) 460static void dwmac100_clear_tx_ic(struct dma_desc *p)
456{ 461{
457 p->des01.tx.interrupt = 0; 462 p->des01.tx.interrupt = 0;
458} 463}
459 464
460static void mac100_close_tx_desc(struct dma_desc *p) 465static void dwmac100_close_tx_desc(struct dma_desc *p)
461{ 466{
462 p->des01.tx.last_segment = 1; 467 p->des01.tx.last_segment = 1;
463 p->des01.tx.interrupt = 1; 468 p->des01.tx.interrupt = 1;
464} 469}
465 470
466static int mac100_get_rx_frame_len(struct dma_desc *p) 471static int dwmac100_get_rx_frame_len(struct dma_desc *p)
467{ 472{
468 return p->des01.rx.frame_length; 473 return p->des01.rx.frame_length;
469} 474}
470 475
471struct stmmac_ops mac100_ops = { 476struct stmmac_ops dwmac100_ops = {
472 .core_init = mac100_core_init, 477 .core_init = dwmac100_core_init,
473 .dump_regs = mac100_dump_mac_regs, 478 .dump_regs = dwmac100_dump_mac_regs,
474 .host_irq_status = mac100_irq_status, 479 .host_irq_status = dwmac100_irq_status,
475 .set_filter = mac100_set_filter, 480 .set_filter = dwmac100_set_filter,
476 .flow_ctrl = mac100_flow_ctrl, 481 .flow_ctrl = dwmac100_flow_ctrl,
477 .pmt = mac100_pmt, 482 .pmt = dwmac100_pmt,
478 .set_umac_addr = mac100_set_umac_addr, 483 .set_umac_addr = dwmac100_set_umac_addr,
479 .get_umac_addr = mac100_get_umac_addr, 484 .get_umac_addr = dwmac100_get_umac_addr,
480}; 485};
481 486
482struct stmmac_dma_ops mac100_dma_ops = { 487struct stmmac_dma_ops dwmac100_dma_ops = {
483 .init = mac100_dma_init, 488 .init = dwmac100_dma_init,
484 .dump_regs = mac100_dump_dma_regs, 489 .dump_regs = dwmac100_dump_dma_regs,
485 .dma_mode = mac100_dma_operation_mode, 490 .dma_mode = dwmac100_dma_operation_mode,
486 .dma_diagnostic_fr = mac100_dma_diagnostic_fr, 491 .dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
487 .enable_dma_transmission = dwmac_enable_dma_transmission, 492 .enable_dma_transmission = dwmac_enable_dma_transmission,
488 .enable_dma_irq = dwmac_enable_dma_irq, 493 .enable_dma_irq = dwmac_enable_dma_irq,
489 .disable_dma_irq = dwmac_disable_dma_irq, 494 .disable_dma_irq = dwmac_disable_dma_irq,
@@ -494,35 +499,35 @@ struct stmmac_dma_ops mac100_dma_ops = {
494 .dma_interrupt = dwmac_dma_interrupt, 499 .dma_interrupt = dwmac_dma_interrupt,
495}; 500};
496 501
497struct stmmac_desc_ops mac100_desc_ops = { 502struct stmmac_desc_ops dwmac100_desc_ops = {
498 .tx_status = mac100_get_tx_frame_status, 503 .tx_status = dwmac100_get_tx_frame_status,
499 .rx_status = mac100_get_rx_frame_status, 504 .rx_status = dwmac100_get_rx_frame_status,
500 .get_tx_len = mac100_get_tx_len, 505 .get_tx_len = dwmac100_get_tx_len,
501 .init_rx_desc = mac100_init_rx_desc, 506 .init_rx_desc = dwmac100_init_rx_desc,
502 .init_tx_desc = mac100_init_tx_desc, 507 .init_tx_desc = dwmac100_init_tx_desc,
503 .get_tx_owner = mac100_get_tx_owner, 508 .get_tx_owner = dwmac100_get_tx_owner,
504 .get_rx_owner = mac100_get_rx_owner, 509 .get_rx_owner = dwmac100_get_rx_owner,
505 .release_tx_desc = mac100_release_tx_desc, 510 .release_tx_desc = dwmac100_release_tx_desc,
506 .prepare_tx_desc = mac100_prepare_tx_desc, 511 .prepare_tx_desc = dwmac100_prepare_tx_desc,
507 .clear_tx_ic = mac100_clear_tx_ic, 512 .clear_tx_ic = dwmac100_clear_tx_ic,
508 .close_tx_desc = mac100_close_tx_desc, 513 .close_tx_desc = dwmac100_close_tx_desc,
509 .get_tx_ls = mac100_get_tx_ls, 514 .get_tx_ls = dwmac100_get_tx_ls,
510 .set_tx_owner = mac100_set_tx_owner, 515 .set_tx_owner = dwmac100_set_tx_owner,
511 .set_rx_owner = mac100_set_rx_owner, 516 .set_rx_owner = dwmac100_set_rx_owner,
512 .get_rx_frame_len = mac100_get_rx_frame_len, 517 .get_rx_frame_len = dwmac100_get_rx_frame_len,
513}; 518};
514 519
515struct mac_device_info *mac100_setup(unsigned long ioaddr) 520struct mac_device_info *dwmac100_setup(unsigned long ioaddr)
516{ 521{
517 struct mac_device_info *mac; 522 struct mac_device_info *mac;
518 523
519 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL); 524 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
520 525
521 pr_info("\tMAC 10/100\n"); 526 pr_info("\tDWMAC100\n");
522 527
523 mac->mac = &mac100_ops; 528 mac->mac = &dwmac100_ops;
524 mac->desc = &mac100_desc_ops; 529 mac->desc = &dwmac100_desc_ops;
525 mac->dma = &mac100_dma_ops; 530 mac->dma = &dwmac100_dma_ops;
526 531
527 mac->pmt = PMT_NOT_SUPPORTED; 532 mac->pmt = PMT_NOT_SUPPORTED;
528 mac->link.port = MAC_CONTROL_PS; 533 mac->link.port = MAC_CONTROL_PS;
diff --git a/drivers/net/stmmac/mac100.h b/drivers/net/stmmac/dwmac100.h
index 0f8f110d004a..0f8f110d004a 100644
--- a/drivers/net/stmmac/mac100.h
+++ b/drivers/net/stmmac/dwmac100.h
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index e6c5a3cf4af2..e79e00b6f147 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -1585,7 +1585,7 @@ static int stmmac_mac_device_setup(struct net_device *dev)
1585 if (priv->is_gmac) 1585 if (priv->is_gmac)
1586 device = gmac_setup(ioaddr); 1586 device = gmac_setup(ioaddr);
1587 else 1587 else
1588 device = mac100_setup(ioaddr); 1588 device = dwmac100_setup(ioaddr);
1589 1589
1590 if (!device) 1590 if (!device)
1591 return -ENOMEM; 1591 return -ENOMEM;