clk: mxs: add clock support for imx28

Add imx28 clock support based on common clk framework.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

2 files changed, 338 insertions, 0 deletions

diff --git a/drivers/clk/mxs/Makefile b/drivers/clk/mxs/Makefile
index 7086ad3c56d1..7bedeec08524 100644
--- a/drivers/clk/mxs/Makefile
+++ b/drivers/clk/mxs/Makefile
@@ -5,3 +5,4 @@
 obj-y += clk.o clk-pll.o clk-ref.o clk-div.o clk-frac.o
 
 obj-$(CONFIG_SOC_IMX23) += clk-imx23.o
+obj-$(CONFIG_SOC_IMX28) += clk-imx28.o
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
new file mode 100644
index 000000000000..4bfd1f4a8736
--- /dev/null
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <mach/common.h>
+#include <mach/mx28.h>
+#include "clk.h"
+
+#define CLKCTRL                 MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
+#define PLL0CTRL0               (CLKCTRL + 0x0000)
+#define PLL1CTRL0               (CLKCTRL + 0x0020)
+#define PLL2CTRL0               (CLKCTRL + 0x0040)
+#define CPU                     (CLKCTRL + 0x0050)
+#define HBUS                    (CLKCTRL + 0x0060)
+#define XBUS                    (CLKCTRL + 0x0070)
+#define XTAL                    (CLKCTRL + 0x0080)
+#define SSP0                    (CLKCTRL + 0x0090)
+#define SSP1                    (CLKCTRL + 0x00a0)
+#define SSP2                    (CLKCTRL + 0x00b0)
+#define SSP3                    (CLKCTRL + 0x00c0)
+#define GPMI                    (CLKCTRL + 0x00d0)
+#define SPDIF                   (CLKCTRL + 0x00e0)
+#define EMI                     (CLKCTRL + 0x00f0)
+#define SAIF0                   (CLKCTRL + 0x0100)
+#define SAIF1                   (CLKCTRL + 0x0110)
+#define LCDIF                   (CLKCTRL + 0x0120)
+#define ETM                     (CLKCTRL + 0x0130)
+#define ENET                    (CLKCTRL + 0x0140)
+#define FLEXCAN                 (CLKCTRL + 0x0160)
+#define FRAC0                   (CLKCTRL + 0x01b0)
+#define FRAC1                   (CLKCTRL + 0x01c0)
+#define CLKSEQ                  (CLKCTRL + 0x01d0)
+
+#define BP_CPU_INTERRUPT_WAIT   12
+#define BP_SAIF_DIV_FRAC_EN     16
+#define BP_ENET_DIV_TIME        21
+#define BP_ENET_SLEEP           31
+#define BP_CLKSEQ_BYPASS_SAIF0  0
+#define BP_CLKSEQ_BYPASS_SSP0   3
+#define BP_FRAC0_IO1FRAC        16
+#define BP_FRAC0_IO0FRAC        24
+
+#define DIGCTRL                 MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
+#define BP_SAIF_CLKMUX          10
+
+/*
+ * HW_SAIF_CLKMUX_SEL:
+ *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
+ *              clock pins selected for SAIF1 input clocks.
+ *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
+ *              SAIF0 clock inputs selected for SAIF1 input clocks.
+ *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
+ *              clocks.
+ *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
+ *              clocks.
+ */
+int mxs_saif_clkmux_select(unsigned int clkmux)
+{
+        if (clkmux > 0x3)
+                return -EINVAL;
+
+        __mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL);
+        __mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL);
+
+        return 0;
+}
+
+static void __init clk_misc_init(void)
+{
+        u32 val;
+
+        /* Gate off cpu clock in WFI for power saving */
+        __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
+
+        /* 0 is a bad default value for a divider */
+        __mxs_setl(1 << BP_ENET_DIV_TIME, ENET);
+
+        /* Clear BYPASS for SAIF */
+        __mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ);
+
+        /* SAIF has to use frac div for functional operation */
+        val = readl_relaxed(SAIF0);
+        val |= 1 << BP_SAIF_DIV_FRAC_EN;
+        writel_relaxed(val, SAIF0);
+
+        val = readl_relaxed(SAIF1);
+        val |= 1 << BP_SAIF_DIV_FRAC_EN;
+        writel_relaxed(val, SAIF1);
+
+        /* Extra fec clock setting */
+        val = readl_relaxed(ENET);
+        val &= ~(1 << BP_ENET_SLEEP);
+        writel_relaxed(val, ENET);
+
+        /*
+         * Source ssp clock from ref_io than ref_xtal,
+         * as ref_xtal only provides 24 MHz as maximum.
+         */
+        __mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ);
+
+        /*
+         * 480 MHz seems too high to be ssp clock source directly,
+         * so set frac0 to get a 288 MHz ref_io0.
+         */
+        val = readl_relaxed(FRAC0);
+        val &= ~(0x3f << BP_FRAC0_IO0FRAC);
+        val |= 30 << BP_FRAC0_IO0FRAC;
+        writel_relaxed(val, FRAC0);
+}
+
+static struct clk_lookup uart_lookups[] __initdata = {
+        { .dev_id = "duart", },
+        { .dev_id = "mxs-auart.0", },
+        { .dev_id = "mxs-auart.1", },
+        { .dev_id = "mxs-auart.2", },
+        { .dev_id = "mxs-auart.3", },
+        { .dev_id = "mxs-auart.4", },
+        { .dev_id = "8006a000.serial", },
+        { .dev_id = "8006c000.serial", },
+        { .dev_id = "8006e000.serial", },
+        { .dev_id = "80070000.serial", },
+        { .dev_id = "80072000.serial", },
+        { .dev_id = "80074000.serial", },
+};
+
+static struct clk_lookup hbus_lookups[] __initdata = {
+        { .dev_id = "mxs-dma-apbh", },
+        { .dev_id = "80004000.dma-apbh", },
+};
+
+static struct clk_lookup xbus_lookups[] __initdata = {
+        { .dev_id = "duart", .con_id = "apb_pclk"},
+        { .dev_id = "mxs-dma-apbx", },
+        { .dev_id = "80024000.dma-apbx", },
+};
+
+static struct clk_lookup ssp0_lookups[] __initdata = {
+        { .dev_id = "mxs-mmc.0", },
+        { .dev_id = "80010000.ssp", },
+};
+
+static struct clk_lookup ssp1_lookups[] __initdata = {
+        { .dev_id = "mxs-mmc.1", },
+        { .dev_id = "80012000.ssp", },
+};
+
+static struct clk_lookup ssp2_lookups[] __initdata = {
+        { .dev_id = "mxs-mmc.2", },
+        { .dev_id = "80014000.ssp", },
+};
+
+static struct clk_lookup ssp3_lookups[] __initdata = {
+        { .dev_id = "mxs-mmc.3", },
+        { .dev_id = "80016000.ssp", },
+};
+
+static struct clk_lookup lcdif_lookups[] __initdata = {
+        { .dev_id = "imx28-fb", },
+        { .dev_id = "80030000.lcdif", },
+};
+
+static struct clk_lookup gpmi_lookups[] __initdata = {
+        { .dev_id = "imx28-gpmi-nand", },
+        { .dev_id = "8000c000.gpmi", },
+};
+
+static struct clk_lookup fec_lookups[] __initdata = {
+        { .dev_id = "imx28-fec.0", },
+        { .dev_id = "imx28-fec.1", },
+        { .dev_id = "800f0000.ethernet", },
+        { .dev_id = "800f4000.ethernet", },
+};
+
+static struct clk_lookup can0_lookups[] __initdata = {
+        { .dev_id = "flexcan.0", },
+        { .dev_id = "80032000.can", },
+};