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authorRob Herring <rob.herring@calxeda.com>2012-10-25 12:59:09 -0400
committerRob Herring <rob.herring@calxeda.com>2012-10-31 14:46:17 -0400
commit7d6ab9b8620bbca6718b36242113f4f069840641 (patch)
tree9d26ff4c09ae674d0079ea652907fd51845f86e7
parent185bdffb4b2997a2d4ee2e88d52a6539bde59eea (diff)
ARM: dts: Add Calxeda ECX-2000 support
Separate out common dts pieces from highbank dts and add support for Calxeda ECX-2000 (Midway) SOC. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/calxeda.txt13
-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/ecx-2000.dts104
-rw-r--r--arch/arm/boot/dts/ecx-common.dtsi237
-rw-r--r--arch/arm/boot/dts/highbank.dts219
5 files changed, 356 insertions, 220 deletions
diff --git a/Documentation/devicetree/bindings/arm/calxeda.txt b/Documentation/devicetree/bindings/arm/calxeda.txt
index 4755caaccba6..25fcf96795ca 100644
--- a/Documentation/devicetree/bindings/arm/calxeda.txt
+++ b/Documentation/devicetree/bindings/arm/calxeda.txt
@@ -1,8 +1,15 @@
1Calxeda Highbank Platforms Device Tree Bindings 1Calxeda Platforms Device Tree Bindings
2----------------------------------------------- 2-----------------------------------------------
3 3
4Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following 4Boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC shall have the
5properties. 5following properties.
6 6
7Required root node properties: 7Required root node properties:
8 - compatible = "calxeda,highbank"; 8 - compatible = "calxeda,highbank";
9
10
11Boards with Calxeda Cortex-A15 based ECX-2000 SOC shall have the following
12properties.
13
14Required root node properties:
15 - compatible = "calxeda,ecx-2000";
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f37cf9fa5fa0..5cc95667fa3b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -24,7 +24,8 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
24 exynos4210-smdkv310.dtb \ 24 exynos4210-smdkv310.dtb \
25 exynos4210-trats.dtb \ 25 exynos4210-trats.dtb \
26 exynos5250-smdk5250.dtb 26 exynos5250-smdk5250.dtb
27dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb 27dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
28 ecx-2000.dtb
28dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ 29dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
29 integratorcp.dtb 30 integratorcp.dtb
30dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb 31dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
new file mode 100644
index 000000000000..46477ac1de99
--- /dev/null
+++ b/arch/arm/boot/dts/ecx-2000.dts
@@ -0,0 +1,104 @@
1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18
19/* First 4KB has pen for secondary cores. */
20/memreserve/ 0x00000000 0x0001000;
21
22/ {
23 model = "Calxeda ECX-2000";
24 compatible = "calxeda,ecx-2000";
25 #address-cells = <2>;
26 #size-cells = <2>;
27 clock-ranges;
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 compatible = "arm,cortex-a15";
35 reg = <0>;
36 clocks = <&a9pll>;
37 clock-names = "cpu";
38 };
39
40 cpu@1 {
41 compatible = "arm,cortex-a15";
42 reg = <1>;
43 clocks = <&a9pll>;
44 clock-names = "cpu";
45 };
46
47 cpu@2 {
48 compatible = "arm,cortex-a15";
49 reg = <2>;
50 clocks = <&a9pll>;
51 clock-names = "cpu";
52 };
53
54 cpu@3 {
55 compatible = "arm,cortex-a15";
56 reg = <3>;
57 clocks = <&a9pll>;
58 clock-names = "cpu";
59 };
60 };
61
62 memory@0 {
63 name = "memory";
64 device_type = "memory";
65 reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
66 };
67
68 memory@200000000 {
69 name = "memory";
70 device_type = "memory";
71 reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
72 };
73
74 soc {
75 ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;
76
77 timer {
78 compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; interrupts = <1 13 0xf08>,
79 <1 14 0xf08>,
80 <1 11 0xf08>,
81 <1 10 0xf08>;
82 };
83
84 intc: interrupt-controller@fff11000 {
85 compatible = "arm,cortex-a15-gic";
86 #interrupt-cells = <3>;
87 #size-cells = <0>;
88 #address-cells = <1>;
89 interrupt-controller;
90 interrupts = <1 9 0xf04>;
91 reg = <0xfff11000 0x1000>,
92 <0xfff12000 0x1000>,
93 <0xfff14000 0x2000>,
94 <0xfff16000 0x2000>;
95 };
96
97 pmu {
98 compatible = "arm,cortex-a9-pmu";
99 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
100 };
101 };
102};
103
104/include/ "ecx-common.dtsi"
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
new file mode 100644
index 000000000000..d61b535f682a
--- /dev/null
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -0,0 +1,237 @@
1/*
2 * Copyright 2011-2012 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/ {
18 chosen {
19 bootargs = "console=ttyAMA0";
20 };
21
22 soc {
23 #address-cells = <1>;
24 #size-cells = <1>;
25 compatible = "simple-bus";
26 interrupt-parent = <&intc>;
27
28 sata@ffe08000 {
29 compatible = "calxeda,hb-ahci";
30 reg = <0xffe08000 0x10000>;
31 interrupts = <0 83 4>;
32 dma-coherent;
33 calxeda,port-phys = <&combophy5 0 &combophy0 0
34 &combophy0 1 &combophy0 2
35 &combophy0 3>;
36 };
37
38 sdhci@ffe0e000 {
39 compatible = "calxeda,hb-sdhci";
40 reg = <0xffe0e000 0x1000>;
41 interrupts = <0 90 4>;
42 clocks = <&eclk>;
43 status = "disabled";
44 };
45
46 memory-controller@fff00000 {
47 compatible = "calxeda,hb-ddr-ctrl";
48 reg = <0xfff00000 0x1000>;
49 interrupts = <0 91 4>;
50 };
51
52 ipc@fff20000 {
53 compatible = "arm,pl320", "arm,primecell";
54 reg = <0xfff20000 0x1000>;
55 interrupts = <0 7 4>;
56 clocks = <&pclk>;
57 clock-names = "apb_pclk";
58 };
59
60 gpioe: gpio@fff30000 {
61 #gpio-cells = <2>;
62 compatible = "arm,pl061", "arm,primecell";
63 gpio-controller;
64 reg = <0xfff30000 0x1000>;
65 interrupts = <0 14 4>;
66 clocks = <&pclk>;
67 clock-names = "apb_pclk";
68 status = "disabled";
69 };
70
71 gpiof: gpio@fff31000 {
72 #gpio-cells = <2>;
73 compatible = "arm,pl061", "arm,primecell";
74 gpio-controller;
75 reg = <0xfff31000 0x1000>;
76 interrupts = <0 15 4>;
77 clocks = <&pclk>;
78 clock-names = "apb_pclk";
79 status = "disabled";
80 };
81
82 gpiog: gpio@fff32000 {
83 #gpio-cells = <2>;
84 compatible = "arm,pl061", "arm,primecell";
85 gpio-controller;
86 reg = <0xfff32000 0x1000>;
87 interrupts = <0 16 4>;
88 clocks = <&pclk>;
89 clock-names = "apb_pclk";
90 status = "disabled";
91 };
92
93 gpioh: gpio@fff33000 {
94 #gpio-cells = <2>;
95 compatible = "arm,pl061", "arm,primecell";
96 gpio-controller;
97 reg = <0xfff33000 0x1000>;
98 interrupts = <0 17 4>;
99 clocks = <&pclk>;
100 clock-names = "apb_pclk";
101 status = "disabled";
102 };
103
104 timer@fff34000 {
105 compatible = "arm,sp804", "arm,primecell";
106 reg = <0xfff34000 0x1000>;
107 interrupts = <0 18 4>;
108 clocks = <&pclk>;
109 clock-names = "apb_pclk";
110 };
111
112 rtc@fff35000 {
113 compatible = "arm,pl031", "arm,primecell";
114 reg = <0xfff35000 0x1000>;
115 interrupts = <0 19 4>;
116 clocks = <&pclk>;
117 clock-names = "apb_pclk";
118 };
119
120 serial@fff36000 {
121 compatible = "arm,pl011", "arm,primecell";
122 reg = <0xfff36000 0x1000>;
123 interrupts = <0 20 4>;
124 clocks = <&pclk>;
125 clock-names = "apb_pclk";
126 };
127
128 smic@fff3a000 {
129 compatible = "ipmi-smic";
130 device_type = "ipmi";
131 reg = <0xfff3a000 0x1000>;
132 interrupts = <0 24 4>;
133 reg-size = <4>;
134 reg-spacing = <4>;
135 };
136
137 sregs@fff3c000 {
138 compatible = "calxeda,hb-sregs";
139 reg = <0xfff3c000 0x1000>;
140
141 clocks {
142 #address-cells = <1>;
143 #size-cells = <0>;
144
145 osc: oscillator {
146 #clock-cells = <0>;
147 compatible = "fixed-clock";
148 clock-frequency = <33333000>;
149 };
150
151 ddrpll: ddrpll {
152 #clock-cells = <0>;
153 compatible = "calxeda,hb-pll-clock";
154 clocks = <&osc>;
155 reg = <0x108>;
156 };
157
158 a9pll: a9pll {
159 #clock-cells = <0>;
160 compatible = "calxeda,hb-pll-clock";
161 clocks = <&osc>;
162 reg = <0x100>;
163 };
164
165 a9periphclk: a9periphclk {
166 #clock-cells = <0>;
167 compatible = "calxeda,hb-a9periph-clock";
168 clocks = <&a9pll>;
169 reg = <0x104>;
170 };
171
172 a9bclk: a9bclk {
173 #clock-cells = <0>;
174 compatible = "calxeda,hb-a9bus-clock";
175 clocks = <&a9pll>;
176 reg = <0x104>;
177 };
178
179 emmcpll: emmcpll {
180 #clock-cells = <0>;
181 compatible = "calxeda,hb-pll-clock";
182 clocks = <&osc>;
183 reg = <0x10C>;
184 };
185
186 eclk: eclk {
187 #clock-cells = <0>;
188 compatible = "calxeda,hb-emmc-clock";
189 clocks = <&emmcpll>;
190 reg = <0x114>;
191 };
192
193 pclk: pclk {
194 #clock-cells = <0>;
195 compatible = "fixed-clock";
196 clock-frequency = <150000000>;
197 };
198 };
199 };
200
201 dma@fff3d000 {
202 compatible = "arm,pl330", "arm,primecell";
203 reg = <0xfff3d000 0x1000>;
204 interrupts = <0 92 4>;
205 clocks = <&pclk>;
206 clock-names = "apb_pclk";
207 };
208
209 ethernet@fff50000 {
210 compatible = "calxeda,hb-xgmac";
211 reg = <0xfff50000 0x1000>;
212 interrupts = <0 77 4 0 78 4 0 79 4>;
213 dma-coherent;
214 };
215
216 ethernet@fff51000 {
217 compatible = "calxeda,hb-xgmac";
218 reg = <0xfff51000 0x1000>;
219 interrupts = <0 80 4 0 81 4 0 82 4>;
220 dma-coherent;
221 };
222
223 combophy0: combo-phy@fff58000 {
224 compatible = "calxeda,hb-combophy";
225 #phy-cells = <1>;
226 reg = <0xfff58000 0x1000>;
227 phydev = <5>;
228 };
229
230 combophy5: combo-phy@fff5d000 {
231 compatible = "calxeda,hb-combophy";
232 #phy-cells = <1>;
233 reg = <0xfff5d000 0x1000>;
234 phydev = <31>;
235 };
236 };
237};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index e39a79a61e0c..a9ae5d32e80d 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -69,16 +69,8 @@
69 reg = <0x00000000 0xff900000>; 69 reg = <0x00000000 0xff900000>;
70 }; 70 };
71 71
72 chosen {
73 bootargs = "console=ttyAMA0";
74 };
75
76 soc { 72 soc {
77 #address-cells = <1>; 73 ranges = <0x00000000 0x00000000 0xffffffff>;
78 #size-cells = <1>;
79 compatible = "simple-bus";
80 interrupt-parent = <&intc>;
81 ranges;
82 74
83 timer@fff10600 { 75 timer@fff10600 {
84 compatible = "arm,cortex-a9-twd-timer"; 76 compatible = "arm,cortex-a9-twd-timer";
@@ -117,178 +109,6 @@
117 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>; 109 interrupts = <0 76 4 0 75 4 0 74 4 0 73 4>;
118 }; 110 };
119 111
120 sata@ffe08000 {
121 compatible = "calxeda,hb-ahci";
122 reg = <0xffe08000 0x10000>;
123 interrupts = <0 83 4>;
124 calxeda,port-phys = <&combophy5 0 &combophy0 0
125 &combophy0 1 &combophy0 2
126 &combophy0 3>;
127 dma-coherent;
128 };
129
130 sdhci@ffe0e000 {
131 compatible = "calxeda,hb-sdhci";
132 reg = <0xffe0e000 0x1000>;
133 interrupts = <0 90 4>;
134 clocks = <&eclk>;
135 status = "disabled";
136 };
137
138 memory-controller@fff00000 {
139 compatible = "calxeda,hb-ddr-ctrl";
140 reg = <0xfff00000 0x1000>;
141 interrupts = <0 91 4>;
142 };
143
144 ipc@fff20000 {
145 compatible = "arm,pl320", "arm,primecell";
146 reg = <0xfff20000 0x1000>;
147 interrupts = <0 7 4>;
148 clocks = <&pclk>;
149 clock-names = "apb_pclk";
150 };
151
152 gpioe: gpio@fff30000 {
153 #gpio-cells = <2>;
154 compatible = "arm,pl061", "arm,primecell";
155 gpio-controller;
156 reg = <0xfff30000 0x1000>;
157 interrupts = <0 14 4>;
158 clocks = <&pclk>;
159 clock-names = "apb_pclk";
160 status = "disabled";
161 };
162
163 gpiof: gpio@fff31000 {
164 #gpio-cells = <2>;
165 compatible = "arm,pl061", "arm,primecell";
166 gpio-controller;
167 reg = <0xfff31000 0x1000>;
168 interrupts = <0 15 4>;
169 clocks = <&pclk>;
170 clock-names = "apb_pclk";
171 status = "disabled";
172 };
173
174 gpiog: gpio@fff32000 {
175 #gpio-cells = <2>;
176 compatible = "arm,pl061", "arm,primecell";
177 gpio-controller;
178 reg = <0xfff32000 0x1000>;
179 interrupts = <0 16 4>;
180 clocks = <&pclk>;
181 clock-names = "apb_pclk";
182 status = "disabled";
183 };
184
185 gpioh: gpio@fff33000 {
186 #gpio-cells = <2>;
187 compatible = "arm,pl061", "arm,primecell";
188 gpio-controller;
189 reg = <0xfff33000 0x1000>;
190 interrupts = <0 17 4>;
191 clocks = <&pclk>;
192 clock-names = "apb_pclk";
193 status = "disabled";
194 };
195
196 timer {
197 compatible = "arm,sp804", "arm,primecell";
198 reg = <0xfff34000 0x1000>;
199 interrupts = <0 18 4>;
200 clocks = <&pclk>;
201 clock-names = "apb_pclk";
202 };
203
204 rtc@fff35000 {
205 compatible = "arm,pl031", "arm,primecell";
206 reg = <0xfff35000 0x1000>;
207 interrupts = <0 19 4>;
208 clocks = <&pclk>;
209 clock-names = "apb_pclk";
210 };
211
212 serial@fff36000 {
213 compatible = "arm,pl011", "arm,primecell";
214 reg = <0xfff36000 0x1000>;
215 interrupts = <0 20 4>;
216 clocks = <&pclk>;
217 clock-names = "apb_pclk";
218 };
219
220 smic@fff3a000 {
221 compatible = "ipmi-smic";
222 device_type = "ipmi";
223 reg = <0xfff3a000 0x1000>;
224 interrupts = <0 24 4>;
225 reg-size = <4>;
226 reg-spacing = <4>;
227 };
228
229 sregs@fff3c000 {
230 compatible = "calxeda,hb-sregs";
231 reg = <0xfff3c000 0x1000>;
232
233 clocks {
234 #address-cells = <1>;
235 #size-cells = <0>;
236
237 osc: oscillator {
238 #clock-cells = <0>;
239 compatible = "fixed-clock";
240 clock-frequency = <33333000>;
241 };
242
243 ddrpll: ddrpll {
244 #clock-cells = <0>;
245 compatible = "calxeda,hb-pll-clock";
246 clocks = <&osc>;
247 reg = <0x108>;
248 };
249
250 a9pll: a9pll {
251 #clock-cells = <0>;
252 compatible = "calxeda,hb-pll-clock";
253 clocks = <&osc>;
254 reg = <0x100>;
255 };
256
257 a9periphclk: a9periphclk {
258 #clock-cells = <0>;
259 compatible = "calxeda,hb-a9periph-clock";
260 clocks = <&a9pll>;
261 reg = <0x104>;
262 };
263
264 a9bclk: a9bclk {
265 #clock-cells = <0>;
266 compatible = "calxeda,hb-a9bus-clock";
267 clocks = <&a9pll>;
268 reg = <0x104>;
269 };
270
271 emmcpll: emmcpll {
272 #clock-cells = <0>;
273 compatible = "calxeda,hb-pll-clock";
274 clocks = <&osc>;
275 reg = <0x10C>;
276 };
277
278 eclk: eclk {
279 #clock-cells = <0>;
280 compatible = "calxeda,hb-emmc-clock";
281 clocks = <&emmcpll>;
282 reg = <0x114>;
283 };
284
285 pclk: pclk {
286 #clock-cells = <0>;
287 compatible = "fixed-clock";
288 clock-frequency = <150000000>;
289 };
290 };
291 };
292 112
293 sregs@fff3c200 { 113 sregs@fff3c200 {
294 compatible = "calxeda,hb-sregs-l2-ecc"; 114 compatible = "calxeda,hb-sregs-l2-ecc";
@@ -296,40 +116,7 @@
296 interrupts = <0 71 4 0 72 4>; 116 interrupts = <0 71 4 0 72 4>;
297 }; 117 };
298 118
299 dma@fff3d000 {
300 compatible = "arm,pl330", "arm,primecell";
301 reg = <0xfff3d000 0x1000>;
302 interrupts = <0 92 4>;
303 clocks = <&pclk>;
304 clock-names = "apb_pclk";
305 };
306
307 ethernet@fff50000 {
308 compatible = "calxeda,hb-xgmac";
309 reg = <0xfff50000 0x1000>;
310 interrupts = <0 77 4 0 78 4 0 79 4>;
311 dma-coherent;
312 };
313
314 ethernet@fff51000 {
315 compatible = "calxeda,hb-xgmac";
316 reg = <0xfff51000 0x1000>;
317 interrupts = <0 80 4 0 81 4 0 82 4>;
318 dma-coherent;
319 };
320
321 combophy0: combo-phy@fff58000 {
322 compatible = "calxeda,hb-combophy";
323 #phy-cells = <1>;
324 reg = <0xfff58000 0x1000>;
325 phydev = <5>;
326 };
327
328 combophy5: combo-phy@fff5d000 {
329 compatible = "calxeda,hb-combophy";
330 #phy-cells = <1>;
331 reg = <0xfff5d000 0x1000>;
332 phydev = <31>;
333 };
334 }; 119 };
335}; 120};
121
122/include/ "ecx-common.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 07:14:13 -0500