Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Pull m68knommu arch updates from Greg Ungerer:
 "Most of it is a cleanup of the ColdFire hardware header files.  We
  have had a few occurrances of bugs caused by inconsistent definitions
  of peripheral addresses.  These patches make them all consistent, and
  also clean out a bunch of old crap.  Overall we remove about 1000
  lines."

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (27 commits)
  m68knommu: fix inconsistent formating in ColdFire 5407 definitions
  m68knommu: fix inconsistent formating in ColdFire 5307 definitions
  m68knommu: fix inconsistent formating in ColdFire 527x definitions
  m68knommu: fix inconsistent formating in ColdFire 5272 definitions
  m68knommu: fix inconsistent formating in ColdFire 523x definitions
  m68knommu: clean up ColdFire 54xx General Timer definitions
  m68knommu: clean up Pin Assignment definitions for the 54xx ColdFire CPU
  m68knommu: fix multi-function pin setup for FEC module on ColdFire 523x
  m68knommu: move ColdFire slice timer address defiens to 54xx header
  m68knommu: use read/write IO access functions in ColdFire m532x setup code
  m68knommu: modify ColdFire 532x GPIO register definitions to be consistent
  m68knommu: remove a lot of unsed definitions for 532x ColdFire
  m68knommu: use definitions for the ColdFire 528x FEC multi-function pins
  m68knommu: remove address offsets relative to IPSBAR for ColdFire 527x
  m68knommu: remove unused ColdFire 5282 register definitions
  m68knommu: fix wrong register offsets used for ColdFire 5272 multi-function pins
  m68knommu: make ColdFire 5249 MBAR2 register definitions absolute addresses
  m68knommu: make remaining ColdFire 5272 register definitions absolute addresses
  m68knommu: make ColdFire Park and Assignment register definitions absolute addresses
  m68knommu: make ColdFire Chip Select register definitions absolute addresses
  ...

35 files changed, 702 insertions, 1778 deletions

diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 7cafb537d03c..d2b3935ae147 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -34,10 +34,9 @@ static inline void __clear_cache_all(void)
 {
 #ifdef CACHE_INVALIDATE
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATE) : "d0" );
+                : : "r" (CACHE_INVALIDATE) );
 #endif
 }
 
@@ -58,10 +57,9 @@ static inline void __flush_icache_all(void)
 {
 #ifdef CACHE_INVALIDATEI
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATEI) : "d0" );
+                : : "r" (CACHE_INVALIDATEI) );
 #endif
 }
 
@@ -72,19 +70,18 @@ static inline void __flush_dcache_all(void)
 #endif
 #ifdef CACHE_INVALIDATED
         __asm__ __volatile__ (
-                "movel  %0, %%d0\n\t"
-                "movec  %%d0, %%CACR\n\t"
+                "movec  %0, %%CACR\n\t"
                 "nop\n\t"
-                : : "i" (CACHE_INVALIDATED) : "d0" );
+                : : "r" (CACHE_INVALIDATED) );
 #else
-        /* Flush the wrtite buffer */
+        /* Flush the write buffer */
         __asm__ __volatile__ ( "nop" );
 #endif
 }
 
 /*
  * Push cache entries at supplied address. We want to write back any dirty
- * data and the invalidate the cache lines associated with this address.
+ * data and then invalidate the cache lines associated with this address.
  */
 static inline void cache_push(unsigned long paddr, int len)
 {
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 69722366b084..4cf864f5ea7a 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -21,33 +21,33 @@
 /*
  *      Define the 5206 SIM register set addresses.
  */
-#define MCFSIM_SIMR             0x03            /* SIM Config reg (r/w) */
-#define MCFSIM_ICR1             0x14            /* Intr Ctrl reg 1 (r/w) */
-#define MCFSIM_ICR2             0x15            /* Intr Ctrl reg 2 (r/w) */
-#define MCFSIM_ICR3             0x16            /* Intr Ctrl reg 3 (r/w) */
-#define MCFSIM_ICR4             0x17            /* Intr Ctrl reg 4 (r/w) */
-#define MCFSIM_ICR5             0x18            /* Intr Ctrl reg 5 (r/w) */
-#define MCFSIM_ICR6             0x19            /* Intr Ctrl reg 6 (r/w) */
-#define MCFSIM_ICR7             0x1a            /* Intr Ctrl reg 7 (r/w) */
-#define MCFSIM_ICR8             0x1b            /* Intr Ctrl reg 8 (r/w) */
-#define MCFSIM_ICR9             0x1c            /* Intr Ctrl reg 9 (r/w) */
-#define MCFSIM_ICR10            0x1d            /* Intr Ctrl reg 10 (r/w) */
-#define MCFSIM_ICR11            0x1e            /* Intr Ctrl reg 11 (r/w) */
-#define MCFSIM_ICR12            0x1f            /* Intr Ctrl reg 12 (r/w) */
-#define MCFSIM_ICR13            0x20            /* Intr Ctrl reg 13 (r/w) */
+#define MCFSIM_SIMR             (MCF_MBAR + 0x03)       /* SIM Config reg */
+#define MCFSIM_ICR1             (MCF_MBAR + 0x14)       /* Intr Ctrl reg 1 */
+#define MCFSIM_ICR2             (MCF_MBAR + 0x15)       /* Intr Ctrl reg 2 */
+#define MCFSIM_ICR3             (MCF_MBAR + 0x16)       /* Intr Ctrl reg 3 */
+#define MCFSIM_ICR4             (MCF_MBAR + 0x17)       /* Intr Ctrl reg 4 */
+#define MCFSIM_ICR5             (MCF_MBAR + 0x18)       /* Intr Ctrl reg 5 */
+#define MCFSIM_ICR6             (MCF_MBAR + 0x19)       /* Intr Ctrl reg 6 */
+#define MCFSIM_ICR7             (MCF_MBAR + 0x1a)       /* Intr Ctrl reg 7 */
+#define MCFSIM_ICR8             (MCF_MBAR + 0x1b)       /* Intr Ctrl reg 8 */
+#define MCFSIM_ICR9             (MCF_MBAR + 0x1c)       /* Intr Ctrl reg 9 */
+#define MCFSIM_ICR10            (MCF_MBAR + 0x1d)       /* Intr Ctrl reg 10 */
+#define MCFSIM_ICR11            (MCF_MBAR + 0x1e)       /* Intr Ctrl reg 11 */
+#define MCFSIM_ICR12            (MCF_MBAR + 0x1f)       /* Intr Ctrl reg 12 */
+#define MCFSIM_ICR13            (MCF_MBAR + 0x20)       /* Intr Ctrl reg 13 */
 #ifdef CONFIG_M5206e
-#define MCFSIM_ICR14            0x21            /* Intr Ctrl reg 14 (r/w) */
-#define MCFSIM_ICR15            0x22            /* Intr Ctrl reg 15 (r/w) */
+#define MCFSIM_ICR14            (MCF_MBAR + 0x21)       /* Intr Ctrl reg 14 */
+#define MCFSIM_ICR15            (MCF_MBAR + 0x22)       /* Intr Ctrl reg 15 */
 #endif
 
-#define MCFSIM_IMR              0x36            /* Interrupt Mask reg (r/w) */
-#define MCFSIM_IPR              0x3a            /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR              (MCF_MBAR + 0x36)       /* Interrupt Mask */
+#define MCFSIM_IPR              (MCF_MBAR + 0x3a)       /* Interrupt Pending */
 
-#define MCFSIM_RSR              0x40            /* Reset Status reg (r/w) */
-#define MCFSIM_SYPCR            0x41            /* System Protection reg (r/w)*/
+#define MCFSIM_RSR              (MCF_MBAR + 0x40)       /* Reset Status */
+#define MCFSIM_SYPCR            (MCF_MBAR + 0x41)       /* System Protection */
 
-#define MCFSIM_SWIVR            0x42            /* SW Watchdog intr reg (r/w) */
-#define MCFSIM_SWSR             0x43            /* SW Watchdog service (r/w) */
+#define MCFSIM_SWIVR            (MCF_MBAR + 0x42)       /* SW Watchdog intr */
+#define MCFSIM_SWSR             (MCF_MBAR + 0x43)       /* SW Watchdog srv */
 
 #define MCFSIM_DCRR             (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */