MIPS: cacheops.h: Increase indentation by one tab.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
author: Ralf Baechle <ralf@linux-mips.org> 2013-09-27 13:07:18 -0400
committer: Ralf Baechle <ralf@linux-mips.org> 2013-10-29 16:25:22 -0400
commit: 7b784c634b4147345b46251884be6be4bd45fd43 (patch)
tree: a07d095d366d8a5a37e23d639fc3bd8723d76f04
parent: c1724c89973e28a12a605f66e5151bdb8c354b76 (diff)
1 files changed, 43 insertions, 43 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 68f37e3eccc7..0644c985d153 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -14,56 +14,56 @@
 /*
 * Cache Operations available on all MIPS processors with R4000-style caches
 */
-#define Index_Invalidate_I      0x00
+#define Index_Invalidate_I              0x00
-#define Index_Writeback_Inv_D   0x01
+#define Index_Writeback_Inv_D           0x01
-#define Index_Load_Tag_I        0x04
+#define Index_Load_Tag_I                0x04
-#define Index_Load_Tag_D        0x05
+#define Index_Load_Tag_D                0x05
-#define Index_Store_Tag_I       0x08
+#define Index_Store_Tag_I               0x08
-#define Index_Store_Tag_D       0x09
+#define Index_Store_Tag_D               0x09
 #if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I        0x00
+#define Hit_Invalidate_I                0x00
 #else
-#define Hit_Invalidate_I        0x10
+#define Hit_Invalidate_I                0x10
 #endif
-#define Hit_Invalidate_D        0x11
+#define Hit_Invalidate_D                0x11
-#define Hit_Writeback_Inv_D     0x15
+#define Hit_Writeback_Inv_D             0x15
 /*
 * R4000-specific cacheops
 */
-#define Create_Dirty_Excl_D     0x0d
+#define Create_Dirty_Excl_D             0x0d
-#define Fill                    0x14
+#define Fill                            0x14
-#define Hit_Writeback_I         0x18
+#define Hit_Writeback_I                 0x18
-#define Hit_Writeback_D         0x19
+#define Hit_Writeback_D                 0x19
 /*
 * R4000SC and R4400SC-specific cacheops
 */
-#define Index_Invalidate_SI     0x02
+#define Index_Invalidate_SI             0x02
-#define Index_Writeback_Inv_SD  0x03
+#define Index_Writeback_Inv_SD          0x03
-#define Index_Load_Tag_SI       0x06
+#define Index_Load_Tag_SI               0x06
-#define Index_Load_Tag_SD       0x07
+#define Index_Load_Tag_SD               0x07
-#define Index_Store_Tag_SI      0x0A
+#define Index_Store_Tag_SI              0x0A
-#define Index_Store_Tag_SD      0x0B
+#define Index_Store_Tag_SD              0x0B
-#define Create_Dirty_Excl_SD    0x0f
+#define Create_Dirty_Excl_SD            0x0f
-#define Hit_Invalidate_SI       0x12
+#define Hit_Invalidate_SI               0x12
-#define Hit_Invalidate_SD       0x13
+#define Hit_Invalidate_SD               0x13
-#define Hit_Writeback_Inv_SD    0x17
+#define Hit_Writeback_Inv_SD            0x17
-#define Hit_Writeback_SD        0x1b
+#define Hit_Writeback_SD                0x1b
-#define Hit_Set_Virtual_SI      0x1e
+#define Hit_Set_Virtual_SI              0x1e
-#define Hit_Set_Virtual_SD      0x1f
+#define Hit_Set_Virtual_SD              0x1f
 /*
 * R5000-specific cacheops
 */
-#define R5K_Page_Invalidate_S   0x17
+#define R5K_Page_Invalidate_S           0x17
 /*
 * RM7000-specific cacheops
 */
-#define Page_Invalidate_T       0x16
+#define Page_Invalidate_T               0x16
-#define Index_Store_Tag_T       0x0a
+#define Index_Store_Tag_T               0x0a
-#define Index_Load_Tag_T        0x06
+#define Index_Load_Tag_T                0x06
 /*
 * R10000-specific cacheops
@@ -71,17 +71,17 @@
 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
 * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
 */
-#define Index_Writeback_Inv_S   0x03
+#define Index_Writeback_Inv_S           0x03
-#define Index_Load_Tag_S        0x07
+#define Index_Load_Tag_S                0x07
-#define Index_Store_Tag_S       0x0B
+#define Index_Store_Tag_S               0x0B
-#define Hit_Invalidate_S        0x13
+#define Hit_Invalidate_S                0x13
-#define Cache_Barrier           0x14
+#define Cache_Barrier                   0x14
-#define Hit_Writeback_Inv_S     0x17
+#define Hit_Writeback_Inv_S             0x17
-#define Index_Load_Data_I       0x18
+#define Index_Load_Data_I               0x18
-#define Index_Load_Data_D       0x19
+#define Index_Load_Data_D               0x19
-#define Index_Load_Data_S       0x1b
+#define Index_Load_Data_S               0x1b
-#define Index_Store_Data_I      0x1c
+#define Index_Store_Data_I              0x1c
-#define Index_Store_Data_D      0x1d
+#define Index_Store_Data_D              0x1d
-#define Index_Store_Data_S      0x1f
+#define Index_Store_Data_S              0x1f
 #endif  /* __ASM_CACHEOPS_H */
author	Ralf Baechle <ralf@linux-mips.org>	2013-09-27 13:07:18 -0400
committer	Ralf Baechle <ralf@linux-mips.org>	2013-10-29 16:25:22 -0400
commit	7b784c634b4147345b46251884be6be4bd45fd43 (patch)
tree	a07d095d366d8a5a37e23d639fc3bd8723d76f04
parent	c1724c89973e28a12a605f66e5151bdb8c354b76 (diff)

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h index 68f37e3eccc7..0644c985d153 100644 --- a/arch/mips/include/asm/cacheops.h +++ b/arch/mips/include/asm/cacheops.h
@@ -14,56 +14,56 @@
14	/*	14	/*
15	* Cache Operations available on all MIPS processors with R4000-style caches	15	* Cache Operations available on all MIPS processors with R4000-style caches
16	*/	16	*/
17	#define Index_Invalidate_I 0x00	17	#define Index_Invalidate_I 0x00
18	#define Index_Writeback_Inv_D 0x01	18	#define Index_Writeback_Inv_D 0x01
19	#define Index_Load_Tag_I 0x04	19	#define Index_Load_Tag_I 0x04
20	#define Index_Load_Tag_D 0x05	20	#define Index_Load_Tag_D 0x05
21	#define Index_Store_Tag_I 0x08	21	#define Index_Store_Tag_I 0x08
22	#define Index_Store_Tag_D 0x09	22	#define Index_Store_Tag_D 0x09
23	#if defined(CONFIG_CPU_LOONGSON2)	23	#if defined(CONFIG_CPU_LOONGSON2)
24	#define Hit_Invalidate_I 0x00	24	#define Hit_Invalidate_I 0x00
25	#else	25	#else
26	#define Hit_Invalidate_I 0x10	26	#define Hit_Invalidate_I 0x10
27	#endif	27	#endif
28	#define Hit_Invalidate_D 0x11	28	#define Hit_Invalidate_D 0x11
29	#define Hit_Writeback_Inv_D 0x15	29	#define Hit_Writeback_Inv_D 0x15
30		30
31	/*	31	/*
32	* R4000-specific cacheops	32	* R4000-specific cacheops
33	*/	33	*/
34	#define Create_Dirty_Excl_D 0x0d	34	#define Create_Dirty_Excl_D 0x0d
35	#define Fill 0x14	35	#define Fill 0x14
36	#define Hit_Writeback_I 0x18	36	#define Hit_Writeback_I 0x18
37	#define Hit_Writeback_D 0x19	37	#define Hit_Writeback_D 0x19
38		38
39	/*	39	/*
40	* R4000SC and R4400SC-specific cacheops	40	* R4000SC and R4400SC-specific cacheops
41	*/	41	*/
42	#define Index_Invalidate_SI 0x02	42	#define Index_Invalidate_SI 0x02
43	#define Index_Writeback_Inv_SD 0x03	43	#define Index_Writeback_Inv_SD 0x03
44	#define Index_Load_Tag_SI 0x06	44	#define Index_Load_Tag_SI 0x06
45	#define Index_Load_Tag_SD 0x07	45	#define Index_Load_Tag_SD 0x07
46	#define Index_Store_Tag_SI 0x0A	46	#define Index_Store_Tag_SI 0x0A
47	#define Index_Store_Tag_SD 0x0B	47	#define Index_Store_Tag_SD 0x0B
48	#define Create_Dirty_Excl_SD 0x0f	48	#define Create_Dirty_Excl_SD 0x0f
49	#define Hit_Invalidate_SI 0x12	49	#define Hit_Invalidate_SI 0x12
50	#define Hit_Invalidate_SD 0x13	50	#define Hit_Invalidate_SD 0x13
51	#define Hit_Writeback_Inv_SD 0x17	51	#define Hit_Writeback_Inv_SD 0x17
52	#define Hit_Writeback_SD 0x1b	52	#define Hit_Writeback_SD 0x1b
53	#define Hit_Set_Virtual_SI 0x1e	53	#define Hit_Set_Virtual_SI 0x1e
54	#define Hit_Set_Virtual_SD 0x1f	54	#define Hit_Set_Virtual_SD 0x1f
55		55
56	/*	56	/*
57	* R5000-specific cacheops	57	* R5000-specific cacheops
58	*/	58	*/
59	#define R5K_Page_Invalidate_S 0x17	59	#define R5K_Page_Invalidate_S 0x17
60		60
61	/*	61	/*
62	* RM7000-specific cacheops	62	* RM7000-specific cacheops
63	*/	63	*/
64	#define Page_Invalidate_T 0x16	64	#define Page_Invalidate_T 0x16
65	#define Index_Store_Tag_T 0x0a	65	#define Index_Store_Tag_T 0x0a
66	#define Index_Load_Tag_T 0x06	66	#define Index_Load_Tag_T 0x06
67		67
68	/*	68	/*
69	* R10000-specific cacheops	69	* R10000-specific cacheops
@@ -71,17 +71,17 @@
71	* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.	71	* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
72	* Most of the _S cacheops are identical to the R4000SC _SD cacheops.	72	* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
73	*/	73	*/
74	#define Index_Writeback_Inv_S 0x03	74	#define Index_Writeback_Inv_S 0x03
75	#define Index_Load_Tag_S 0x07	75	#define Index_Load_Tag_S 0x07
76	#define Index_Store_Tag_S 0x0B	76	#define Index_Store_Tag_S 0x0B
77	#define Hit_Invalidate_S 0x13	77	#define Hit_Invalidate_S 0x13
78	#define Cache_Barrier 0x14	78	#define Cache_Barrier 0x14
79	#define Hit_Writeback_Inv_S 0x17	79	#define Hit_Writeback_Inv_S 0x17
80	#define Index_Load_Data_I 0x18	80	#define Index_Load_Data_I 0x18
81	#define Index_Load_Data_D 0x19	81	#define Index_Load_Data_D 0x19
82	#define Index_Load_Data_S 0x1b	82	#define Index_Load_Data_S 0x1b
83	#define Index_Store_Data_I 0x1c	83	#define Index_Store_Data_I 0x1c
84	#define Index_Store_Data_D 0x1d	84	#define Index_Store_Data_D 0x1d
85	#define Index_Store_Data_S 0x1f	85	#define Index_Store_Data_S 0x1f
86		86
87	#endif /* __ASM_CACHEOPS_H */	87	#endif /* __ASM_CACHEOPS_H */