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authorGrant Grundler <grundler@parisc-linux.org>2008-02-17 13:30:23 -0500
committerJeff Garzik <jeff@garzik.org>2008-02-23 23:55:03 -0500
commit7a7d23dac29825a75e375800573d53e49d864a42 (patch)
treeec96df83459e857efcabfe4624f2a74c39ec4001
parent740db6d7f5bf194abf327613a5a500e3729fc19a (diff)
uli526x partially recognizing interface
Patch fixes: http://bugzilla.kernel.org/show_bug.cgi?id=5839 Init sequence needs to poll phy until phy reset is complete. This is the same problem that I fixed in 2002 in tulip driver. Thanks to manty@manty.net for testing this patch. Thanks to Pozsar Balazs <pozsy@uhulinux.hu> for posting/testing a similar patch before: http://lkml.org/lkml/2006/8/21/45 Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r--drivers/net/tulip/uli526x.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/net/tulip/uli526x.c b/drivers/net/tulip/uli526x.c
index a7afeea156bd..a59c1f224aa8 100644
--- a/drivers/net/tulip/uli526x.c
+++ b/drivers/net/tulip/uli526x.c
@@ -482,9 +482,11 @@ static void uli526x_init(struct net_device *dev)
482 struct uli526x_board_info *db = netdev_priv(dev); 482 struct uli526x_board_info *db = netdev_priv(dev);
483 unsigned long ioaddr = db->ioaddr; 483 unsigned long ioaddr = db->ioaddr;
484 u8 phy_tmp; 484 u8 phy_tmp;
485 u8 timeout;
485 u16 phy_value; 486 u16 phy_value;
486 u16 phy_reg_reset; 487 u16 phy_reg_reset;
487 488
489
488 ULI526X_DBUG(0, "uli526x_init()", 0); 490 ULI526X_DBUG(0, "uli526x_init()", 0);
489 491
490 /* Reset M526x MAC controller */ 492 /* Reset M526x MAC controller */
@@ -509,11 +511,19 @@ static void uli526x_init(struct net_device *dev)
509 /* Parser SROM and media mode */ 511 /* Parser SROM and media mode */
510 db->media_mode = uli526x_media_mode; 512 db->media_mode = uli526x_media_mode;
511 513
512 /* Phyxcer capability setting */ 514 /* phyxcer capability setting */
513 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id); 515 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
514 phy_reg_reset = (phy_reg_reset | 0x8000); 516 phy_reg_reset = (phy_reg_reset | 0x8000);
515 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id); 517 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
518
519 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
520 * functions") or phy data sheet for details on phy reset
521 */
516 udelay(500); 522 udelay(500);
523 timeout = 10;
524 while (timeout-- &&
525 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
526 udelay(100);
517 527
518 /* Process Phyxcer Media Mode */ 528 /* Process Phyxcer Media Mode */
519 uli526x_set_phyxcer(db); 529 uli526x_set_phyxcer(db);