diff options
| author | Heiko Stübner <heiko@sntech.de> | 2013-03-21 00:10:13 -0400 |
|---|---|---|
| committer | Wolfram Sang <wsa@the-dreams.de> | 2013-03-24 05:30:57 -0400 |
| commit | 7a6674dabfe240cc7015fc201f9662d0640e8081 (patch) | |
| tree | d06fe0da0f4b85ba1aeddd02c7a157728e475035 | |
| parent | e636602ac2613da8c1777cb42443223994be4107 (diff) | |
i2c: s3c2410: fixup the styling of the newly moved register definitions
Make them conform more to established standards.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| -rw-r--r-- | drivers/i2c/busses/i2c-s3c2410.c | 52 |
1 files changed, 25 insertions, 27 deletions
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c index 216fea12e2e9..0a81f1f4aee1 100644 --- a/drivers/i2c/busses/i2c-s3c2410.c +++ b/drivers/i2c/busses/i2c-s3c2410.c | |||
| @@ -46,35 +46,33 @@ | |||
| 46 | 46 | ||
| 47 | /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ | 47 | /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ |
| 48 | 48 | ||
| 49 | #define S3C2410_IICREG(x) (x) | 49 | #define S3C2410_IICCON 0x00 |
| 50 | 50 | #define S3C2410_IICSTAT 0x04 | |
| 51 | #define S3C2410_IICCON S3C2410_IICREG(0x00) | 51 | #define S3C2410_IICADD 0x08 |
| 52 | #define S3C2410_IICSTAT S3C2410_IICREG(0x04) | 52 | #define S3C2410_IICDS 0x0C |
| 53 | #define S3C2410_IICADD S3C2410_IICREG(0x08) | 53 | #define S3C2440_IICLC 0x10 |
| 54 | #define S3C2410_IICDS S3C2410_IICREG(0x0C) | 54 | |
| 55 | #define S3C2440_IICLC S3C2410_IICREG(0x10) | 55 | #define S3C2410_IICCON_ACKEN (1 << 7) |
| 56 | 56 | #define S3C2410_IICCON_TXDIV_16 (0 << 6) | |
| 57 | #define S3C2410_IICCON_ACKEN (1<<7) | 57 | #define S3C2410_IICCON_TXDIV_512 (1 << 6) |
| 58 | #define S3C2410_IICCON_TXDIV_16 (0<<6) | 58 | #define S3C2410_IICCON_IRQEN (1 << 5) |
| 59 | #define S3C2410_IICCON_TXDIV_512 (1<<6) | 59 | #define S3C2410_IICCON_IRQPEND (1 << 4) |
| 60 | #define S3C2410_IICCON_IRQEN (1<<5) | 60 | #define S3C2410_IICCON_SCALE(x) ((x) & 0xf) |
| 61 | #define S3C2410_IICCON_IRQPEND (1<<4) | ||
| 62 | #define S3C2410_IICCON_SCALE(x) ((x)&15) | ||
| 63 | #define S3C2410_IICCON_SCALEMASK (0xf) | 61 | #define S3C2410_IICCON_SCALEMASK (0xf) |
| 64 | 62 | ||
| 65 | #define S3C2410_IICSTAT_MASTER_RX (2<<6) | 63 | #define S3C2410_IICSTAT_MASTER_RX (2 << 6) |
| 66 | #define S3C2410_IICSTAT_MASTER_TX (3<<6) | 64 | #define S3C2410_IICSTAT_MASTER_TX (3 << 6) |
| 67 | #define S3C2410_IICSTAT_SLAVE_RX (0<<6) | 65 | #define S3C2410_IICSTAT_SLAVE_RX (0 << 6) |
| 68 | #define S3C2410_IICSTAT_SLAVE_TX (1<<6) | 66 | #define S3C2410_IICSTAT_SLAVE_TX (1 << 6) |
| 69 | #define S3C2410_IICSTAT_MODEMASK (3<<6) | 67 | #define S3C2410_IICSTAT_MODEMASK (3 << 6) |
| 70 | 68 | ||
| 71 | #define S3C2410_IICSTAT_START (1<<5) | 69 | #define S3C2410_IICSTAT_START (1 << 5) |
| 72 | #define S3C2410_IICSTAT_BUSBUSY (1<<5) | 70 | #define S3C2410_IICSTAT_BUSBUSY (1 << 5) |
| 73 | #define S3C2410_IICSTAT_TXRXEN (1<<4) | 71 | #define S3C2410_IICSTAT_TXRXEN (1 << 4) |
| 74 | #define S3C2410_IICSTAT_ARBITR (1<<3) | 72 | #define S3C2410_IICSTAT_ARBITR (1 << 3) |
| 75 | #define S3C2410_IICSTAT_ASSLAVE (1<<2) | 73 | #define S3C2410_IICSTAT_ASSLAVE (1 << 2) |
| 76 | #define S3C2410_IICSTAT_ADDR0 (1<<1) | 74 | #define S3C2410_IICSTAT_ADDR0 (1 << 1) |
| 77 | #define S3C2410_IICSTAT_LASTBIT (1<<0) | 75 | #define S3C2410_IICSTAT_LASTBIT (1 << 0) |
| 78 | 76 | ||
| 79 | #define S3C2410_IICLC_SDA_DELAY0 (0 << 0) | 77 | #define S3C2410_IICLC_SDA_DELAY0 (0 << 0) |
| 80 | #define S3C2410_IICLC_SDA_DELAY5 (1 << 0) | 78 | #define S3C2410_IICLC_SDA_DELAY5 (1 << 0) |
| @@ -82,7 +80,7 @@ | |||
| 82 | #define S3C2410_IICLC_SDA_DELAY15 (3 << 0) | 80 | #define S3C2410_IICLC_SDA_DELAY15 (3 << 0) |
| 83 | #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) | 81 | #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) |
| 84 | 82 | ||
| 85 | #define S3C2410_IICLC_FILTER_ON (1<<2) | 83 | #define S3C2410_IICLC_FILTER_ON (1 << 2) |
| 86 | 84 | ||
| 87 | /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ | 85 | /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ |
| 88 | #define QUIRK_S3C2440 (1 << 0) | 86 | #define QUIRK_S3C2440 (1 << 0) |