diff options
author | Francois Romieu <romieu@fr.zoreil.com> | 2011-08-21 12:32:05 -0400 |
---|---|---|
committer | Francois Romieu <romieu@fr.zoreil.com> | 2011-08-25 05:08:16 -0400 |
commit | 78f6a6bd89e9a33e4be1bc61e6990a1172aa396e (patch) | |
tree | dbbe9fcf40e564aea1e45f2f42a7afc546cc1333 | |
parent | 0856a304091b33a8e8f9f9c98e776f425af2b625 (diff) |
dl2k: use standard #defines from mii.h.
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
-rw-r--r-- | drivers/net/ethernet/dlink/dl2k.c | 105 | ||||
-rw-r--r-- | drivers/net/ethernet/dlink/dl2k.h | 110 |
2 files changed, 53 insertions, 162 deletions
diff --git a/drivers/net/ethernet/dlink/dl2k.c b/drivers/net/ethernet/dlink/dl2k.c index 3fa91408532f..b2dc2c81a147 100644 --- a/drivers/net/ethernet/dlink/dl2k.c +++ b/drivers/net/ethernet/dlink/dl2k.c | |||
@@ -1428,7 +1428,7 @@ mii_wait_link (struct net_device *dev, int wait) | |||
1428 | 1428 | ||
1429 | do { | 1429 | do { |
1430 | bmsr = mii_read (dev, phy_addr, MII_BMSR); | 1430 | bmsr = mii_read (dev, phy_addr, MII_BMSR); |
1431 | if (bmsr & MII_BMSR_LINK_STATUS) | 1431 | if (bmsr & BMSR_LSTATUS) |
1432 | return 0; | 1432 | return 0; |
1433 | mdelay (1); | 1433 | mdelay (1); |
1434 | } while (--wait > 0); | 1434 | } while (--wait > 0); |
@@ -1449,60 +1449,60 @@ mii_get_media (struct net_device *dev) | |||
1449 | 1449 | ||
1450 | bmsr = mii_read (dev, phy_addr, MII_BMSR); | 1450 | bmsr = mii_read (dev, phy_addr, MII_BMSR); |
1451 | if (np->an_enable) { | 1451 | if (np->an_enable) { |
1452 | if (!(bmsr & MII_BMSR_AN_COMPLETE)) { | 1452 | if (!(bmsr & BMSR_ANEGCOMPLETE)) { |
1453 | /* Auto-Negotiation not completed */ | 1453 | /* Auto-Negotiation not completed */ |
1454 | return -1; | 1454 | return -1; |
1455 | } | 1455 | } |
1456 | negotiate = mii_read (dev, phy_addr, MII_ANAR) & | 1456 | negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) & |
1457 | mii_read (dev, phy_addr, MII_ANLPAR); | 1457 | mii_read (dev, phy_addr, MII_LPA); |
1458 | mscr = mii_read (dev, phy_addr, MII_MSCR); | 1458 | mscr = mii_read (dev, phy_addr, MII_CTRL1000); |
1459 | mssr = mii_read (dev, phy_addr, MII_MSSR); | 1459 | mssr = mii_read (dev, phy_addr, MII_STAT1000); |
1460 | if (mscr & MII_MSCR_1000BT_FD && mssr & MII_MSSR_LP_1000BT_FD) { | 1460 | if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) { |
1461 | np->speed = 1000; | 1461 | np->speed = 1000; |
1462 | np->full_duplex = 1; | 1462 | np->full_duplex = 1; |
1463 | printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); | 1463 | printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n"); |
1464 | } else if (mscr & MII_MSCR_1000BT_HD && mssr & MII_MSSR_LP_1000BT_HD) { | 1464 | } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) { |
1465 | np->speed = 1000; | 1465 | np->speed = 1000; |
1466 | np->full_duplex = 0; | 1466 | np->full_duplex = 0; |
1467 | printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); | 1467 | printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n"); |
1468 | } else if (negotiate & MII_ANAR_100BX_FD) { | 1468 | } else if (negotiate & ADVERTISE_100FULL) { |
1469 | np->speed = 100; | 1469 | np->speed = 100; |
1470 | np->full_duplex = 1; | 1470 | np->full_duplex = 1; |
1471 | printk (KERN_INFO "Auto 100 Mbps, Full duplex\n"); | 1471 | printk (KERN_INFO "Auto 100 Mbps, Full duplex\n"); |
1472 | } else if (negotiate & MII_ANAR_100BX_HD) { | 1472 | } else if (negotiate & ADVERTISE_100HALF) { |
1473 | np->speed = 100; | 1473 | np->speed = 100; |
1474 | np->full_duplex = 0; | 1474 | np->full_duplex = 0; |
1475 | printk (KERN_INFO "Auto 100 Mbps, Half duplex\n"); | 1475 | printk (KERN_INFO "Auto 100 Mbps, Half duplex\n"); |
1476 | } else if (negotiate & MII_ANAR_10BT_FD) { | 1476 | } else if (negotiate & ADVERTISE_10FULL) { |
1477 | np->speed = 10; | 1477 | np->speed = 10; |
1478 | np->full_duplex = 1; | 1478 | np->full_duplex = 1; |
1479 | printk (KERN_INFO "Auto 10 Mbps, Full duplex\n"); | 1479 | printk (KERN_INFO "Auto 10 Mbps, Full duplex\n"); |
1480 | } else if (negotiate & MII_ANAR_10BT_HD) { | 1480 | } else if (negotiate & ADVERTISE_10HALF) { |
1481 | np->speed = 10; | 1481 | np->speed = 10; |
1482 | np->full_duplex = 0; | 1482 | np->full_duplex = 0; |
1483 | printk (KERN_INFO "Auto 10 Mbps, Half duplex\n"); | 1483 | printk (KERN_INFO "Auto 10 Mbps, Half duplex\n"); |
1484 | } | 1484 | } |
1485 | if (negotiate & MII_ANAR_PAUSE) { | 1485 | if (negotiate & ADVERTISE_PAUSE_CAP) { |
1486 | np->tx_flow &= 1; | 1486 | np->tx_flow &= 1; |
1487 | np->rx_flow &= 1; | 1487 | np->rx_flow &= 1; |
1488 | } else if (negotiate & MII_ANAR_ASYMMETRIC) { | 1488 | } else if (negotiate & ADVERTISE_PAUSE_ASYM) { |
1489 | np->tx_flow = 0; | 1489 | np->tx_flow = 0; |
1490 | np->rx_flow &= 1; | 1490 | np->rx_flow &= 1; |
1491 | } | 1491 | } |
1492 | /* else tx_flow, rx_flow = user select */ | 1492 | /* else tx_flow, rx_flow = user select */ |
1493 | } else { | 1493 | } else { |
1494 | __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR); | 1494 | __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR); |
1495 | switch (bmcr & (MII_BMCR_SPEED_100 | MII_BMCR_SPEED_1000)) { | 1495 | switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) { |
1496 | case MII_BMCR_SPEED_1000: | 1496 | case BMCR_SPEED1000: |
1497 | printk (KERN_INFO "Operating at 1000 Mbps, "); | 1497 | printk (KERN_INFO "Operating at 1000 Mbps, "); |
1498 | break; | 1498 | break; |
1499 | case MII_BMCR_SPEED_100: | 1499 | case BMCR_SPEED100: |
1500 | printk (KERN_INFO "Operating at 100 Mbps, "); | 1500 | printk (KERN_INFO "Operating at 100 Mbps, "); |
1501 | break; | 1501 | break; |
1502 | case 0: | 1502 | case 0: |
1503 | printk (KERN_INFO "Operating at 10 Mbps, "); | 1503 | printk (KERN_INFO "Operating at 10 Mbps, "); |
1504 | } | 1504 | } |
1505 | if (bmcr & MII_BMCR_DUPLEX_MODE) { | 1505 | if (bmcr & BMCR_FULLDPLX) { |
1506 | printk (KERN_CONT "Full duplex\n"); | 1506 | printk (KERN_CONT "Full duplex\n"); |
1507 | } else { | 1507 | } else { |
1508 | printk (KERN_CONT "Half duplex\n"); | 1508 | printk (KERN_CONT "Half duplex\n"); |
@@ -1536,24 +1536,22 @@ mii_set_media (struct net_device *dev) | |||
1536 | if (np->an_enable) { | 1536 | if (np->an_enable) { |
1537 | /* Advertise capabilities */ | 1537 | /* Advertise capabilities */ |
1538 | bmsr = mii_read (dev, phy_addr, MII_BMSR); | 1538 | bmsr = mii_read (dev, phy_addr, MII_BMSR); |
1539 | anar = mii_read (dev, phy_addr, MII_ANAR) & | 1539 | anar = mii_read (dev, phy_addr, MII_ADVERTISE) & |
1540 | ~MII_ANAR_100BX_FD & | 1540 | ~(ADVERTISE_100FULL | ADVERTISE_10FULL | |
1541 | ~MII_ANAR_100BX_HD & | 1541 | ADVERTISE_100HALF | ADVERTISE_10HALF | |
1542 | ~MII_ANAR_100BT4 & | 1542 | ADVERTISE_100BASE4); |
1543 | ~MII_ANAR_10BT_FD & | 1543 | if (bmsr & BMSR_100FULL) |
1544 | ~MII_ANAR_10BT_HD; | 1544 | anar |= ADVERTISE_100FULL; |
1545 | if (bmsr & MII_BMSR_100BX_FD) | 1545 | if (bmsr & BMSR_100HALF) |
1546 | anar |= MII_ANAR_100BX_FD; | 1546 | anar |= ADVERTISE_100HALF; |
1547 | if (bmsr & MII_BMSR_100BX_HD) | 1547 | if (bmsr & BMSR_100BASE4) |
1548 | anar |= MII_ANAR_100BX_HD; | 1548 | anar |= ADVERTISE_100BASE4; |
1549 | if (bmsr & MII_BMSR_100BT4) | 1549 | if (bmsr & BMSR_10FULL) |
1550 | anar |= MII_ANAR_100BT4; | 1550 | anar |= ADVERTISE_10FULL; |
1551 | if (bmsr & MII_BMSR_10BT_FD) | 1551 | if (bmsr & BMSR_10HALF) |
1552 | anar |= MII_ANAR_10BT_FD; | 1552 | anar |= ADVERTISE_10HALF; |
1553 | if (bmsr & MII_BMSR_10BT_HD) | 1553 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1554 | anar |= MII_ANAR_10BT_HD; | 1554 | mii_write (dev, phy_addr, MII_ADVERTISE, anar); |
1555 | anar |= MII_ANAR_PAUSE | MII_ANAR_ASYMMETRIC; | ||
1556 | mii_write (dev, phy_addr, MII_ANAR, anar); | ||
1557 | 1555 | ||
1558 | /* Enable Auto crossover */ | 1556 | /* Enable Auto crossover */ |
1559 | pscr = mii_read (dev, phy_addr, MII_PHY_SCR); | 1557 | pscr = mii_read (dev, phy_addr, MII_PHY_SCR); |
@@ -1561,8 +1559,8 @@ mii_set_media (struct net_device *dev) | |||
1561 | mii_write (dev, phy_addr, MII_PHY_SCR, pscr); | 1559 | mii_write (dev, phy_addr, MII_PHY_SCR, pscr); |
1562 | 1560 | ||
1563 | /* Soft reset PHY */ | 1561 | /* Soft reset PHY */ |
1564 | mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); | 1562 | mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET); |
1565 | bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | MII_BMCR_RESET; | 1563 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; |
1566 | mii_write (dev, phy_addr, MII_BMCR, bmcr); | 1564 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1567 | mdelay(1); | 1565 | mdelay(1); |
1568 | } else { | 1566 | } else { |
@@ -1574,7 +1572,7 @@ mii_set_media (struct net_device *dev) | |||
1574 | 1572 | ||
1575 | /* 2) PHY Reset */ | 1573 | /* 2) PHY Reset */ |
1576 | bmcr = mii_read (dev, phy_addr, MII_BMCR); | 1574 | bmcr = mii_read (dev, phy_addr, MII_BMCR); |
1577 | bmcr |= MII_BMCR_RESET; | 1575 | bmcr |= BMCR_RESET; |
1578 | mii_write (dev, phy_addr, MII_BMCR, bmcr); | 1576 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1579 | 1577 | ||
1580 | /* 3) Power Down */ | 1578 | /* 3) Power Down */ |
@@ -1583,25 +1581,25 @@ mii_set_media (struct net_device *dev) | |||
1583 | mdelay (100); /* wait a certain time */ | 1581 | mdelay (100); /* wait a certain time */ |
1584 | 1582 | ||
1585 | /* 4) Advertise nothing */ | 1583 | /* 4) Advertise nothing */ |
1586 | mii_write (dev, phy_addr, MII_ANAR, 0); | 1584 | mii_write (dev, phy_addr, MII_ADVERTISE, 0); |
1587 | 1585 | ||
1588 | /* 5) Set media and Power Up */ | 1586 | /* 5) Set media and Power Up */ |
1589 | bmcr = MII_BMCR_POWER_DOWN; | 1587 | bmcr = BMCR_PDOWN; |
1590 | if (np->speed == 100) { | 1588 | if (np->speed == 100) { |
1591 | bmcr |= MII_BMCR_SPEED_100; | 1589 | bmcr |= BMCR_SPEED100; |
1592 | printk (KERN_INFO "Manual 100 Mbps, "); | 1590 | printk (KERN_INFO "Manual 100 Mbps, "); |
1593 | } else if (np->speed == 10) { | 1591 | } else if (np->speed == 10) { |
1594 | printk (KERN_INFO "Manual 10 Mbps, "); | 1592 | printk (KERN_INFO "Manual 10 Mbps, "); |
1595 | } | 1593 | } |
1596 | if (np->full_duplex) { | 1594 | if (np->full_duplex) { |
1597 | bmcr |= MII_BMCR_DUPLEX_MODE; | 1595 | bmcr |= BMCR_FULLDPLX; |
1598 | printk (KERN_CONT "Full duplex\n"); | 1596 | printk (KERN_CONT "Full duplex\n"); |
1599 | } else { | 1597 | } else { |
1600 | printk (KERN_CONT "Half duplex\n"); | 1598 | printk (KERN_CONT "Half duplex\n"); |
1601 | } | 1599 | } |
1602 | #if 0 | 1600 | #if 0 |
1603 | /* Set 1000BaseT Master/Slave setting */ | 1601 | /* Set 1000BaseT Master/Slave setting */ |
1604 | mscr = mii_read (dev, phy_addr, MII_MSCR); | 1602 | mscr = mii_read (dev, phy_addr, MII_CTRL1000); |
1605 | mscr |= MII_MSCR_CFG_ENABLE; | 1603 | mscr |= MII_MSCR_CFG_ENABLE; |
1606 | mscr &= ~MII_MSCR_CFG_VALUE = 0; | 1604 | mscr &= ~MII_MSCR_CFG_VALUE = 0; |
1607 | #endif | 1605 | #endif |
@@ -1624,7 +1622,7 @@ mii_get_media_pcs (struct net_device *dev) | |||
1624 | 1622 | ||
1625 | bmsr = mii_read (dev, phy_addr, PCS_BMSR); | 1623 | bmsr = mii_read (dev, phy_addr, PCS_BMSR); |
1626 | if (np->an_enable) { | 1624 | if (np->an_enable) { |
1627 | if (!(bmsr & MII_BMSR_AN_COMPLETE)) { | 1625 | if (!(bmsr & BMSR_ANEGCOMPLETE)) { |
1628 | /* Auto-Negotiation not completed */ | 1626 | /* Auto-Negotiation not completed */ |
1629 | return -1; | 1627 | return -1; |
1630 | } | 1628 | } |
@@ -1649,7 +1647,7 @@ mii_get_media_pcs (struct net_device *dev) | |||
1649 | } else { | 1647 | } else { |
1650 | __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR); | 1648 | __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR); |
1651 | printk (KERN_INFO "Operating at 1000 Mbps, "); | 1649 | printk (KERN_INFO "Operating at 1000 Mbps, "); |
1652 | if (bmcr & MII_BMCR_DUPLEX_MODE) { | 1650 | if (bmcr & BMCR_FULLDPLX) { |
1653 | printk (KERN_CONT "Full duplex\n"); | 1651 | printk (KERN_CONT "Full duplex\n"); |
1654 | } else { | 1652 | } else { |
1655 | printk (KERN_CONT "Half duplex\n"); | 1653 | printk (KERN_CONT "Half duplex\n"); |
@@ -1682,7 +1680,7 @@ mii_set_media_pcs (struct net_device *dev) | |||
1682 | if (np->an_enable) { | 1680 | if (np->an_enable) { |
1683 | /* Advertise capabilities */ | 1681 | /* Advertise capabilities */ |
1684 | esr = mii_read (dev, phy_addr, PCS_ESR); | 1682 | esr = mii_read (dev, phy_addr, PCS_ESR); |
1685 | anar = mii_read (dev, phy_addr, MII_ANAR) & | 1683 | anar = mii_read (dev, phy_addr, MII_ADVERTISE) & |
1686 | ~PCS_ANAR_HALF_DUPLEX & | 1684 | ~PCS_ANAR_HALF_DUPLEX & |
1687 | ~PCS_ANAR_FULL_DUPLEX; | 1685 | ~PCS_ANAR_FULL_DUPLEX; |
1688 | if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD)) | 1686 | if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD)) |
@@ -1690,22 +1688,21 @@ mii_set_media_pcs (struct net_device *dev) | |||
1690 | if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD)) | 1688 | if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD)) |
1691 | anar |= PCS_ANAR_FULL_DUPLEX; | 1689 | anar |= PCS_ANAR_FULL_DUPLEX; |
1692 | anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC; | 1690 | anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC; |
1693 | mii_write (dev, phy_addr, MII_ANAR, anar); | 1691 | mii_write (dev, phy_addr, MII_ADVERTISE, anar); |
1694 | 1692 | ||
1695 | /* Soft reset PHY */ | 1693 | /* Soft reset PHY */ |
1696 | mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET); | 1694 | mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET); |
1697 | bmcr = MII_BMCR_AN_ENABLE | MII_BMCR_RESTART_AN | | 1695 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; |
1698 | MII_BMCR_RESET; | ||
1699 | mii_write (dev, phy_addr, MII_BMCR, bmcr); | 1696 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1700 | mdelay(1); | 1697 | mdelay(1); |
1701 | } else { | 1698 | } else { |
1702 | /* Force speed setting */ | 1699 | /* Force speed setting */ |
1703 | /* PHY Reset */ | 1700 | /* PHY Reset */ |
1704 | bmcr = MII_BMCR_RESET; | 1701 | bmcr = BMCR_RESET; |
1705 | mii_write (dev, phy_addr, MII_BMCR, bmcr); | 1702 | mii_write (dev, phy_addr, MII_BMCR, bmcr); |
1706 | mdelay(10); | 1703 | mdelay(10); |
1707 | if (np->full_duplex) { | 1704 | if (np->full_duplex) { |
1708 | bmcr = MII_BMCR_DUPLEX_MODE; | 1705 | bmcr = BMCR_FULLDPLX; |
1709 | printk (KERN_INFO "Manual full duplex\n"); | 1706 | printk (KERN_INFO "Manual full duplex\n"); |
1710 | } else { | 1707 | } else { |
1711 | bmcr = 0; | 1708 | bmcr = 0; |
@@ -1715,7 +1712,7 @@ mii_set_media_pcs (struct net_device *dev) | |||
1715 | mdelay(10); | 1712 | mdelay(10); |
1716 | 1713 | ||
1717 | /* Advertise nothing */ | 1714 | /* Advertise nothing */ |
1718 | mii_write (dev, phy_addr, MII_ANAR, 0); | 1715 | mii_write (dev, phy_addr, MII_ADVERTISE, 0); |
1719 | } | 1716 | } |
1720 | return 0; | 1717 | return 0; |
1721 | } | 1718 | } |
diff --git a/drivers/net/ethernet/dlink/dl2k.h b/drivers/net/ethernet/dlink/dl2k.h index 7caab3d26a9e..ba0adcafa55a 100644 --- a/drivers/net/ethernet/dlink/dl2k.h +++ b/drivers/net/ethernet/dlink/dl2k.h | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/init.h> | 28 | #include <linux/init.h> |
29 | #include <linux/crc32.h> | 29 | #include <linux/crc32.h> |
30 | #include <linux/ethtool.h> | 30 | #include <linux/ethtool.h> |
31 | #include <linux/mii.h> | ||
31 | #include <linux/bitops.h> | 32 | #include <linux/bitops.h> |
32 | #include <asm/processor.h> /* Processor type for cache alignment. */ | 33 | #include <asm/processor.h> /* Processor type for cache alignment. */ |
33 | #include <asm/io.h> | 34 | #include <asm/io.h> |
@@ -271,20 +272,9 @@ enum RFS_bits { | |||
271 | #define MII_RESET_TIME_OUT 10000 | 272 | #define MII_RESET_TIME_OUT 10000 |
272 | /* MII register */ | 273 | /* MII register */ |
273 | enum _mii_reg { | 274 | enum _mii_reg { |
274 | MII_BMCR = 0, | ||
275 | MII_BMSR = 1, | ||
276 | MII_PHY_ID1 = 2, | ||
277 | MII_PHY_ID2 = 3, | ||
278 | MII_ANAR = 4, | ||
279 | MII_ANLPAR = 5, | ||
280 | MII_ANER = 6, | ||
281 | MII_ANNPT = 7, | ||
282 | MII_ANLPRNP = 8, | ||
283 | MII_MSCR = 9, | ||
284 | MII_MSSR = 10, | ||
285 | MII_ESR = 15, | ||
286 | MII_PHY_SCR = 16, | 275 | MII_PHY_SCR = 16, |
287 | }; | 276 | }; |
277 | |||
288 | /* PCS register */ | 278 | /* PCS register */ |
289 | enum _pcs_reg { | 279 | enum _pcs_reg { |
290 | PCS_BMCR = 0, | 280 | PCS_BMCR = 0, |
@@ -297,102 +287,6 @@ enum _pcs_reg { | |||
297 | PCS_ESR = 15, | 287 | PCS_ESR = 15, |
298 | }; | 288 | }; |
299 | 289 | ||
300 | /* Basic Mode Control Register */ | ||
301 | enum _mii_bmcr { | ||
302 | MII_BMCR_RESET = 0x8000, | ||
303 | MII_BMCR_LOOP_BACK = 0x4000, | ||
304 | MII_BMCR_SPEED_LSB = 0x2000, | ||
305 | MII_BMCR_AN_ENABLE = 0x1000, | ||
306 | MII_BMCR_POWER_DOWN = 0x0800, | ||
307 | MII_BMCR_ISOLATE = 0x0400, | ||
308 | MII_BMCR_RESTART_AN = 0x0200, | ||
309 | MII_BMCR_DUPLEX_MODE = 0x0100, | ||
310 | MII_BMCR_COL_TEST = 0x0080, | ||
311 | MII_BMCR_SPEED_MSB = 0x0040, | ||
312 | MII_BMCR_SPEED_RESERVED = 0x003f, | ||
313 | MII_BMCR_SPEED_10 = 0, | ||
314 | MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB, | ||
315 | MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB, | ||
316 | }; | ||
317 | |||
318 | /* Basic Mode Status Register */ | ||
319 | enum _mii_bmsr { | ||
320 | MII_BMSR_100BT4 = 0x8000, | ||
321 | MII_BMSR_100BX_FD = 0x4000, | ||
322 | MII_BMSR_100BX_HD = 0x2000, | ||
323 | MII_BMSR_10BT_FD = 0x1000, | ||
324 | MII_BMSR_10BT_HD = 0x0800, | ||
325 | MII_BMSR_100BT2_FD = 0x0400, | ||
326 | MII_BMSR_100BT2_HD = 0x0200, | ||
327 | MII_BMSR_EXT_STATUS = 0x0100, | ||
328 | MII_BMSR_PREAMBLE_SUPP = 0x0040, | ||
329 | MII_BMSR_AN_COMPLETE = 0x0020, | ||
330 | MII_BMSR_REMOTE_FAULT = 0x0010, | ||
331 | MII_BMSR_AN_ABILITY = 0x0008, | ||
332 | MII_BMSR_LINK_STATUS = 0x0004, | ||
333 | MII_BMSR_JABBER_DETECT = 0x0002, | ||
334 | MII_BMSR_EXT_CAP = 0x0001, | ||
335 | }; | ||
336 | |||
337 | /* ANAR */ | ||
338 | enum _mii_anar { | ||
339 | MII_ANAR_NEXT_PAGE = 0x8000, | ||
340 | MII_ANAR_REMOTE_FAULT = 0x4000, | ||
341 | MII_ANAR_ASYMMETRIC = 0x0800, | ||
342 | MII_ANAR_PAUSE = 0x0400, | ||
343 | MII_ANAR_100BT4 = 0x0200, | ||
344 | MII_ANAR_100BX_FD = 0x0100, | ||
345 | MII_ANAR_100BX_HD = 0x0080, | ||
346 | MII_ANAR_10BT_FD = 0x0020, | ||
347 | MII_ANAR_10BT_HD = 0x0010, | ||
348 | MII_ANAR_SELECTOR = 0x001f, | ||
349 | MII_IEEE8023_CSMACD = 0x0001, | ||
350 | }; | ||
351 | |||
352 | /* ANLPAR */ | ||
353 | enum _mii_anlpar { | ||
354 | MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE, | ||
355 | MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT, | ||
356 | MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC, | ||
357 | MII_ANLPAR_PAUSE = MII_ANAR_PAUSE, | ||
358 | MII_ANLPAR_100BT4 = MII_ANAR_100BT4, | ||
359 | MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD, | ||
360 | MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD, | ||
361 | MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD, | ||
362 | MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD, | ||
363 | MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR, | ||
364 | }; | ||
365 | |||
366 | /* Auto-Negotiation Expansion Register */ | ||
367 | enum _mii_aner { | ||
368 | MII_ANER_PAR_DETECT_FAULT = 0x0010, | ||
369 | MII_ANER_LP_NEXTPAGABLE = 0x0008, | ||
370 | MII_ANER_NETXTPAGABLE = 0x0004, | ||
371 | MII_ANER_PAGE_RECEIVED = 0x0002, | ||
372 | MII_ANER_LP_NEGOTIABLE = 0x0001, | ||
373 | }; | ||
374 | |||
375 | /* MASTER-SLAVE Control Register */ | ||
376 | enum _mii_mscr { | ||
377 | MII_MSCR_TEST_MODE = 0xe000, | ||
378 | MII_MSCR_CFG_ENABLE = 0x1000, | ||
379 | MII_MSCR_CFG_VALUE = 0x0800, | ||
380 | MII_MSCR_PORT_VALUE = 0x0400, | ||
381 | MII_MSCR_1000BT_FD = 0x0200, | ||
382 | MII_MSCR_1000BT_HD = 0X0100, | ||
383 | }; | ||
384 | |||
385 | /* MASTER-SLAVE Status Register */ | ||
386 | enum _mii_mssr { | ||
387 | MII_MSSR_CFG_FAULT = 0x8000, | ||
388 | MII_MSSR_CFG_RES = 0x4000, | ||
389 | MII_MSSR_LOCAL_RCV_STATUS = 0x2000, | ||
390 | MII_MSSR_REMOTE_RCVR = 0x1000, | ||
391 | MII_MSSR_LP_1000BT_FD = 0x0800, | ||
392 | MII_MSSR_LP_1000BT_HD = 0x0400, | ||
393 | MII_MSSR_IDLE_ERR_COUNT = 0x00ff, | ||
394 | }; | ||
395 | |||
396 | /* IEEE Extened Status Register */ | 290 | /* IEEE Extened Status Register */ |
397 | enum _mii_esr { | 291 | enum _mii_esr { |
398 | MII_ESR_1000BX_FD = 0x8000, | 292 | MII_ESR_1000BX_FD = 0x8000, |