aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOlof Johansson <olof@lixom.net>2012-09-20 19:44:06 -0400
committerOlof Johansson <olof@lixom.net>2012-09-20 19:44:06 -0400
commit78901d05e727a0eb28209e9210a92078af3117f2 (patch)
treed0c0281dd068028473af057a6799334760294bb1
parent827cbe71886bc82125212630a52c5fe94b284330 (diff)
parent1128658a0841dbfdc95dc2e3e8d573e4eb1f6a40 (diff)
Merge branch 'next/dt-gscaler' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim: Here is G-Scaler DT for supporting EXYNOS5 SoCs. * 'next/dt-gscaler' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: Adds G-Scaler device from Device Tree ARM: EXYNOS: Add clock support for G-Scaler
-rw-r--r--Documentation/devicetree/bindings/media/exynos5-gsc.txt30
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi28
-rw-r--r--arch/arm/mach-exynos/clock-exynos5.c86
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h5
-rw-r--r--arch/arm/mach-exynos/mach-exynos5-dt.c8
5 files changed, 157 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/media/exynos5-gsc.txt b/Documentation/devicetree/bindings/media/exynos5-gsc.txt
new file mode 100644
index 000000000000..0604d42f38d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/exynos5-gsc.txt
@@ -0,0 +1,30 @@
1* Samsung Exynos5 G-Scaler device
2
3G-Scaler is used for scaling and color space conversion on EXYNOS5 SoCs.
4
5Required properties:
6- compatible: should be "samsung,exynos5-gsc"
7- reg: should contain G-Scaler physical address location and length.
8- interrupts: should contain G-Scaler interrupt number
9
10Example:
11
12gsc_0: gsc@0x13e00000 {
13 compatible = "samsung,exynos5-gsc";
14 reg = <0x13e00000 0x1000>;
15 interrupts = <0 85 0>;
16};
17
18Aliases:
19Each G-Scaler node should have a numbered alias in the aliases node,
20in the form of gscN, N = 0...3. G-Scaler driver uses these aliases
21to retrieve the device IDs using "of_alias_get_id()" call.
22
23Example:
24
25aliases {
26 gsc0 =&gsc_0;
27 gsc1 =&gsc_1;
28 gsc2 =&gsc_2;
29 gsc3 =&gsc_3;
30};
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 004aaa8d123c..b55794b494b4 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -27,6 +27,10 @@
27 spi0 = &spi_0; 27 spi0 = &spi_0;
28 spi1 = &spi_1; 28 spi1 = &spi_1;
29 spi2 = &spi_2; 29 spi2 = &spi_2;
30 gsc0 = &gsc_0;
31 gsc1 = &gsc_1;
32 gsc2 = &gsc_2;
33 gsc3 = &gsc_3;
30 }; 34 };
31 35
32 gic:interrupt-controller@10481000 { 36 gic:interrupt-controller@10481000 {
@@ -460,4 +464,28 @@
460 #gpio-cells = <4>; 464 #gpio-cells = <4>;
461 }; 465 };
462 }; 466 };
467
468 gsc_0: gsc@0x13e00000 {
469 compatible = "samsung,exynos5-gsc";
470 reg = <0x13e00000 0x1000>;
471 interrupts = <0 85 0>;
472 };
473
474 gsc_1: gsc@0x13e10000 {
475 compatible = "samsung,exynos5-gsc";
476 reg = <0x13e10000 0x1000>;
477 interrupts = <0 86 0>;
478 };
479
480 gsc_2: gsc@0x13e20000 {
481 compatible = "samsung,exynos5-gsc";
482 reg = <0x13e20000 0x1000>;
483 interrupts = <0 87 0>;
484 };
485
486 gsc_3: gsc@0x13e30000 {
487 compatible = "samsung,exynos5-gsc";
488 reg = <0x13e30000 0x1000>;
489 interrupts = <0 88 0>;
490 };
463}; 491};
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c67066..1f819ffebbf1 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -552,6 +552,68 @@ static struct clksrc_clk exynos5_clk_aclk_66 = {
552 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 }, 552 .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
553}; 553};
554 554
555static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
556 .clk = {
557 .name = "mout_aclk_300_gscl_mid",
558 },
559 .sources = &exynos5_clkset_aclk,
560 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
561};
562
563static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
564 [0] = &exynos5_clk_sclk_vpll.clk,
565 [1] = &exynos5_clk_mout_cpll.clk,
566};
567
568static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
569 .sources = exynos5_clkset_aclk_300_mid1_list,
570 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
571};
572
573static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
574 .clk = {
575 .name = "mout_aclk_300_gscl_mid1",
576 },
577 .sources = &exynos5_clkset_aclk_300_gscl_mid1,
578 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
579};
580
581static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
582 [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
583 [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
584};
585
586static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
587 .sources = exynos5_clkset_aclk_300_gscl_list,
588 .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
589};
590
591static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
592 .clk = {
593 .name = "mout_aclk_300_gscl",
594 },
595 .sources = &exynos5_clkset_aclk_300_gscl,
596 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
597};
598
599static struct clk *exynos5_clk_src_gscl_300_list[] = {
600 [0] = &clk_ext_xtal_mux,
601 [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
602};
603
604static struct clksrc_sources exynos5_clk_src_gscl_300 = {
605 .sources = exynos5_clk_src_gscl_300_list,
606 .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
607};
608
609static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
610 .clk = {
611 .name = "aclk_300_gscl",
612 },
613 .sources = &exynos5_clk_src_gscl_300,
614 .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
615};
616
555static struct clk exynos5_init_clocks_off[] = { 617static struct clk exynos5_init_clocks_off[] = {
556 { 618 {
557 .name = "timers", 619 .name = "timers",
@@ -764,6 +826,26 @@ static struct clk exynos5_init_clocks_off[] = {
764 .enable = exynos5_clk_ip_peric_ctrl, 826 .enable = exynos5_clk_ip_peric_ctrl,
765 .ctrlbit = (1 << 18), 827 .ctrlbit = (1 << 18),
766 }, { 828 }, {
829 .name = "gscl",
830 .devname = "exynos-gsc.0",
831 .enable = exynos5_clk_ip_gscl_ctrl,
832 .ctrlbit = (1 << 0),
833 }, {
834 .name = "gscl",
835 .devname = "exynos-gsc.1",
836 .enable = exynos5_clk_ip_gscl_ctrl,
837 .ctrlbit = (1 << 1),
838 }, {
839 .name = "gscl",
840 .devname = "exynos-gsc.2",
841 .enable = exynos5_clk_ip_gscl_ctrl,
842 .ctrlbit = (1 << 2),
843 }, {
844 .name = "gscl",
845 .devname = "exynos-gsc.3",
846 .enable = exynos5_clk_ip_gscl_ctrl,
847 .ctrlbit = (1 << 3),
848 }, {
767 .name = SYSMMU_CLOCK_NAME, 849 .name = SYSMMU_CLOCK_NAME,
768 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), 850 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
769 .enable = &exynos5_clk_ip_mfc_ctrl, 851 .enable = &exynos5_clk_ip_mfc_ctrl,
@@ -1225,6 +1307,10 @@ static struct clksrc_clk *exynos5_sysclks[] = {
1225 &exynos5_clk_aclk_266, 1307 &exynos5_clk_aclk_266,
1226 &exynos5_clk_aclk_200, 1308 &exynos5_clk_aclk_200,
1227 &exynos5_clk_aclk_166, 1309 &exynos5_clk_aclk_166,
1310 &exynos5_clk_aclk_300_gscl,
1311 &exynos5_clk_mout_aclk_300_gscl,
1312 &exynos5_clk_mout_aclk_300_gscl_mid,
1313 &exynos5_clk_mout_aclk_300_gscl_mid1,
1228 &exynos5_clk_aclk_66_pre, 1314 &exynos5_clk_aclk_66_pre,
1229 &exynos5_clk_aclk_66, 1315 &exynos5_clk_aclk_66,
1230 &exynos5_clk_dout_mmc0, 1316 &exynos5_clk_dout_mmc0,
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675b3e4b..0300d7adc151 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -121,6 +121,11 @@
121#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000 121#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
122#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000 122#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
123 123
124#define EXYNOS5_PA_GSC0 0x13E00000
125#define EXYNOS5_PA_GSC1 0x13E10000
126#define EXYNOS5_PA_GSC2 0x13E20000
127#define EXYNOS5_PA_GSC3 0x13E30000
128
124#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000 129#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
125#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000 130#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
126#define EXYNOS5_PA_SYSMMU_2D 0x10A60000 131#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index ef770bc2318f..e707eb1b1eab 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -56,6 +56,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
56 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), 56 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
57 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), 57 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
58 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), 58 OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
59 OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
60 "exynos-gsc.0", NULL),
61 OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
62 "exynos-gsc.1", NULL),
63 OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
64 "exynos-gsc.2", NULL),
65 OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
66 "exynos-gsc.3", NULL),
59 {}, 67 {},
60}; 68};
61 69