Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc fixes from Ben Herrenschmidt:
 "This includes small series from Michael Neuling to fix a couple of
  nasty remaining problems with the new Power8 support, also targeted at
  stable 3.10, without which some new userspace accessible registers
  aren't properly context switched, and in some case, can be clobbered
  by the user of transactional memory.

  Along with that, a few slightly more minor things, such as a missing
  Kconfig option to enable handling of denorm exceptions when not
  running under a hypervisor (or userspace will randomly crash when
  hitting denorms with the vector unit), some nasty bugs in the new
  pstore oops code, and other simple bug fixes worth having in now.

  Note: I picked up the two powerpc KVM fixes as Alex Graf asked me to
  handle KVM bits while he is on vacation.  However I'll let him decide
  whether they should go to -stable or not when he is back"

* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc:
  powerpc/tm: Fix context switching TAR, PPR and DSCR SPRs
  powerpc: Save the TAR register earlier
  powerpc: Fix context switch DSCR on POWER8
  powerpc: Rework setting up H/FSCR bit definitions
  powerpc: Fix hypervisor facility unavaliable vector number
  powerpc/kvm/book3s_pr: Return appropriate error when allocation fails
  powerpc/kvm: Add signed type cast for comparation
  powerpc/eeh: Add missing procfs entry for PowerNV
  powerpc/pseries: Add backward compatibilty to read old kernel oops-log
  powerpc/pseries: Fix buffer overflow when reading from pstore
  powerpc: On POWERNV enable PPC_DENORMALISATION by default

14 files changed, 170 insertions, 99 deletions

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 3bf72cd2c8fc..dbd9d3c991e8 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -566,7 +566,7 @@ config SCHED_SMT
 config PPC_DENORMALISATION
         bool "PowerPC denormalisation exception handling"
         depends on PPC_BOOK3S_64
-        default "n"
+        default "y" if PPC_POWERNV
         ---help---
           Add support for handling denormalisation of single precision
           values.  Useful for bare metal only.  If unsure say Y here.
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 47a35b08b963..e378cccfca55 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -247,6 +247,10 @@ struct thread_struct {
         unsigned long   tm_orig_msr;    /* Thread's MSR on ctx switch */
         struct pt_regs  ckpt_regs;      /* Checkpointed registers */
 
+        unsigned long   tm_tar;
+        unsigned long   tm_ppr;
+        unsigned long   tm_dscr;
+
         /*
          * Transactional FP and VSX 0-31 register set.
          * NOTE: the sense of these is the opposite of the integer ckpt_regs!
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index a6840e4e24f7..99222e27f173 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -254,19 +254,28 @@
 #define SPRN_HRMOR      0x139   /* Real mode offset register */
 #define SPRN_HSRR0      0x13A   /* Hypervisor Save/Restore 0 */
 #define SPRN_HSRR1      0x13B   /* Hypervisor Save/Restore 1 */
+/* HFSCR and FSCR bit numbers are the same */
+#define FSCR_TAR_LG     8       /* Enable Target Address Register */
+#define FSCR_EBB_LG     7       /* Enable Event Based Branching */
+#define FSCR_TM_LG      5       /* Enable Transactional Memory */
+#define FSCR_PM_LG      4       /* Enable prob/priv access to PMU SPRs */
+#define FSCR_BHRB_LG    3       /* Enable Branch History Rolling Buffer*/
+#define FSCR_DSCR_LG    2       /* Enable Data Stream Control Register */
+#define FSCR_VECVSX_LG  1       /* Enable VMX/VSX  */
+#define FSCR_FP_LG      0       /* Enable Floating Point */
 #define SPRN_FSCR       0x099   /* Facility Status & Control Register */
-#define   FSCR_TAR      (1 << (63-55)) /* Enable Target Address Register */
-#define   FSCR_EBB      (1 << (63-56)) /* Enable Event Based Branching */
-#define   FSCR_DSCR     (1 << (63-61)) /* Enable Data Stream Control Register */
+#define   FSCR_TAR      __MASK(FSCR_TAR_LG)
+#define   FSCR_EBB      __MASK(FSCR_EBB_LG)
+#define   FSCR_DSCR     __MASK(FSCR_DSCR_LG)
 #define SPRN_HFSCR      0xbe    /* HV=1 Facility Status & Control Register */
-#define   HFSCR_TAR     (1 << (63-55)) /* Enable Target Address Register */
-#define   HFSCR_EBB     (1 << (63-56)) /* Enable Event Based Branching */
-#define   HFSCR_TM      (1 << (63-58)) /* Enable Transactional Memory */
-#define   HFSCR_PM      (1 << (63-60)) /* Enable prob/priv access to PMU SPRs */
-#define   HFSCR_BHRB    (1 << (63-59)) /* Enable Branch History Rolling Buffer*/
-#define   HFSCR_DSCR    (1 << (63-61)) /* Enable Data Stream Control Register */
-#define   HFSCR_VECVSX  (1 << (63-62)) /* Enable VMX/VSX  */
-#define   HFSCR_FP      (1 << (63-63)) /* Enable Floating Point */
+#define   HFSCR_TAR     __MASK(FSCR_TAR_LG)
+#define   HFSCR_EBB     __MASK(FSCR_EBB_LG)
+#define   HFSCR_TM      __MASK(FSCR_TM_LG)
+#define   HFSCR_PM      __MASK(FSCR_PM_LG)
+#define   HFSCR_BHRB    __MASK(FSCR_BHRB_LG)
+#define   HFSCR_DSCR    __MASK(FSCR_DSCR_LG)
+#define   HFSCR_VECVSX  __MASK(FSCR_VECVSX_LG)
+#define   HFSCR_FP      __MASK(FSCR_FP_LG)
 #define SPRN_TAR        0x32f   /* Target Address Register */
 #define SPRN_LPCR       0x13E   /* LPAR Control Register */
 #define   LPCR_VPM0     (1ul << (63-0))
diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
index 49a13e0ef234..294c2cedcf7a 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -15,6 +15,15 @@ extern struct task_struct *__switch_to(struct task_struct *,
 struct thread_struct;
 extern struct task_struct *_switch(struct thread_struct *prev,
                                    struct thread_struct *next);
+#ifdef CONFIG_PPC_BOOK3S_64
+static inline void save_tar(struct thread_struct *prev)
+{
+        if (cpu_has_feature(CPU_FTR_ARCH_207S))
+                prev->tar = mfspr(SPRN_TAR);
+}
+#else
+static inline void save_tar(struct thread_struct *prev) {}
+#endif
 
 extern void giveup_fpu(struct task_struct *);
 extern void load_up_fpu(void);
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index c7e8afc2ead0..8207459efe56 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -138,6 +138,9 @@ int main(void)
         DEFINE(THREAD_TM_TFHAR, offsetof(struct thread_struct, tm_tfhar));
         DEFINE(THREAD_TM_TEXASR, offsetof(struct thread_struct, tm_texasr));
         DEFINE(THREAD_TM_TFIAR, offsetof(struct thread_struct, tm_tfiar));
+        DEFINE(THREAD_TM_TAR, offsetof(struct thread_struct, tm_tar));
+        DEFINE(THREAD_TM_PPR, offsetof(struct thread_struct, tm_ppr));
+        DEFINE(THREAD_TM_DSCR, offsetof(struct thread_struct, tm_dscr));
         DEFINE(PT_CKPT_REGS, offsetof(struct thread_struct, ckpt_regs));
         DEFINE(THREAD_TRANSACT_VR0, offsetof(struct thread_struct,
                                          transact_vr[0]));
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index ea9414c8088d..55593ee2d5aa 100644
--- a/arch/powerpc/kernel/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -1061,7 +1061,7 @@ static const struct file_operations proc_eeh_operations = {
 
 static int __init eeh_init_proc(void)
 {
-        if (machine_is(pseries))
+        if (machine_is(pseries) || machine_is(powernv))
                 proc_create("powerpc/eeh", 0, NULL, &proc_eeh_operations);
         return 0;
 }
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index ab15b8d057ad..2bd0b885b0fe 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -449,15 +449,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
 
 #ifdef CONFIG_PPC_BOOK3S_64
 BEGIN_FTR_SECTION
-        /*
-         * Back up the TAR across context switches.  Note that the TAR is not
-         * available for use in the kernel.  (To provide this, the TAR should
-         * be backed up/restored on exception entry/exit instead, and be in
-         * pt_regs.  FIXME, this should be in pt_regs anyway (for debug).)
-         */
-        mfspr   r0,SPRN_TAR
-        std     r0,THREAD_TAR(r3)
-
         /* Event based branch registers */
         mfspr   r0, SPRN_BESCR
         std     r0, THREAD_BESCR(r3)
@@ -584,9 +575,34 @@ BEGIN_FTR_SECTION
         ld      r7,DSCR_DEFAULT@toc(2)
         ld      r0,THREAD_DSCR(r4)
         cmpwi   r6,0
+        li      r8, FSCR_DSCR
         bne     1f
         ld      r0,0(r7)