drm/i915/skl: Implement WaEnableLbsSlaRetryTimerDecrement

This W/A is put in a gen9 specific function because it may well be
needed on other gen9 platforms.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 14 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b522d3f529d..1dc91de7d2e6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5285,6 +5285,9 @@ enum skl_disp_power_wells {
 #define HSW_SCRATCH1                            0xb038
 #define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE   (1<<27)
 
+#define BDW_SCRATCH1                                    0xb11c
+#define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE      (1<<2)
+
 /* PCH */
 
 /* south display engine interrupt: IBX */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 325f640c16c4..f68d12cb0246 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -52,10 +52,21 @@
 #define INTEL_RC6p_ENABLE                       (1<<1)
 #define INTEL_RC6pp_ENABLE                      (1<<2)
 
+static void gen9_init_clock_gating(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        /* WaEnableLbsSlaRetryTimerDecrement:skl */
+        I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
+                   GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+}
+
 static void skl_init_clock_gating(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
 
+        gen9_init_clock_gating(dev);
+
         if (INTEL_REVID(dev) == SKL_REVID_A0) {
                 /*
                  * WaDisableSDEUnitClockGating:skl