Octeon: Fix interrupt irq settings for performance counters.

Octeon uses different interrupt irq for timer and performance counters.
Set CvmCtl[IPPCI] to correct irq value very early.

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Cc: Chandrakala Chavva <cchavva@caviumnetworks.com>
Patchwork: https://patchwork.linux-mips.org/patch/2085/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 5 insertions, 7 deletions

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 0707fae3f0ee..2d9028f1474c 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -288,7 +288,6 @@ void octeon_user_io_init(void)
         union octeon_cvmemctl cvmmemctl;
         union cvmx_iob_fau_timeout fau_timeout;
         union cvmx_pow_nw_tim nm_tim;
-        uint64_t cvmctl;
 
         /* Get the current settings for CP0_CVMMEMCTL_REG */
         cvmmemctl.u64 = read_c0_cvmmemctl();
@@ -392,12 +391,6 @@ void octeon_user_io_init(void)
                           CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
                           CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
 
-        /* Move the performance counter interrupts to IRQ 6 */
-        cvmctl = read_c0_cvmctl();
-        cvmctl &= ~(7 << 7);
-        cvmctl |= 6 << 7;
-        write_c0_cvmctl(cvmctl);
-
         /* Set a default for the hardware timeouts */
         fau_timeout.u64 = 0;
         fau_timeout.s.tout_val = 0xfff;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index 0b2b5eb22e9b..dedef7d2b01f 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -63,6 +63,11 @@
         # CN30XX Disable instruction prefetching
         or  v0, v0, 0x2000
 skip:
+        # First clear off CvmCtl[IPPCI] bit and move the performance
+        # counters interrupt to IRQ 6
+        li      v1, ~(7 << 7)
+        and     v0, v0, v1
+        ori     v0, v0, (6 << 7)
         # Write the cavium control register
         dmtc0   v0, CP0_CVMCTL_REG
         sync