diff options
author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2013-12-24 08:38:26 -0500 |
---|---|---|
committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2014-03-19 03:31:27 -0400 |
commit | 75af25f581b1ffc63e06cb01547b3141d4cd5f58 (patch) | |
tree | 12add3b2c60c2ff96f2378ef8860bae9f6a8f23f | |
parent | d3e6573c48f4472147b37e92cb345271e04d34d9 (diff) |
clk: hisi: remove static variable
Remove the static variable. So these common clock register helper could
be used in more SoCs.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
-rw-r--r-- | drivers/clk/hisilicon/clk-hi3620.c | 25 | ||||
-rw-r--r-- | drivers/clk/hisilicon/clk-hip04.c | 8 | ||||
-rw-r--r-- | drivers/clk/hisilicon/clk.c | 64 | ||||
-rw-r--r-- | drivers/clk/hisilicon/clk.h | 17 |
4 files changed, 72 insertions, 42 deletions
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index f24ad6a3a797..cc6dff19d6e4 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c | |||
@@ -210,33 +210,24 @@ static struct hisi_gate_clock hi3620_seperated_gate_clks[] __initdata = { | |||
210 | 210 | ||
211 | static void __init hi3620_clk_init(struct device_node *np) | 211 | static void __init hi3620_clk_init(struct device_node *np) |
212 | { | 212 | { |
213 | void __iomem *base; | 213 | struct hisi_clock_data *clk_data; |
214 | 214 | ||
215 | if (np) { | 215 | clk_data = hisi_clk_init(np, HI3620_NR_CLKS); |
216 | base = of_iomap(np, 0); | 216 | if (!clk_data) |
217 | if (!base) { | ||
218 | pr_err("failed to map Hi3620 clock registers\n"); | ||
219 | return; | ||
220 | } | ||
221 | } else { | ||
222 | pr_err("failed to find Hi3620 clock node in DTS\n"); | ||
223 | return; | 217 | return; |
224 | } | ||
225 | |||
226 | hisi_clk_init(np, HI3620_NR_CLKS); | ||
227 | 218 | ||
228 | hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks, | 219 | hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks, |
229 | ARRAY_SIZE(hi3620_fixed_rate_clks), | 220 | ARRAY_SIZE(hi3620_fixed_rate_clks), |
230 | base); | 221 | clk_data); |
231 | hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks, | 222 | hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks, |
232 | ARRAY_SIZE(hi3620_fixed_factor_clks), | 223 | ARRAY_SIZE(hi3620_fixed_factor_clks), |
233 | base); | 224 | clk_data); |
234 | hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks), | 225 | hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks), |
235 | base); | 226 | clk_data); |
236 | hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks), | 227 | hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks), |
237 | base); | 228 | clk_data); |
238 | hisi_clk_register_gate_sep(hi3620_seperated_gate_clks, | 229 | hisi_clk_register_gate_sep(hi3620_seperated_gate_clks, |
239 | ARRAY_SIZE(hi3620_seperated_gate_clks), | 230 | ARRAY_SIZE(hi3620_seperated_gate_clks), |
240 | base); | 231 | clk_data); |
241 | } | 232 | } |
242 | CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init); | 233 | CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init); |
diff --git a/drivers/clk/hisilicon/clk-hip04.c b/drivers/clk/hisilicon/clk-hip04.c index bdc6cd05f4ca..132b57a0ce09 100644 --- a/drivers/clk/hisilicon/clk-hip04.c +++ b/drivers/clk/hisilicon/clk-hip04.c | |||
@@ -45,10 +45,14 @@ static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = { | |||
45 | 45 | ||
46 | static void __init hip04_clk_init(struct device_node *np) | 46 | static void __init hip04_clk_init(struct device_node *np) |
47 | { | 47 | { |
48 | hisi_clk_init(np, HIP04_NR_CLKS); | 48 | struct hisi_clock_data *clk_data; |
49 | |||
50 | clk_data = hisi_clk_init(np, HIP04_NR_CLKS); | ||
51 | if (!clk_data) | ||
52 | return; | ||
49 | 53 | ||
50 | hisi_clk_register_fixed_rate(hip04_fixed_rate_clks, | 54 | hisi_clk_register_fixed_rate(hip04_fixed_rate_clks, |
51 | ARRAY_SIZE(hip04_fixed_rate_clks), | 55 | ARRAY_SIZE(hip04_fixed_rate_clks), |
52 | NULL); | 56 | clk_data); |
53 | } | 57 | } |
54 | CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init); | 58 | CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init); |
diff --git a/drivers/clk/hisilicon/clk.c b/drivers/clk/hisilicon/clk.c index 18fc21f0ea15..276f672e7b1a 100644 --- a/drivers/clk/hisilicon/clk.c +++ b/drivers/clk/hisilicon/clk.c | |||
@@ -37,23 +37,49 @@ | |||
37 | #include "clk.h" | 37 | #include "clk.h" |
38 | 38 | ||
39 | static DEFINE_SPINLOCK(hisi_clk_lock); | 39 | static DEFINE_SPINLOCK(hisi_clk_lock); |
40 | static struct clk **clk_table; | ||
41 | static struct clk_onecell_data clk_data; | ||
42 | 40 | ||
43 | void __init hisi_clk_init(struct device_node *np, int nr_clks) | 41 | struct hisi_clock_data __init *hisi_clk_init(struct device_node *np, |
42 | int nr_clks) | ||
44 | { | 43 | { |
44 | struct hisi_clock_data *clk_data; | ||
45 | struct clk **clk_table; | ||
46 | void __iomem *base; | ||
47 | |||
48 | if (np) { | ||
49 | base = of_iomap(np, 0); | ||
50 | if (!base) { | ||
51 | pr_err("failed to map Hisilicon clock registers\n"); | ||
52 | goto err; | ||
53 | } | ||
54 | } else { | ||
55 | pr_err("failed to find Hisilicon clock node in DTS\n"); | ||
56 | goto err; | ||
57 | } | ||
58 | |||
59 | clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); | ||
60 | if (!clk_data) { | ||
61 | pr_err("%s: could not allocate clock data\n", __func__); | ||
62 | goto err; | ||
63 | } | ||
64 | clk_data->base = base; | ||
65 | |||
45 | clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); | 66 | clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); |
46 | if (!clk_table) { | 67 | if (!clk_table) { |
47 | pr_err("%s: could not allocate clock lookup table\n", __func__); | 68 | pr_err("%s: could not allocate clock lookup table\n", __func__); |
48 | return; | 69 | goto err_data; |
49 | } | 70 | } |
50 | clk_data.clks = clk_table; | 71 | clk_data->clk_data.clks = clk_table; |
51 | clk_data.clk_num = nr_clks; | 72 | clk_data->clk_data.clk_num = nr_clks; |
52 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); | 73 | of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); |
74 | return clk_data; | ||
75 | err_data: | ||
76 | kfree(clk_data); | ||
77 | err: | ||
78 | return NULL; | ||
53 | } | 79 | } |
54 | 80 | ||
55 | void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, | 81 | void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, |
56 | int nums, void __iomem *base) | 82 | int nums, struct hisi_clock_data *data) |
57 | { | 83 | { |
58 | struct clk *clk; | 84 | struct clk *clk; |
59 | int i; | 85 | int i; |
@@ -68,12 +94,13 @@ void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks, | |||
68 | __func__, clks[i].name); | 94 | __func__, clks[i].name); |
69 | continue; | 95 | continue; |
70 | } | 96 | } |
71 | clk_table[clks[i].id] = clk; | 97 | data->clk_data.clks[clks[i].id] = clk; |
72 | } | 98 | } |
73 | } | 99 | } |
74 | 100 | ||
75 | void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, | 101 | void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, |
76 | int nums, void __iomem *base) | 102 | int nums, |
103 | struct hisi_clock_data *data) | ||
77 | { | 104 | { |
78 | struct clk *clk; | 105 | struct clk *clk; |
79 | int i; | 106 | int i; |
@@ -88,14 +115,15 @@ void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks, | |||
88 | __func__, clks[i].name); | 115 | __func__, clks[i].name); |
89 | continue; | 116 | continue; |
90 | } | 117 | } |
91 | clk_table[clks[i].id] = clk; | 118 | data->clk_data.clks[clks[i].id] = clk; |
92 | } | 119 | } |
93 | } | 120 | } |
94 | 121 | ||
95 | void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, | 122 | void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, |
96 | int nums, void __iomem *base) | 123 | int nums, struct hisi_clock_data *data) |
97 | { | 124 | { |
98 | struct clk *clk; | 125 | struct clk *clk; |
126 | void __iomem *base = data->base; | ||
99 | int i; | 127 | int i; |
100 | 128 | ||
101 | for (i = 0; i < nums; i++) { | 129 | for (i = 0; i < nums; i++) { |
@@ -113,14 +141,15 @@ void __init hisi_clk_register_mux(struct hisi_mux_clock *clks, | |||
113 | if (clks[i].alias) | 141 | if (clks[i].alias) |
114 | clk_register_clkdev(clk, clks[i].alias, NULL); | 142 | clk_register_clkdev(clk, clks[i].alias, NULL); |
115 | 143 | ||
116 | clk_table[clks[i].id] = clk; | 144 | data->clk_data.clks[clks[i].id] = clk; |
117 | } | 145 | } |
118 | } | 146 | } |
119 | 147 | ||
120 | void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, | 148 | void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, |
121 | int nums, void __iomem *base) | 149 | int nums, struct hisi_clock_data *data) |
122 | { | 150 | { |
123 | struct clk *clk; | 151 | struct clk *clk; |
152 | void __iomem *base = data->base; | ||
124 | int i; | 153 | int i; |
125 | 154 | ||
126 | for (i = 0; i < nums; i++) { | 155 | for (i = 0; i < nums; i++) { |
@@ -141,14 +170,15 @@ void __init hisi_clk_register_divider(struct hisi_divider_clock *clks, | |||
141 | if (clks[i].alias) | 170 | if (clks[i].alias) |
142 | clk_register_clkdev(clk, clks[i].alias, NULL); | 171 | clk_register_clkdev(clk, clks[i].alias, NULL); |
143 | 172 | ||
144 | clk_table[clks[i].id] = clk; | 173 | data->clk_data.clks[clks[i].id] = clk; |
145 | } | 174 | } |
146 | } | 175 | } |
147 | 176 | ||
148 | void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, | 177 | void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, |
149 | int nums, void __iomem *base) | 178 | int nums, struct hisi_clock_data *data) |
150 | { | 179 | { |
151 | struct clk *clk; | 180 | struct clk *clk; |
181 | void __iomem *base = data->base; | ||
152 | int i; | 182 | int i; |
153 | 183 | ||
154 | for (i = 0; i < nums; i++) { | 184 | for (i = 0; i < nums; i++) { |
@@ -168,6 +198,6 @@ void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks, | |||
168 | if (clks[i].alias) | 198 | if (clks[i].alias) |
169 | clk_register_clkdev(clk, clks[i].alias, NULL); | 199 | clk_register_clkdev(clk, clks[i].alias, NULL); |
170 | 200 | ||
171 | clk_table[clks[i].id] = clk; | 201 | data->clk_data.clks[clks[i].id] = clk; |
172 | } | 202 | } |
173 | } | 203 | } |
diff --git a/drivers/clk/hisilicon/clk.h b/drivers/clk/hisilicon/clk.h index 4a6beebefb7a..43fa5da88f02 100644 --- a/drivers/clk/hisilicon/clk.h +++ b/drivers/clk/hisilicon/clk.h | |||
@@ -30,6 +30,11 @@ | |||
30 | #include <linux/io.h> | 30 | #include <linux/io.h> |
31 | #include <linux/spinlock.h> | 31 | #include <linux/spinlock.h> |
32 | 32 | ||
33 | struct hisi_clock_data { | ||
34 | struct clk_onecell_data clk_data; | ||
35 | void __iomem *base; | ||
36 | }; | ||
37 | |||
33 | struct hisi_fixed_rate_clock { | 38 | struct hisi_fixed_rate_clock { |
34 | unsigned int id; | 39 | unsigned int id; |
35 | char *name; | 40 | char *name; |
@@ -89,15 +94,15 @@ struct clk *hisi_register_clkgate_sep(struct device *, const char *, | |||
89 | void __iomem *, u8, | 94 | void __iomem *, u8, |
90 | u8, spinlock_t *); | 95 | u8, spinlock_t *); |
91 | 96 | ||
92 | void __init hisi_clk_init(struct device_node *, int); | 97 | struct hisi_clock_data __init *hisi_clk_init(struct device_node *, int); |
93 | void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, | 98 | void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *, |
94 | int, void __iomem *); | 99 | int, struct hisi_clock_data *); |
95 | void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, | 100 | void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *, |
96 | int, void __iomem *); | 101 | int, struct hisi_clock_data *); |
97 | void __init hisi_clk_register_mux(struct hisi_mux_clock *, int, | 102 | void __init hisi_clk_register_mux(struct hisi_mux_clock *, int, |
98 | void __iomem *); | 103 | struct hisi_clock_data *); |
99 | void __init hisi_clk_register_divider(struct hisi_divider_clock *, | 104 | void __init hisi_clk_register_divider(struct hisi_divider_clock *, |
100 | int, void __iomem *); | 105 | int, struct hisi_clock_data *); |
101 | void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, | 106 | void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *, |
102 | int, void __iomem *); | 107 | int, struct hisi_clock_data *); |
103 | #endif /* __HISI_CLK_H */ | 108 | #endif /* __HISI_CLK_H */ |