diff options
author | Alexander Shiyan <shc_work@mail.ru> | 2014-02-22 04:32:35 -0500 |
---|---|---|
committer | Shawn Guo <shawn.guo@linaro.org> | 2014-02-23 22:05:09 -0500 |
commit | 74ded659a7ac4b5c74c344583f3f55b93a49fa16 (patch) | |
tree | df23f34eee315615a10d0cae93b69564d3e28156 | |
parent | 9089ce520f6fdcb3c921a12d24834197251bd56f (diff) |
ARM: dts: imx27-phytec-phycore-som: Add USBOTG node
This patch adds USBOTG devicetree node of Phytec PCM038 module.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r-- | arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi index 05b0ecd348e0..cefaa6994623 100644 --- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | |||
@@ -250,6 +250,23 @@ | |||
250 | MX27_PAD_NFWE_B__NFWE_B 0x0 | 250 | MX27_PAD_NFWE_B__NFWE_B 0x0 |
251 | >; | 251 | >; |
252 | }; | 252 | }; |
253 | |||
254 | pinctrl_usbotg: usbotggrp { | ||
255 | fsl,pins = < | ||
256 | MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0 | ||
257 | MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0 | ||
258 | MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0 | ||
259 | MX27_PAD_USBOTG_STP__USBOTG_STP 0x0 | ||
260 | MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0 | ||
261 | MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0 | ||
262 | MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0 | ||
263 | MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0 | ||
264 | MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0 | ||
265 | MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0 | ||
266 | MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0 | ||
267 | MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0 | ||
268 | >; | ||
269 | }; | ||
253 | }; | 270 | }; |
254 | }; | 271 | }; |
255 | 272 | ||
@@ -262,6 +279,19 @@ | |||
262 | status = "okay"; | 279 | status = "okay"; |
263 | }; | 280 | }; |
264 | 281 | ||
282 | &usbotg { | ||
283 | pinctrl-names = "default"; | ||
284 | pinctrl-0 = <&pinctrl_usbotg>; | ||
285 | dr_mode = "otg"; | ||
286 | phy_type = "ulpi"; | ||
287 | vbus-supply = <&sw3_reg>; | ||
288 | status = "okay"; | ||
289 | }; | ||
290 | |||
291 | &usbphy0 { | ||
292 | vcc-supply = <&sw3_reg>; | ||
293 | }; | ||
294 | |||
265 | &weim { | 295 | &weim { |
266 | status = "okay"; | 296 | status = "okay"; |
267 | 297 | ||