diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-03-24 13:26:36 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-04-08 20:15:35 -0400 |
| commit | 747943ea187e5acceb7ffc762ff2c84cb3449745 (patch) | |
| tree | 9db964f6ff1883b7b1e902cde1073494956b0ff1 | |
| parent | 0fcdb61e78050f8f0b31029eeafa5ae013ce0f35 (diff) | |
drm/radeon/kms/evergreen: add soft reset function
Works pretty similarly to r6xx/r7xx.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 73 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreend.h | 63 |
2 files changed, 132 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index afcff06ef291..a6130a494c56 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
| @@ -511,12 +511,81 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev) | |||
| 511 | return false; | 511 | return false; |
| 512 | } | 512 | } |
| 513 | 513 | ||
| 514 | int evergreen_asic_reset(struct radeon_device *rdev) | 514 | static int evergreen_gpu_soft_reset(struct radeon_device *rdev) |
| 515 | { | 515 | { |
| 516 | /* FIXME: implement for evergreen */ | 516 | struct evergreen_mc_save save; |
| 517 | u32 srbm_reset = 0; | ||
| 518 | u32 grbm_reset = 0; | ||
| 519 | |||
| 520 | dev_info(rdev->dev, "GPU softreset \n"); | ||
| 521 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", | ||
| 522 | RREG32(GRBM_STATUS)); | ||
| 523 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", | ||
| 524 | RREG32(GRBM_STATUS_SE0)); | ||
| 525 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", | ||
| 526 | RREG32(GRBM_STATUS_SE1)); | ||
| 527 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", | ||
| 528 | RREG32(SRBM_STATUS)); | ||
| 529 | evergreen_mc_stop(rdev, &save); | ||
| 530 | if (evergreen_mc_wait_for_idle(rdev)) { | ||
| 531 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); | ||
| 532 | } | ||
| 533 | /* Disable CP parsing/prefetching */ | ||
| 534 | WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); | ||
| 535 | |||
| 536 | /* reset all the gfx blocks */ | ||
| 537 | grbm_reset = (SOFT_RESET_CP | | ||
| 538 | SOFT_RESET_CB | | ||
| 539 | SOFT_RESET_DB | | ||
| 540 | SOFT_RESET_PA | | ||
| 541 | SOFT_RESET_SC | | ||
| 542 | SOFT_RESET_SPI | | ||
| 543 | SOFT_RESET_SH | | ||
| 544 | SOFT_RESET_SX | | ||
| 545 | SOFT_RESET_TC | | ||
| 546 | SOFT_RESET_TA | | ||
| 547 | SOFT_RESET_VC | | ||
| 548 | SOFT_RESET_VGT); | ||
| 549 | |||
| 550 | dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset); | ||
| 551 | WREG32(GRBM_SOFT_RESET, grbm_reset); | ||
| 552 | (void)RREG32(GRBM_SOFT_RESET); | ||
| 553 | udelay(50); | ||
| 554 | WREG32(GRBM_SOFT_RESET, 0); | ||
| 555 | (void)RREG32(GRBM_SOFT_RESET); | ||
| 556 | |||
| 557 | /* reset all the system blocks */ | ||
| 558 | srbm_reset = SRBM_SOFT_RESET_ALL_MASK; | ||
| 559 | |||
| 560 | dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset); | ||
| 561 | WREG32(SRBM_SOFT_RESET, srbm_reset); | ||
| 562 | (void)RREG32(SRBM_SOFT_RESET); | ||
| 563 | udelay(50); | ||
| 564 | WREG32(SRBM_SOFT_RESET, 0); | ||
| 565 | (void)RREG32(SRBM_SOFT_RESET); | ||
| 566 | /* Wait a little for things to settle down */ | ||
| 567 | udelay(50); | ||
| 568 | dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", | ||
| 569 | RREG32(GRBM_STATUS)); | ||
| 570 | dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", | ||
| 571 | RREG32(GRBM_STATUS_SE0)); | ||
| 572 | dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n", | ||
| 573 | RREG32(GRBM_STATUS_SE1)); | ||
| 574 | dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", | ||
| 575 | RREG32(SRBM_STATUS)); | ||
| 576 | /* After reset we need to reinit the asic as GPU often endup in an | ||
| 577 | * incoherent state. | ||
| 578 | */ | ||
| 579 | atom_asic_init(rdev->mode_info.atom_context); | ||
| 580 | evergreen_mc_resume(rdev, &save); | ||
| 517 | return 0; | 581 | return 0; |
| 518 | } | 582 | } |
| 519 | 583 | ||
| 584 | int evergreen_asic_reset(struct radeon_device *rdev) | ||
| 585 | { | ||
| 586 | return evergreen_gpu_soft_reset(rdev); | ||
| 587 | } | ||
| 588 | |||
| 520 | static int evergreen_startup(struct radeon_device *rdev) | 589 | static int evergreen_startup(struct radeon_device *rdev) |
| 521 | { | 590 | { |
| 522 | int r; | 591 | int r; |
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 5cf707a54562..7c290a6dd0e3 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h | |||
| @@ -78,10 +78,53 @@ | |||
| 78 | #define GRBM_CNTL 0x8000 | 78 | #define GRBM_CNTL 0x8000 |
| 79 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | 79 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) |
| 80 | #define GRBM_SOFT_RESET 0x8020 | 80 | #define GRBM_SOFT_RESET 0x8020 |
| 81 | #define SOFT_RESET_CP (1<<0) | 81 | #define SOFT_RESET_CP (1 << 0) |
| 82 | #define SOFT_RESET_CB (1 << 1) | ||
| 83 | #define SOFT_RESET_DB (1 << 3) | ||
| 84 | #define SOFT_RESET_PA (1 << 5) | ||
| 85 | #define SOFT_RESET_SC (1 << 6) | ||
| 86 | #define SOFT_RESET_SPI (1 << 8) | ||
| 87 | #define SOFT_RESET_SH (1 << 9) | ||
| 88 | #define SOFT_RESET_SX (1 << 10) | ||
| 89 | #define SOFT_RESET_TC (1 << 11) | ||
| 90 | #define SOFT_RESET_TA (1 << 12) | ||
| 91 | #define SOFT_RESET_VC (1 << 13) | ||
| 92 | #define SOFT_RESET_VGT (1 << 14) | ||
| 93 | |||
| 82 | #define GRBM_STATUS 0x8010 | 94 | #define GRBM_STATUS 0x8010 |
| 83 | #define CMDFIFO_AVAIL_MASK 0x0000000F | 95 | #define CMDFIFO_AVAIL_MASK 0x0000000F |
| 84 | #define GUI_ACTIVE (1<<31) | 96 | #define SRBM_RQ_PENDING (1 << 5) |
| 97 | #define CF_RQ_PENDING (1 << 7) | ||
| 98 | #define PF_RQ_PENDING (1 << 8) | ||
| 99 | #define GRBM_EE_BUSY (1 << 10) | ||
| 100 | #define SX_CLEAN (1 << 11) | ||
| 101 | #define DB_CLEAN (1 << 12) | ||
| 102 | #define CB_CLEAN (1 << 13) | ||
| 103 | #define TA_BUSY (1 << 14) | ||
| 104 | #define VGT_BUSY_NO_DMA (1 << 16) | ||
| 105 | #define VGT_BUSY (1 << 17) | ||
| 106 | #define SX_BUSY (1 << 20) | ||
| 107 | #define SH_BUSY (1 << 21) | ||
| 108 | #define SPI_BUSY (1 << 22) | ||
| 109 | #define SC_BUSY (1 << 24) | ||
| 110 | #define PA_BUSY (1 << 25) | ||
| 111 | #define DB_BUSY (1 << 26) | ||
| 112 | #define CP_COHERENCY_BUSY (1 << 28) | ||
| 113 | #define CP_BUSY (1 << 29) | ||
| 114 | #define CB_BUSY (1 << 30) | ||
| 115 | #define GUI_ACTIVE (1 << 31) | ||
| 116 | #define GRBM_STATUS_SE0 0x8014 | ||
| 117 | #define GRBM_STATUS_SE1 0x8018 | ||
| 118 | #define SE_SX_CLEAN (1 << 0) | ||
| 119 | #define SE_DB_CLEAN (1 << 1) | ||
| 120 | #define SE_CB_CLEAN (1 << 2) | ||
| 121 | #define SE_TA_BUSY (1 << 25) | ||
| 122 | #define SE_SX_BUSY (1 << 26) | ||
| 123 | #define SE_SPI_BUSY (1 << 27) | ||
| 124 | #define SE_SH_BUSY (1 << 28) | ||
| 125 | #define SE_SC_BUSY (1 << 29) | ||
| 126 | #define SE_DB_BUSY (1 << 30) | ||
| 127 | #define SE_CB_BUSY (1 << 31) | ||
| 85 | 128 | ||
| 86 | #define HDP_HOST_PATH_CNTL 0x2C00 | 129 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 87 | #define HDP_NONSURFACE_BASE 0x2C04 | 130 | #define HDP_NONSURFACE_BASE 0x2C04 |
| @@ -266,5 +309,21 @@ | |||
| 266 | #define WAIT_UNTIL 0x8040 | 309 | #define WAIT_UNTIL 0x8040 |
| 267 | 310 | ||
| 268 | #define SRBM_STATUS 0x0E50 | 311 | #define SRBM_STATUS 0x0E50 |
| 312 | #define SRBM_SOFT_RESET 0x0E60 | ||
| 313 | #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 | ||
| 314 | #define SOFT_RESET_BIF (1 << 1) | ||
| 315 | #define SOFT_RESET_CG (1 << 2) | ||
| 316 | #define SOFT_RESET_DC (1 << 5) | ||
| 317 | #define SOFT_RESET_GRBM (1 << 8) | ||
| 318 | #define SOFT_RESET_HDP (1 << 9) | ||
| 319 | #define SOFT_RESET_IH (1 << 10) | ||
| 320 | #define SOFT_RESET_MC (1 << 11) | ||
| 321 | #define SOFT_RESET_RLC (1 << 13) | ||
| 322 | #define SOFT_RESET_ROM (1 << 14) | ||
| 323 | #define SOFT_RESET_SEM (1 << 15) | ||
| 324 | #define SOFT_RESET_VMC (1 << 17) | ||
| 325 | #define SOFT_RESET_TST (1 << 21) | ||
| 326 | #define SOFT_RESET_REGBB (1 << 22) | ||
| 327 | #define SOFT_RESET_ORB (1 << 23) | ||
| 269 | 328 | ||
| 270 | #endif | 329 | #endif |