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authorStephen Warren <swarren@nvidia.com>2013-11-11 15:25:54 -0500
committerStephen Warren <swarren@nvidia.com>2013-12-11 18:45:02 -0500
commit74511c4befe40731b175f81684d446c4300d6060 (patch)
tree5ed0e1953a63fa5787f9e6e3b333c25c1bf33e3c
parent2bd541ffaab3609fbd79c80aded1960fb5bddf03 (diff)
ARM: tegra: remove legacy DMA entries from DT
Now that all Tegra drivers have been converted to use DMA APIs which retrieve DMA channel information from standard DMA DT properties, we can remove all the legacy DT DMA-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi14
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi13
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi12
3 files changed, 0 insertions, 39 deletions
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index d0da8b7aa4df..731249fbe206 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -128,7 +128,6 @@
128 reg = <0x70006000 0x40>; 128 reg = <0x70006000 0x40>;
129 reg-shift = <2>; 129 reg-shift = <2>;
130 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 130 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
131 nvidia,dma-request-selector = <&apbdma 8>;
132 clocks = <&tegra_car TEGRA114_CLK_UARTA>; 131 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
133 resets = <&tegra_car 6>; 132 resets = <&tegra_car 6>;
134 reset-names = "serial"; 133 reset-names = "serial";
@@ -142,7 +141,6 @@
142 reg = <0x70006040 0x40>; 141 reg = <0x70006040 0x40>;
143 reg-shift = <2>; 142 reg-shift = <2>;
144 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 143 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
145 nvidia,dma-request-selector = <&apbdma 9>;
146 clocks = <&tegra_car TEGRA114_CLK_UARTB>; 144 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
147 resets = <&tegra_car 7>; 145 resets = <&tegra_car 7>;
148 reset-names = "serial"; 146 reset-names = "serial";
@@ -156,7 +154,6 @@
156 reg = <0x70006200 0x100>; 154 reg = <0x70006200 0x100>;
157 reg-shift = <2>; 155 reg-shift = <2>;
158 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 156 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
159 nvidia,dma-request-selector = <&apbdma 10>;
160 clocks = <&tegra_car TEGRA114_CLK_UARTC>; 157 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
161 resets = <&tegra_car 55>; 158 resets = <&tegra_car 55>;
162 reset-names = "serial"; 159 reset-names = "serial";
@@ -170,7 +167,6 @@
170 reg = <0x70006300 0x100>; 167 reg = <0x70006300 0x100>;
171 reg-shift = <2>; 168 reg-shift = <2>;
172 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 169 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
173 nvidia,dma-request-selector = <&apbdma 19>;
174 clocks = <&tegra_car TEGRA114_CLK_UARTD>; 170 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
175 resets = <&tegra_car 65>; 171 resets = <&tegra_car 65>;
176 reset-names = "serial"; 172 reset-names = "serial";
@@ -268,7 +264,6 @@
268 compatible = "nvidia,tegra114-spi"; 264 compatible = "nvidia,tegra114-spi";
269 reg = <0x7000d400 0x200>; 265 reg = <0x7000d400 0x200>;
270 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 266 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
271 nvidia,dma-request-selector = <&apbdma 15>;
272 #address-cells = <1>; 267 #address-cells = <1>;
273 #size-cells = <0>; 268 #size-cells = <0>;
274 clocks = <&tegra_car TEGRA114_CLK_SBC1>; 269 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
@@ -284,7 +279,6 @@
284 compatible = "nvidia,tegra114-spi"; 279 compatible = "nvidia,tegra114-spi";
285 reg = <0x7000d600 0x200>; 280 reg = <0x7000d600 0x200>;
286 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 281 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
287 nvidia,dma-request-selector = <&apbdma 16>;
288 #address-cells = <1>; 282 #address-cells = <1>;
289 #size-cells = <0>; 283 #size-cells = <0>;
290 clocks = <&tegra_car TEGRA114_CLK_SBC2>; 284 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
@@ -300,7 +294,6 @@
300 compatible = "nvidia,tegra114-spi"; 294 compatible = "nvidia,tegra114-spi";
301 reg = <0x7000d800 0x200>; 295 reg = <0x7000d800 0x200>;
302 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 296 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
303 nvidia,dma-request-selector = <&apbdma 17>;
304 #address-cells = <1>; 297 #address-cells = <1>;
305 #size-cells = <0>; 298 #size-cells = <0>;
306 clocks = <&tegra_car TEGRA114_CLK_SBC3>; 299 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
@@ -316,7 +309,6 @@
316 compatible = "nvidia,tegra114-spi"; 309 compatible = "nvidia,tegra114-spi";
317 reg = <0x7000da00 0x200>; 310 reg = <0x7000da00 0x200>;
318 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 311 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
319 nvidia,dma-request-selector = <&apbdma 18>;
320 #address-cells = <1>; 312 #address-cells = <1>;
321 #size-cells = <0>; 313 #size-cells = <0>;
322 clocks = <&tegra_car TEGRA114_CLK_SBC4>; 314 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
@@ -332,7 +324,6 @@
332 compatible = "nvidia,tegra114-spi"; 324 compatible = "nvidia,tegra114-spi";
333 reg = <0x7000dc00 0x200>; 325 reg = <0x7000dc00 0x200>;
334 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 326 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
335 nvidia,dma-request-selector = <&apbdma 27>;
336 #address-cells = <1>; 327 #address-cells = <1>;
337 #size-cells = <0>; 328 #size-cells = <0>;
338 clocks = <&tegra_car TEGRA114_CLK_SBC5>; 329 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
@@ -348,7 +339,6 @@
348 compatible = "nvidia,tegra114-spi"; 339 compatible = "nvidia,tegra114-spi";
349 reg = <0x7000de00 0x200>; 340 reg = <0x7000de00 0x200>;
350 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 341 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
351 nvidia,dma-request-selector = <&apbdma 28>;
352 #address-cells = <1>; 342 #address-cells = <1>;
353 #size-cells = <0>; 343 #size-cells = <0>;
354 clocks = <&tegra_car TEGRA114_CLK_SBC6>; 344 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
@@ -401,10 +391,6 @@
401 <0x70080200 0x100>, 391 <0x70080200 0x100>,
402 <0x70081000 0x200>; 392 <0x70081000 0x200>;
403 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 393 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
404 nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
405 <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
406 <&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
407 <&apbdma 29>;
408 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, 394 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
409 <&tegra_car TEGRA114_CLK_APBIF>; 395 <&tegra_car TEGRA114_CLK_APBIF>;
410 clock-names = "d_audio", "apbif"; 396 clock-names = "d_audio", "apbif";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 4d903affa7d0..c90d0aac3afe 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -248,7 +248,6 @@
248 compatible = "nvidia,tegra20-ac97"; 248 compatible = "nvidia,tegra20-ac97";
249 reg = <0x70002000 0x200>; 249 reg = <0x70002000 0x200>;
250 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 250 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
251 nvidia,dma-request-selector = <&apbdma 12>;
252 clocks = <&tegra_car TEGRA20_CLK_AC97>; 251 clocks = <&tegra_car TEGRA20_CLK_AC97>;
253 resets = <&tegra_car 3>; 252 resets = <&tegra_car 3>;
254 reset-names = "ac97"; 253 reset-names = "ac97";
@@ -261,7 +260,6 @@
261 compatible = "nvidia,tegra20-i2s"; 260 compatible = "nvidia,tegra20-i2s";
262 reg = <0x70002800 0x200>; 261 reg = <0x70002800 0x200>;
263 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
264 nvidia,dma-request-selector = <&apbdma 2>;
265 clocks = <&tegra_car TEGRA20_CLK_I2S1>; 263 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
266 resets = <&tegra_car 11>; 264 resets = <&tegra_car 11>;
267 reset-names = "i2s"; 265 reset-names = "i2s";
@@ -274,7 +272,6 @@
274 compatible = "nvidia,tegra20-i2s"; 272 compatible = "nvidia,tegra20-i2s";
275 reg = <0x70002a00 0x200>; 273 reg = <0x70002a00 0x200>;
276 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 274 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
277 nvidia,dma-request-selector = <&apbdma 1>;
278 clocks = <&tegra_car TEGRA20_CLK_I2S2>; 275 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
279 resets = <&tegra_car 18>; 276 resets = <&tegra_car 18>;
280 reset-names = "i2s"; 277 reset-names = "i2s";
@@ -295,7 +292,6 @@
295 reg = <0x70006000 0x40>; 292 reg = <0x70006000 0x40>;
296 reg-shift = <2>; 293 reg-shift = <2>;
297 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 294 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
298 nvidia,dma-request-selector = <&apbdma 8>;
299 clocks = <&tegra_car TEGRA20_CLK_UARTA>; 295 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
300 resets = <&tegra_car 6>; 296 resets = <&tegra_car 6>;
301 reset-names = "serial"; 297 reset-names = "serial";
@@ -309,7 +305,6 @@
309 reg = <0x70006040 0x40>; 305 reg = <0x70006040 0x40>;
310 reg-shift = <2>; 306 reg-shift = <2>;
311 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
312 nvidia,dma-request-selector = <&apbdma 9>;
313 clocks = <&tegra_car TEGRA20_CLK_UARTB>; 308 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
314 resets = <&tegra_car 7>; 309 resets = <&tegra_car 7>;
315 reset-names = "serial"; 310 reset-names = "serial";
@@ -323,7 +318,6 @@
323 reg = <0x70006200 0x100>; 318 reg = <0x70006200 0x100>;
324 reg-shift = <2>; 319 reg-shift = <2>;
325 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 320 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
326 nvidia,dma-request-selector = <&apbdma 10>;
327 clocks = <&tegra_car TEGRA20_CLK_UARTC>; 321 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
328 resets = <&tegra_car 55>; 322 resets = <&tegra_car 55>;
329 reset-names = "serial"; 323 reset-names = "serial";
@@ -337,7 +331,6 @@
337 reg = <0x70006300 0x100>; 331 reg = <0x70006300 0x100>;
338 reg-shift = <2>; 332 reg-shift = <2>;
339 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 333 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
340 nvidia,dma-request-selector = <&apbdma 19>;
341 clocks = <&tegra_car TEGRA20_CLK_UARTD>; 334 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
342 resets = <&tegra_car 65>; 335 resets = <&tegra_car 65>;
343 reset-names = "serial"; 336 reset-names = "serial";
@@ -351,7 +344,6 @@
351 reg = <0x70006400 0x100>; 344 reg = <0x70006400 0x100>;
352 reg-shift = <2>; 345 reg-shift = <2>;
353 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 346 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
354 nvidia,dma-request-selector = <&apbdma 20>;
355 clocks = <&tegra_car TEGRA20_CLK_UARTE>; 347 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
356 resets = <&tegra_car 66>; 348 resets = <&tegra_car 66>;
357 reset-names = "serial"; 349 reset-names = "serial";
@@ -397,7 +389,6 @@
397 compatible = "nvidia,tegra20-sflash"; 389 compatible = "nvidia,tegra20-sflash";
398 reg = <0x7000c380 0x80>; 390 reg = <0x7000c380 0x80>;
399 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 391 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
400 nvidia,dma-request-selector = <&apbdma 11>;
401 #address-cells = <1>; 392 #address-cells = <1>;
402 #size-cells = <0>; 393 #size-cells = <0>;
403 clocks = <&tegra_car TEGRA20_CLK_SPI>; 394 clocks = <&tegra_car TEGRA20_CLK_SPI>;
@@ -460,7 +451,6 @@
460 compatible = "nvidia,tegra20-slink"; 451 compatible = "nvidia,tegra20-slink";
461 reg = <0x7000d400 0x200>; 452 reg = <0x7000d400 0x200>;
462 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 453 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
463 nvidia,dma-request-selector = <&apbdma 15>;
464 #address-cells = <1>; 454 #address-cells = <1>;
465 #size-cells = <0>; 455 #size-cells = <0>;
466 clocks = <&tegra_car TEGRA20_CLK_SBC1>; 456 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
@@ -475,7 +465,6 @@
475 compatible = "nvidia,tegra20-slink"; 465 compatible = "nvidia,tegra20-slink";
476 reg = <0x7000d600 0x200>; 466 reg = <0x7000d600 0x200>;
477 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 467 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
478 nvidia,dma-request-selector = <&apbdma 16>;
479 #address-cells = <1>; 468 #address-cells = <1>;
480 #size-cells = <0>; 469 #size-cells = <0>;
481 clocks = <&tegra_car TEGRA20_CLK_SBC2>; 470 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
@@ -490,7 +479,6 @@
490 compatible = "nvidia,tegra20-slink"; 479 compatible = "nvidia,tegra20-slink";
491 reg = <0x7000d800 0x200>; 480 reg = <0x7000d800 0x200>;
492 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 481 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
493 nvidia,dma-request-selector = <&apbdma 17>;
494 #address-cells = <1>; 482 #address-cells = <1>;
495 #size-cells = <0>; 483 #size-cells = <0>;
496 clocks = <&tegra_car TEGRA20_CLK_SBC3>; 484 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
@@ -505,7 +493,6 @@
505 compatible = "nvidia,tegra20-slink"; 493 compatible = "nvidia,tegra20-slink";
506 reg = <0x7000da00 0x200>; 494 reg = <0x7000da00 0x200>;
507 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 495 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
508 nvidia,dma-request-selector = <&apbdma 18>;
509 #address-cells = <1>; 496 #address-cells = <1>;
510 #size-cells = <0>; 497 #size-cells = <0>;
511 clocks = <&tegra_car TEGRA20_CLK_SBC4>; 498 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index cf84edf0f435..31259b09e7cc 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -345,7 +345,6 @@
345 reg = <0x70006000 0x40>; 345 reg = <0x70006000 0x40>;
346 reg-shift = <2>; 346 reg-shift = <2>;
347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
348 nvidia,dma-request-selector = <&apbdma 8>;
349 clocks = <&tegra_car TEGRA30_CLK_UARTA>; 348 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
350 resets = <&tegra_car 6>; 349 resets = <&tegra_car 6>;
351 reset-names = "serial"; 350 reset-names = "serial";
@@ -359,7 +358,6 @@
359 reg = <0x70006040 0x40>; 358 reg = <0x70006040 0x40>;
360 reg-shift = <2>; 359 reg-shift = <2>;
361 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 360 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
362 nvidia,dma-request-selector = <&apbdma 9>;
363 clocks = <&tegra_car TEGRA30_CLK_UARTB>; 361 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
364 resets = <&tegra_car 7>; 362 resets = <&tegra_car 7>;
365 reset-names = "serial"; 363 reset-names = "serial";
@@ -373,7 +371,6 @@
373 reg = <0x70006200 0x100>; 371 reg = <0x70006200 0x100>;
374 reg-shift = <2>; 372 reg-shift = <2>;
375 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 373 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
376 nvidia,dma-request-selector = <&apbdma 10>;
377 clocks = <&tegra_car TEGRA30_CLK_UARTC>; 374 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
378 resets = <&tegra_car 55>; 375 resets = <&tegra_car 55>;
379 reset-names = "serial"; 376 reset-names = "serial";
@@ -387,7 +384,6 @@
387 reg = <0x70006300 0x100>; 384 reg = <0x70006300 0x100>;
388 reg-shift = <2>; 385 reg-shift = <2>;
389 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 386 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
390 nvidia,dma-request-selector = <&apbdma 19>;
391 clocks = <&tegra_car TEGRA30_CLK_UARTD>; 387 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
392 resets = <&tegra_car 65>; 388 resets = <&tegra_car 65>;
393 reset-names = "serial"; 389 reset-names = "serial";
@@ -401,7 +397,6 @@
401 reg = <0x70006400 0x100>; 397 reg = <0x70006400 0x100>;
402 reg-shift = <2>; 398 reg-shift = <2>;
403 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 399 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
404 nvidia,dma-request-selector = <&apbdma 20>;
405 clocks = <&tegra_car TEGRA30_CLK_UARTE>; 400 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
406 resets = <&tegra_car 66>; 401 resets = <&tegra_car 66>;
407 reset-names = "serial"; 402 reset-names = "serial";
@@ -511,7 +506,6 @@
511 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 506 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
512 reg = <0x7000d400 0x200>; 507 reg = <0x7000d400 0x200>;
513 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 508 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
514 nvidia,dma-request-selector = <&apbdma 15>;
515 #address-cells = <1>; 509 #address-cells = <1>;
516 #size-cells = <0>; 510 #size-cells = <0>;
517 clocks = <&tegra_car TEGRA30_CLK_SBC1>; 511 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
@@ -526,7 +520,6 @@
526 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 520 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
527 reg = <0x7000d600 0x200>; 521 reg = <0x7000d600 0x200>;
528 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 522 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
529 nvidia,dma-request-selector = <&apbdma 16>;
530 #address-cells = <1>; 523 #address-cells = <1>;
531 #size-cells = <0>; 524 #size-cells = <0>;
532 clocks = <&tegra_car TEGRA30_CLK_SBC2>; 525 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
@@ -541,7 +534,6 @@
541 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 534 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
542 reg = <0x7000d800 0x200>; 535 reg = <0x7000d800 0x200>;
543 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 536 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
544 nvidia,dma-request-selector = <&apbdma 17>;
545 #address-cells = <1>; 537 #address-cells = <1>;
546 #size-cells = <0>; 538 #size-cells = <0>;
547 clocks = <&tegra_car TEGRA30_CLK_SBC3>; 539 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
@@ -556,7 +548,6 @@
556 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 548 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
557 reg = <0x7000da00 0x200>; 549 reg = <0x7000da00 0x200>;
558 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 550 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
559 nvidia,dma-request-selector = <&apbdma 18>;
560 #address-cells = <1>; 551 #address-cells = <1>;
561 #size-cells = <0>; 552 #size-cells = <0>;
562 clocks = <&tegra_car TEGRA30_CLK_SBC4>; 553 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
@@ -571,7 +562,6 @@
571 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 562 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
572 reg = <0x7000dc00 0x200>; 563 reg = <0x7000dc00 0x200>;
573 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 564 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
574 nvidia,dma-request-selector = <&apbdma 27>;
575 #address-cells = <1>; 565 #address-cells = <1>;
576 #size-cells = <0>; 566 #size-cells = <0>;
577 clocks = <&tegra_car TEGRA30_CLK_SBC5>; 567 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
@@ -586,7 +576,6 @@
586 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; 576 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
587 reg = <0x7000de00 0x200>; 577 reg = <0x7000de00 0x200>;
588 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 578 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
589 nvidia,dma-request-selector = <&apbdma 28>;
590 #address-cells = <1>; 579 #address-cells = <1>;
591 #size-cells = <0>; 580 #size-cells = <0>;
592 clocks = <&tegra_car TEGRA30_CLK_SBC6>; 581 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
@@ -638,7 +627,6 @@
638 reg = <0x70080000 0x200 627 reg = <0x70080000 0x200
639 0x70080200 0x100>; 628 0x70080200 0x100>;
640 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 629 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
641 nvidia,dma-request-selector = <&apbdma 1>;
642 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 630 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
643 <&tegra_car TEGRA30_CLK_APBIF>; 631 <&tegra_car TEGRA30_CLK_APBIF>;
644 clock-names = "d_audio", "apbif"; 632 clock-names = "d_audio", "apbif";
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-01 05:36:46 -0400