Merge tag 'omap-devel-b-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-prcm

Some OMAP PRCM updates for 3.5.  Includes some clock, clockdomain,
powerdomain, PRM, and CM changes.

18 files changed, 97 insertions, 87 deletions

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d9f4931513f9..5c4e66542169 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -439,7 +439,7 @@ void omap2_clk_disable_unused(struct clk *clk)
                 clk->ops->disable(clk);
         }
         if (clk->clkdm != NULL)
-                pwrdm_clkdm_state_switch(clk->clkdm);
+                pwrdm_state_switch(clk->clkdm->pwrdm.ptr);
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index f4a626f7c79e..4e1a3b0e8cc8 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -1,7 +1,7 @@
 /*
  * OMAP3 clock data
  *
- * Copyright (C) 2007-2010 Texas Instruments, Inc.
+ * Copyright (C) 2007-2010, 2012 Texas Instruments, Inc.
  * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Written by Paul Walmsley
@@ -1640,6 +1640,7 @@ static struct clk hdq_fck = {
         .name           = "hdq_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &core_12m_fck,
+        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
         .recalc         = &followparent_recalc,
@@ -3294,8 +3295,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
+        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
         CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
@@ -3419,7 +3420,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
         CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
-        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_3505 | CK_3517),
+        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_AM35XX),
         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
@@ -3513,21 +3514,9 @@ int __init omap3xxx_clk_init(void)
         struct omap_clk *c;
         u32 cpu_clkflg = 0;
 
-        /*
-         * 3505 must be tested before 3517, since 3517 returns true
-         * for both AM3517 chips and AM3517 family chips, which
-         * includes 3505.  Unfortunately there's no obvious family
-         * test for 3517/3505 :-(
-         */
-        if (cpu_is_omap3505()) {
-                cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_3505;
-        } else if (cpu_is_omap3517()) {
-                cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_3517;
-        } else if (cpu_is_omap3505()) {
+        if (cpu_is_omap3517()) {
                 cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_3505;
+                cpu_clkflg = CK_AM35XX;
         } else if (cpu_is_omap3630()) {
                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
                 cpu_clkflg = CK_36XX;
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index fa6ea65ad44b..2172f6603848 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3355,17 +3355,6 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
         CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
         CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index ad07689e1563..8664f5a8bfb6 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -840,7 +840,7 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
         spin_lock_irqsave(&clkdm->lock, flags);
         clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
         arch_clkdm->clkdm_allow_idle(clkdm);
-        pwrdm_clkdm_state_switch(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
         spin_unlock_irqrestore(&clkdm->lock, flags);
 }
 
@@ -924,8 +924,7 @@ static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
 
         spin_lock_irqsave(&clkdm->lock, flags);
         arch_clkdm->clkdm_clk_enable(clkdm);
-        pwrdm_wait_transition(clkdm->pwrdm.ptr);
-        pwrdm_clkdm_state_switch(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
         spin_unlock_irqrestore(&clkdm->lock, flags);
 
         pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
@@ -950,7 +949,7 @@ static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
 
         spin_lock_irqsave(&clkdm->lock, flags);
         arch_clkdm->clkdm_clk_disable(clkdm);
-        pwrdm_clkdm_state_switch(clkdm);
+        pwrdm_state_switch(clkdm->pwrdm.ptr);
         spin_unlock_irqrestore(&clkdm->lock, flags);
 
         pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index b84e138d99c8..6038adb97710 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -53,9 +53,9 @@
  * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
  */
 static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
-        { .clkdm_name = "iva2_clkdm", },
-        { .clkdm_name = "mpu_clkdm", },
-        { .clkdm_name = "wkup_clkdm", },
+        { .clkdm_name = "iva2_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
         { NULL },
 };
 
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index b91275908f33..8083a8cdc55f 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -79,7 +79,7 @@
 
 /* CM_CLKSEL1_PLL_IVA2 */
 #define OMAP3430_IVA2_CLK_SRC_SHIFT                     19
-#define OMAP3430_IVA2_CLK_SRC_MASK                      (0x3 << 19)
+#define OMAP3430_IVA2_CLK_SRC_MASK                      (0x7 << 19)
 #define OMAP3430_IVA2_DPLL_MULT_SHIFT                   8
 #define OMAP3430_IVA2_DPLL_MULT_MASK                    (0x7ff << 8)
 #define OMAP3430_IVA2_DPLL_DIV_SHIFT                    0
@@ -124,7 +124,7 @@
 
 /* CM_CLKSEL1_PLL_MPU */
 #define OMAP3430_MPU_CLK_SRC_SHIFT                      19
-#define OMAP3430_MPU_CLK_SRC_MASK                       (0x3 << 19)
+#define OMAP3430_MPU_CLK_SRC_MASK                       (0x7 << 19)
 #define OMAP3430_MPU_DPLL_MULT_SHIFT                    8
 #define OMAP3430_MPU_DPLL_MULT_MASK                     (0x7ff << 8)
 #define OMAP3430_MPU_DPLL_DIV_SHIFT                     0
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index bd8810c3753f..8c86d294b1a3 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -32,6 +32,7 @@
 #include "prcm44xx.h"
 #include "prm44xx.h"
 #include "prcm_mpu44xx.h"
+#include "prcm-common.h"
 
 /*
  * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
@@ -49,14 +50,21 @@
 #define CLKCTRL_IDLEST_INTERFACE_IDLE           0x2
 #define CLKCTRL_IDLEST_DISABLED                 0x3
 
-static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
-        [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
-        [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
-        [OMAP4430_CM1_PARTITION]                = OMAP4430_CM1_BASE,
-        [OMAP4430_CM2_PARTITION]                = OMAP4430_CM2_BASE,
-        [OMAP4430_SCRM_PARTITION]               = 0,
-        [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
-};
+static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
+
+/**
+ * omap_cm_base_init - Populates the cm partitions
+ *
+ * Populates the base addresses of the _cm_bases
+ * array used for read/write of cm module registers.
+ */
+void omap_cm_base_init(void)
+{
+        _cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
+        _cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
+        _cm_bases[OMAP4430_CM2_PARTITION] = cm2_base;
+        _cm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+}
 
 /* Private functions */
 
@@ -106,7 +114,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_cm_bases[part]);
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+        return __raw_readl(_cm_bases[part] + inst + idx);
 }
 
 /* Write into a register in a CM instance */
@@ -115,7 +123,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_cm_bases[part]);
-        __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
+        __raw_writel(val, _cm_bases[part] + inst + idx);
 }
 
 /* Read-modify-write a register in CM1. Caller must lock */
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 1549c11000d3..8a6953a34fe2 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -166,6 +166,7 @@ static struct omap_globals omap4_globals = {
         .prm    = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
         .cm     = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
         .cm2    = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
+        .prcm_mpu       = OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE),
 };
 
 void __init omap2_set_globals_443x(void)
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 57da7f406e28..0672fc54b30f 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -111,6 +111,7 @@ struct omap_globals {
         void __iomem    *prm;            /* Power and Reset Management */
         void __iomem    *cm;             /* Clock Management */
         void __iomem    *cm2;
+        void __iomem    *prcm_mpu;
 };
 
 void omap2_set_globals_242x(void);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index fc56745676fa..f0f10beeffe8 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -142,7 +142,8 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
 
         ai = omap3_dpll_autoidle_read(clk);
 
-        omap3_dpll_deny_idle(clk);
+        if (ai)
+                omap3_dpll_deny_idle(clk);
 
         _omap3_dpll_write_clken(clk, DPLL_LOCKED);
 
@@ -186,8 +187,6 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
 
         if (ai)
                 omap3_dpll_allow_idle(clk);
-        else
-                omap3_dpll_deny_idle(clk);
 
         return r;
 }
@@ -216,8 +215,6 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
 
         if (ai)
                 omap3_dpll_allow_idle(clk);
-        else
-                omap3_dpll_deny_idle(clk);
 
         return 0;
 }
@@ -519,6 +516,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk)
 
         dd = clk->dpll_data;
 
+        if (!dd->autoidle_reg)
+                return -EINVAL;
+
         v = __raw_readl(dd->autoidle_reg);
         v &= dd->autoidle_mask;
         v >>= __ffs(dd->autoidle_mask);
@@ -545,6 +545,12 @@ void omap3_dpll_allow_idle(struct clk *clk)
 
         dd = clk->dpll_data;
 
+        if (!dd->autoidle_reg) {
+                pr_debug("clock: DPLL %s: autoidle not supported\n",
+                        clk->name);
+                return;
+        }
+
         /*
          * REVISIT: CORE DPLL can optionally enter low-power bypass
          * by writing 0x5 instead of 0x1.  Add some mechanism to
@@ -554,6 +560,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
         v &= ~dd->autoidle_mask;
         v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
         __raw_writel(v, dd->autoidle_reg);
+
 }
 
 /**
@@ -572,6 +579,12 @@ void omap3_dpll_deny_idle(struct clk *clk)
 
         dd = clk->dpll_data;
 
+        if (!dd->autoidle_reg) {
+                pr_debug("clock: DPLL %s: autoidle not supported\n",
+                        clk->name);
+                return;
+        }
+
         v = __raw_readl(dd->autoidle_reg);
         v &= ~dd->autoidle_mask;
         v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 96ad3dbeac34..96114901b932 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -981,16 +981,6 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
         return ret;
 }
 
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm)
-{
-        if (clkdm != NULL && clkdm->pwrdm.ptr != NULL) {
-                pwrdm_wait_transition(clkdm->pwrdm.ptr);
-                return pwrdm_state_switch(clkdm->pwrdm.ptr);
-        }
-
-        return -EINVAL;
-}
-
 int pwrdm_pre_transition(void)
 {
         pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0d72a8a8ce4d..8f88d65c46ea 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -213,7 +213,6 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
 int pwrdm_wait_transition(struct powerdomain *pwrdm);
 
 int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
 int pwrdm_pre_transition(void);
 int pwrdm_post_transition(void);
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 5aa5435e3ff1..6da3ba483ad1 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -177,6 +177,8 @@
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
 #define OMAP24XX_ST_GPIOS_SHIFT                         2
 #define OMAP24XX_ST_GPIOS_MASK                          (1 << 2)
+#define OMAP24XX_ST_32KSYNC_SHIFT                       1
+#define OMAP24XX_ST_32KSYNC_MASK                        (1 << 1)
 #define OMAP24XX_ST_GPT1_SHIFT                          0
 #define OMAP24XX_ST_GPT1_MASK                           (1 << 0)
 
@@ -307,6 +309,8 @@
 #define OMAP3430_ST_SR1_MASK                            (1 << 6)
 #define OMAP3430_ST_GPIO1_SHIFT                         3
 #define OMAP3430_ST_GPIO1_MASK                          (1 << 3)
+#define OMAP3430_ST_32KSYNC_SHIFT                       2
+#define OMAP3430_ST_32KSYNC_MASK                        (1 << 2)
 #define OMAP3430_ST_GPT12_SHIFT                         1
 #define OMAP3430_ST_GPT12_MASK                          (1 << 1)
 #define OMAP3430_ST_GPT1_SHIFT                          0
@@ -410,6 +414,19 @@
 extern void __iomem *prm_base;
 extern void __iomem *cm_base;
 extern void __iomem *cm2_base;
+extern void __iomem *prcm_mpu_base;
+
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
+extern void omap_prm_base_init(void);
+extern void omap_cm_base_init(void);
+#else
+static inline void omap_prm_base_init(void)
+{
+}
+static inline void omap_cm_base_init(void)
+{
+}
+#endif
 
 /**
  * struct omap_prcm_irq - describes a PRCM interrupt bit
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 626acfad7190..480f40a5ee42 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -42,6 +42,7 @@
 void __iomem *prm_base;
 void __iomem *cm_base;
 void __iomem *cm2_base;
+void __iomem *prcm_mpu_base;
 
 #define MAX_MODULE_ENABLE_WAIT          100000
 
@@ -155,4 +156,11 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
                 cm_base = omap2_globals->cm;
         if (omap2_globals->cm2)
                 cm2_base = omap2_globals->cm2;
+        if (omap2_globals->prcm_mpu)
+                prcm_mpu_base = omap2_globals->prcm_mpu;
+
+        if (cpu_is_omap44xx()) {
+                omap_prm_base_init();
+                omap_cm_base_init();
+        }
 }
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 9b3898a3ac9b..c12320c0ae95 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -18,20 +18,26 @@
 
 #include "iomap.h"
 #include "common.h"
+#include "prcm-common.h"
 #include "prm44xx.h"
 #include "prminst44xx.h"
 #include "prm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prcm_mpu44xx.h"
 
-static u32 _prm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
-        [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
-        [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
-        [OMAP4430_CM1_PARTITION]                = 0,
-        [OMAP4430_CM2_PARTITION]                = 0,
-        [OMAP4430_SCRM_PARTITION]               = 0,
-        [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
-};
+static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
+
+/**
+ * omap_prm_base_init - Populates the prm partitions
+ *
+ * Populates the base addresses of the _prm_bases
+ * array used for read/write of prm module registers.
+ */
+void omap_prm_base_init(void)
+{
+        _prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
+        _prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
+}
 
 /* Read a register in a PRM instance */
 u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
@@ -39,8 +45,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_prm_bases[part]);
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst +
-                                               idx));
+        return __raw_readl(_prm_bases[part] + inst + idx);
 }
 
 /* Write into a register in a PRM instance */
@@ -49,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
                part == OMAP4430_INVALID_PRCM_PARTITION ||
                !_prm_bases[part]);
-        __raw_writel(val, OMAP2_L4_IO_ADDRESS(_prm_bases[part] + inst + idx));
+        __raw_writel(val, _prm_bases[part] + inst + idx);
 }
 
 /* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index ecec873e78cd..1b7835865c83 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -178,13 +178,6 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
         if (IS_ERR(timer->fclk))
                 return -ENODEV;
 
-        sprintf(name, "gpt%d_ick", gptimer_id);
-        timer->iclk = clk_get(NULL, name);
-        if (IS_ERR(timer->iclk)) {
-                clk_put(timer->fclk);
-                return -ENODEV;
-        }
-
         omap_hwmod_enable(oh);
 
         sys_timer_reserved |= (1 << (gptimer_id - 1));
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index b299b8d201c8..d0ed8c443a63 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -34,8 +34,7 @@ struct omap_clk {
 #define CK_243X         (1 << 5)        /* 243x, 253x */
 #define CK_3430ES1      (1 << 6)        /* 34xxES1 only */
 #define CK_3430ES2PLUS  (1 << 7)        /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_3505         (1 << 8)
-#define CK_3517         (1 << 9)
+#define CK_AM35XX       (1 << 9)        /* Sitara AM35xx */
 #define CK_36XX         (1 << 10)       /* 36xx/37xx-specific clocks */
 #define CK_443X         (1 << 11)
 #define CK_TI816X       (1 << 12)
@@ -44,7 +43,6 @@ struct omap_clk {
 
 
 #define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
-#define CK_AM35XX       (CK_3505 | CK_3517)     /* all Sitara AM35xx */
 #define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
 
 
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 9418f00b6c38..be2b8c48a9bf 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -259,7 +259,7 @@ struct omap_dm_timer {
         unsigned long phys_base;
         int id;
         int irq;
-        struct clk *iclk, *fclk;
+        struct clk *fclk;
 
         void __iomem    *io_base;
         void __iomem    *sys_stat;      /* TISTAT timer status */