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authorSonic Zhang <sonic.zhang@analog.com>2012-08-30 06:54:24 -0400
committerBob Liu <lliubbo@gmail.com>2012-10-08 02:36:29 -0400
commit740dd8c2bc180bdad27868208c00f969281b69ac (patch)
tree5b1ce10a7ad193b4ef02b1c710fa257b9f25180d
parent810f1512dc8a1f64c22229c3def85fc398b6a24f (diff)
Blackfin: bf60x: Add bf608 and bf609 specific perpheral MMRs
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
Diffstat
-rw-r--r--arch/blackfin/mach-bf609/include/mach/defBF609.h271
1 files changed, 271 insertions, 0 deletions
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h
index 19690cc42113..8045ade34370 100644
--- a/arch/blackfin/mach-bf609/include/mach/defBF609.h
+++ b/arch/blackfin/mach-bf609/include/mach/defBF609.h
@@ -11,5 +11,276 @@
11#include "defBF60x_base.h" 11#include "defBF60x_base.h"
12 12
13/* The following are the #defines needed by ADSP-BF609 that are not in the common header */ 13/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
14/* =========================
15 PIXC Registers
16 ========================= */
17
18/* =========================
19 PIXC0
20 ========================= */
21#define PIXC0_CTL 0xFFC19000 /* PIXC0 Control Register */
22#define PIXC0_PPL 0xFFC19004 /* PIXC0 Pixels Per Line Register */
23#define PIXC0_LPF 0xFFC19008 /* PIXC0 Line Per Frame Register */
24#define PIXC0_HSTART_A 0xFFC1900C /* PIXC0 Overlay A Horizontal Start Register */
25#define PIXC0_HEND_A 0xFFC19010 /* PIXC0 Overlay A Horizontal End Register */
26#define PIXC0_VSTART_A 0xFFC19014 /* PIXC0 Overlay A Vertical Start Register */
27#define PIXC0_VEND_A 0xFFC19018 /* PIXC0 Overlay A Vertical End Register */
28#define PIXC0_TRANSP_A 0xFFC1901C /* PIXC0 Overlay A Transparency Ratio Register */
29#define PIXC0_HSTART_B 0xFFC19020 /* PIXC0 Overlay B Horizontal Start Register */
30#define PIXC0_HEND_B 0xFFC19024 /* PIXC0 Overlay B Horizontal End Register */
31#define PIXC0_VSTART_B 0xFFC19028 /* PIXC0 Overlay B Vertical Start Register */
32#define PIXC0_VEND_B 0xFFC1902C /* PIXC0 Overlay B Vertical End Register */
33#define PIXC0_TRANSP_B 0xFFC19030 /* PIXC0 Overlay B Transparency Ratio Register */
34#define PIXC0_IRQSTAT 0xFFC1903C /* PIXC0 Interrupt Status Register */
35#define PIXC0_CONRY 0xFFC19040 /* PIXC0 RY Conversion Component Register */
36#define PIXC0_CONGU 0xFFC19044 /* PIXC0 GU Conversion Component Register */
37#define PIXC0_CONBV 0xFFC19048 /* PIXC0 BV Conversion Component Register */
38#define PIXC0_CCBIAS 0xFFC1904C /* PIXC0 Conversion Bias Register */
39#define PIXC0_TC 0xFFC19050 /* PIXC0 Transparency Register */
40#define PIXC0_REVID 0xFFC19054 /* PIXC0 PIXC Revision Id */
41
42/* =========================
43 PVP Registers
44 ========================= */
45
46/* =========================
47 PVP0
48 ========================= */
49#define PVP0_REVID 0xFFC1A000 /* PVP0 Revision ID */
50#define PVP0_CTL 0xFFC1A004 /* PVP0 Control */
51#define PVP0_IMSK0 0xFFC1A008 /* PVP0 INTn interrupt line masks */
52#define PVP0_IMSK1 0xFFC1A00C /* PVP0 INTn interrupt line masks */
53#define PVP0_STAT 0xFFC1A010 /* PVP0 Status */
54#define PVP0_ILAT 0xFFC1A014 /* PVP0 Latched status */
55#define PVP0_IREQ0 0xFFC1A018 /* PVP0 INT0 masked latched status */
56#define PVP0_IREQ1 0xFFC1A01C /* PVP0 INT0 masked latched status */
57#define PVP0_OPF0_CFG 0xFFC1A020 /* PVP0 Config */
58#define PVP0_OPF1_CFG 0xFFC1A040 /* PVP0 Config */
59#define PVP0_OPF2_CFG 0xFFC1A060 /* PVP0 Config */
60#define PVP0_OPF0_CTL 0xFFC1A024 /* PVP0 Control */
61#define PVP0_OPF1_CTL 0xFFC1A044 /* PVP0 Control */
62#define PVP0_OPF2_CTL 0xFFC1A064 /* PVP0 Control */
63#define PVP0_OPF3_CFG 0xFFC1A080 /* PVP0 Config */
64#define PVP0_OPF3_CTL 0xFFC1A084 /* PVP0 Control */
65#define PVP0_PEC_CFG 0xFFC1A0A0 /* PVP0 Config */
66#define PVP0_PEC_CTL 0xFFC1A0A4 /* PVP0 Control */
67#define PVP0_PEC_D1TH0 0xFFC1A0A8 /* PVP0 Lower Hysteresis Threshold */
68#define PVP0_PEC_D1TH1 0xFFC1A0AC /* PVP0 Upper Hysteresis Threshold */
69#define PVP0_PEC_D2TH0 0xFFC1A0B0 /* PVP0 Weak Zero Crossing Threshold */
70#define PVP0_PEC_D2TH1 0xFFC1A0B4 /* PVP0 Strong Zero Crossing Threshold */
71#define PVP0_IIM0_CFG 0xFFC1A0C0 /* PVP0 Config */
72#define PVP0_IIM1_CFG 0xFFC1A0E0 /* PVP0 Config */
73#define PVP0_IIM0_CTL 0xFFC1A0C4 /* PVP0 Control */
74#define PVP0_IIM1_CTL 0xFFC1A0E4 /* PVP0 Control */
75#define PVP0_IIM0_SCALE 0xFFC1A0C8 /* PVP0 Scaler Values */
76#define PVP0_IIM1_SCALE 0xFFC1A0E8 /* PVP0 Scaler Values */
77#define PVP0_IIM0_SOVF_STAT 0xFFC1A0CC /* PVP0 Signed Overflow Status */
78#define PVP0_IIM1_SOVF_STAT 0xFFC1A0EC /* PVP0 Signed Overflow Status */
79#define PVP0_IIM0_UOVF_STAT 0xFFC1A0D0 /* PVP0 Unsigned Overflow Status */
80#define PVP0_IIM1_UOVF_STAT 0xFFC1A0F0 /* PVP0 Unsigned Overflow Status */
81#define PVP0_ACU_CFG 0xFFC1A100 /* PVP0 ACU Configuration Register */
82#define PVP0_ACU_CTL 0xFFC1A104 /* PVP0 ACU Control Register */
83#define PVP0_ACU_OFFSET 0xFFC1A108 /* PVP0 SUM constant register */
84#define PVP0_ACU_FACTOR 0xFFC1A10C /* PVP0 PROD constant register */
85#define PVP0_ACU_SHIFT 0xFFC1A110 /* PVP0 Shift constant register */
86#define PVP0_ACU_MIN 0xFFC1A114 /* PVP0 Lower saturation threshold set to MIN */
87#define PVP0_ACU_MAX 0xFFC1A118 /* PVP0 Upper saturation threshold set to MAX */
88#define PVP0_UDS_CFG 0xFFC1A140 /* PVP0 UDS Configuration Register */
89#define PVP0_UDS_CTL 0xFFC1A144 /* PVP0 UDS Control Register */
90#define PVP0_UDS_OHCNT 0xFFC1A148 /* PVP0 UDS Output H Dimension */
91#define PVP0_UDS_OVCNT 0xFFC1A14C /* PVP0 UDS Output V Dimension */
92#define PVP0_UDS_HAVG 0xFFC1A150 /* PVP0 UDS H Taps */
93#define PVP0_UDS_VAVG 0xFFC1A154 /* PVP0 UDS V Taps */
94#define PVP0_IPF0_CFG 0xFFC1A180 /* PVP0 Configuration */
95#define PVP0_IPF0_PIPECTL 0xFFC1A184 /* PVP0 Pipe Control */
96#define PVP0_IPF1_PIPECTL 0xFFC1A1C4 /* PVP0 Pipe Control */
97#define PVP0_IPF0_CTL 0xFFC1A188 /* PVP0 Control */
98#define PVP0_IPF1_CTL 0xFFC1A1C8 /* PVP0 Control */
99#define PVP0_IPF0_TAG 0xFFC1A18C /* PVP0 TAG Value */
100#define PVP0_IPF1_TAG 0xFFC1A1CC /* PVP0 TAG Value */
101#define PVP0_IPF0_FCNT 0xFFC1A190 /* PVP0 Frame Count */
102#define PVP0_IPF1_FCNT 0xFFC1A1D0 /* PVP0 Frame Count */
103#define PVP0_IPF0_HCNT 0xFFC1A194 /* PVP0 Horizontal Count */
104#define PVP0_IPF1_HCNT 0xFFC1A1D4 /* PVP0 Horizontal Count */
105#define PVP0_IPF0_VCNT 0xFFC1A198 /* PVP0 Vertical Count */
106#define PVP0_IPF1_VCNT 0xFFC1A1D8 /* PVP0 Vertical Count */
107#define PVP0_IPF0_HPOS 0xFFC1A19C /* PVP0 Horizontal Position */
108#define PVP0_IPF0_VPOS 0xFFC1A1A0 /* PVP0 Vertical Position */
109#define PVP0_IPF0_TAG_STAT 0xFFC1A1A4 /* PVP0 TAG Status */
110#define PVP0_IPF1_TAG_STAT 0xFFC1A1E4 /* PVP0 TAG Status */
111#define PVP0_IPF1_CFG 0xFFC1A1C0 /* PVP0 Configuration */
112#define PVP0_CNV0_CFG 0xFFC1A200 /* PVP0 Configuration */
113#define PVP0_CNV1_CFG 0xFFC1A280 /* PVP0 Configuration */
114#define PVP0_CNV2_CFG 0xFFC1A300 /* PVP0 Configuration */
115#define PVP0_CNV3_CFG 0xFFC1A380 /* PVP0 Configuration */
116#define PVP0_CNV0_CTL 0xFFC1A204 /* PVP0 Control */
117#define PVP0_CNV1_CTL 0xFFC1A284 /* PVP0 Control */
118#define PVP0_CNV2_CTL 0xFFC1A304 /* PVP0 Control */
119#define PVP0_CNV3_CTL 0xFFC1A384 /* PVP0 Control */
120#define PVP0_CNV0_C00C01 0xFFC1A208 /* PVP0 Coefficients 0, 0 and 0, 1 */
121#define PVP0_CNV1_C00C01 0xFFC1A288 /* PVP0 Coefficients 0, 0 and 0, 1 */
122#define PVP0_CNV2_C00C01 0xFFC1A308 /* PVP0 Coefficients 0, 0 and 0, 1 */
123#define PVP0_CNV3_C00C01 0xFFC1A388 /* PVP0 Coefficients 0, 0 and 0, 1 */
124#define PVP0_CNV0_C02C03 0xFFC1A20C /* PVP0 Coefficients 0, 2 and 0, 3 */
125#define PVP0_CNV1_C02C03 0xFFC1A28C /* PVP0 Coefficients 0, 2 and 0, 3 */
126#define PVP0_CNV2_C02C03 0xFFC1A30C /* PVP0 Coefficients 0, 2 and 0, 3 */
127#define PVP0_CNV3_C02C03 0xFFC1A38C /* PVP0 Coefficients 0, 2 and 0, 3 */
128#define PVP0_CNV0_C04 0xFFC1A210 /* PVP0 Coefficient 0, 4 */
129#define PVP0_CNV1_C04 0xFFC1A290 /* PVP0 Coefficient 0, 4 */
130#define PVP0_CNV2_C04 0xFFC1A310 /* PVP0 Coefficient 0, 4 */
131#define PVP0_CNV3_C04 0xFFC1A390 /* PVP0 Coefficient 0, 4 */
132#define PVP0_CNV0_C10C11 0xFFC1A214 /* PVP0 Coefficients 1, 0 and 1, 1 */
133#define PVP0_CNV1_C10C11 0xFFC1A294 /* PVP0 Coefficients 1, 0 and 1, 1 */
134#define PVP0_CNV2_C10C11 0xFFC1A314 /* PVP0 Coefficients 1, 0 and 1, 1 */
135#define PVP0_CNV3_C10C11 0xFFC1A394 /* PVP0 Coefficients 1, 0 and 1, 1 */
136#define PVP0_CNV0_C12C13 0xFFC1A218 /* PVP0 Coefficients 1, 2 and 1, 3 */
137#define PVP0_CNV1_C12C13 0xFFC1A298 /* PVP0 Coefficients 1, 2 and 1, 3 */
138#define PVP0_CNV2_C12C13 0xFFC1A318 /* PVP0 Coefficients 1, 2 and 1, 3 */
139#define PVP0_CNV3_C12C13 0xFFC1A398 /* PVP0 Coefficients 1, 2 and 1, 3 */
140#define PVP0_CNV0_C14 0xFFC1A21C /* PVP0 Coefficient 1, 4 */
141#define PVP0_CNV1_C14 0xFFC1A29C /* PVP0 Coefficient 1, 4 */
142#define PVP0_CNV2_C14 0xFFC1A31C /* PVP0 Coefficient 1, 4 */
143#define PVP0_CNV3_C14 0xFFC1A39C /* PVP0 Coefficient 1, 4 */
144#define PVP0_CNV0_C20C21 0xFFC1A220 /* PVP0 Coefficients 2, 0 and 2, 1 */
145#define PVP0_CNV1_C20C21 0xFFC1A2A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
146#define PVP0_CNV2_C20C21 0xFFC1A320 /* PVP0 Coefficients 2, 0 and 2, 1 */
147#define PVP0_CNV3_C20C21 0xFFC1A3A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
148#define PVP0_CNV0_C22C23 0xFFC1A224 /* PVP0 Coefficients 2, 2 and 2, 3 */
149#define PVP0_CNV1_C22C23 0xFFC1A2A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
150#define PVP0_CNV2_C22C23 0xFFC1A324 /* PVP0 Coefficients 2, 2 and 2, 3 */
151#define PVP0_CNV3_C22C23 0xFFC1A3A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
152#define PVP0_CNV0_C24 0xFFC1A228 /* PVP0 Coefficient 2,4 */
153#define PVP0_CNV1_C24 0xFFC1A2A8 /* PVP0 Coefficient 2,4 */
154#define PVP0_CNV2_C24 0xFFC1A328 /* PVP0 Coefficient 2,4 */
155#define PVP0_CNV3_C24 0xFFC1A3A8 /* PVP0 Coefficient 2,4 */
156#define PVP0_CNV0_C30C31 0xFFC1A22C /* PVP0 Coefficients 3, 0 and 3, 1 */
157#define PVP0_CNV1_C30C31 0xFFC1A2AC /* PVP0 Coefficients 3, 0 and 3, 1 */
158#define PVP0_CNV2_C30C31 0xFFC1A32C /* PVP0 Coefficients 3, 0 and 3, 1 */
159#define PVP0_CNV3_C30C31 0xFFC1A3AC /* PVP0 Coefficients 3, 0 and 3, 1 */
160#define PVP0_CNV0_C32C33 0xFFC1A230 /* PVP0 Coefficients 3, 2 and 3, 3 */
161#define PVP0_CNV1_C32C33 0xFFC1A2B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
162#define PVP0_CNV2_C32C33 0xFFC1A330 /* PVP0 Coefficients 3, 2 and 3, 3 */
163#define PVP0_CNV3_C32C33 0xFFC1A3B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
164#define PVP0_CNV0_C34 0xFFC1A234 /* PVP0 Coefficient 3, 4 */
165#define PVP0_CNV1_C34 0xFFC1A2B4 /* PVP0 Coefficient 3, 4 */
166#define PVP0_CNV2_C34 0xFFC1A334 /* PVP0 Coefficient 3, 4 */