b43: N-PHY: split workarounds into per-PHY-ver functions

Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
author: Rafał Miłecki <zajec5@gmail.com> 2011-09-04 17:23:52 -0400
committer: John W. Linville <linville@tuxdriver.com> 2011-09-14 13:56:29 -0400
commit: 73d07a39ee3eadb9ff6734432151a10c50329804 (patch)
tree: 95c4f64aeb491fd561ba82dd8ef734e3439eb25b
parent: 44f4008b5983f058fbea6d238f8c78908676d092 (diff)
1 files changed, 157 insertions, 143 deletions
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index c291ae576b3d..8647933f9321 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -1428,180 +1428,194 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
        }
 }
-/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
+static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
-static void b43_nphy_workarounds(struct b43_wldev *dev)
 {
        struct ssb_sprom *sprom = dev->dev->bus_sprom;
-        struct b43_phy *phy = &dev->phy;
-        struct b43_phy_n *nphy = phy->n;
-        u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
-        u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
-        u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
-        u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
        u16 tmp16;
        u32 tmp32;
-        if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
+        tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
-                b43_nphy_classifier(dev, 1, 0);
+        tmp32 &= 0xffffff;
-        else
+        b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
-                b43_nphy_classifier(dev, 1, 1);
-        if (nphy->hang_avoid)
+        b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
-                b43_nphy_stay_in_carrier_search(dev, 1);
+        b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
+        b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
+        b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
+        b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
+        b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
-        b43_phy_set(dev, B43_NPHY_IQFLIP,
+        b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
-                    B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
+        b43_phy_write(dev, 0x2AE, 0x000C);
-        if (dev->phy.rev >= 3) {
+        /* TODO */
-                tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
-                tmp32 &= 0xffffff;
-                b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
-                b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
+        tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
-                b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
+                0x2 : 0x9C40;
-                b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
+        b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
-                b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
-                b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
-                b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
-                b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
+        b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
-                b43_phy_write(dev, 0x2AE, 0x000C);
-                /* TODO */
+        b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
+        b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
-                tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
+        b43_nphy_gain_ctrl_workarounds(dev);
-                        0x2 : 0x9C40;
-                b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
-                b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
+        b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
+        b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
-                b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
+        /* TODO */
-                b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
-                b43_nphy_gain_ctrl_workarounds(dev);
+        b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
+        b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
+        b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
+        b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
+        b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
+        b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
+        b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
+        b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
+        b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
+        b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
+        /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
+        if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
+             b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
+            (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
+             b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
+                tmp32 = 0x00088888;
+        else
+                tmp32 = 0x88888888;
+        b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
+        b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
+        b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
+        if (dev->phy.rev == 4 &&
+                b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
+                b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
+                                0x70);
+                b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
+                                0x70);
+        }
-                b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
+        b43_phy_write(dev, 0x224, 0x039C);
-                b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
+        b43_phy_write(dev, 0x225, 0x0357);
+        b43_phy_write(dev, 0x226, 0x0317);
+        b43_phy_write(dev, 0x227, 0x02D7);
+        b43_phy_write(dev, 0x228, 0x039C);
+        b43_phy_write(dev, 0x229, 0x0357);
+        b43_phy_write(dev, 0x22A, 0x0317);
+        b43_phy_write(dev, 0x22B, 0x02D7);
+        b43_phy_write(dev, 0x22C, 0x039C);
+        b43_phy_write(dev, 0x22D, 0x0357);
+        b43_phy_write(dev, 0x22E, 0x0317);
+        b43_phy_write(dev, 0x22F, 0x02D7);
+}
-                /* TODO */
+static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
+{
+        struct ssb_sprom *sprom = dev->dev->bus_sprom;
+        struct b43_phy *phy = &dev->phy;
+        struct b43_phy_n *nphy = phy->n;
-                b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
+        u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
-                b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
+        u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
-                b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
-                b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
-                b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
-                b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
-                b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
-                b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
-                b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
-                b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
-                /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
-                if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
-                    b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
-                    (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
-                    b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
-                        tmp32 = 0x00088888;
-                else
-                        tmp32 = 0x88888888;
-                b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
-                b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
-                b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
-                if (dev->phy.rev == 4 &&
-                    b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
-                        b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
-                                        0x70);
-                        b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
-                                        0x70);
-                }
-                b43_phy_write(dev, 0x224, 0x039C);
+        u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
-                b43_phy_write(dev, 0x225, 0x0357);
+        u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
-                b43_phy_write(dev, 0x226, 0x0317);
-                b43_phy_write(dev, 0x227, 0x02D7);
+        if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
-                b43_phy_write(dev, 0x228, 0x039C);
+            nphy->band5g_pwrgain) {
-                b43_phy_write(dev, 0x229, 0x0357);
+                b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
-                b43_phy_write(dev, 0x22A, 0x0317);
+                b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
-                b43_phy_write(dev, 0x22B, 0x02D7);
-                b43_phy_write(dev, 0x22C, 0x039C);
-                b43_phy_write(dev, 0x22D, 0x0357);
-                b43_phy_write(dev, 0x22E, 0x0317);
-                b43_phy_write(dev, 0x22F, 0x02D7);
        } else {
-                if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
+                b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
-                    nphy->band5g_pwrgain) {
+                b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
-                        b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
+        }
-                        b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
-                } else {
-                        b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
-                        b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
-                }
-                b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
+        b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
-                b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
+        b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
-                b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
+        b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
-                b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
+        b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
-                if (dev->phy.rev < 2) {
+        if (dev->phy.rev < 2) {
-                        b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
+                b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
-                        b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
+                b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
-                        b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
+                b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
-                        b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
+                b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
-                        b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
+                b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
-                        b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
+                b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
-                }
+        }
-                b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
+        b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
-                b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
+        b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
-                b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
+        b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
-                b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
+        b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
-                if (sprom->boardflags2_lo & 0x100 &&
+        if (sprom->boardflags2_lo & 0x100 &&
-                    dev->dev->board_type == 0x8B) {
+                dev->dev->board_type == 0x8B) {
-                        delays1[0] = 0x1;
+                delays1[0] = 0x1;
-                        delays1[5] = 0x14;
+                delays1[5] = 0x14;
-                }
+        }
-                b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
+        b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
-                b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
+        b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
-                b43_nphy_gain_ctrl_workarounds(dev);
+        b43_nphy_gain_ctrl_workarounds(dev);
-                if (dev->phy.rev < 2) {
+        if (dev->phy.rev < 2) {
-                        if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
+                if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
-                                b43_hf_write(dev, b43_hf_read(dev) |
+                        b43_hf_write(dev, b43_hf_read(dev) |
-                                                B43_HF_MLADVW);
+                                        B43_HF_MLADVW);
-                } else if (dev->phy.rev == 2) {
+        } else if (dev->phy.rev == 2) {
-                        b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
+                b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
-                        b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
+                b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
-                }
+        }
-                if (dev->phy.rev < 2)
+        if (dev->phy.rev < 2)
-                        b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
+                b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
-                                        ~B43_NPHY_SCRAM_SIGCTL_SCM);
+                                ~B43_NPHY_SCRAM_SIGCTL_SCM);
+        /* Set phase track alpha and beta */
+        b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
+        b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
+        b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
+        b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
+        b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
+        b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
+        b43_phy_mask(dev, B43_NPHY_PIL_DW1,
+                        ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
+        b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
+        b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
+        b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
+        if (dev->phy.rev == 2)
+                b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
+                                B43_NPHY_FINERX2_CGC_DECGC);
+}
-                /* Set phase track alpha and beta */
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
-                b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
+static void b43_nphy_workarounds(struct b43_wldev *dev)
-                b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
+{
-                b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
+        struct b43_phy *phy = &dev->phy;
-                b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
+        struct b43_phy_n *nphy = phy->n;
-                b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
-                b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
-                b43_phy_mask(dev, B43_NPHY_PIL_DW1,
+        if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
-                                ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
+                b43_nphy_classifier(dev, 1, 0);
-                b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
+        else
-                b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
+                b43_nphy_classifier(dev, 1, 1);
-                b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
-                if (dev->phy.rev == 2)
+        if (nphy->hang_avoid)
-                        b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
+                b43_nphy_stay_in_carrier_search(dev, 1);
-                                        B43_NPHY_FINERX2_CGC_DECGC);
-        }
+        b43_phy_set(dev, B43_NPHY_IQFLIP,
+                    B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
+        if (dev->phy.rev >= 3)
+                b43_nphy_workarounds_rev3plus(dev);
+        else
+                b43_nphy_workarounds_rev1_2(dev);
        if (nphy->hang_avoid)
                b43_nphy_stay_in_carrier_search(dev, 0);
author	Rafał Miłecki <zajec5@gmail.com>	2011-09-04 17:23:52 -0400
committer	John W. Linville <linville@tuxdriver.com>	2011-09-14 13:56:29 -0400
commit	73d07a39ee3eadb9ff6734432151a10c50329804 (patch)
tree	95c4f64aeb491fd561ba82dd8ef734e3439eb25b
parent	44f4008b5983f058fbea6d238f8c78908676d092 (diff)

diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c index c291ae576b3d..8647933f9321 100644 --- a/drivers/net/wireless/b43/phy_n.c +++ b/drivers/net/wireless/b43/phy_n.c
@@ -1428,180 +1428,194 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
1428	}	1428	}
1429	}	1429	}
1430		1430
1431	/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */	1431	static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1432	static void b43_nphy_workarounds(struct b43_wldev *dev)
1433	{	1432	{
1434	struct ssb_sprom *sprom = dev->dev->bus_sprom;	1433	struct ssb_sprom *sprom = dev->dev->bus_sprom;
1435	struct b43_phy *phy = &dev->phy;
1436	struct b43_phy_n *nphy = phy->n;
1437
1438	u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1439	u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1440
1441	u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1442	u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1443		1434
1444	u16 tmp16;	1435	u16 tmp16;
1445	u32 tmp32;	1436	u32 tmp32;
1446		1437
1447	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)	1438	tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1448	b43_nphy_classifier(dev, 1, 0);	1439	tmp32 &= 0xffffff;
1449	else	1440	b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1450	b43_nphy_classifier(dev, 1, 1);
1451		1441
1452	if (nphy->hang_avoid)	1442	b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1453	b43_nphy_stay_in_carrier_search(dev, 1);	1443	b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
		1444	b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
		1445	b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
		1446	b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
		1447	b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1454		1448
1455	b43_phy_set(dev, B43_NPHY_IQFLIP,	1449	b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1456	B43_NPHY_IQFLIP_ADC1 \| B43_NPHY_IQFLIP_ADC2);	1450	b43_phy_write(dev, 0x2AE, 0x000C);
1457		1451
1458	if (dev->phy.rev >= 3) {	1452	/* TODO */
1459	tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1460	tmp32 &= 0xffffff;
1461	b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1462		1453
1463	b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);	1454	tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1464	b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);	1455	0x2 : 0x9C40;
1465	b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);	1456	b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1466	b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1467	b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1468	b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1469		1457
1470	b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);	1458	b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1471	b43_phy_write(dev, 0x2AE, 0x000C);
1472		1459
1473	/* TODO */	1460	b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
		1461	b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1474		1462
1475	tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?	1463	b43_nphy_gain_ctrl_workarounds(dev);
1476	0x2 : 0x9C40;
1477	b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1478		1464
1479	b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);	1465	b43_ntab_write(dev, B43_NTAB32(8, 0), 2);
		1466	b43_ntab_write(dev, B43_NTAB32(8, 16), 2);
1480		1467
1481	b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);	1468	/* TODO */
1482	b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1483		1469
1484	b43_nphy_gain_ctrl_workarounds(dev);	1470	b43_radio_write(dev, B2056_RX0 \| B2056_RX_MIXA_MAST_BIAS, 0x00);
		1471	b43_radio_write(dev, B2056_RX1 \| B2056_RX_MIXA_MAST_BIAS, 0x00);
		1472	b43_radio_write(dev, B2056_RX0 \| B2056_RX_MIXA_BIAS_MAIN, 0x06);
		1473	b43_radio_write(dev, B2056_RX1 \| B2056_RX_MIXA_BIAS_MAIN, 0x06);
		1474	b43_radio_write(dev, B2056_RX0 \| B2056_RX_MIXA_BIAS_AUX, 0x07);
		1475	b43_radio_write(dev, B2056_RX1 \| B2056_RX_MIXA_BIAS_AUX, 0x07);
		1476	b43_radio_write(dev, B2056_RX0 \| B2056_RX_MIXA_LOB_BIAS, 0x88);
		1477	b43_radio_write(dev, B2056_RX1 \| B2056_RX_MIXA_LOB_BIAS, 0x88);
		1478	b43_radio_write(dev, B2056_RX0 \| B2056_RX_MIXG_CMFB_IDAC, 0x00);
		1479	b43_radio_write(dev, B2056_RX1 \| B2056_RX_MIXG_CMFB_IDAC, 0x00);
		1480
		1481	/* N PHY WAR TX Chain Update with hw_phytxchain as argument */
		1482
		1483	if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
		1484	b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) \|\|
		1485	(sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
		1486	b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
		1487	tmp32 = 0x00088888;
		1488	else
		1489	tmp32 = 0x88888888;
		1490	b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
		1491	b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
		1492	b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
		1493
		1494	if (dev->phy.rev == 4 &&
		1495	b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
		1496	b43_radio_write(dev, B2056_TX0 \| B2056_TX_GMBB_IDAC,
		1497	0x70);
		1498	b43_radio_write(dev, B2056_TX1 \| B2056_TX_GMBB_IDAC,
		1499	0x70);
		1500	}
1485		1501
1486	b43_ntab_write(dev, B43_NTAB32(8, 0), 2);	1502	b43_phy_write(dev, 0x224, 0x039C);
1487	b43_ntab_write(dev, B43_NTAB32(8, 16), 2);	1503	b43_phy_write(dev, 0x225, 0x0357);
		1504	b43_phy_write(dev, 0x226, 0x0317);
		1505	b43_phy_write(dev, 0x227, 0x02D7);
		1506	b43_phy_write(dev, 0x228, 0x039C);
		1507	b43_phy_write(dev, 0x229, 0x0357);
		1508	b43_phy_write(dev, 0x22A, 0x0317);
		1509	b43_phy_write(dev, 0x22B, 0x02D7);
		1510	b43_phy_write(dev, 0x22C, 0x039C);
		1511	b43_phy_write(dev, 0x22D, 0x0357);
		1512	b43_phy_write(dev, 0x22E, 0x0317);
		1513	b43_phy_write(dev, 0x22F, 0x02D7);
		1514	}
1488		1515
1489	/* TODO */	1516	static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
		1517	{
		1518	struct ssb_sprom *sprom = dev->dev->bus_sprom;
		1519	struct b43_phy *phy = &dev->phy;
		1520	struct b43_phy_n *nphy = phy->n;
1490		1521
1491	b43_radio_write(dev, B2056_RX0 \| B2056_RX_MIXA_MAST_BIAS, 0x00);	1522	u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1492	b43_radio_write(dev, B2056_RX1 \| B2056_RX_MIXA_MAST_BIAS, 0x00);	1523	u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1493	b43_radio_write(dev, B2056_RX0 \| B2056_RX_MIXA_BIAS_MAIN, 0x06);
1494	b43_radio_write(dev, B2056_RX1 \| B2056_RX_MIXA_BIAS_MAIN, 0x06);
1495	b43_radio_write(dev, B2056_RX0 \| B2056_RX_MIXA_BIAS_AUX, 0x07);
1496	b43_radio_write(dev, B2056_RX1 \| B2056_RX_MIXA_BIAS_AUX, 0x07);
1497	b43_radio_write(dev, B2056_RX0 \| B2056_RX_MIXA_LOB_BIAS, 0x88);
1498	b43_radio_write(dev, B2056_RX1 \| B2056_RX_MIXA_LOB_BIAS, 0x88);
1499	b43_radio_write(dev, B2056_RX0 \| B2056_RX_MIXG_CMFB_IDAC, 0x00);
1500	b43_radio_write(dev, B2056_RX1 \| B2056_RX_MIXG_CMFB_IDAC, 0x00);
1501
1502	/* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1503
1504	if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1505	b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) \|\|
1506	(sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1507	b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1508	tmp32 = 0x00088888;
1509	else
1510	tmp32 = 0x88888888;
1511	b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1512	b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1513	b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1514
1515	if (dev->phy.rev == 4 &&
1516	b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1517	b43_radio_write(dev, B2056_TX0 \| B2056_TX_GMBB_IDAC,
1518	0x70);
1519	b43_radio_write(dev, B2056_TX1 \| B2056_TX_GMBB_IDAC,
1520	0x70);
1521	}
1522		1524
1523	b43_phy_write(dev, 0x224, 0x039C);	1525	u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1524	b43_phy_write(dev, 0x225, 0x0357);	1526	u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1525	b43_phy_write(dev, 0x226, 0x0317);	1527
1526	b43_phy_write(dev, 0x227, 0x02D7);	1528	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1527	b43_phy_write(dev, 0x228, 0x039C);	1529	nphy->band5g_pwrgain) {
1528	b43_phy_write(dev, 0x229, 0x0357);	1530	b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1529	b43_phy_write(dev, 0x22A, 0x0317);	1531	b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1530	b43_phy_write(dev, 0x22B, 0x02D7);
1531	b43_phy_write(dev, 0x22C, 0x039C);
1532	b43_phy_write(dev, 0x22D, 0x0357);
1533	b43_phy_write(dev, 0x22E, 0x0317);
1534	b43_phy_write(dev, 0x22F, 0x02D7);
1535	} else {	1532	} else {
1536	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&	1533	b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1537	nphy->band5g_pwrgain) {	1534	b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1538	b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);	1535	}
1539	b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1540	} else {
1541	b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1542	b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1543	}
1544		1536
1545	b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);	1537	b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
1546	b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);	1538	b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
1547	b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);	1539	b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
1548	b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);	1540	b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
1549		1541
1550	if (dev->phy.rev < 2) {	1542	if (dev->phy.rev < 2) {
1551	b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);	1543	b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
1552	b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);	1544	b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
1553	b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);	1545	b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
1554	b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);	1546	b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
1555	b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);	1547	b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
1556	b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);	1548	b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
1557	}	1549	}
1558		1550
1559	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);	1551	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1560	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);	1552	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1561	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);	1553	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1562	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);	1554	b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1563		1555
1564	if (sprom->boardflags2_lo & 0x100 &&	1556	if (sprom->boardflags2_lo & 0x100 &&
1565	dev->dev->board_type == 0x8B) {	1557	dev->dev->board_type == 0x8B) {
1566	delays1[0] = 0x1;	1558	delays1[0] = 0x1;
1567	delays1[5] = 0x14;	1559	delays1[5] = 0x14;
1568	}	1560	}
1569	b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);	1561	b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1570	b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);	1562	b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1571		1563
1572	b43_nphy_gain_ctrl_workarounds(dev);	1564	b43_nphy_gain_ctrl_workarounds(dev);
1573		1565
1574	if (dev->phy.rev < 2) {	1566	if (dev->phy.rev < 2) {
1575	if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)	1567	if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1576	b43_hf_write(dev, b43_hf_read(dev) \|	1568	b43_hf_write(dev, b43_hf_read(dev) \|
1577	B43_HF_MLADVW);	1569	B43_HF_MLADVW);
1578	} else if (dev->phy.rev == 2) {	1570	} else if (dev->phy.rev == 2) {
1579	b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);	1571	b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1580	b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);	1572	b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1581	}	1573	}
1582		1574
1583	if (dev->phy.rev < 2)	1575	if (dev->phy.rev < 2)
1584	b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,	1576	b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1585	~B43_NPHY_SCRAM_SIGCTL_SCM);	1577	~B43_NPHY_SCRAM_SIGCTL_SCM);
		1578
		1579	/* Set phase track alpha and beta */
		1580	b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
		1581	b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
		1582	b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
		1583	b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
		1584	b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
		1585	b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
		1586
		1587	b43_phy_mask(dev, B43_NPHY_PIL_DW1,
		1588	~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
		1589	b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
		1590	b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
		1591	b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
		1592
		1593	if (dev->phy.rev == 2)
		1594	b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
		1595	B43_NPHY_FINERX2_CGC_DECGC);
		1596	}
1586		1597
1587	/* Set phase track alpha and beta */	1598	/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1588	b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);	1599	static void b43_nphy_workarounds(struct b43_wldev *dev)
1589	b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);	1600	{
1590	b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);	1601	struct b43_phy *phy = &dev->phy;
1591	b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);	1602	struct b43_phy_n *nphy = phy->n;
1592	b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1593	b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1594		1603
1595	b43_phy_mask(dev, B43_NPHY_PIL_DW1,	1604	if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1596	~B43_NPHY_PIL_DW_64QAM & 0xFFFF);	1605	b43_nphy_classifier(dev, 1, 0);
1597	b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);	1606	else
1598	b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);	1607	b43_nphy_classifier(dev, 1, 1);
1599	b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1600		1608
1601	if (dev->phy.rev == 2)	1609	if (nphy->hang_avoid)
1602	b43_phy_set(dev, B43_NPHY_FINERX2_CGC,	1610	b43_nphy_stay_in_carrier_search(dev, 1);
1603	B43_NPHY_FINERX2_CGC_DECGC);	1611
1604	}	1612	b43_phy_set(dev, B43_NPHY_IQFLIP,
		1613	B43_NPHY_IQFLIP_ADC1 \| B43_NPHY_IQFLIP_ADC2);
		1614
		1615	if (dev->phy.rev >= 3)
		1616	b43_nphy_workarounds_rev3plus(dev);
		1617	else
		1618	b43_nphy_workarounds_rev1_2(dev);
1605		1619
1606	if (nphy->hang_avoid)	1620	if (nphy->hang_avoid)
1607	b43_nphy_stay_in_carrier_search(dev, 0);	1621	b43_nphy_stay_in_carrier_search(dev, 0);