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authorGábor Stefanik <netrolller.3d@gmail.com>2009-08-02 19:28:12 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-08-04 16:44:24 -0400
commit738f0f4301587ad09b58651390b122205086b484 (patch)
tree6d5f51d1980db2ef37537b0bc6c1a5a694324e40
parentd8cc8926e9b4dc2ce513ee3325bf16b4ea6d94e8 (diff)
b43: implement baseband init for LP-PHY <= rev1
Implement baseband init for rev.0 and rev.1 LP PHYs. Convert boardflags_hi values to defines. Implement b43_phy_copy for easier copying between registers, as needed by LP-PHY init. Signed-off-by: Gábor Stefanik<netrolller.3d@gmail.com> Cc: Michael Buesch<mb@bu3sch.de> Cc: Larry Finger<larry.finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/b43/b43.h11
-rw-r--r--drivers/net/wireless/b43/phy_common.c7
-rw-r--r--drivers/net/wireless/b43/phy_common.h5
-rw-r--r--drivers/net/wireless/b43/phy_lp.c94
-rw-r--r--drivers/net/wireless/b43/phy_lp.h11
-rw-r--r--drivers/net/wireless/b43/phy_n.c3
6 files changed, 127 insertions, 4 deletions
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index 40448067e4cc..b6811cff18ba 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -142,6 +142,17 @@
142#define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ 142#define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
143#define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ 143#define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
144 144
145/* SPROM boardflags_hi values */
146#define B43_BFH_NOPA 0x0001 /* has no PA */
147#define B43_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
148#define B43_BFH_PAREF 0x0004 /* uses the PARef LDO */
149#define B43_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared
150 * with bluetooth */
151#define B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
152#define B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */
153#define B43_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna
154 * with bluetooth */
155
145/* GPIO register offset, in both ChipCommon and PCI core. */ 156/* GPIO register offset, in both ChipCommon and PCI core. */
146#define B43_GPIO_CONTROL 0x6c 157#define B43_GPIO_CONTROL 0x6c
147 158
diff --git a/drivers/net/wireless/b43/phy_common.c b/drivers/net/wireless/b43/phy_common.c
index f537bfef690a..51686ec96984 100644
--- a/drivers/net/wireless/b43/phy_common.c
+++ b/drivers/net/wireless/b43/phy_common.c
@@ -240,6 +240,13 @@ void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
240 dev->phy.ops->phy_write(dev, reg, value); 240 dev->phy.ops->phy_write(dev, reg, value);
241} 241}
242 242
243void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
244{
245 assert_mac_suspended(dev);
246 dev->phy.ops->phy_write(dev, destreg,
247 dev->phy.ops->phy_read(dev, srcreg));
248}
249
243void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask) 250void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
244{ 251{
245 b43_phy_write(dev, offset, 252 b43_phy_write(dev, offset,
diff --git a/drivers/net/wireless/b43/phy_common.h b/drivers/net/wireless/b43/phy_common.h
index 44cc918e4fc6..9f9f23cab72a 100644
--- a/drivers/net/wireless/b43/phy_common.h
+++ b/drivers/net/wireless/b43/phy_common.h
@@ -291,6 +291,11 @@ u16 b43_phy_read(struct b43_wldev *dev, u16 reg);
291void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value); 291void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value);
292 292
293/** 293/**
294 * b43_phy_copy - copy contents of 16bit PHY register to another
295 */
296void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg);
297
298/**
294 * b43_phy_mask - Mask a PHY register with a mask 299 * b43_phy_mask - Mask a PHY register with a mask
295 */ 300 */
296void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask); 301void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask);
diff --git a/drivers/net/wireless/b43/phy_lp.c b/drivers/net/wireless/b43/phy_lp.c
index ea0d3a3a6a64..aa1486a1354b 100644
--- a/drivers/net/wireless/b43/phy_lp.c
+++ b/drivers/net/wireless/b43/phy_lp.c
@@ -66,7 +66,99 @@ static void lpphy_table_init(struct b43_wldev *dev)
66 66
67static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev) 67static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
68{ 68{
69 B43_WARN_ON(1);//TODO rev < 2 not supported, yet. 69 struct ssb_bus *bus = dev->dev->bus;
70 u16 tmp, tmp2;
71
72 if (dev->phy.rev == 1 &&
73 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
74 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
75 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
76 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
77 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
78 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
79 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
80 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
81 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
82 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
83 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
84 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
85 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
86 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
87 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
88 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
89 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
90 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
91 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
92 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
93 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
94 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
95 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
96 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
97 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
98 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
99 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
100 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
101 } else if (dev->phy.rev == 1 ||
102 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
103 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
104 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
105 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
106 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
107 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
108 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
109 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
110 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
111 } else {
112 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
113 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
114 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
115 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
116 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
117 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
118 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
119 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
120 }
121 if (dev->phy.rev == 1) {
122 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
123 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
124 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
125 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
126 }
127 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
128 (bus->chip_id == 0x5354) &&
129 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
130 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
131 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
132 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
133 b43_hf_write(dev, b43_hf_read(dev) | 0x0800ULL << 32);
134 }
135 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
136 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
137 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
138 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
139 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
140 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
141 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
142 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
143 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
144 } else { /* 5GHz */
145 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
146 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
147 }
148 if (dev->phy.rev == 1) {
149 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
150 tmp2 = (tmp & 0x03E0) >> 5;
151 tmp2 |= tmp << 5;
152 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
153 tmp = b43_phy_read(dev, B43_LPPHY_OFDMSYNCTHRESH0);
154 tmp2 = (tmp & 0x1F00) >> 8;
155 tmp2 |= tmp << 5;
156 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
157 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
158 tmp2 = tmp & 0x00FF;
159 tmp2 |= tmp << 8;
160 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
161 }
70} 162}
71 163
72static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev) 164static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
diff --git a/drivers/net/wireless/b43/phy_lp.h b/drivers/net/wireless/b43/phy_lp.h
index 18370b4ac38e..829b2bba3ee1 100644
--- a/drivers/net/wireless/b43/phy_lp.h
+++ b/drivers/net/wireless/b43/phy_lp.h
@@ -273,12 +273,19 @@
273#define B43_LPPHY_AFE_DDFS_POINTER_INIT B43_PHY_OFDM(0xB8) /* AFE DDFS pointer init */ 273#define B43_LPPHY_AFE_DDFS_POINTER_INIT B43_PHY_OFDM(0xB8) /* AFE DDFS pointer init */
274#define B43_LPPHY_AFE_DDFS_INCR_INIT B43_PHY_OFDM(0xB9) /* AFE DDFS incr init */ 274#define B43_LPPHY_AFE_DDFS_INCR_INIT B43_PHY_OFDM(0xB9) /* AFE DDFS incr init */
275#define B43_LPPHY_MRCNOISEREDUCTION B43_PHY_OFDM(0xBA) /* mrcNoiseReduction */ 275#define B43_LPPHY_MRCNOISEREDUCTION B43_PHY_OFDM(0xBA) /* mrcNoiseReduction */
276#define B43_LPPHY_TRLOOKUP3 B43_PHY_OFDM(0xBB) /* TRLookup3 */ 276#define B43_LPPHY_TR_LOOKUP_3 B43_PHY_OFDM(0xBB) /* TR Lookup 3 */
277#define B43_LPPHY_TRLOOKUP4 B43_PHY_OFDM(0xBC) /* TRLookup4 */ 277#define B43_LPPHY_TR_LOOKUP_4 B43_PHY_OFDM(0xBC) /* TR Lookup 4 */
278#define B43_LPPHY_RADAR_FIFO_STAT B43_PHY_OFDM(0xBD) /* Radar FIFO Status */ 278#define B43_LPPHY_RADAR_FIFO_STAT B43_PHY_OFDM(0xBD) /* Radar FIFO Status */
279#define B43_LPPHY_GPIO_OUTEN B43_PHY_OFDM(0xBE) /* GPIO Out enable */ 279#define B43_LPPHY_GPIO_OUTEN B43_PHY_OFDM(0xBE) /* GPIO Out enable */
280#define B43_LPPHY_GPIO_SELECT B43_PHY_OFDM(0xBF) /* GPIO Select */ 280#define B43_LPPHY_GPIO_SELECT B43_PHY_OFDM(0xBF) /* GPIO Select */
281#define B43_LPPHY_GPIO_OUT B43_PHY_OFDM(0xC0) /* GPIO Out */ 281#define B43_LPPHY_GPIO_OUT B43_PHY_OFDM(0xC0) /* GPIO Out */
282#define B43_LPPHY_4C3 B43_PHY_OFDM(0xC3) /* unknown, used during BB init */
283#define B43_LPPHY_4C4 B43_PHY_OFDM(0xC4) /* unknown, used during BB init */
284#define B43_LPPHY_4C5 B43_PHY_OFDM(0xC5) /* unknown, used during BB init */
285#define B43_LPPHY_TR_LOOKUP_5 B43_PHY_OFDM(0xC7) /* TR Lookup 5 */
286#define B43_LPPHY_TR_LOOKUP_6 B43_PHY_OFDM(0xC8) /* TR Lookup 6 */
287#define B43_LPPHY_TR_LOOKUP_7 B43_PHY_OFDM(0xC9) /* TR Lookup 7 */
288#define B43_LPPHY_TR_LOOKUP_8 B43_PHY_OFDM(0xCA) /* TR Lookup 8 */
282 289
283 290
284 291
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index be7b5604947b..992318a78077 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -137,7 +137,8 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
137 137
138 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); 138 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
139 msleep(1); 139 msleep(1);
140 if ((sprom->revision != 4) || !(sprom->boardflags_hi & 0x0002)) { 140 if ((sprom->revision != 4) ||
141 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
141 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) || 142 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
142 (binfo->type != 0x46D) || 143 (binfo->type != 0x46D) ||
143 (binfo->rev < 0x41)) { 144 (binfo->rev < 0x41)) {