drm/i915: add support for physical memory objects

This is an initial patch to do support for objects which needs physical
contiguous main ram, cursors and overlay registers on older chipsets.

These objects are bound on cursor bin, like pinning, and we copy
the data to/from the backing store object into the real one on attach/detach.

notes:
possible over the top in attach/detach operations.
no overlay support yet.

Signed-off-by: Dave Airlie <airlied@redhat.com>

4 files changed, 233 insertions, 13 deletions

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 868f574363ad..bbadf1c04142 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1160,6 +1160,8 @@ int i915_driver_unload(struct drm_device *dev)
         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
                 intel_modeset_cleanup(dev);
 
+                i915_gem_free_all_phys_object(dev);
+
                 mutex_lock(&dev->struct_mutex);
                 i915_gem_cleanup_ringbuffer(dev);
                 mutex_unlock(&dev->struct_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 563de18063fd..e13518252007 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -72,6 +72,18 @@ enum pipe {
 #define WATCH_INACTIVE  0
 #define WATCH_PWRITE    0
 
+#define I915_GEM_PHYS_CURSOR_0 1
+#define I915_GEM_PHYS_CURSOR_1 2
+#define I915_GEM_PHYS_OVERLAY_REGS 3
+#define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
+
+struct drm_i915_gem_phys_object {
+        int id;
+        struct page **page_list;
+        drm_dma_handle_t *handle;
+        struct drm_gem_object *cur_obj;
+};
+
 typedef struct _drm_i915_ring_buffer {
         int tail_mask;
         unsigned long Size;
@@ -358,6 +370,9 @@ typedef struct drm_i915_private {
                 uint32_t bit_6_swizzle_x;
                 /** Bit 6 swizzling required for Y tiling */
                 uint32_t bit_6_swizzle_y;
+
+                /* storage for physical objects */
+                struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
         } mm;
 } drm_i915_private_t;
 
@@ -436,6 +451,9 @@ struct drm_i915_gem_object {
         /** User space pin count and filp owning the pin */
         uint32_t user_pin_count;
         struct drm_file *pin_filp;
+
+        /** for phy allocated objects */
+        struct drm_i915_gem_phys_object *phys_obj;
 };
 
 /**
@@ -598,6 +616,11 @@ int i915_gem_do_init(struct drm_device *dev, unsigned long start,
 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
                                       int write);
+int i915_gem_attach_phys_object(struct drm_device *dev,
+                                struct drm_gem_object *obj, int id);
+void i915_gem_detach_phys_object(struct drm_device *dev,
+                                 struct drm_gem_object *obj);
+void i915_gem_free_all_phys_object(struct drm_device *dev);
 
 /* i915_gem_tiling.c */
 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 1384d6686555..96316fd47233 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -55,6 +55,9 @@ static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
 static void i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
 static int i915_gem_evict_something(struct drm_device *dev);
+static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
+                                struct drm_i915_gem_pwrite *args,
+                                struct drm_file *file_priv);
 
 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
                      unsigned long end)
@@ -386,8 +389,10 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
          * pread/pwrite currently are reading and writing from the CPU
          * perspective, requiring manual detiling by the client.
          */
-        if (obj_priv->tiling_mode == I915_TILING_NONE &&
-            dev->gtt_total != 0)
+        if (obj_priv->phys_obj)
+                ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
+        else if (obj_priv->tiling_mode == I915_TILING_NONE &&
+                 dev->gtt_total != 0)
                 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
         else
                 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
@@ -2858,6 +2863,9 @@ void i915_gem_free_object(struct drm_gem_object *obj)
         while (obj_priv->pin_count > 0)
                 i915_gem_object_unpin(obj);
 
+        if (obj_priv->phys_obj)
+                i915_gem_detach_phys_object(dev, obj);
+
         i915_gem_object_unbind(obj);
 
         list = &obj->map_list;
@@ -3293,3 +3301,180 @@ i915_gem_load(struct drm_device *dev)
 
         i915_gem_detect_bit_6_swizzle(dev);
 }
+
+/*
+ * Create a physically contiguous memory object for this object
+ * e.g. for cursor + overlay regs
+ */
+int i915_gem_init_phys_object(struct drm_device *dev,
+                              int id, int size)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        struct drm_i915_gem_phys_object *phys_obj;
+        int ret;
+
+        if (dev_priv->mm.phys_objs[id - 1] || !size)
+                return 0;
+
+        phys_obj = drm_calloc(1, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
+        if (!phys_obj)
+                return -ENOMEM;
+
+        phys_obj->id = id;
+
+        phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
+        if (!phys_obj->handle) {
+                ret = -ENOMEM;
+                goto kfree_obj;
+        }
+#ifdef CONFIG_X86
+        set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
+#endif
+
+        dev_priv->mm.phys_objs[id - 1] = phys_obj;
+
+        return 0;
+kfree_obj:
+        drm_free(phys_obj, sizeof(struct drm_i915_gem_phys_object), DRM_MEM_DRIVER);
+        return ret;
+}
+
+void i915_gem_free_phys_object(struct drm_device *dev, int id)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        struct drm_i915_gem_phys_object *phys_obj;
+
+        if (!dev_priv->mm.phys_objs[id - 1])
+                return;
+
+        phys_obj = dev_priv->mm.phys_objs[id - 1];
+        if (phys_obj->cur_obj) {
+                i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
+        }
+
+#ifdef CONFIG_X86
+        set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
+#endif
+        drm_pci_free(dev, phys_obj->handle);
+        kfree(phys_obj);
+        dev_priv->mm.phys_objs[id - 1] = NULL;
+}
+
+void i915_gem_free_all_phys_object(struct drm_device *dev)
+{