diff options
author | Wang Dongsheng <dongsheng.wang@freescale.com> | 2013-12-17 03:16:59 -0500 |
---|---|---|
committer | Scott Wood <scottwood@freescale.com> | 2014-01-07 20:29:23 -0500 |
commit | 71a6fa17e1526d3f26f4711cc55d339f96c49a95 (patch) | |
tree | 524d05b5382d59a3ff096cc02d13522150f96275 | |
parent | 1e83bf875e1eb14f99b3ce1cb5580a09f18ac8af (diff) |
powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 define
E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec
idle patches.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
-rw-r--r-- | arch/powerpc/include/asm/reg.h | 2 | ||||
-rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 9 |
2 files changed, 11 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index fa8388ed94c5..62b114e079cf 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
@@ -1075,6 +1075,8 @@ | |||
1075 | #define PVR_8560 0x80200000 | 1075 | #define PVR_8560 0x80200000 |
1076 | #define PVR_VER_E500V1 0x8020 | 1076 | #define PVR_VER_E500V1 0x8020 |
1077 | #define PVR_VER_E500V2 0x8021 | 1077 | #define PVR_VER_E500V2 0x8021 |
1078 | #define PVR_VER_E6500 0x8040 | ||
1079 | |||
1078 | /* | 1080 | /* |
1079 | * For the 8xx processors, all of them report the same PVR family for | 1081 | * For the 8xx processors, all of them report the same PVR family for |
1080 | * the PowerPC core. The various versions of these processors must be | 1082 | * the PowerPC core. The various versions of these processors must be |
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 1f7134dd0946..163c3b05a76e 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h | |||
@@ -171,6 +171,7 @@ | |||
171 | #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ | 171 | #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status Register 1 */ |
172 | #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ | 172 | #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ |
173 | #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ | 173 | #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ |
174 | #define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */ | ||
174 | #define SPRN_SVR 0x3FF /* System Version Register */ | 175 | #define SPRN_SVR 0x3FF /* System Version Register */ |
175 | 176 | ||
176 | /* | 177 | /* |
@@ -217,6 +218,14 @@ | |||
217 | #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ | 218 | #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ |
218 | #define CCR1_TCS 0x00000080 /* Timer Clock Select */ | 219 | #define CCR1_TCS 0x00000080 /* Timer Clock Select */ |
219 | 220 | ||
221 | /* Bit definitions for PWRMGTCR0. */ | ||
222 | #define PWRMGTCR0_PW20_WAIT (1 << 14) /* PW20 state enable bit */ | ||
223 | #define PWRMGTCR0_PW20_ENT_SHIFT 8 | ||
224 | #define PWRMGTCR0_PW20_ENT 0x3F00 | ||
225 | #define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22) /* Altivec idle enable */ | ||
226 | #define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16 | ||
227 | #define PWRMGTCR0_AV_IDLE_CNT 0x3F0000 | ||
228 | |||
220 | /* Bit definitions for the MCSR. */ | 229 | /* Bit definitions for the MCSR. */ |
221 | #define MCSR_MCS 0x80000000 /* Machine Check Summary */ | 230 | #define MCSR_MCS 0x80000000 /* Machine Check Summary */ |
222 | #define MCSR_IB 0x40000000 /* Instruction PLB Error */ | 231 | #define MCSR_IB 0x40000000 /* Instruction PLB Error */ |