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authorDavid Howells <dhowells@redhat.com>2012-10-04 13:21:50 -0400
committerDavid Howells <dhowells@redhat.com>2012-10-04 13:21:50 -0400
commit718dcedd7e87f448a1eeeda4d1a986284c243110 (patch)
tree48bd3730e4eea9c359d94ae4e990c2d9c574931b
parentf3dfd599af993385b40fc7a1c947afc12729bc4d (diff)
UAPI: (Scripted) Disintegrate include/drm
Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Michael Kerrisk <mtk.manpages@gmail.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Acked-by: Dave Jones <davej@redhat.com>
Diffstat
-rw-r--r--include/drm/Kbuild15
-rw-r--r--include/drm/exynos_drm.h174
-rw-r--r--include/drm/i915_drm.h920
-rw-r--r--include/uapi/drm/Kbuild15
-rw-r--r--include/uapi/drm/drm.h (renamed from include/drm/drm.h)0
-rw-r--r--include/uapi/drm/drm_fourcc.h (renamed from include/drm/drm_fourcc.h)0
-rw-r--r--include/uapi/drm/drm_mode.h (renamed from include/drm/drm_mode.h)0
-rw-r--r--include/uapi/drm/drm_sarea.h (renamed from include/drm/drm_sarea.h)0
-rw-r--r--include/uapi/drm/exynos_drm.h203
-rw-r--r--include/uapi/drm/i810_drm.h (renamed from include/drm/i810_drm.h)0
-rw-r--r--include/uapi/drm/i915_drm.h947
-rw-r--r--include/uapi/drm/mga_drm.h (renamed from include/drm/mga_drm.h)0
-rw-r--r--include/uapi/drm/nouveau_drm.h (renamed from include/drm/nouveau_drm.h)0
-rw-r--r--include/uapi/drm/r128_drm.h (renamed from include/drm/r128_drm.h)0
-rw-r--r--include/uapi/drm/radeon_drm.h (renamed from include/drm/radeon_drm.h)0
-rw-r--r--include/uapi/drm/savage_drm.h (renamed from include/drm/savage_drm.h)0
-rw-r--r--include/uapi/drm/sis_drm.h (renamed from include/drm/sis_drm.h)0
-rw-r--r--include/uapi/drm/via_drm.h (renamed from include/drm/via_drm.h)0
-rw-r--r--include/uapi/drm/vmwgfx_drm.h (renamed from include/drm/vmwgfx_drm.h)0
19 files changed, 1167 insertions, 1107 deletions
diff --git a/include/drm/Kbuild b/include/drm/Kbuild
index 1e38a19d68f6..e69de29bb2d1 100644
--- a/include/drm/Kbuild
+++ b/include/drm/Kbuild
@@ -1,15 +0,0 @@
1header-y += drm.h
2header-y += drm_fourcc.h
3header-y += drm_mode.h
4header-y += drm_sarea.h
5header-y += exynos_drm.h
6header-y += i810_drm.h
7header-y += i915_drm.h
8header-y += mga_drm.h
9header-y += nouveau_drm.h
10header-y += r128_drm.h
11header-y += radeon_drm.h
12header-y += savage_drm.h
13header-y += sis_drm.h
14header-y += via_drm.h
15header-y += vmwgfx_drm.h
diff --git a/include/drm/exynos_drm.h b/include/drm/exynos_drm.h
index 1f2acdfbfd6d..0fcc185bf147 100644
--- a/include/drm/exynos_drm.h
+++ b/include/drm/exynos_drm.h
@@ -25,182 +25,11 @@
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE. 26 * OTHER DEALINGS IN THE SOFTWARE.
27 */ 27 */
28
29#ifndef _EXYNOS_DRM_H_ 28#ifndef _EXYNOS_DRM_H_
30#define _EXYNOS_DRM_H_ 29#define _EXYNOS_DRM_H_
31 30
32#include <drm/drm.h> 31#include <uapi/drm/exynos_drm.h>
33
34/**
35 * User-desired buffer creation information structure.
36 *
37 * @size: user-desired memory allocation size.
38 * - this size value would be page-aligned internally.
39 * @flags: user request for setting memory type or cache attributes.
40 * @handle: returned a handle to created gem object.
41 * - this handle will be set by gem module of kernel side.
42 */
43struct drm_exynos_gem_create {
44 uint64_t size;
45 unsigned int flags;
46 unsigned int handle;
47};
48
49/**
50 * A structure for getting buffer offset.
51 *
52 * @handle: a pointer to gem object created.
53 * @pad: just padding to be 64-bit aligned.
54 * @offset: relatived offset value of the memory region allocated.
55 * - this value should be set by user.
56 */
57struct drm_exynos_gem_map_off {
58 unsigned int handle;
59 unsigned int pad;
60 uint64_t offset;
61};
62
63/**
64 * A structure for mapping buffer.
65 *
66 * @handle: a handle to gem object created.
67 * @pad: just padding to be 64-bit aligned.
68 * @size: memory size to be mapped.
69 * @mapped: having user virtual address mmaped.
70 * - this variable would be filled by exynos gem module
71 * of kernel side with user virtual address which is allocated
72 * by do_mmap().
73 */
74struct drm_exynos_gem_mmap {
75 unsigned int handle;
76 unsigned int pad;
77 uint64_t size;
78 uint64_t mapped;
79};
80
81/**
82 * A structure to gem information.
83 *
84 * @handle: a handle to gem object created.
85 * @flags: flag value including memory type and cache attribute and
86 * this value would be set by driver.
87 * @size: size to memory region allocated by gem and this size would
88 * be set by driver.
89 */
90struct drm_exynos_gem_info {
91 unsigned int handle;
92 unsigned int flags;
93 uint64_t size;
94};
95
96/**
97 * A structure for user connection request of virtual display.
98 *
99 * @connection: indicate whether doing connetion or not by user.
100 * @extensions: if this value is 1 then the vidi driver would need additional
101 * 128bytes edid data.
102 * @edid: the edid data pointer from user side.
103 */
104struct drm_exynos_vidi_connection {
105 unsigned int connection;
106 unsigned int extensions;
107 uint64_t edid;
108};
109
110/* memory type definitions. */
111enum e_drm_exynos_gem_mem_type {
112 /* Physically Continuous memory and used as default. */
113 EXYNOS_BO_CONTIG = 0 << 0,
114 /* Physically Non-Continuous memory. */
115 EXYNOS_BO_NONCONTIG = 1 << 0,
116 /* non-cachable mapping and used as default. */
117 EXYNOS_BO_NONCACHABLE = 0 << 1,
118 /* cachable mapping. */
119 EXYNOS_BO_CACHABLE = 1 << 1,
120 /* write-combine mapping. */
121 EXYNOS_BO_WC = 1 << 2,
122 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
123 EXYNOS_BO_WC
124};
125
126struct drm_exynos_g2d_get_ver {
127 __u32 major;
128 __u32 minor;
129};
130
131struct drm_exynos_g2d_cmd {
132 __u32 offset;
133 __u32 data;
134};
135
136enum drm_exynos_g2d_event_type {
137 G2D_EVENT_NOT,
138 G2D_EVENT_NONSTOP,
139 G2D_EVENT_STOP, /* not yet */
140};
141
142struct drm_exynos_g2d_set_cmdlist {
143 __u64 cmd;
144 __u64 cmd_gem;
145 __u32 cmd_nr;
146 __u32 cmd_gem_nr;
147
148 /* for g2d event */
149 __u64 event_type;
150 __u64 user_data;
151};
152
153struct drm_exynos_g2d_exec {
154 __u64 async;
155};
156
157#define DRM_EXYNOS_GEM_CREATE 0x00
158#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
159#define DRM_EXYNOS_GEM_MMAP 0x02
160/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
161#define DRM_EXYNOS_GEM_GET 0x04
162#define DRM_EXYNOS_VIDI_CONNECTION 0x07
163
164/* G2D */
165#define DRM_EXYNOS_G2D_GET_VER 0x20
166#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
167#define DRM_EXYNOS_G2D_EXEC 0x22
168
169#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
170 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
171
172#define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
173 DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off)
174
175#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \
176 DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
177
178#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
179 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
180
181#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
182 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
183
184#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
185 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
186#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
187 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
188#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
189 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
190
191/* EXYNOS specific events */
192#define DRM_EXYNOS_G2D_EVENT 0x80000000
193
194struct drm_exynos_g2d_event {
195 struct drm_event base;
196 __u64 user_data;
197 __u32 tv_sec;
198 __u32 tv_usec;
199 __u32 cmdlist_no;
200 __u32 reserved;
201};
202 32
203#ifdef __KERNEL__
204 33
205/** 34/**
206 * A structure for lcd panel information. 35 * A structure for lcd panel information.
@@ -257,5 +86,4 @@ struct exynos_drm_hdmi_pdata {
257 int (*get_hpd)(void); 86 int (*get_hpd)(void);
258}; 87};
259 88
260#endif /* __KERNEL__ */
261#endif /* _EXYNOS_DRM_H_ */ 89#endif /* _EXYNOS_DRM_H_ */
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index a940d4e18917..63d609d8a3f6 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -23,933 +23,15 @@
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * 24 *
25 */ 25 */
26
27#ifndef _I915_DRM_H_ 26#ifndef _I915_DRM_H_
28#define _I915_DRM_H_ 27#define _I915_DRM_H_
29 28
30#include <drm/drm.h> 29#include <uapi/drm/i915_drm.h>
31
32/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
34 */
35 30
36#ifdef __KERNEL__
37/* For use by IPS driver */ 31/* For use by IPS driver */
38extern unsigned long i915_read_mch_val(void); 32extern unsigned long i915_read_mch_val(void);
39extern bool i915_gpu_raise(void); 33extern bool i915_gpu_raise(void);
40extern bool i915_gpu_lower(void); 34extern bool i915_gpu_lower(void);
41extern bool i915_gpu_busy(void); 35extern bool i915_gpu_busy(void);
42extern bool i915_gpu_turbo_disable(void); 36extern bool i915_gpu_turbo_disable(void);
43#endif
44
45/* Each region is a minimum of 16k, and there are at most 255 of them.
46 */
47#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
48 * of chars for next/prev indices */
49#define I915_LOG_MIN_TEX_REGION_SIZE 14
50
51typedef struct _drm_i915_init {
52 enum {
53 I915_INIT_DMA = 0x01,
54 I915_CLEANUP_DMA = 0x02,
55 I915_RESUME_DMA = 0x03
56 } func;
57 unsigned int mmio_offset;
58 int sarea_priv_offset;
59 unsigned int ring_start;
60 unsigned int ring_end;
61 unsigned int ring_size;
62 unsigned int front_offset;
63 unsigned int back_offset;
64 unsigned int depth_offset;
65 unsigned int w;
66 unsigned int h;
67 unsigned int pitch;
68 unsigned int pitch_bits;
69 unsigned int back_pitch;
70 unsigned int depth_pitch;
71 unsigned int cpp;
72 unsigned int chipset;
73} drm_i915_init_t;
74
75typedef struct _drm_i915_sarea {
76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
77 int last_upload; /* last time texture was uploaded */
78 int last_enqueue; /* last time a buffer was enqueued */
79 int last_dispatch; /* age of the most recently dispatched buffer */
80 int ctxOwner; /* last context to upload state */
81 int texAge;
82 int pf_enabled; /* is pageflipping allowed? */
83 int pf_active;
84 int pf_current_page; /* which buffer is being displayed? */
85 int perf_boxes; /* performance boxes to be displayed */
86 int width, height; /* screen size in pixels */
87
88 drm_handle_t front_handle;
89 int front_offset;
90 int front_size;
91
92 drm_handle_t back_handle;
93 int back_offset;
94 int back_size;
95
96 drm_handle_t depth_handle;
97 int depth_offset;
98 int depth_size;
99
100 drm_handle_t tex_handle;
101 int tex_offset;
102 int tex_size;
103 int log_tex_granularity;
104 int pitch;
105 int rotation; /* 0, 90, 180 or 270 */
106 int rotated_offset;
107 int rotated_size;
108 int rotated_pitch;
109 int virtualX, virtualY;
110
111 unsigned int front_tiled;
112 unsigned int back_tiled;
113 unsigned int depth_tiled;
114 unsigned int rotated_tiled;
115 unsigned int rotated2_tiled;
116
117 int pipeA_x;
118 int pipeA_y;
119 int pipeA_w;
120 int pipeA_h;
121 int pipeB_x;
122 int pipeB_y;
123 int pipeB_w;
124 int pipeB_h;
125
126 /* fill out some space for old userspace triple buffer */
127 drm_handle_t unused_handle;
128 __u32 unused1, unused2, unused3;
129
130 /* buffer object handles for static buffers. May change
131 * over the lifetime of the client.
132 */
133 __u32 front_bo_handle;
134 __u32 back_bo_handle;
135 __u32 unused_bo_handle;
136 __u32 depth_bo_handle;
137
138} drm_i915_sarea_t;
139
140/* due to userspace building against these headers we need some compat here */
141#define planeA_x pipeA_x
142#define planeA_y pipeA_y
143#define planeA_w pipeA_w
144#define planeA_h pipeA_h
145#define planeB_x pipeB_x
146#define planeB_y pipeB_y
147#define planeB_w pipeB_w
148#define planeB_h pipeB_h
149
150/* Flags for perf_boxes
151 */
152#define I915_BOX_RING_EMPTY 0x1
153#define I915_BOX_FLIP 0x2
154#define I915_BOX_WAIT 0x4
155#define I915_BOX_TEXTURE_LOAD 0x8
156#define I915_BOX_LOST_CONTEXT 0x10
157
158/* I915 specific ioctls
159 * The device specific ioctl range is 0x40 to 0x79.
160 */
161#define DRM_I915_INIT 0x00
162#define DRM_I915_FLUSH 0x01
163#define DRM_I915_FLIP 0x02
164#define DRM_I915_BATCHBUFFER 0x03
165#define DRM_I915_IRQ_EMIT 0x04
166#define DRM_I915_IRQ_WAIT 0x05
167#define DRM_I915_GETPARAM 0x06
168#define DRM_I915_SETPARAM 0x07
169#define DRM_I915_ALLOC 0x08
170#define DRM_I915_FREE 0x09
171#define DRM_I915_INIT_HEAP 0x0a
172#define DRM_I915_CMDBUFFER 0x0b
173#define DRM_I915_DESTROY_HEAP 0x0c
174#define DRM_I915_SET_VBLANK_PIPE 0x0d
175#define DRM_I915_GET_VBLANK_PIPE 0x0e
176#define DRM_I915_VBLANK_SWAP 0x0f
177#define DRM_I915_HWS_ADDR 0x11
178#define DRM_I915_GEM_INIT 0x13
179#define DRM_I915_GEM_EXECBUFFER 0x14
180#define DRM_I915_GEM_PIN 0x15
181#define DRM_I915_GEM_UNPIN 0x16
182#define DRM_I915_GEM_BUSY 0x17
183#define DRM_I915_GEM_THROTTLE 0x18
184#define DRM_I915_GEM_ENTERVT 0x19
185#define DRM_I915_GEM_LEAVEVT 0x1a
186#define DRM_I915_GEM_CREATE 0x1b
187#define DRM_I915_GEM_PREAD 0x1c
188#define DRM_I915_GEM_PWRITE 0x1d
189#define DRM_I915_GEM_MMAP 0x1e
190#define DRM_I915_GEM_SET_DOMAIN 0x1f
191#define DRM_I915_GEM_SW_FINISH 0x20
192#define DRM_I915_GEM_SET_TILING 0x21
193#define DRM_I915_GEM_GET_TILING 0x22
194#define DRM_I915_GEM_GET_APERTURE 0x23
195#define DRM_I915_GEM_MMAP_GTT 0x24
196#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
197#define DRM_I915_GEM_MADVISE 0x26
198#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
199#define DRM_I915_OVERLAY_ATTRS 0x28
200#define DRM_I915_GEM_EXECBUFFER2 0x29
201#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
202#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
203#define DRM_I915_GEM_WAIT 0x2c
204#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
205#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
206#define DRM_I915_GEM_SET_CACHING 0x2f
207#define DRM_I915_GEM_GET_CACHING 0x30
208#define DRM_I915_REG_READ 0x31
209
210#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
211#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
212#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
213#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
214#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
215#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
216#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
217#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
218#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
219#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
220#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
221#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
222#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
223#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
224#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
225#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
226#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
227#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
228#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
229#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
230#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
231#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
232#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
233#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
234#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
235#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
236#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
237#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
238#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
239#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
240#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
241#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
242#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
243#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
244#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
245#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
246#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
247#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
248#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
249#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
250#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
251#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
252#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
253#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
254#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
255#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
256#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
257#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
258
259/* Allow drivers to submit batchbuffers directly to hardware, relying
260 * on the security mechanisms provided by hardware.
261 */
262typedef struct drm_i915_batchbuffer {
263 int start; /* agp offset */
264 int used; /* nr bytes in use */
265 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
266 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
267 int num_cliprects; /* mulitpass with multiple cliprects? */
268 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
269} drm_i915_batchbuffer_t;
270
271/* As above, but pass a pointer to userspace buffer which can be
272 * validated by the kernel prior to sending to hardware.
273 */
274typedef struct _drm_i915_cmdbuffer {
275 char __user *buf; /* pointer to userspace command buffer */
276 int sz; /* nr bytes in buf */
277 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
278 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
279 int num_cliprects; /* mulitpass with multiple cliprects? */
280 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
281} drm_i915_cmdbuffer_t;
282
283/* Userspace can request & wait on irq's:
284 */
285typedef struct drm_i915_irq_emit {
286 int __user *irq_seq;
287} drm_i915_irq_emit_t;
288
289typedef struct drm_i915_irq_wait {
290 int irq_seq;
291} drm_i915_irq_wait_t;
292
293/* Ioctl to query kernel params:
294 */
295#define I915_PARAM_IRQ_ACTIVE 1
296#define I915_PARAM_ALLOW_BATCHBUFFER 2
297#define I915_PARAM_LAST_DISPATCH 3
298#define I915_PARAM_CHIPSET_ID 4
299#define I915_PARAM_HAS_GEM 5
300#define I915_PARAM_NUM_FENCES_AVAIL 6
301#define I915_PARAM_HAS_OVERLAY 7
302#define I915_PARAM_HAS_PAGEFLIPPING 8
303#define I915_PARAM_HAS_EXECBUF2 9
304#define I915_PARAM_HAS_BSD 10
305#define I915_PARAM_HAS_BLT 11
306#define I915_PARAM_HAS_RELAXED_FENCING 12
307#define I915_PARAM_HAS_COHERENT_RINGS 13
308#define I915_PARAM_HAS_EXEC_CONSTANTS 14
309#define I915_PARAM_HAS_RELAXED_DELTA 15
310#define I915_PARAM_HAS_GEN7_SOL_RESET 16
311#define I915_PARAM_HAS_LLC 17
312#define I915_PARAM_HAS_ALIASING_PPGTT 18
313#define I915_PARAM_HAS_WAIT_TIMEOUT 19
314#define I915_PARAM_HAS_SEMAPHORES 20
315#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
316#define I915_PARAM_RSVD_FOR_FUTURE_USE 22
317
318typedef struct drm_i915_getparam {
319 int param;
320 int __user *value;
321} drm_i915_getparam_t;
322
323/* Ioctl to set kernel params:
324 */
325#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
326#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
327#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
328#define I915_SETPARAM_NUM_USED_FENCES 4
329
330typedef struct drm_i915_setparam {
331 int param;
332 int value;
333} drm_i915_setparam_t;
334
335/* A memory manager for regions of shared memory:
336 */
337#define I915_MEM_REGION_AGP 1
338
339typedef struct drm_i915_mem_alloc {
340 int region;
341 int alignment;
342 int size;
343 int __user *region_offset; /* offset from start of fb or agp */
344} drm_i915_mem_alloc_t;
345
346typedef struct drm_i915_mem_free {
347 int region;
348 int region_offset;
349} drm_i915_mem_free_t;
350
351typedef struct drm_i915_mem_init_heap {
352 int region;
353 int size;
354 int start;
355} drm_i915_mem_init_heap_t;
356
357/* Allow memory manager to be torn down and re-initialized (eg on
358 * rotate):
359 */
360typedef struct drm_i915_mem_destroy_heap {
361 int region;
362} drm_i915_mem_destroy_heap_t;
363
364/* Allow X server to configure which pipes to monitor for vblank signals
365 */
366#define DRM_I915_VBLANK_PIPE_A 1
367#define DRM_I915_VBLANK_PIPE_B 2
368
369typedef struct drm_i915_vblank_pipe {
370 int pipe;
371} drm_i915_vblank_pipe_t;
372
373/* Schedule buffer swap at given vertical blank:
374 */
375typedef struct drm_i915_vblank_swap {
376 drm_drawable_t drawable;
377 enum drm_vblank_seq_type seqtype;
378 unsigned int sequence;
379} drm_i915_vblank_swap_t;
380
381typedef struct drm_i915_hws_addr {
382 __u64 addr;
383} drm_i915_hws_addr_t;
384
385struct drm_i915_gem_init {
386 /**
387 * Beginning offset in the GTT to be managed by the DRM memory
388 * manager.
389 */
390 __u64 gtt_start;
391 /**
392 * Ending offset in the GTT to be managed by the DRM memory
393 * manager.
394 */
395 __u64 gtt_end;
396};
397
398struct drm_i915_gem_create {
399 /**
400 * Requested size for the object.
401 *
402 * The (page-aligned) allocated size for the object will be returned.
403 */
404 __u64 size;
405 /**
406 * Returned handle for the object.
407 *
408 * Object handles are nonzero.
409 */
410 __u32 handle;
411 __u32 pad;
412};
413
414struct drm_i915_gem_pread {
415 /** Handle for the object being read. */
416 __u32 handle;
417 __u32 pad;
418 /** Offset into the object to read from */
419 __u64 offset;
420 /** Length of data to read */
421 __u64 size;
422 /**
423 * Pointer to write the data into.
424 *
425 * This is a fixed-size type for 32/64 compatibility.
426 */
427 __u64 data_ptr;
428};
429
430struct drm_i915_gem_pwrite {
431 /** Handle for the object being written to. */
432 __u32 handle;
433 __u32 pad;
434 /** Offset into the object to write to */
435 __u64 offset;
436 /** Length of data to write */
437 __u64 size;
438 /**
439 * Pointer to read the data from.
440 *
441 * This is a fixed-size type for 32/64 compatibility.
442 */
443 __u64 data_ptr;
444};
445
446struct drm_i915_gem_mmap {
447 /** Handle for the object being mapped. */
448 __u32 handle;
449 __u32 pad;
450 /** Offset in the object to map. */
451 __u64 offset;
452 /**
453 * Length of data to map.
454 *
455 * The value will be page-aligned.
456 */
457 __u64 size;
458 /**
459 * Returned pointer the data was mapped at.
460 *
461 * This is a fixed-size type for 32/64 compatibility.
462 */
463 __u64 addr_ptr;
464};
465
466struct drm_i915_gem_mmap_gtt {
467 /** Handle for the object being mapped. */
468 __u32 handle;
469 __u32 pad;
470 /**
471 * Fake offset to use for subsequent mmap call
472 *
473 * This is a fixed-size type for 32/64 compatibility.
474 */
475 __u64 offset;
476};
477
478struct drm_i915_gem_set_domain {
479 /** Handle for the object */
480 __u32 handle;
481
482 /** New read domains */
483 __u32 read_domains;
484
485 /** New write domain */
486 __u32 write_domain;
487};
488
489struct drm_i915_gem_sw_finish {
490 /** Handle for the object */
491 __u32 handle;
492};
493
494struct drm_i915_gem_relocation_entry {
495 /**
496 * Handle of the buffer being pointed to by this relocation entry.
497 *
498 * It's appealing to make this be an index into the mm_validate_entry
499 * list to refer to the buffer, but this allows the driver to create
500 * a relocation list for state buffers and not re-write it per
501 * exec using the buffer.
502 */
503 __u32 target_handle;
504
505 /**
506 * Value to be added to the offset of the target buffer to make up
507 * the relocation entry.
508 */
509 __u32 delta;
510
511 /** Offset in the buffer the relocation entry will be written into */
512 __u64 offset;
513
514 /**
515 * Offset value of the target buffer that the relocation entry was last
516 * written as.
517 *
518 * If the buffer has the same offset as last time, we can skip syncing
519 * and writing the relocation. This value is written back out by
520 * the execbuffer ioctl when the relocation is written.
521 */
522 __u64 presumed_offset;
523
524 /**
525 * Target memory domains read by this operation.
526 */
527 __u32 read_domains;
528
529 /**
530 * Target memory domains written by this operation.
531 *
532 * Note that only one domain may be written by the whole
533 * execbuffer operation, so that where there are conflicts,
534 * the application will get -EINVAL back.
535 */
536 __u32 write_domain;
537};
538
539/** @{
540 * Intel memory domains
541 *
542 * Most of these just align with the various caches in
543 * the system and are used to flush and invalidate as
544 * objects end up cached in different domains.
545 */
546/** CPU cache */
547#define I915_GEM_DOMAIN_CPU 0x00000001
548/** Render cache, used by 2D and 3D drawing */
549#define I915_GEM_DOMAIN_RENDER 0x00000002
550/** Sampler cache, used by texture engine */
551#define I915_GEM_DOMAIN_SAMPLER 0x00000004
552/** Command queue, used to load batch buffers */
553#define I915_GEM_DOMAIN_COMMAND 0x00000008
554/** Instruction cache, used by shader programs */
555#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
556/** Vertex address cache */
557#define I915_GEM_DOMAIN_VERTEX 0x00000020
558/** GTT domain - aperture and scanout */
559#define I915_GEM_DOMAIN_GTT 0x00000040
560/** @} */
561
562struct drm_i915_gem_exec_object {
563 /**
564 * User's handle for a buffer to be bound into the GTT for this
565 * operation.
566 */
567 __u32 handle;
568
569 /** Number of relocations to be performed on this buffer */
570 __u32 relocation_count;
571 /**
572 * Pointer to array of struct drm_i915_gem_relocation_entry containing
573 * the relocations to be performed in this buffer.
574 */
575 __u64 relocs_ptr;
576
577 /** Required alignment in graphics aperture */
578 __u64 alignment;
579
580 /**
581 * Returned value of the updated offset of the object, for future
582 * presumed_offset writes.
583 */
584 __u64 offset;
585};
586
587struct drm_i915_gem_execbuffer {
588 /**
589 * List of buffers to be validated with their relocations to be
590 * performend on them.
591 *
592 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
593 *
594 * These buffers must be listed in an order such that all relocations
595 * a buffer is performing refer to buffers that have already appeared
596 * in the validate list.
597 */
598 __u64 buffers_ptr;
599 __u32 buffer_count;
600
601 /** Offset in the batchbuffer to start execution from. */
602 __u32 batch_start_offset;
603 /** Bytes used in batchbuffer from batch_start_offset */
604 __u32 batch_len;
605 __u32 DR1;
606 __u32 DR4;
607 __u32 num_cliprects;
608 /** This is a struct drm_clip_rect *cliprects */
609 __u64 cliprects_ptr;
610};
611
612struct drm_i915_gem_exec_object2 {
613 /**
614 * User's handle for a buffer to be bound into the GTT for this
615 * operation.
616 */
617 __u32 handle;
618
619 /** Number of relocations to be performed on this buffer */
620 __u32 relocation_count;
621 /**
622 * Pointer to array of struct drm_i915_gem_relocation_entry containing
623 * the relocations to be performed in this buffer.
624 */
625 __u64 relocs_ptr;
626
627 /** Required alignment in graphics aperture */
628 __u64 alignment;
629
630 /**
631 * Returned value of the updated offset of the object, for future
632 * presumed_offset writes.
633 */
634 __u64 offset;
635
636#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
637 __u64 flags;
638 __u64 rsvd1;
639 __u64 rsvd2;
640};
641
642struct drm_i915_gem_execbuffer2 {
643 /**
644 * List of gem_exec_object2 structs
645 */
646 __u64 buffers_ptr;
647 __u32 buffer_count;
648
649 /** Offset in the batchbuffer to start execution from. */
650 __u32 batch_start_offset;
651 /** Bytes used in batchbuffer from batch_start_offset */
652 __u32 batch_len;
653 __u32 DR1;
654 __u32 DR4;
655 __u32 num_cliprects;
656 /** This is a struct drm_clip_rect *cliprects */
657 __u64 cliprects_ptr;
658#define I915_EXEC_RING_MASK (7<<0)
659#define I915_EXEC_DEFAULT (0<<0)
660#define I915_EXEC_RENDER (1<<0)
661#define I915_EXEC_BSD (2<<0)
662#define I915_EXEC_BLT (3<<0)
663
664/* Used for switching the constants addressing mode on gen4+ RENDER ring.
665 * Gen6+ only supports relative addressing to dynamic state (default) and
666 * absolute addressing.
667 *
668 * These flags are ignored for the BSD and BLT rings.
669 */
670#define I915_EXEC_CONSTANTS_MASK (3<<6)
671#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
672#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
673#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
674 __u64 flags;
675 __u64 rsvd1; /* now used for context info */
676 __u64 rsvd2;
677};
678
679/** Resets the SO write offset registers for transform feedback on gen7. */
680#define I915_EXEC_GEN7_SOL_RESET (1<<8)
681
682#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
683#define i915_execbuffer2_set_context_id(eb2, context) \
684 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
685#define i915_execbuffer2_get_context_id(eb2) \
686 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
687
688struct drm_i915_gem_pin {
689 /** Handle of the buffer to be pinned. */
690 __u32 handle;
691 __u32 pad;
692
693 /** alignment required within the aperture */
694 __u64 alignment;
695
696 /** Returned GTT offset of the buffer. */
697 __u64 offset;
698};
699
700struct drm_i915_gem_unpin {
701 /** Handle of the buffer to be unpinned. */
702 __u32 handle;
703 __u32 pad;
704};
705
706struct drm_i915_gem_busy {
707 /** Handle of the buffer to check for busy */
708 __u32 handle;
709
710 /** Return busy status (1 if busy, 0 if idle).
711 * The high word is used to indicate on which rings the object
712 * currently resides:
713 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
714 */
715 __u32 busy;
716};
717
718#define I915_CACHING_NONE 0
719#define I915_CACHING_CACHED 1
720
721struct drm_i915_gem_caching {
722 /**
723 * Handle of the buffer to set/get the caching level of. */
724 __u32 handle;
725
726 /**
727 * Cacheing level to apply or return value
728 *
729 * bits0-15 are for generic caching control (i.e. the above defined
730 * values). bits16-31 are reserved for platform-specific variations
731 * (e.g. l3$ caching on gen7). */
732 __u32 caching;
733};
734
735#define I915_TILING_NONE 0
736#define I915_TILING_X 1
737#define I915_TILING_Y 2
738
739#define I915_BIT_6_SWIZZLE_NONE 0
740#define I915_BIT_6_SWIZZLE_9 1
741#define I915_BIT_6_SWIZZLE_9_10 2
742#define I915_BIT_6_SWIZZLE_9_11 3
743#define I915_BIT_6_SWIZZLE_9_10_11 4
744/* Not seen by userland */
745#define I915_BIT_6_SWIZZLE_UNKNOWN 5
746/* Seen by userland. */
747#define I915_BIT_6_SWIZZLE_9_17 6
748#define I915_BIT_6_SWIZZLE_9_10_17 7
749
750struct drm_i915_gem_set_tiling {
751 /** Handle of the buffer to have its tiling state updated */
752 __u32 handle;
753
754 /**
755 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
756 * I915_TILING_Y).
757 *
758 * This value is to be set on request, and will be updated by the
759 * kernel on successful return with the actual chosen tiling layout.
760 *
761 * The tiling mode may be demoted to I915_TILING_NONE when the system
762 * has bit 6 swizzling that can't be managed correctly by GEM.
763 *
764 * Buffer contents become undefined when changing tiling_mode.
765 */
766 __u32 tiling_mode;
767
768 /**
769 * Stride in bytes for the object when in I915_TILING_X or
770 * I915_TILING_Y.
771 */
772 __u32 stride;
773
774 /**
775 * Returned address bit 6 swizzling required for CPU access through
776 * mmap mapping.
777 */
778 __u32 swizzle_mode;
779};
780
781struct drm_i915_gem_get_tiling {
782 /** Handle of the buffer to get tiling state for. */
783 __u32 handle;
784
785 /**
786 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
787 * I915_TILING_Y).
788 */
789 __u32 tiling_mode;
790
791 /**
792 * Returned address bit 6 swizzling required for CPU access through
793 * mmap mapping.
794 */
795 __u32 swizzle_mode;
796};
797
798struct drm_i915_gem_get_aperture {
799 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
800 __u64 aper_size;
801
802 /**
803 * Available space in the aperture used by i915_gem_execbuffer, in
804 * bytes
805 */
806 __u64 aper_available_size;
807};
808
809struct drm_i915_get_pipe_from_crtc_id {
810 /** ID of CRTC being requested **/
811 __u32 crtc_id;
812
813 /** pipe of requested CRTC **/
814 __u32 pipe;
815};
816
817#define I915_MADV_WILLNEED 0
818#define I915_MADV_DONTNEED 1
819#define __I915_MADV_PURGED 2 /* internal state */
820
821struct drm_i915_gem_madvise {
822 /** Handle of the buffer to change the backing store advice */
823 __u32 handle;
824
825 /* Advice: either the buffer will be needed again in the near future,
826 * or wont be and could be discarded under memory pressure.
827 */
828 __u32 madv;
829
830 /** Whether the backing store still exists. */
831 __u32 retained;
832};
833
834/* flags */
835#define I915_OVERLAY_TYPE_MASK 0xff
836#define I915_OVERLAY_YUV_PLANAR 0x01
837#define I915_OVERLAY_YUV_PACKED 0x02
838#define I915_OVERLAY_RGB 0x03
839
840#define I915_OVERLAY_DEPTH_MASK 0xff00
841#define I915_OVERLAY_RGB24 0x1000
842#define I915_OVERLAY_RGB16 0x2000
843#define I915_OVERLAY_RGB15 0x3000
844#define I915_OVERLAY_YUV422 0x0100
845#define I915_OVERLAY_YUV411 0x0200
846#define I915_OVERLAY_YUV420 0x0300
847#define I915_OVERLAY_YUV410 0x0400
848
849#define I915_OVERLAY_SWAP_MASK 0xff0000
850#define I915_OVERLAY_NO_SWAP 0x000000
851#define I915_OVERLAY_UV_SWAP 0x010000
852#define I915_OVERLAY_Y_SWAP 0x020000
853#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
854
855#define I915_OVERLAY_FLAGS_MASK 0xff000000
856#define I915_OVERLAY_ENABLE 0x01000000
857
858struct drm_intel_overlay_put_image {
859 /* various flags and src format description */
860 __u32 flags;
861 /* source picture description */
862 __u32 bo_handle;
863 /* stride values and offsets are in bytes, buffer relative */
864 __u16 stride_Y; /* stride for packed formats */
865 __u16 stride_UV;
866 __u32 offset_Y; /* offset for packet formats */
867 __u32 offset_U;
868 __u32 offset_V;
869 /* in pixels */
870 __u16 src_width;
871 __u16 src_height;
872 /* to compensate the scaling factors for partially covered surfaces */
873 __u16 src_scan_width;
874 __u16 src_scan_height;
875 /* output crtc description */
876 __u32 crtc_id;
877 __u16 dst_x;
878 __u16 dst_y;
879 __u16 dst_width;
880 __u16 dst_height;
881};
882
883/* flags */
884#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
885#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
886struct drm_intel_overlay_attrs {
887 __u32 flags;
888 __u32 color_key;
889 __s32 brightness;
890 __u32 contrast;
891 __u32 saturation;
892 __u32 gamma0;
893 __u32 gamma1;
894 __u32 gamma2;
895 __u32 gamma3;
896 __u32 gamma4;
897 __u32 gamma5;
898};
899
900/*
901 * Intel sprite handling
902 *
903 * Color keying works with a min/mask/max tuple. Both source and destination
904 * color keying is allowed.
905 *
906 * Source keying:
907 * Sprite pixels within the min & max values, masked against the color channels
908 * specified in the mask field, will be transparent. All other pixels will
909 * be displayed on top of the primary plane. For RGB surfaces, only the min
910 * and mask fields will be used; ranged compares are not allowed.
911 *
912 * Destination keying:
913 * Primary plane pixels that match the min value, masked against the color
914 * channels specified in the mask field, will be replaced by corresponding
915 * pixels from the sprite plane.
916 *
917 * Note that source & destination keying are exclusive; only one can be
918 * active on a given plane.
919 */
920
921#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
922#define I915_SET_COLORKEY_DESTINATION (1<<1)
923#define I915_SET_COLORKEY_SOURCE (1<<2)
924struct drm_intel_sprite_colorkey {
925 __u32 plane_id;
926 __u32 min_value;
927 __u32 channel_mask;
928 __u32 max_value;
929 __u32 flags;
930};
931
932struct drm_i915_gem_wait {
933 /** Handle of BO we shall wait on */
934 __u32 bo_handle;
935 __u32 flags;
936 /** Number of nanoseconds to wait, Returns time remaining. */
937 __s64 timeout_ns;
938};
939
940struct drm_i915_gem_context_create {
941 /* output: id of new context*/
942 __u32 ctx_id;
943 __u32 pad;
944};
945
946struct drm_i915_gem_context_destroy {
947 __u32 ctx_id;
948 __u32 pad;
949};
950
951struct drm_i915_reg_read {
952 __u64 offset;
953 __u64 val; /* Return value */
954};
955#endif /* _I915_DRM_H_ */ 37#endif /* _I915_DRM_H_ */
diff --git a/include/uapi/drm/Kbuild b/include/uapi/drm/Kbuild
index aafaa5aa54d4..ba99ce3f7372 100644
--- a/include/uapi/drm/Kbuild
+++ b/include/uapi/drm/Kbuild
@@ -1 +1,16 @@
1# UAPI Header export list 1# UAPI Header export list
2header-y += drm.h
3header-y += drm_fourcc.h
4header-y += drm_mode.h
5header-y += drm_sarea.h
6header-y += exynos_drm.h
7header-y += i810_drm.h
8header-y += i915_drm.h
9header-y += mga_drm.h
10header-y += nouveau_drm.h
11header-y += r128_drm.h
12header-y += radeon_drm.h
13header-y += savage_drm.h
14header-y += sis_drm.h
15header-y += via_drm.h
16header-y += vmwgfx_drm.h
diff --git a/include/drm/drm.h b/include/uapi/drm/drm.h
index 1e3481edf062..1e3481edf062 100644
--- a/include/drm/drm.h
+++ b/include/uapi/drm/drm.h
diff --git a/include/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 646ae5f39f42..646ae5f39f42 100644
--- a/include/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
diff --git a/include/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 3d6301b6ec16..3d6301b6ec16 100644
--- a/include/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
diff --git a/include/drm/drm_sarea.h b/include/uapi/drm/drm_sarea.h
index 413a5642d49f..413a5642d49f 100644
--- a/include/drm/drm_sarea.h
+++ b/include/uapi/drm/drm_sarea.h
diff --git a/include/uapi/drm/exynos_drm.h b/include/uapi/drm/exynos_drm.h
new file mode 100644
index 000000000000..c0494d586e23
--- /dev/null
+++ b/include/uapi/drm/exynos_drm.h
@@ -0,0 +1,203 @@
1/* exynos_drm.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * Authors:
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
7 * Seung-Woo Kim <sw0312.kim@samsung.com>
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
26 * OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29#ifndef _UAPI_EXYNOS_DRM_H_
30#define _UAPI_EXYNOS_DRM_H_
31
32#include <drm/drm.h>
33
34/**
35 * User-desired buffer creation information structure.
36 *
37 * @size: user-desired memory allocation size.
38 * - this size value would be page-aligned internally.
39 * @flags: user request for setting memory type or cache attributes.
40 * @handle: returned a handle to created gem object.
41 * - this handle will be set by gem module of kernel side.
42 */
43struct drm_exynos_gem_create {
44 uint64_t size;
45 unsigned int flags;
46 unsigned int handle;
47};
48
49/**
50 * A structure for getting buffer offset.
51 *
52 * @handle: a pointer to gem object created.
53 * @pad: just padding to be 64-bit aligned.
54 * @offset: relatived offset value of the memory region allocated.
55 * - this value should be set by user.
56 */
57struct drm_exynos_gem_map_off {
58 unsigned int handle;
59 unsigned int pad;
60 uint64_t offset;
61};
62
63/**
64 * A structure for mapping buffer.
65 *
66 * @handle: a handle to gem object created.
67 * @pad: just padding to be 64-bit aligned.
68 * @size: memory size to be mapped.
69 * @mapped: having user virtual address mmaped.
70 * - this variable would be filled by exynos gem module
71 * of kernel side with user virtual address which is allocated
72 * by do_mmap().
73 */
74struct drm_exynos_gem_mmap {
75 unsigned int handle;
76 unsigned int pad;
77 uint64_t size;
78 uint64_t mapped;
79};
80
81/**
82 * A structure to gem information.
83 *
84 * @handle: a handle to gem object created.
85 * @flags: flag value including memory type and cache attribute and
86 * this value would be set by driver.
87 * @size: size to memory region allocated by gem and this size would
88 * be set by driver.
89 */
90struct drm_exynos_gem_info {
91 unsigned int handle;
92 unsigned int flags;
93 uint64_t size;
94};
95
96/**
97 * A structure for user connection request of virtual display.
98 *
99 * @connection: indicate whether doing connetion or not by user.
100 * @extensions: if this value is 1 then the vidi driver would need additional
101 * 128bytes edid data.
102 * @edid: the edid data pointer from user side.
103 */
104struct drm_exynos_vidi_connection {
105 unsigned int connection;
106 unsigned int extensions;
107 uint64_t edid;
108};
109
110/* memory type definitions. */
111enum e_drm_exynos_gem_mem_type {
112 /* Physically Continuous memory and used as default. */
113 EXYNOS_BO_CONTIG = 0 << 0,
114 /* Physically Non-Continuous memory. */
115 EXYNOS_BO_NONCONTIG = 1 << 0,
116 /* non-cachable mapping and used as default. */
117 EXYNOS_BO_NONCACHABLE = 0 << 1,
118 /* cachable mapping. */
119 EXYNOS_BO_CACHABLE = 1 << 1,
120 /* write-combine mapping. */
121 EXYNOS_BO_WC = 1 << 2,
122 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
123 EXYNOS_BO_WC
124};
125
126struct drm_exynos_g2d_get_ver {
127 __u32 major;
128 __u32 minor;
129};
130
131struct drm_exynos_g2d_cmd {
132 __u32 offset;
133 __u32 data;
134};
135
136enum drm_exynos_g2d_event_type {
137 G2D_EVENT_NOT,
138 G2D_EVENT_NONSTOP,
139 G2D_EVENT_STOP, /* not yet */
140};
141
142struct drm_exynos_g2d_set_cmdlist {
143 __u64 cmd;
144 __u64 cmd_gem;
145 __u32 cmd_nr;
146 __u32 cmd_gem_nr;
147
148 /* for g2d event */
149 __u64 event_type;
150 __u64 user_data;
151};
152
153struct drm_exynos_g2d_exec {
154 __u64 async;
155};
156
157#define DRM_EXYNOS_GEM_CREATE 0x00
158#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
159#define DRM_EXYNOS_GEM_MMAP 0x02
160/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
161#define DRM_EXYNOS_GEM_GET 0x04
162#define DRM_EXYNOS_VIDI_CONNECTION 0x07
163
164/* G2D */
165#define DRM_EXYNOS_G2D_GET_VER 0x20
166#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
167#define DRM_EXYNOS_G2D_EXEC 0x22
168
169#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
170 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
171
172#define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \
173 DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off)
174
175#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \
176 DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
177
178#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
179 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
180
181#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
182 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
183
184#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
185 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
186#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
187 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
188#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
189 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
190
191/* EXYNOS specific events */
192#define DRM_EXYNOS_G2D_EVENT 0x80000000
193
194struct drm_exynos_g2d_event {
195 struct drm_event base;
196 __u64 user_data;
197 __u32 tv_sec;
198 __u32 tv_usec;
199 __u32 cmdlist_no;
200 __u32 reserved;
201};
202
203#endif /* _UAPI_EXYNOS_DRM_H_ */
diff --git a/include/drm/i810_drm.h b/include/uapi/drm/i810_drm.h
index 7a10bb6f2c0f..7a10bb6f2c0f 100644
--- a/include/drm/i810_drm.h
+++ b/include/uapi/drm/i810_drm.h
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
new file mode 100644
index 000000000000..4322b1e7d2ed
--- /dev/null
+++ b/include/uapi/drm/i915_drm.h
@@ -0,0 +1,947 @@
1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _UAPI_I915_DRM_H_
28#define _UAPI_I915_DRM_H_
29
30#include <drm/drm.h>
31
32/* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
34 */
35
36
37/* Each region is a minimum of 16k, and there are at most 255 of them.
38 */
39#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
40 * of chars for next/prev indices */
41#define I915_LOG_MIN_TEX_REGION_SIZE 14
42
43typedef struct _drm_i915_init {
44 enum {
45 I915_INIT_DMA = 0x01,
46 I915_CLEANUP_DMA = 0x02,
47 I915_RESUME_DMA = 0x03
48 } func;
49 unsigned int mmio_offset;
50 int sarea_priv_offset;
51 unsigned int ring_start;
52 unsigned int ring_end;
53 unsigned int ring_size;
54 unsigned int front_offset;
55 unsigned int back_offset;
56 unsigned int depth_offset;
57 unsigned int w;
58 unsigned int h;
59 unsigned int pitch;
60 unsigned int pitch_bits;
61 unsigned int back_pitch;
62 unsigned int depth_pitch;
63 unsigned int cpp;
64 unsigned int chipset;
65} drm_i915_init_t;
66
67typedef struct _drm_i915_sarea {
68 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
69 int last_upload; /* last time texture was uploaded */
70 int last_enqueue; /* last time a buffer was enqueued */
71 int last_dispatch; /* age of the most recently dispatched buffer */
72 int ctxOwner; /* last context to upload state */
73 int texAge;
74 int pf_enabled; /* is pageflipping allowed? */
75 int pf_active;
76 int pf_current_page; /* which buffer is being displayed? */
77 int perf_boxes; /* performance boxes to be displayed */
78 int width, height; /* screen size in pixels */
79
80 drm_handle_t front_handle;
81 int front_offset;
82 int front_size;
83
84 drm_handle_t back_handle;
85 int back_offset;
86 int back_size;
87
88 drm_handle_t depth_handle;
89 int depth_offset;
90 int depth_size;
91
92 drm_handle_t tex_handle;
93 int tex_offset;
94 int tex_size;
95 int log_tex_granularity;
96 int pitch;
97 int rotation; /* 0, 90, 180 or 270 */
98 int rotated_offset;
99 int rotated_size;
100 int rotated_pitch;
101 int virtualX, virtualY;
102
103 unsigned int front_tiled;
104 unsigned int back_tiled;
105 unsigned int depth_tiled;
106 unsigned int rotated_tiled;
107 unsigned int rotated2_tiled;
108
109 int pipeA_x;
110 int pipeA_y;
111 int pipeA_w;
112 int pipeA_h;
113 int pipeB_x;
114 int pipeB_y;
115 int pipeB_w;
116 int pipeB_h;
117
118 /* fill out some space for old userspace triple buffer */
119 drm_handle_t unused_handle;
120 __u32 unused1, unused2, unused3;
121
122 /* buffer object handles for static buffers. May change
123 * over the lifetime of the client.
124 */
125 __u32 front_bo_handle;
126 __u32 back_bo_handle;
127 __u32 unused_bo_handle;
128 __u32 depth_bo_handle;
129
130} drm_i915_sarea_t;
131
132/* due to userspace building against these headers we need some compat here */
133#define planeA_x pipeA_x
134#define planeA_y pipeA_y
135#define planeA_w pipeA_w
136#define planeA_h pipeA_h
137#define planeB_x pipeB_x
138#define planeB_y pipeB_y
139#define planeB_w pipeB_w
140#define planeB_h pipeB_h
141
142/* Flags for perf_boxes
143 */
144#define I915_BOX_RING_EMPTY 0x1
145#define I915_BOX_FLIP 0x2
146#define I915_BOX_WAIT 0x4
147#define I915_BOX_TEXTURE_LOAD 0x8
148#define I915_BOX_LOST_CONTEXT 0x10
149
150/* I915 specific ioctls
151 * The device specific ioctl range is 0x40 to 0x79.
152 */
153#define DRM_I915_INIT 0x00
154#define DRM_I915_FLUSH 0x01
155#define DRM_I915_FLIP 0x02
156#define DRM_I915_BATCHBUFFER 0x03
157#define DRM_I915_IRQ_EMIT 0x04
158#define DRM_I915_IRQ_WAIT 0x05
159#define DRM_I915_GETPARAM 0x06
160#define DRM_I915_SETPARAM 0x07
161#define DRM_I915_ALLOC 0x08
162#define DRM_I915_FREE 0x09
163#define DRM_I915_INIT_HEAP 0x0a
164#define DRM_I915_CMDBUFFER 0x0b
165#define DRM_I915_DESTROY_HEAP 0x0c
166#define DRM_I915_SET_VBLANK_PIPE 0x0d
167#define DRM_I915_GET_VBLANK_PIPE 0x0e
168#define DRM_I915_VBLANK_SWAP 0x0f
169#define DRM_I915_HWS_ADDR 0x11
170#define DRM_I915_GEM_INIT 0x13
171#define DRM_I915_GEM_EXECBUFFER 0x14
172#define DRM_I915_GEM_PIN 0x15
173#define DRM_I915_GEM_UNPIN 0x16
174#define DRM_I915_GEM_BUSY 0x17
175#define DRM_I915_GEM_THROTTLE 0x18
176#define DRM_I915_GEM_ENTERVT 0x19
177#define DRM_I915_GEM_LEAVEVT 0x1a
178#define DRM_I915_GEM_CREATE 0x1b
179#define DRM_I915_GEM_PREAD 0x1c
180#define DRM_I915_GEM_PWRITE 0x1d
181#define DRM_I915_GEM_MMAP 0x1e
182#define DRM_I915_GEM_SET_DOMAIN 0x1f
183#define DRM_I915_GEM_SW_FINISH 0x20
184#define DRM_I915_GEM_SET_TILING 0x21
185#define DRM_I915_GEM_GET_TILING 0x22
186#define DRM_I915_GEM_GET_APERTURE 0x23
187#define DRM_I915_GEM_MMAP_GTT 0x24
188#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
189#define DRM_I915_GEM_MADVISE 0x26
190#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
191#define DRM_I915_OVERLAY_ATTRS 0x28
192#define DRM_I915_GEM_EXECBUFFER2 0x29
193#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
194#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
195#define DRM_I915_GEM_WAIT 0x2c
196#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
197#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
198#define DRM_I915_GEM_SET_CACHING 0x2f
199#define DRM_I915_GEM_GET_CACHING 0x30
200#define DRM_I915_REG_READ 0x31
201
202#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
203#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
204#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
205#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
206#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
207#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
208#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
209#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
210#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
211#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
212#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
213#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
214#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
215#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
216#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
217#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
218#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
219#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
220#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
221#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
222#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
223#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
224#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
225#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
226#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
227#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
228#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
229#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
230#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
231#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
232#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
233#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
234#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
235#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
236#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
237#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
238#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
239#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
240#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
241#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
242#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
243#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
244#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
245#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
246#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
247#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
248#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
249#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
250
251/* Allow drivers to submit batchbuffers directly to hardware, relying
252 * on the security mechanisms provided by hardware.
253 */
254typedef struct drm_i915_batchbuffer {
255 int start; /* agp offset */
256 int used; /* nr bytes in use */
257 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
258 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
259 int num_cliprects; /* mulitpass with multiple cliprects? */
260 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
261} drm_i915_batchbuffer_t;
262
263/* As above, but pass a pointer to userspace buffer which can be
264 * validated by the kernel prior to sending to hardware.
265 */
266typedef struct _drm_i915_cmdbuffer {
267 char __user *buf; /* pointer to userspace command buffer */
268 int sz; /* nr bytes in buf */
269 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
270 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
271 int num_cliprects; /* mulitpass with multiple cliprects? */
272 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
273} drm_i915_cmdbuffer_t;
274
275/* Userspace can request & wait on irq's:
276 */
277typedef struct drm_i915_irq_emit {
278 int __user *irq_seq;
279} drm_i915_irq_emit_t;
280
281typedef struct drm_i915_irq_wait {
282 int irq_seq;
283} drm_i915_irq_wait_t;
284
285/* Ioctl to query kernel params:
286 */
287#define I915_PARAM_IRQ_ACTIVE 1
288#define I915_PARAM_ALLOW_BATCHBUFFER 2
289#define I915_PARAM_LAST_DISPATCH 3
290#define I915_PARAM_CHIPSET_ID 4
291#define I915_PARAM_HAS_GEM 5
292#define I915_PARAM_NUM_FENCES_AVAIL 6
293#define I915_PARAM_HAS_OVERLAY 7
294#define I915_PARAM_HAS_PAGEFLIPPING 8
295#define I915_PARAM_HAS_EXECBUF2 9
296#define I915_PARAM_HAS_BSD 10
297#define I915_PARAM_HAS_BLT 11
298#define I915_PARAM_HAS_RELAXED_FENCING 12
299#define I915_PARAM_HAS_COHERENT_RINGS 13
300#define I915_PARAM_HAS_EXEC_CONSTANTS 14
301#define I915_PARAM_HAS_RELAXED_DELTA 15
302#define I915_PARAM_HAS_GEN7_SOL_RESET 16
303#define I915_PARAM_HAS_LLC 17
304#define I915_PARAM_HAS_ALIASING_PPGTT 18
305#define I915_PARAM_HAS_WAIT_TIMEOUT 19
306#define I915_PARAM_HAS_SEMAPHORES 20
307#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
308#define I915_PARAM_RSVD_FOR_FUTURE_USE 22
309
310typedef struct drm_i915_getparam {
311 int param;
312 int __user *value;
313} drm_i915_getparam_t;
314
315/* Ioctl to set kernel params:
316 */
317#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
318#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
319#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
320#define I915_SETPARAM_NUM_USED_FENCES 4
321
322typedef struct drm_i915_setparam {
323 int param;
324 int value;
325} drm_i915_setparam_t;
326
327/* A memory manager for regions of shared memory:
328 */
329#define I915_MEM_REGION_AGP 1
330
331typedef struct drm_i915_mem_alloc {
332 int region;
333 int alignment;
334 int size;
335 int __user *region_offset; /* offset from start of fb or agp */
336} drm_i915_mem_alloc_t;
337
338typedef struct drm_i915_mem_free {
339 int region;
340 int region_offset;
341} drm_i915_mem_free_t;
342
343typedef struct drm_i915_mem_init_heap {
344 int region;
345 int size;
346 int start;
347} drm_i915_mem_init_heap_t;
348
349/* Allow memory manager to be torn down and re-initialized (eg on
350 * rotate):
351 */
352typedef struct drm_i915_mem_destroy_heap {
353 int region;
354} drm_i915_mem_destroy_heap_t;
355
356/* Allow X server to configure which pipes to monitor for vblank signals
357 */
358#define DRM_I915_VBLANK_PIPE_A 1
359#define DRM_I915_VBLANK_PIPE_B 2
360
361typedef struct drm_i915_vblank_pipe {
362 int pipe;
363} drm_i915_vblank_pipe_t;
364
365/* Schedule buffer swap at given vertical blank:
366 */
367typedef struct drm_i915_vblank_swap {
368 drm_drawable_t drawable;
369 enum drm_vblank_seq_type seqtype;
370 unsigned int sequence;
371} drm_i915_vblank_swap_t;
372
373typedef struct drm_i915_hws_addr {
374 __u64 addr;
375} drm_i915_hws_addr_t;
376
377struct drm_i915_gem_init {
378 /**
379 * Beginning offset in the GTT to be managed by the DRM memory
380 * manager.
381 */
382 __u64 gtt_start;
383 /**
384 * Ending offset in the GTT to be managed by the DRM memory
385 * manager.
386 */
387 __u64 gtt_end;
388};
389
390struct drm_i915_gem_create {
391 /**
392 * Requested size for the object.
393 *
394 * The (page-aligned) allocated size for the object will be returned.
395 */
396 __u64 size;
397 /**
398 * Returned handle for the object.
399 *
400 * Object handles are nonzero.
401 */
402 __u32 handle;
403 __u32 pad;
404};
405
406struct drm_i915_gem_pread {
407 /** Handle for the object being read. */
408 __u32 handle;
409 __u32 pad;
410 /** Offset into the object to read from */
411 __u64 offset;
412 /** Length of data to read */
413 __u64 size;
414 /**
415 * Pointer to write the data into.
416 *
417 * This is a fixed-size type for 32/64 compatibility.
418 */
419 __u64 data_ptr;
420};
421
422struct drm_i915_gem_pwrite {
423 /** Handle for the object being written to. */
424 __u32 handle;
425 __u32 pad;
426 /** Offset into the object to write to */
427 __u64 offset;
428 /** Length of data to write */
429 __u64 size;
430 /**
431 * Pointer to read the data from.
432 *
433 * This is a fixed-size type for 32/64 compatibility.
434 */
435 __u64 data_ptr;
436};
437
438struct drm_i915_gem_mmap {
439 /** Handle for the object being mapped. */
440 __u32 handle;
441 __u32 pad;
442 /** Offset in the object to map. */
443 __u64 offset;
444 /**
445 * Length of data to map.
446 *
447 * The value will be page-aligned.
448 */
449 __u64 size;
450 /**
451 * Returned pointer the data was mapped at.
452 *
453 * This is a fixed-size type for 32/64 compatibility.
454 */
455 __u64 addr_ptr;
456};
457
458struct drm_i915_gem_mmap_gtt {
459 /** Handle for the object being mapped. */
460 __u32 handle;
461 __u32 pad;
462 /**
463 * Fake offset to use for subsequent mmap call
464 *
465 * This is a fixed-size type for 32/64 compatibility.
466 */
467 __u64 offset;
468};
469
470struct drm_i915_gem_set_domain {
471 /** Handle for the object */
472 __u32 handle;
473
474 /** New read domains */
475 __u32 read_domains;
476
477 /** New write domain */
478 __u32 write_domain;
479};
480
481struct drm_i915_gem_sw_finish {
482 /** Handle for the object */
483 __u32 handle;
484};
485
486struct drm_i915_gem_relocation_entry {
487 /**
488 * Handle of the buffer being pointed to by this relocation entry.
489 *
490 * It's appealing to make this be an index into the mm_validate_entry
491 * list to refer to the buffer, but this allows the driver to create
492 * a relocation list for state buffers and not re-write it per
493 * exec using the buffer.
494 */
495 __u32 target_handle;
496
497 /**
498 * Value to be added to the offset of the target buffer to make up
499 * the relocation entry.
500 */
501 __u32 delta;
502
503 /** Offset in the buffer the relocation entry will be written into */
504 __u64 offset;
505
506 /**
507 * Offset value of the target buffer that the relocation entry was last
508 * written as.
509 *
510 * If the buffer has the same offset as last time, we can skip syncing
511 * and writing the relocation. This value is written back out by
512 * the execbuffer ioctl when the relocation is written.
513 */
514 __u64 presumed_offset;
515
516 /**
517 * Target memory domains read by this operation.
518 */
519 __u32 read_domains;
520
521 /**
522 * Target memory domains written by this operation.
523 *
524 * Note that only one domain may be written by the whole
525 * execbuffer operation, so that where there are conflicts,
526 * the application will get -EINVAL back.
527 */
528 __u32 write_domain;
529};
530
531/** @{
532 * Intel memory domains
533 *
534 * Most of these just align with the various caches in
535 * the system and are used to flush and invalidate as
536 * objects end up cached in different domains.
537 */
538/** CPU cache */
539#define I915_GEM_DOMAIN_CPU 0x00000001
540/** Render cache, used by 2D and 3D drawing */
541#define I915_GEM_DOMAIN_RENDER 0x00000002
542/** Sampler cache, used by texture engine */
543#define I915_GEM_DOMAIN_SAMPLER 0x00000004
544/** Command queue, used to load batch buffers */
545#define I915_GEM_DOMAIN_COMMAND 0x00000008
546/** Instruction cache, used by shader programs */
547#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
548/** Vertex address cache */
549#define I915_GEM_DOMAIN_VERTEX 0x00000020
550/** GTT domain - aperture and scanout */
551#define I915_GEM_DOMAIN_GTT 0x00000040
552/** @} */
553
554struct drm_i915_gem_exec_object {
555 /**
556 * User's handle for a buffer to be bound into the GTT for this
557 * operation.
558 */
559 __u32 handle;
560
561 /** Number of relocations to be performed on this buffer */
562 __u32 relocation_count;
563 /**
564 * Pointer to array of struct drm_i915_gem_relocation_entry containing
565 * the relocations to be performed in this buffer.
566 */
567 __u64 relocs_ptr;
568
569 /** Required alignment in graphics aperture */
570 __u64 alignment;
571
572 /**
573 * Returned value of the updated offset of the object, for future
574 * presumed_offset writes.
575 */
576 __u64 offset;
577};
578
579struct drm_i915_gem_execbuffer {
580 /**
581 * List of buffers to be validated with their relocations to be
582 * performend on them.
583 *
584 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
585 *
586 * These buffers must be listed in an order such that all relocations
587 * a buffer is performing refer to buffers that have already appeared
588 * in the validate list.
589 */
590 __u64 buffers_ptr;
591 __u32 buffer_count;
592
593 /** Offset in the batchbuffer to start execution from. */
594 __u32 batch_start_offset;
595 /** Bytes used in batchbuffer from batch_start_offset */
596 __u32 batch_len;
597 __u32 DR1;
598 __u32 DR4;
599 __u32 num_cliprects;
600 /** This is a struct drm_clip_rect *cliprects */
601 __u64 cliprects_ptr;
602};
603
604struct drm_i915_gem_exec_object2 {
605 /**
606 * User's handle for a buffer to be bound into the GTT for this
607 * operation.
608 */
609 __u32 handle;
610
611 /** Number of relocations to be performed on this buffer */
612 __u32 relocation_count;
613 /**
614 * Pointer to array of struct drm_i915_gem_relocation_entry containing
615 * the relocations to be performed in this buffer.
616 */
617 __u64 relocs_ptr;
618
619 /** Required alignment in graphics aperture */
620 __u64 alignment;
621
622 /**
623 * Returned value of the updated offset of the object, for future
624 * presumed_offset writes.
625 */
626 __u64 offset;
627
628#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
629 __u64 flags;
630 __u64 rsvd1;
631 __u64 rsvd2;
632};
633
634struct drm_i915_gem_execbuffer2 {
635 /**
636 * List of gem_exec_object2 structs
637 */
638 __u64 buffers_ptr;
639 __u32 buffer_count;
640
641 /** Offset in the batchbuffer to start execution from. */
642 __u32 batch_start_offset;
643 /** Bytes used in batchbuffer from batch_start_offset */
644 __u32 batch_len;
645 __u32 DR1;
646 __u32 DR4;
647 __u32 num_cliprects;
648 /** This is a struct drm_clip_rect *cliprects */
649 __u64 cliprects_ptr;
650#define I915_EXEC_RING_MASK (7<<0)
651#define I915_EXEC_DEFAULT (0<<0)
652#define I915_EXEC_RENDER (1<<0)
653#define I915_EXEC_BSD (2<<0)
654#define I915_EXEC_BLT (3<<0)
655
656/* Used for switching the constants addressing mode on gen4+ RENDER ring.
657 * Gen6+ only supports relative addressing to dynamic state (default) and
658 * absolute addressing.
659 *
660 * These flags are ignored for the BSD and BLT rings.
661 */
662#define I915_EXEC_CONSTANTS_MASK (3<<6)
663#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
664#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
665#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
666 __u64 flags;
667 __u64 rsvd1; /* now used for context info */
668 __u64 rsvd2;
669};
670
671/** Resets the SO write offset registers for transform feedback on gen7. */
672#define I915_EXEC_GEN7_SOL_RESET (1<<8)
673
674#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
675#define i915_execbuffer2_set_context_id(eb2, context) \
676 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
677#define i915_execbuffer2_get_context_id(eb2) \
678 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
679
680struct drm_i915_gem_pin {
681 /** Handle of the buffer to be pinned. */
682 __u32 handle;
683 __u32 pad;
684
685 /** alignment required within the aperture */
686 __u64 alignment;
687
688 /** Returned GTT offset of the buffer. */
689 __u64 offset;
690};
691
692struct drm_i915_gem_unpin {
693 /** Handle of the buffer to be unpinned. */
694 __u32 handle;
695 __u32 pad;
696};
697
698struct drm_i915_gem_busy {
699 /** Handle of the buffer to check for busy */
700 __u32 handle;
701
702 /** Return busy status (1 if busy, 0 if idle).
703 * The high word is used to indicate on which rings the object
704 * currently resides:
705 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
706 */
707 __u32 busy;
708};
709
710#define I915_CACHING_NONE 0
711#define I915_CACHING_CACHED 1
712
713struct drm_i915_gem_caching {
714 /**
715 * Handle of the buffer to set/get the caching level of. */
716 __u32 handle;
717
718 /**
719 * Cacheing level to apply or return value
720 *
721 * bits0-15 are for generic caching control (i.e. the above defined
722 * values). bits16-31 are reserved for platform-specific variations
723 * (e.g. l3$ caching on gen7). */
724 __u32 caching;
725};
726
727#define I915_TILING_NONE 0
728#define I915_TILING_X 1
729#define I915_TILING_Y 2
730
731#define I915_BIT_6_SWIZZLE_NONE 0
732#define I915_BIT_6_SWIZZLE_9 1
733#define I915_BIT_6_SWIZZLE_9_10 2
734#define I915_BIT_6_SWIZZLE_9_11 3
735#define I915_BIT_6_SWIZZLE_9_10_11 4
736/* Not seen by userland */
737#define I915_BIT_6_SWIZZLE_UNKNOWN 5
738/* Seen by userland. */
739#define I915_BIT_6_SWIZZLE_9_17 6
740#define I915_BIT_6_SWIZZLE_9_10_17 7
741
742struct drm_i915_gem_set_tiling {
743 /** Handle of the buffer to have its tiling state updated */
744 __u32 handle;
745
746 /**
747 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
748 * I915_TILING_Y).
749 *
750 * This value is to be set on request, and will be updated by the
751 * kernel on successful return with the actual chosen tiling layout.
752 *
753 * The tiling mode may be demoted to I915_TILING_NONE when the system
754 * has bit 6 swizzling that can't be managed correctly by GEM.
755 *
756 * Buffer contents become undefined when changing tiling_mode.
757 */
758 __u32 tiling_mode;
759
760 /**
761 * Stride in bytes for the object when in I915_TILING_X or
762 * I915_TILING_Y.
763 */
764 __u32 stride;
765
766 /**
767 * Returned address bit 6 swizzling required for CPU access through
768 * mmap mapping.
769 */
770 __u32 swizzle_mode;
771};
772
773struct drm_i915_gem_get_tiling {
774 /** Handle of the buffer to get tiling state for. */
775 __u32 handle;
776
777 /**
778 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
779 * I915_TILING_Y).
780 */
781 __u32 tiling_mode;
782
783 /**
784 * Returned address bit 6 swizzling required for CPU access through
785 * mmap mapping.
786 */
787 __u32 swizzle_mode;
788};
789
790struct drm_i915_gem_get_aperture {
791 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
792 __u64 aper_size;
793
794 /**
795 * Available space in the aperture used by i915_gem_execbuffer, in
796 * bytes
797 */
798 __u64 aper_available_size;
799};
800
801struct drm_i915_get_pipe_from_crtc_id {
802 /** ID of CRTC being requested **/
803 __u32 crtc_id;
804
805 /** pipe of requested CRTC **/
806 __u32 pipe;
807};
808
809#define I915_MADV_WILLNEED 0
810#define I915_MADV_DONTNEED 1
811#define __I915_MADV_PURGED 2 /* internal state */
812
813struct drm_i915_gem_madvise {
814 /** Handle of the buffer to change the backing store advice */
815 __u32 handle;
816
817 /* Advice: either the buffer will be needed again in the near future,
818 * or wont be and could be discarded under memory pressure.
819 */
820 __u32 madv;
821
822 /** Whether the backing store still exists. */
823 __u32 retained;
824};
825
826/* flags */
827#define I915_OVERLAY_TYPE_MASK 0xff
828#define I915_OVERLAY_YUV_PLANAR 0x01
829#define I915_OVERLAY_YUV_PACKED 0x02
830#define I915_OVERLAY_RGB 0x03
831
832#define I915_OVERLAY_DEPTH_MASK 0xff00
833#define I915_OVERLAY_RGB24 0x1000
834#define I915_OVERLAY_RGB16 0x2000
835#define I915_OVERLAY_RGB15 0x3000
836#define I915_OVERLAY_YUV422 0x0100
837#define I915_OVERLAY_YUV411 0x0200
838#define I915_OVERLAY_YUV420 0x0300
839#define I915_OVERLAY_YUV410 0x0400
840
841#define I915_OVERLAY_SWAP_MASK 0xff0000
842#define I915_OVERLAY_NO_SWAP 0x000000
843#define I915_OVERLAY_UV_SWAP 0x010000
844#define I915_OVERLAY_Y_SWAP 0x020000
845#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
846
847#define I915_OVERLAY_FLAGS_MASK 0xff000000
848#define I915_OVERLAY_ENABLE 0x01000000
849
850struct drm_intel_overlay_put_image {
851 /* various flags and src format description */
852 __u32 flags;
853 /* source picture description */
854 __u32 bo_handle;
855 /* stride values and offsets are in bytes, buffer relative */
856 __u16 stride_Y; /* stride for packed formats */
857 __u16 stride_UV;
858 __u32 offset_Y; /* offset for packet formats */
859 __u32 offset_U;
860 __u32 offset_V;
861 /* in pixels */
862 __u16 src_width;
863 __u16 src_height;
864 /* to compensate the scaling factors for partially covered surfaces */
865 __u16 src_scan_width;
866 __u16 src_scan_height;
867 /* output crtc description */
868 __u32 crtc_id;
869 __u16 dst_x;
870 __u16 dst_y;
871 __u16 dst_width;
872 __u16 dst_height;
873};
874
875/* flags */
876#define I915_OVERLAY_UPDATE_ATTRS (1<<0)
877#define I915_OVERLAY_UPDATE_GAMMA (1<<1)
878struct drm_intel_overlay_attrs {
879 __u32 flags;
880 __u32 color_key;
881 __s32 brightness;
882 __u32 contrast;
883 __u32 saturation;
884 __u32 gamma0;
885 __u32 gamma1;
886 __u32 gamma2;
887 __u32 gamma3;
888 __u32 gamma4;
889 __u32 gamma5;
890};
891
892/*
893 * Intel sprite handling
894 *
895 * Color keying works with a min/mask/max tuple. Both source and destination
896 * color keying is allowed.
897 *
898 * Source keying:
899 * Sprite pixels within the min & max values, masked against the color channels
900 * specified in the mask field, will be transparent. All other pixels will
901 * be displayed on top of the primary plane. For RGB surfaces, only the min
902 * and mask fields will be used; ranged compares are not allowed.
903 *
904 * Destination keying:
905 * Primary plane pixels that match the min value, masked against the color
906 * channels specified in the mask field, will be replaced by corresponding
907 * pixels from the sprite plane.
908 *
909 * Note that source & destination keying are exclusive; only one can be
910 * active on a given plane.
911 */
912
913#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
914#define I915_SET_COLORKEY_DESTINATION (1<<1)
915#define I915_SET_COLORKEY_SOURCE (1<<2)
916struct drm_intel_sprite_colorkey {
917 __u32 plane_id;
918 __u32 min_value;
919 __u32 channel_mask;
920 __u32 max_value;
921 __u32 flags;
922};
923
924struct drm_i915_gem_wait {
925 /** Handle of BO we shall wait on */
926 __u32 bo_handle;
927 __u32 flags;
928 /** Number of nanoseconds to wait, Returns time remaining. */
929 __s64 timeout_ns;
930};
931
932struct drm_i915_gem_context_create {
933 /* output: id of new context*/
934 __u32 ctx_id;
935 __u32 pad;
936};
937
938struct drm_i915_gem_context_destroy {
939 __u32 ctx_id;
940 __u32 pad;
941};
942
943struct drm_i915_reg_read {
944 __u64 offset;
945 __u64 val; /* Return value */
946};
947#endif /* _UAPI_I915_DRM_H_ */
diff --git a/include/drm/mga_drm.h b/include/uapi/drm/mga_drm.h
index 2375bfd6e5e9..2375bfd6e5e9 100644
--- a/include/drm/mga_drm.h
+++ b/include/uapi/drm/mga_drm.h
diff --git a/include/drm/nouveau_drm.h b/include/uapi/drm/nouveau_drm.h
index 2a5769fdf8ba..2a5769fdf8ba 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/uapi/drm/nouveau_drm.h
diff --git a/include/drm/r128_drm.h b/include/uapi/drm/r128_drm.h
index 8d8878b55f55..8d8878b55f55 100644
--- a/include/drm/r128_drm.h
+++ b/include/uapi/drm/r128_drm.h
diff --git a/include/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index 4766c0f6a838..4766c0f6a838 100644
--- a/include/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
diff --git a/include/drm/savage_drm.h b/include/uapi/drm/savage_drm.h
index 818d49be2e6e..818d49be2e6e 100644
--- a/include/drm/savage_drm.h
+++ b/include/uapi/drm/savage_drm.h
diff --git a/include/drm/sis_drm.h b/include/uapi/drm/sis_drm.h
index df3763222d73..df3763222d73 100644
--- a/include/drm/sis_drm.h
+++ b/include/uapi/drm/sis_drm.h
diff --git a/include/drm/via_drm.h b/include/uapi/drm/via_drm.h
index 8b0533ccbd5a..8b0533ccbd5a 100644
--- a/include/drm/via_drm.h
+++ b/include/uapi/drm/via_drm.h
diff --git a/include/drm/vmwgfx_drm.h b/include/uapi/drm/vmwgfx_drm.h
index bcb0912afe7a..bcb0912afe7a 100644
--- a/include/drm/vmwgfx_drm.h
+++ b/include/uapi/drm/vmwgfx_drm.h
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 22:10:22 -0500