diff options
author | Alexander Clouter <alex@digriz.org.uk> | 2010-01-31 14:39:57 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 06:53:22 -0500 |
commit | 7084338eb8eb0cc021ba86c340157bad397f3f0b (patch) | |
tree | 86af24efb71a66e333fffe2daab1477dd3af5925 | |
parent | 632b629c0c4b0f8caaf7f2b448911d03859fda59 (diff) |
MIPS: AR7: Make ar7_register_devices much more durable
[Ralf: Fixed up the rejects and changed all the new printk(KERN_...); to
pr_xxx() as suggested by Wu.]
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/920/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/ar7/platform.c | 147 |
1 files changed, 81 insertions, 66 deletions
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 65facecb3ffb..246df7aca2e7 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c | |||
@@ -529,115 +529,130 @@ static struct platform_device ar7_wdt = { | |||
529 | /***************************************************************************** | 529 | /***************************************************************************** |
530 | * Init | 530 | * Init |
531 | ****************************************************************************/ | 531 | ****************************************************************************/ |
532 | static int __init ar7_register_devices(void) | 532 | static int __init ar7_register_uarts(void) |
533 | { | 533 | { |
534 | u16 chip_id; | ||
535 | int res; | ||
536 | u32 *bootcr, val; | ||
537 | #ifdef CONFIG_SERIAL_8250 | 534 | #ifdef CONFIG_SERIAL_8250 |
538 | static struct uart_port uart_port[2] __initdata; | 535 | static struct uart_port uart_port __initdata; |
539 | struct clk *bus_clk; | 536 | struct clk *bus_clk; |
537 | int res; | ||
540 | 538 | ||
541 | memset(uart_port, 0, sizeof(struct uart_port) * 2); | 539 | memset(&uart_port, 0, sizeof(struct uart_port)); |
542 | 540 | ||
543 | bus_clk = clk_get(NULL, "bus"); | 541 | bus_clk = clk_get(NULL, "bus"); |
544 | if (IS_ERR(bus_clk)) | 542 | if (IS_ERR(bus_clk)) |
545 | panic("unable to get bus clk\n"); | 543 | panic("unable to get bus clk\n"); |
546 | 544 | ||
547 | uart_port[0].type = PORT_16550A; | 545 | uart_port.type = PORT_16550A; |
548 | uart_port[0].line = 0; | 546 | uart_port.uartclk = clk_get_rate(bus_clk) / 2; |
549 | uart_port[0].irq = AR7_IRQ_UART0; | 547 | uart_port.iotype = UPIO_MEM32; |
550 | uart_port[0].uartclk = clk_get_rate(bus_clk) / 2; | 548 | uart_port.regshift = 2; |
551 | uart_port[0].iotype = UPIO_MEM32; | 549 | |
552 | uart_port[0].mapbase = AR7_REGS_UART0; | 550 | uart_port.line = 0; |
553 | uart_port[0].membase = ioremap(uart_port[0].mapbase, 256); | 551 | uart_port.irq = AR7_IRQ_UART0; |
554 | uart_port[0].regshift = 2; | 552 | uart_port.mapbase = AR7_REGS_UART0; |
555 | res = early_serial_setup(&uart_port[0]); | 553 | uart_port.membase = ioremap(uart_port.mapbase, 256); |
554 | |||
555 | res = early_serial_setup(&uart_port); | ||
556 | if (res) | 556 | if (res) |
557 | return res; | 557 | return res; |
558 | 558 | ||
559 | /* Only TNETD73xx have a second serial port */ | 559 | /* Only TNETD73xx have a second serial port */ |
560 | if (ar7_has_second_uart()) { | 560 | if (ar7_has_second_uart()) { |
561 | uart_port[1].type = PORT_16550A; | 561 | uart_port.line = 1; |
562 | uart_port[1].line = 1; | 562 | uart_port.irq = AR7_IRQ_UART1; |
563 | uart_port[1].irq = AR7_IRQ_UART1; | 563 | uart_port.mapbase = UR8_REGS_UART1; |
564 | uart_port[1].uartclk = clk_get_rate(bus_clk) / 2; | 564 | uart_port.membase = ioremap(uart_port.mapbase, 256); |
565 | uart_port[1].iotype = UPIO_MEM32; | 565 | |
566 | uart_port[1].mapbase = UR8_REGS_UART1; | 566 | res = early_serial_setup(&uart_port); |
567 | uart_port[1].membase = ioremap(uart_port[1].mapbase, 256); | ||
568 | uart_port[1].regshift = 2; | ||
569 | res = early_serial_setup(&uart_port[1]); | ||
570 | if (res) | 567 | if (res) |
571 | return res; | 568 | return res; |
572 | } | 569 | } |
573 | #endif /* CONFIG_SERIAL_8250 */ | 570 | #endif |
571 | |||
572 | return 0; | ||
573 | } | ||
574 | |||
575 | static int __init ar7_register_devices(void) | ||
576 | { | ||
577 | void __iomem *bootcr; | ||
578 | u32 val; | ||
579 | u16 chip_id; | ||
580 | int res; | ||
581 | |||
582 | res = ar7_register_uarts(); | ||
583 | if (res) | ||
584 | pr_err("unable to setup uart(s): %d\n", res); | ||
585 | |||
574 | res = platform_device_register(&physmap_flash); | 586 | res = platform_device_register(&physmap_flash); |
575 | if (res) | 587 | if (res) |
576 | return res; | 588 | pr_warning("unable to register physmap-flash: %d\n", res); |
577 | 589 | ||
578 | ar7_device_disable(vlynq_low_data.reset_bit); | 590 | ar7_device_disable(vlynq_low_data.reset_bit); |
579 | res = platform_device_register(&vlynq_low); | 591 | res = platform_device_register(&vlynq_low); |
580 | if (res) | 592 | if (res) |
581 | return res; | 593 | pr_warning("unable to register vlynq-low: %d\n", res); |
582 | 594 | ||
583 | if (ar7_has_high_vlynq()) { | 595 | if (ar7_has_high_vlynq()) { |
584 | ar7_device_disable(vlynq_high_data.reset_bit); | 596 | ar7_device_disable(vlynq_high_data.reset_bit); |
585 | res = platform_device_register(&vlynq_high); | 597 | res = platform_device_register(&vlynq_high); |
586 | if (res) | 598 | if (res) |
587 | return res; | 599 | pr_warning("unable to register vlynq-high: %d\n", res); |
588 | } | 600 | } |
589 | 601 | ||
590 | if (ar7_has_high_cpmac()) { | 602 | if (ar7_has_high_cpmac()) { |
591 | res = fixed_phy_add(PHY_POLL, cpmac_high.id, &fixed_phy_status); | 603 | if (!res) { |
592 | if (res && res != -ENODEV) | 604 | cpmac_get_mac(1, cpmac_high_data.dev_addr); |
593 | return res; | 605 | |
594 | cpmac_get_mac(1, cpmac_high_data.dev_addr); | 606 | res = platform_device_register(&cpmac_high); |
595 | res = platform_device_register(&cpmac_high); | 607 | if (res) |
596 | if (res) | 608 | pr_warning("unable to register cpmac-high: %d\n", res); |
597 | return res; | 609 | } else |
598 | } else { | 610 | pr_warning("unable to add cpmac-high phy: %d\n", res); |
611 | } else | ||
599 | cpmac_low_data.phy_mask = 0xffffffff; | 612 | cpmac_low_data.phy_mask = 0xffffffff; |
600 | } | ||
601 | 613 | ||
602 | res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status); | 614 | res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status); |
603 | if (res && res != -ENODEV) | 615 | if (!res) { |
604 | return res; | 616 | cpmac_get_mac(0, cpmac_low_data.dev_addr); |
605 | 617 | res = platform_device_register(&cpmac_low); | |
606 | cpmac_get_mac(0, cpmac_low_data.dev_addr); | 618 | if (res) |
607 | res = platform_device_register(&cpmac_low); | 619 | pr_warning("unable to register cpmac-low: %d\n", res); |
608 | if (res) | 620 | } else |
609 | return res; | 621 | pr_warning("unable to add cpmac-low phy: %d\n", res); |
610 | 622 | ||
611 | detect_leds(); | 623 | detect_leds(); |
612 | res = platform_device_register(&ar7_gpio_leds); | 624 | res = platform_device_register(&ar7_gpio_leds); |
613 | if (res) | 625 | if (res) |
614 | return res; | 626 | pr_warning("unable to register leds: %d\n", res); |
615 | 627 | ||
616 | res = platform_device_register(&ar7_udc); | 628 | res = platform_device_register(&ar7_udc); |
617 | 629 | if (res) | |
618 | chip_id = ar7_chip_id(); | 630 | pr_warning("unable to register usb slave: %d\n", res); |
619 | switch (chip_id) { | ||
620 | case AR7_CHIP_7100: | ||
621 | case AR7_CHIP_7200: | ||
622 | ar7_wdt_res.start = AR7_REGS_WDT; | ||
623 | break; | ||
624 | case AR7_CHIP_7300: | ||
625 | ar7_wdt_res.start = UR8_REGS_WDT; | ||
626 | break; | ||
627 | default: | ||
628 | break; | ||
629 | } | ||
630 | |||
631 | ar7_wdt_res.end = ar7_wdt_res.start + 0x20; | ||
632 | |||
633 | bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); | ||
634 | val = *bootcr; | ||
635 | iounmap(bootcr); | ||
636 | 631 | ||
637 | /* Register watchdog only if enabled in hardware */ | 632 | /* Register watchdog only if enabled in hardware */ |
638 | if (val & AR7_WDT_HW_ENA) | 633 | bootcr = ioremap_nocache(AR7_REGS_DCL, 4); |
634 | val = readl(bootcr); | ||
635 | iounmap(bootcr); | ||
636 | if (val & AR7_WDT_HW_ENA) { | ||
637 | chip_id = ar7_chip_id(); | ||
638 | switch (chip_id) { | ||
639 | case AR7_CHIP_7100: | ||
640 | case AR7_CHIP_7200: | ||
641 | ar7_wdt_res.start = AR7_REGS_WDT; | ||
642 | break; | ||
643 | case AR7_CHIP_7300: | ||
644 | ar7_wdt_res.start = UR8_REGS_WDT; | ||
645 | break; | ||
646 | default: | ||
647 | break; | ||
648 | } | ||
649 | |||
650 | ar7_wdt_res.end = ar7_wdt_res.start + 0x20; | ||
639 | res = platform_device_register(&ar7_wdt); | 651 | res = platform_device_register(&ar7_wdt); |
652 | if (res) | ||
653 | pr_warning("unable to register watchdog: %d\n", res); | ||
654 | } | ||
640 | 655 | ||
641 | return res; | 656 | return 0; |
642 | } | 657 | } |
643 | arch_initcall(ar7_register_devices); | 658 | arch_initcall(ar7_register_devices); |