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authorPeter Ujfalusi <peter.ujfalusi@ti.com>2013-11-14 04:35:29 -0500
committerMark Brown <broonie@linaro.org>2013-12-10 06:22:16 -0500
commit70091a3e6aa2e7a05eaefcaec1a43c27a5023eb7 (patch)
tree30032b1cd73f7dbcbe2277d8730b85cdce4cfa4c
parenteba0ecf067913d60768bb3d11f861b949f072a93 (diff)
ASoC: davinci-mcasp: Rename private struct and it's users (dev -> mcasp)
Rename the private struct from davinci_audio_dev to davinci_mcasp. Change the local use of the pointer to this struct from *dev to *mcasp. The aim is to have better readable code for the first look since having dev->xxxx in the code when using the local private struct is a bit surprising. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Mark Brown <broonie@linaro.org>
-rw-r--r--sound/soc/davinci/davinci-mcasp.c418
1 files changed, 209 insertions, 209 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index ce1607b3c6df..bd85c98bf5a5 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -35,7 +35,7 @@
35#include "davinci-pcm.h" 35#include "davinci-pcm.h"
36#include "davinci-mcasp.h" 36#include "davinci-mcasp.h"
37 37
38struct davinci_audio_dev { 38struct davinci_mcasp {
39 struct davinci_pcm_dma_params dma_params[2]; 39 struct davinci_pcm_dma_params dma_params[2];
40 void __iomem *base; 40 void __iomem *base;
41 struct device *dev; 41 struct device *dev;
@@ -107,36 +107,36 @@ static void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
107 printk(KERN_ERR "GBLCTL write error\n"); 107 printk(KERN_ERR "GBLCTL write error\n");
108} 108}
109 109
110static void mcasp_start_rx(struct davinci_audio_dev *dev) 110static void mcasp_start_rx(struct davinci_mcasp *mcasp)
111{ 111{
112 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST); 112 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
113 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST); 113 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
114 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR); 114 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
115 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0); 115 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXBUF_REG, 0);
116 116
117 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 117 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
118 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 118 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
119 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXBUF_REG, 0); 119 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXBUF_REG, 0);
120 120
121 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST); 121 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
122 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST); 122 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
123} 123}
124 124
125static void mcasp_start_tx(struct davinci_audio_dev *dev) 125static void mcasp_start_tx(struct davinci_mcasp *mcasp)
126{ 126{
127 u8 offset = 0, i; 127 u8 offset = 0, i;
128 u32 cnt; 128 u32 cnt;
129 129
130 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST); 130 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
131 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST); 131 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
132 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR); 132 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
133 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); 133 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0);
134 134
135 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST); 135 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
136 mcasp_set_ctl_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST); 136 mcasp_set_ctl_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
137 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); 137 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0);
138 for (i = 0; i < dev->num_serializer; i++) { 138 for (i = 0; i < mcasp->num_serializer; i++) {
139 if (dev->serial_dir[i] == TX_MODE) { 139 if (mcasp->serial_dir[i] == TX_MODE) {
140 offset = i; 140 offset = i;
141 break; 141 break;
142 } 142 }
@@ -144,116 +144,116 @@ static void mcasp_start_tx(struct davinci_audio_dev *dev)
144 144
145 /* wait for TX ready */ 145 /* wait for TX ready */
146 cnt = 0; 146 cnt = 0;
147 while (!(mcasp_get_reg(dev->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) & 147 while (!(mcasp_get_reg(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(offset)) &
148 TXSTATE) && (cnt < 100000)) 148 TXSTATE) && (cnt < 100000))
149 cnt++; 149 cnt++;
150 150
151 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXBUF_REG, 0); 151 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXBUF_REG, 0);
152} 152}
153 153
154static void davinci_mcasp_start(struct davinci_audio_dev *dev, int stream) 154static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
155{ 155{
156 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 156 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
157 if (dev->txnumevt) { /* enable FIFO */ 157 if (mcasp->txnumevt) { /* enable FIFO */
158 switch (dev->version) { 158 switch (mcasp->version) {
159 case MCASP_VERSION_3: 159 case MCASP_VERSION_3:
160 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL, 160 mcasp_clr_bits(mcasp->base + MCASP_VER3_WFIFOCTL,
161 FIFO_ENABLE); 161 FIFO_ENABLE);
162 mcasp_set_bits(dev->base + MCASP_VER3_WFIFOCTL, 162 mcasp_set_bits(mcasp->base + MCASP_VER3_WFIFOCTL,
163 FIFO_ENABLE); 163 FIFO_ENABLE);
164 break; 164 break;
165 default: 165 default:
166 mcasp_clr_bits(dev->base + 166 mcasp_clr_bits(mcasp->base +
167 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE); 167 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
168 mcasp_set_bits(dev->base + 168 mcasp_set_bits(mcasp->base +
169 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE); 169 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
170 } 170 }
171 } 171 }
172 mcasp_start_tx(dev); 172 mcasp_start_tx(mcasp);
173 } else { 173 } else {
174 if (dev->rxnumevt) { /* enable FIFO */ 174 if (mcasp->rxnumevt) { /* enable FIFO */
175 switch (dev->version) { 175 switch (mcasp->version) {
176 case MCASP_VERSION_3: 176 case MCASP_VERSION_3:
177 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL, 177 mcasp_clr_bits(mcasp->base + MCASP_VER3_RFIFOCTL,
178 FIFO_ENABLE); 178 FIFO_ENABLE);
179 mcasp_set_bits(dev->base + MCASP_VER3_RFIFOCTL, 179 mcasp_set_bits(mcasp->base + MCASP_VER3_RFIFOCTL,
180 FIFO_ENABLE); 180 FIFO_ENABLE);
181 break; 181 break;
182 default: 182 default:
183 mcasp_clr_bits(dev->base + 183 mcasp_clr_bits(mcasp->base +
184 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE); 184 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
185 mcasp_set_bits(dev->base + 185 mcasp_set_bits(mcasp->base +
186 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE); 186 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
187 } 187 }
188 } 188 }
189 mcasp_start_rx(dev); 189 mcasp_start_rx(mcasp);
190 } 190 }
191} 191}
192 192
193static void mcasp_stop_rx(struct davinci_audio_dev *dev) 193static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
194{ 194{
195 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLR_REG, 0); 195 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_GBLCTLR_REG, 0);
196 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 196 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
197} 197}
198 198
199static void mcasp_stop_tx(struct davinci_audio_dev *dev) 199static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
200{ 200{
201 mcasp_set_reg(dev->base + DAVINCI_MCASP_GBLCTLX_REG, 0); 201 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_GBLCTLX_REG, 0);
202 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 202 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
203} 203}
204 204
205static void davinci_mcasp_stop(struct davinci_audio_dev *dev, int stream) 205static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
206{ 206{
207 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 207 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
208 if (dev->txnumevt) { /* disable FIFO */ 208 if (mcasp->txnumevt) { /* disable FIFO */
209 switch (dev->version) { 209 switch (mcasp->version) {
210 case MCASP_VERSION_3: 210 case MCASP_VERSION_3:
211 mcasp_clr_bits(dev->base + MCASP_VER3_WFIFOCTL, 211 mcasp_clr_bits(mcasp->base + MCASP_VER3_WFIFOCTL,
212 FIFO_ENABLE); 212 FIFO_ENABLE);
213 break; 213 break;
214 default: 214 default:
215 mcasp_clr_bits(dev->base + 215 mcasp_clr_bits(mcasp->base +
216 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE); 216 DAVINCI_MCASP_WFIFOCTL, FIFO_ENABLE);
217 } 217 }
218 } 218 }
219 mcasp_stop_tx(dev); 219 mcasp_stop_tx(mcasp);
220 } else { 220 } else {
221 if (dev->rxnumevt) { /* disable FIFO */ 221 if (mcasp->rxnumevt) { /* disable FIFO */
222 switch (dev->version) { 222 switch (mcasp->version) {
223 case MCASP_VERSION_3: 223 case MCASP_VERSION_3:
224 mcasp_clr_bits(dev->base + MCASP_VER3_RFIFOCTL, 224 mcasp_clr_bits(mcasp->base + MCASP_VER3_RFIFOCTL,
225 FIFO_ENABLE); 225 FIFO_ENABLE);
226 break; 226 break;
227 227
228 default: 228 default:
229 mcasp_clr_bits(dev->base + 229 mcasp_clr_bits(mcasp->base +
230 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE); 230 DAVINCI_MCASP_RFIFOCTL, FIFO_ENABLE);
231 } 231 }
232 } 232 }
233 mcasp_stop_rx(dev); 233 mcasp_stop_rx(mcasp);
234 } 234 }
235} 235}
236 236
237static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 237static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
238 unsigned int fmt) 238 unsigned int fmt)
239{ 239{
240 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 240 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
241 void __iomem *base = dev->base; 241 void __iomem *base = mcasp->base;
242 242
243 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 243 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
244 case SND_SOC_DAIFMT_DSP_B: 244 case SND_SOC_DAIFMT_DSP_B:
245 case SND_SOC_DAIFMT_AC97: 245 case SND_SOC_DAIFMT_AC97:
246 mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 246 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
247 mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 247 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
248 break; 248 break;
249 default: 249 default:
250 /* configure a full-word SYNC pulse (LRCLK) */ 250 /* configure a full-word SYNC pulse (LRCLK) */
251 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR); 251 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
252 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR); 252 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
253 253
254 /* make 1st data bit occur one ACLK cycle after the frame sync */ 254 /* make 1st data bit occur one ACLK cycle after the frame sync */
255 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1)); 255 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));
256 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1)); 256 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));
257 break; 257 break;
258 } 258 }
259 259
@@ -342,25 +342,25 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
342 342
343static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div) 343static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
344{ 344{
345 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai); 345 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
346 346
347 switch (div_id) { 347 switch (div_id) {
348 case 0: /* MCLK divider */ 348 case 0: /* MCLK divider */
349 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, 349 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG,
350 AHCLKXDIV(div - 1), AHCLKXDIV_MASK); 350 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
351 mcasp_mod_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, 351 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG,
352 AHCLKRDIV(div - 1), AHCLKRDIV_MASK); 352 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
353 break; 353 break;
354 354
355 case 1: /* BCLK divider */ 355 case 1: /* BCLK divider */
356 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, 356 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG,
357 ACLKXDIV(div - 1), ACLKXDIV_MASK); 357 ACLKXDIV(div - 1), ACLKXDIV_MASK);
358 mcasp_mod_bits(dev->base + DAVINCI_MCASP_ACLKRCTL_REG, 358 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_ACLKRCTL_REG,
359 ACLKRDIV(div - 1), ACLKRDIV_MASK); 359 ACLKRDIV(div - 1), ACLKRDIV_MASK);
360 break; 360 break;
361 361
362 case 2: /* BCLK/LRCLK ratio */ 362 case 2: /* BCLK/LRCLK ratio */
363 dev->bclk_lrclk_ratio = div; 363 mcasp->bclk_lrclk_ratio = div;
364 break; 364 break;
365 365
366 default: 366 default:
@@ -373,22 +373,22 @@ static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div
373static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id, 373static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
374 unsigned int freq, int dir) 374 unsigned int freq, int dir)
375{ 375{
376 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai); 376 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
377 377
378 if (dir == SND_SOC_CLOCK_OUT) { 378 if (dir == SND_SOC_CLOCK_OUT) {
379 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 379 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
380 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 380 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
381 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX); 381 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
382 } else { 382 } else {
383 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE); 383 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
384 mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE); 384 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
385 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, AHCLKX); 385 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG, AHCLKX);
386 } 386 }
387 387
388 return 0; 388 return 0;
389} 389}
390 390
391static int davinci_config_channel_size(struct davinci_audio_dev *dev, 391static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
392 int word_length) 392 int word_length)
393{ 393{
394 u32 fmt; 394 u32 fmt;
@@ -405,70 +405,70 @@ static int davinci_config_channel_size(struct davinci_audio_dev *dev,
405 * both left and right channels), so it has to be divided by number of 405 * both left and right channels), so it has to be divided by number of
406 * tdm-slots (for I2S - divided by 2). 406 * tdm-slots (for I2S - divided by 2).
407 */ 407 */
408 if (dev->bclk_lrclk_ratio) 408 if (mcasp->bclk_lrclk_ratio)
409 word_length = dev->bclk_lrclk_ratio / dev->tdm_slots; 409 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
410 410
411 /* mapping of the XSSZ bit-field as described in the datasheet */ 411 /* mapping of the XSSZ bit-field as described in the datasheet */
412 fmt = (word_length >> 1) - 1; 412 fmt = (word_length >> 1) - 1;
413 413
414 if (dev->op_mode != DAVINCI_MCASP_DIT_MODE) { 414 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
415 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, 415 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG,
416 RXSSZ(fmt), RXSSZ(0x0F)); 416 RXSSZ(fmt), RXSSZ(0x0F));
417 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, 417 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
418 TXSSZ(fmt), TXSSZ(0x0F)); 418 TXSSZ(fmt), TXSSZ(0x0F));
419 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, 419 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
420 TXROT(tx_rotate), TXROT(7)); 420 TXROT(tx_rotate), TXROT(7));
421 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, 421 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG,
422 RXROT(rx_rotate), RXROT(7)); 422 RXROT(rx_rotate), RXROT(7));
423 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXMASK_REG, 423 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXMASK_REG,
424 mask); 424 mask);
425 } 425 }
426 426
427 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXMASK_REG, mask); 427 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXMASK_REG, mask);
428 428
429 return 0; 429 return 0;
430} 430}
431 431
432static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream, 432static int davinci_hw_common_param(struct davinci_mcasp *mcasp, int stream,
433 int channels) 433 int channels)
434{ 434{
435 int i; 435 int i;
436 u8 tx_ser = 0; 436 u8 tx_ser = 0;
437 u8 rx_ser = 0; 437 u8 rx_ser = 0;
438 u8 ser; 438 u8 ser;
439 u8 slots = dev->tdm_slots; 439 u8 slots = mcasp->tdm_slots;
440 u8 max_active_serializers = (channels + slots - 1) / slots; 440 u8 max_active_serializers = (channels + slots - 1) / slots;
441 /* Default configuration */ 441 /* Default configuration */
442 mcasp_set_bits(dev->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT); 442 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
443 443
444 /* All PINS as McASP */ 444 /* All PINS as McASP */
445 mcasp_set_reg(dev->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000); 445 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_PFUNC_REG, 0x00000000);
446 446
447 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 447 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
448 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF); 448 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
449 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, 449 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_XEVTCTL_REG,
450 TXDATADMADIS); 450 TXDATADMADIS);
451 } else { 451 } else {
452 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF); 452 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
453 mcasp_clr_bits(dev->base + DAVINCI_MCASP_REVTCTL_REG, 453 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_REVTCTL_REG,
454 RXDATADMADIS); 454 RXDATADMADIS);
455 } 455 }
456 456
457 for (i = 0; i < dev->num_serializer; i++) { 457 for (i = 0; i < mcasp->num_serializer; i++) {
458 mcasp_set_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i), 458 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(i),
459 dev->serial_dir[i]); 459 mcasp->serial_dir[i]);
460 if (dev->serial_dir[i] == TX_MODE && 460 if (mcasp->serial_dir[i] == TX_MODE &&
461 tx_ser < max_active_serializers) { 461 tx_ser < max_active_serializers) {
462 mcasp_set_bits(dev->base + DAVINCI_MCASP_PDIR_REG, 462 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG,
463 AXR(i)); 463 AXR(i));
464 tx_ser++; 464 tx_ser++;
465 } else if (dev->serial_dir[i] == RX_MODE && 465 } else if (mcasp->serial_dir[i] == RX_MODE &&
466 rx_ser < max_active_serializers) { 466 rx_ser < max_active_serializers) {
467 mcasp_clr_bits(dev->base + DAVINCI_MCASP_PDIR_REG, 467 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_PDIR_REG,
468 AXR(i)); 468 AXR(i));
469 rx_ser++; 469 rx_ser++;
470 } else { 470 } else {
471 mcasp_mod_bits(dev->base + DAVINCI_MCASP_XRSRCTL_REG(i), 471 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_XRSRCTL_REG(i),
472 SRMOD_INACTIVE, SRMOD_MASK); 472 SRMOD_INACTIVE, SRMOD_MASK);
473 } 473 }
474 } 474 }
@@ -479,127 +479,127 @@ static int davinci_hw_common_param(struct davinci_audio_dev *dev, int stream,
479 ser = rx_ser; 479 ser = rx_ser;
480 480
481 if (ser < max_active_serializers) { 481 if (ser < max_active_serializers) {
482 dev_warn(dev->dev, "stream has more channels (%d) than are " 482 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
483 "enabled in mcasp (%d)\n", channels, ser * slots); 483 "enabled in mcasp (%d)\n", channels, ser * slots);
484 return -EINVAL; 484 return -EINVAL;
485 } 485 }
486 486
487 if (dev->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) { 487 if (mcasp->txnumevt && stream == SNDRV_PCM_STREAM_PLAYBACK) {
488 if (dev->txnumevt * tx_ser > 64) 488 if (mcasp->txnumevt * tx_ser > 64)
489 dev->txnumevt = 1; 489 mcasp->txnumevt = 1;
490 490
491 switch (dev->version) { 491 switch (mcasp->version) {
492 case MCASP_VERSION_3: 492 case MCASP_VERSION_3:
493 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, tx_ser, 493 mcasp_mod_bits(mcasp->base + MCASP_VER3_WFIFOCTL, tx_ser,
494 NUMDMA_MASK); 494 NUMDMA_MASK);
495 mcasp_mod_bits(dev->base + MCASP_VER3_WFIFOCTL, 495 mcasp_mod_bits(mcasp->base + MCASP_VER3_WFIFOCTL,
496 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK); 496 ((mcasp->txnumevt * tx_ser) << 8), NUMEVT_MASK);
497 break; 497 break;
498 default: 498 default:
499 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, 499 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_WFIFOCTL,
500 tx_ser, NUMDMA_MASK); 500 tx_ser, NUMDMA_MASK);
501 mcasp_mod_bits(dev->base + DAVINCI_MCASP_WFIFOCTL, 501 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_WFIFOCTL,
502 ((dev->txnumevt * tx_ser) << 8), NUMEVT_MASK); 502 ((mcasp->txnumevt * tx_ser) << 8), NUMEVT_MASK);
503 } 503 }
504 } 504 }
505 505
506 if (dev->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) { 506 if (mcasp->rxnumevt && stream == SNDRV_PCM_STREAM_CAPTURE) {
507 if (dev->rxnumevt * rx_ser > 64) 507 if (mcasp->rxnumevt * rx_ser > 64)
508 dev->rxnumevt = 1; 508 mcasp->rxnumevt = 1;
509 switch (dev->version) { 509 switch (mcasp->version) {
510 case MCASP_VERSION_3: 510 case MCASP_VERSION_3:
511 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, rx_ser, 511 mcasp_mod_bits(mcasp->base + MCASP_VER3_RFIFOCTL, rx_ser,
512 NUMDMA_MASK); 512 NUMDMA_MASK);
513 mcasp_mod_bits(dev->base + MCASP_VER3_RFIFOCTL, 513 mcasp_mod_bits(mcasp->base + MCASP_VER3_RFIFOCTL,
514 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK); 514 ((mcasp->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
515 break; 515 break;
516 default: 516 default:
517 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, 517 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RFIFOCTL,
518 rx_ser, NUMDMA_MASK); 518 rx_ser, NUMDMA_MASK);
519 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RFIFOCTL, 519 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RFIFOCTL,
520 ((dev->rxnumevt * rx_ser) << 8), NUMEVT_MASK); 520 ((mcasp->rxnumevt * rx_ser) << 8), NUMEVT_MASK);
521 } 521 }
522 } 522 }
523 523
524 return 0; 524 return 0;
525} 525}
526 526
527static void davinci_hw_param(struct davinci_audio_dev *dev, int stream) 527static void davinci_hw_param(struct davinci_mcasp *mcasp, int stream)
528{ 528{
529 int i, active_slots; 529 int i, active_slots;
530 u32 mask = 0; 530 u32 mask = 0;
531 531
532 active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots; 532 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
533 for (i = 0; i < active_slots; i++) 533 for (i = 0; i < active_slots; i++)
534 mask |= (1 << i); 534 mask |= (1 << i);
535 535
536 mcasp_clr_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); 536 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
537 537
538 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 538 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
539 /* bit stream is MSB first with no delay */ 539 /* bit stream is MSB first with no delay */
540 /* DSP_B mode */ 540 /* DSP_B mode */
541 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, mask); 541 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXTDM_REG, mask);
542 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, TXORD); 542 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG, TXORD);
543 543
544 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32)) 544 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
545 mcasp_mod_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, 545 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG,
546 FSXMOD(dev->tdm_slots), FSXMOD(0x1FF)); 546 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
547 else 547 else
548 printk(KERN_ERR "playback tdm slot %d not supported\n", 548 printk(KERN_ERR "playback tdm slot %d not supported\n",
549 dev->tdm_slots); 549 mcasp->tdm_slots);
550 } else { 550 } else {
551 /* bit stream is MSB first with no delay */ 551 /* bit stream is MSB first with no delay */
552 /* DSP_B mode */ 552 /* DSP_B mode */
553 mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, RXORD); 553 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_RXFMT_REG, RXORD);
554 mcasp_set_reg(dev->base + DAVINCI_MCASP_RXTDM_REG, mask); 554 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_RXTDM_REG, mask);
555 555
556 if ((dev->tdm_slots >= 2) && (dev->tdm_slots <= 32)) 556 if ((mcasp->tdm_slots >= 2) && (mcasp->tdm_slots <= 32))
557 mcasp_mod_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, 557 mcasp_mod_bits(mcasp->base + DAVINCI_MCASP_RXFMCTL_REG,
558 FSRMOD(dev->tdm_slots), FSRMOD(0x1FF)); 558 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
559 else 559 else
560 printk(KERN_ERR "capture tdm slot %d not supported\n", 560 printk(KERN_ERR "capture tdm slot %d not supported\n",
561 dev->tdm_slots); 561 mcasp->tdm_slots);
562 } 562 }
563} 563}
564 564
565/* S/PDIF */ 565/* S/PDIF */
566static void davinci_hw_dit_param(struct davinci_audio_dev *dev) 566static void davinci_hw_dit_param(struct davinci_mcasp *mcasp)
567{ 567{
568 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0 568 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
569 and LSB first */ 569 and LSB first */
570 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, 570 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXFMT_REG,
571 TXROT(6) | TXSSZ(15)); 571 TXROT(6) | TXSSZ(15));
572 572
573 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */ 573 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
574 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXFMCTL_REG, 574 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXFMCTL_REG,
575 AFSXE | FSXMOD(0x180)); 575 AFSXE | FSXMOD(0x180));
576 576
577 /* Set the TX tdm : for all the slots */ 577 /* Set the TX tdm : for all the slots */
578 mcasp_set_reg(dev->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF); 578 mcasp_set_reg(mcasp->base + DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
579 579
580 /* Set the TX clock controls : div = 1 and internal */ 580 /* Set the TX clock controls : div = 1 and internal */
581 mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, 581 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_ACLKXCTL_REG,
582 ACLKXE | TX_ASYNC); 582 ACLKXE | TX_ASYNC);
583 583
584 mcasp_clr_bits(dev->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS); 584 mcasp_clr_bits(mcasp->base + DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
585 585
586 /* Only 44100 and 48000 are valid, both have the same setting */ 586 /* Only 44100 and 48000 are valid, both have the same setting */
587 mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3)); 587 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
588 588
589 /* Enable the DIT */ 589 /* Enable the DIT */
590 mcasp_set_bits(dev->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN); 590 mcasp_set_bits(mcasp->base + DAVINCI_MCASP_TXDITCTL_REG, DITEN);
591} 591}
592 592
593static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream, 593static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
594 struct snd_pcm_hw_params *params, 594 struct snd_pcm_hw_params *params,
595 struct snd_soc_dai *cpu_dai) 595 struct snd_soc_dai *cpu_dai)
596{ 596{
597 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 597 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
598 struct davinci_pcm_dma_params *dma_params = 598 struct davinci_pcm_dma_params *dma_params =
599 &dev->dma_params[substream->stream]; 599 &mcasp->dma_params[substream->stream];
600 int word_length; 600 int word_length;
601 u8 fifo_level; 601 u8 fifo_level;
602 u8 slots = dev->tdm_slots; 602 u8 slots = mcasp->tdm_slots;
603 u8 active_serializers; 603 u8 active_serializers;
604 int channels; 604 int channels;
605 struct snd_interval *pcm_channels = hw_param_interval(params, 605 struct snd_interval *pcm_channels = hw_param_interval(params,
@@ -608,17 +608,17 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
608 608
609 active_serializers = (channels + slots - 1) / slots; 609 active_serializers = (channels + slots - 1) / slots;
610 610
611 if (davinci_hw_common_param(dev, substream->stream, channels) == -EINVAL) 611 if (davinci_hw_common_param(mcasp, substream->stream, channels) == -EINVAL)
612 return -EINVAL; 612 return -EINVAL;
613 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 613 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
614 fifo_level = dev->txnumevt * active_serializers; 614 fifo_level = mcasp->txnumevt * active_serializers;
615 else 615 else
616 fifo_level = dev->rxnumevt * active_serializers; 616 fifo_level = mcasp->rxnumevt * active_serializers;
617 617
618 if (dev->op_mode == DAVINCI_MCASP_DIT_MODE) 618 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
619 davinci_hw_dit_param(dev); 619 davinci_hw_dit_param(mcasp);
620 else 620 else
621 davinci_hw_param(dev, substream->stream); 621 davinci_hw_param(mcasp, substream->stream);
622 622
623 switch (params_format(params)) { 623 switch (params_format(params)) {
624 case SNDRV_PCM_FORMAT_U8: 624 case SNDRV_PCM_FORMAT_U8:
@@ -652,13 +652,13 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
652 return -EINVAL; 652 return -EINVAL;
653 } 653 }
654 654
655 if (dev->version == MCASP_VERSION_2 && !fifo_level) 655 if (mcasp->version == MCASP_VERSION_2 && !fifo_level)
656 dma_params->acnt = 4; 656 dma_params->acnt = 4;
657 else 657 else
658 dma_params->acnt = dma_params->data_type; 658 dma_params->acnt = dma_params->data_type;
659 659
660 dma_params->fifo_level = fifo_level; 660 dma_params->fifo_level = fifo_level;
661 davinci_config_channel_size(dev, word_length); 661 davinci_config_channel_size(mcasp, word_length);
662 662
663 return 0; 663 return 0;
664} 664}
@@ -666,29 +666,29 @@ static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
666static int davinci_mcasp_trigger(struct snd_pcm_substream *substream, 666static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
667 int cmd, struct snd_soc_dai *cpu_dai) 667 int cmd, struct snd_soc_dai *cpu_dai)
668{ 668{
669 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); 669 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
670 int ret = 0; 670 int ret = 0;
671 671
672 switch (cmd) { 672 switch (cmd) {
673 case SNDRV_PCM_TRIGGER_RESUME: 673 case SNDRV_PCM_TRIGGER_RESUME:
674 case SNDRV_PCM_TRIGGER_START: 674 case SNDRV_PCM_TRIGGER_START:
675 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 675 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
676 ret = pm_runtime_get_sync(dev->dev); 676 ret = pm_runtime_get_sync(mcasp->dev);
677 if (IS_ERR_VALUE(ret)) 677 if (IS_ERR_VALUE(ret))
678 dev_err(dev->dev, "pm_runtime_get_sync() failed\n"); 678 dev_err(mcasp->dev, "pm_runtime_get_sync() failed\n");
679 davinci_mcasp_start(dev, substream->stream); 679 davinci_mcasp_start(mcasp, substream->stream);
680 break; 680 break;
681 681
682 case SNDRV_PCM_TRIGGER_SUSPEND: 682 case SNDRV_PCM_TRIGGER_SUSPEND:
683 davinci_mcasp_stop(dev, substream->stream); 683 davinci_mcasp_stop(mcasp, substream->stream);
684 ret = pm_runtime_put_sync(dev->dev); 684 ret = pm_runtime_put_sync(mcasp->dev);
685 if (IS_ERR_VALUE(ret)) 685 if (IS_ERR_VALUE(ret))
686 dev_err(dev->dev, "pm_runtime_put_sync() failed\n"); 686 dev_err(mcasp->dev, "pm_runtime_put_sync() failed\n");
687 break; 687 break;
688 688
689 case SNDRV_PCM_TRIGGER_STOP: 689 case SNDRV_PCM_TRIGGER_STOP:
690 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 690 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
691 davinci_mcasp_stop(dev, substream->stream); 691 davinci_mcasp_stop(mcasp, substream->stream);
692 break; 692 break;
693 693
694 default: 694 default:
@@ -701,9 +701,9 @@ static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
701static int davinci_mcasp_startup(struct snd_pcm_substream *substream, 701static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
702 struct snd_soc_dai *dai) 702 struct snd_soc_dai *dai)
703{ 703{
704 struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(dai); 704 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
705 705
706 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params); 706 snd_soc_dai_set_dma_data(dai, substream, mcasp->dma_params);
707 return 0; 707 return 0;
708} 708}
709 709
@@ -915,7 +915,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
915 struct davinci_pcm_dma_params *dma_data; 915 struct davinci_pcm_dma_params *dma_data;
916 struct resource *mem, *ioarea, *res, *dat; 916 struct resource *mem, *ioarea, *res, *dat;
917 struct snd_platform_data *pdata; 917 struct snd_platform_data *pdata;
918 struct davinci_audio_dev *dev; 918 struct davinci_mcasp *mcasp;
919 int ret; 919 int ret;
920 920
921 if (!pdev->dev.platform_data && !pdev->dev.of_node) { 921 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
@@ -923,9 +923,9 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
923 return -EINVAL; 923 return -EINVAL;
924 } 924 }
925 925
926 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_audio_dev), 926 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
927 GFP_KERNEL); 927 GFP_KERNEL);
928 if (!dev) 928 if (!mcasp)
929 return -ENOMEM; 929 return -ENOMEM;
930 930
931 pdata = davinci_mcasp_set_pdata_from_of(pdev); 931 pdata = davinci_mcasp_set_pdata_from_of(pdev);
@@ -936,7 +936,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
936 936
937 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu"); 937 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
938 if (!mem) { 938 if (!mem) {
939 dev_warn(dev->dev, 939 dev_warn(mcasp->dev,
940 "\"mpu\" mem resource not found, using index 0\n"); 940 "\"mpu\" mem resource not found, using index 0\n");
941 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 941 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
942 if (!mem) { 942 if (!mem) {
@@ -960,27 +960,27 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
960 return ret; 960 return ret;
961 } 961 }
962 962
963 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); 963 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
964 if (!dev->base) { 964 if (!mcasp->base) {
965 dev_err(&pdev->dev, "ioremap failed\n"); 965 dev_err(&pdev->dev, "ioremap failed\n");
966 ret = -ENOMEM; 966 ret = -ENOMEM;
967 goto err_release_clk; 967 goto err_release_clk;
968 } 968 }
969 969
970 dev->op_mode = pdata->op_mode; 970 mcasp->op_mode = pdata->op_mode;
971 dev->tdm_slots = pdata->tdm_slots; 971 mcasp->tdm_slots = pdata->tdm_slots;
972 dev->num_serializer = pdata->num_serializer; 972 mcasp->num_serializer = pdata->num_serializer;
973 dev->serial_dir = pdata->serial_dir; 973 mcasp->serial_dir = pdata->serial_dir;
974 dev->version = pdata->version; 974 mcasp->version = pdata->version;
975 dev->txnumevt = pdata->txnumevt; 975 mcasp->txnumevt = pdata->txnumevt;
976 dev->rxnumevt = pdata->rxnumevt; 976 mcasp->rxnumevt = pdata->rxnumevt;
977 dev->dev = &pdev->dev; 977 mcasp->dev = &pdev->dev;
978 978
979 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 979 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
980 if (!dat) 980 if (!dat)
981 dat = mem; 981 dat = mem;
982 982
983 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]; 983 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
984 dma_data->asp_chan_q = pdata->asp_chan_q; 984 dma_data->asp_chan_q = pdata->asp_chan_q;
985 dma_data->ram_chan_q = pdata->ram_chan_q; 985 dma_data->ram_chan_q = pdata->ram_chan_q;
986 dma_data->sram_pool = pdata->sram_pool; 986 dma_data->sram_pool = pdata->sram_pool;
@@ -993,7 +993,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
993 else 993 else
994 dma_data->channel = pdata->tx_dma_channel; 994 dma_data->channel = pdata->tx_dma_channel;
995 995
996 dma_data = &dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]; 996 dma_data = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
997 dma_data->asp_chan_q = pdata->asp_chan_q; 997 dma_data->asp_chan_q = pdata->asp_chan_q;
998 dma_data->ram_chan_q = pdata->ram_chan_q; 998 dma_data->ram_chan_q = pdata->ram_chan_q;
999 dma_data->sram_pool = pdata->sram_pool; 999 dma_data->sram_pool = pdata->sram_pool;
@@ -1006,7 +1006,7 @@ static int davinci_mcasp_probe(struct platform_device *pdev)
1006 else 1006 else
1007 dma_data->channel = pdata->rx_dma_channel; 1007 dma_data->channel = pdata->rx_dma_channel;
1008 1008
1009 dev_set_drvdata(&pdev->dev, dev); 1009 dev_set_drvdata(&pdev->dev, mcasp);
1010 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component, 1010 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1011 &davinci_mcasp_dai[pdata->op_mode], 1); 1011 &davinci_mcasp_dai[pdata->op_mode], 1);
1012 1012
@@ -1044,32 +1044,32 @@ static int davinci_mcasp_remove(struct platform_device *pdev)
1044#ifdef CONFIG_PM_SLEEP 1044#ifdef CONFIG_PM_SLEEP
1045static int davinci_mcasp_suspend(struct device *dev) 1045static int davinci_mcasp_suspend(struct device *dev)
1046{ 1046{
1047 struct davinci_audio_dev *a = dev_get_drvdata(dev); 1047 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1048 void __iomem *base = a->base; 1048 void __iomem *base = mcasp->base;
1049 1049
1050 a->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG); 1050 mcasp->context.txfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_TXFMCTL_REG);
1051 a->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG); 1051 mcasp->context.rxfmtctl = mcasp_get_reg(base + DAVINCI_MCASP_RXFMCTL_REG);
1052 a->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG); 1052 mcasp->context.txfmt = mcasp_get_reg(base + DAVINCI_MCASP_TXFMT_REG);
1053 a->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG); 1053 mcasp->context.rxfmt = mcasp_get_reg(base + DAVINCI_MCASP_RXFMT_REG);
1054 a->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG); 1054 mcasp->context.aclkxctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKXCTL_REG);
1055 a->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG); 1055 mcasp->context.aclkrctl = mcasp_get_reg(base + DAVINCI_MCASP_ACLKRCTL_REG);
1056 a->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG); 1056 mcasp->context.pdir = mcasp_get_reg(base + DAVINCI_MCASP_PDIR_REG);
1057 1057
1058 return 0; 1058 return 0;
1059} 1059}
1060 1060
1061static int davinci_mcasp_resume(struct device *dev) 1061static int davinci_mcasp_resume(struct device *dev)
1062{ 1062{
1063 struct davinci_audio_dev *a = dev_get_drvdata(dev); 1063 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
1064 void __iomem *base = a->base; 1064 void __iomem *base = mcasp->base;
1065 1065
1066 mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, a->context.txfmtctl); 1066 mcasp_set_reg(base + DAVINCI_MCASP_TXFMCTL_REG, mcasp->context.txfmtctl);
1067 mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, a->context.rxfmtctl); 1067 mcasp_set_reg(base + DAVINCI_MCASP_RXFMCTL_REG, mcasp->context.rxfmtctl);
1068 mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, a->context.txfmt); 1068 mcasp_set_reg(base + DAVINCI_MCASP_TXFMT_REG, mcasp->context.txfmt);
1069 mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, a->context.rxfmt); 1069 mcasp_set_reg(base + DAVINCI_MCASP_RXFMT_REG, mcasp->context.rxfmt);
1070 mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, a->context.aclkxctl); 1070 mcasp_set_reg(base + DAVINCI_MCASP_ACLKXCTL_REG, mcasp->context.aclkxctl);
1071 mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, a->context.aclkrctl); 1071 mcasp_set_reg(base + DAVINCI_MCASP_ACLKRCTL_REG, mcasp->context.aclkrctl);
1072 mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, a->context.pdir); 1072 mcasp_set_reg(base + DAVINCI_MCASP_PDIR_REG, mcasp->context.pdir);
1073 1073
1074 return 0; 1074 return 0;
1075} 1075}