aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorTony Lindgren <tony@atomide.com>2012-06-22 04:50:22 -0400
committerTony Lindgren <tony@atomide.com>2012-06-22 04:50:22 -0400
commit6fd8246b1c1167c983b089f9eaafa13ef9ca7adf (patch)
tree4380085c128ab80d28fbb96806bfc4f85cd3cbb3
parent08f3098928c991560408e8c71d4af8b1a3ff2d67 (diff)
parent9c80f3aa8b7828c89c5bae5c769955d1ac58630b (diff)
Merge tag 'omap-devel-a-for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into devel-am33xx
Adds AM33xx PRCM support
Diffstat
-rw-r--r--arch/arm/mach-omap2/Makefile6
-rw-r--r--arch/arm/mach-omap2/clockdomain.h2
-rw-r--r--arch/arm/mach-omap2/clockdomain33xx.c74
-rw-r--r--arch/arm/mach-omap2/clockdomains33xx_data.c196
-rw-r--r--arch/arm/mach-omap2/cm-regbits-33xx.h687
-rw-r--r--arch/arm/mach-omap2/cm33xx.c313
-rw-r--r--arch/arm/mach-omap2/cm33xx.h420
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/control.h39
-rw-r--r--arch/arm/mach-omap2/io.c3
-rw-r--r--arch/arm/mach-omap2/powerdomain.h23
-rw-r--r--arch/arm/mach-omap2/powerdomain33xx.c229
-rw-r--r--arch/arm/mach-omap2/powerdomains33xx_data.c185
-rw-r--r--arch/arm/mach-omap2/prm-regbits-33xx.h357
-rw-r--r--arch/arm/mach-omap2/prm33xx.c135
-rw-r--r--arch/arm/mach-omap2/prm33xx.h129
-rw-r--r--arch/arm/mach-omap2/voltage.h1
-rw-r--r--arch/arm/mach-omap2/voltagedomains33xx_data.c43
18 files changed, 2825 insertions, 18 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fa742f3c2629..a4cf93242b0b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -90,6 +90,7 @@ obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
90obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o 90obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o
91obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o 91obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o
92obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o 92obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o
93obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o
93 94
94# OMAP voltage domains 95# OMAP voltage domains
95voltagedomain-common := voltage.o vc.o vp.o 96voltagedomain-common := voltage.o vc.o vp.o
@@ -99,6 +100,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
99obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o 100obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
100obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) 101obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
101obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o 102obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
103obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
102 104
103# OMAP powerdomain framework 105# OMAP powerdomain framework
104powerdomain-common += powerdomain.o powerdomain-common.o 106powerdomain-common += powerdomain.o powerdomain-common.o
@@ -113,6 +115,8 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
113obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) 115obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
114obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o 116obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
115obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o 117obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
118obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
119obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
116 120
117# PRCM clockdomain control 121# PRCM clockdomain control
118clockdomain-common += clockdomain.o 122clockdomain-common += clockdomain.o
@@ -129,6 +133,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
129obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) 133obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
130obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o 134obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
131obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o 135obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
136obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
137obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
132 138
133# Clock framework 139# Clock framework
134obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 140obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index f7b58609bad8..72cb12bbb9c3 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -195,6 +195,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
195extern void __init omap242x_clockdomains_init(void); 195extern void __init omap242x_clockdomains_init(void);
196extern void __init omap243x_clockdomains_init(void); 196extern void __init omap243x_clockdomains_init(void);
197extern void __init omap3xxx_clockdomains_init(void); 197extern void __init omap3xxx_clockdomains_init(void);
198extern void __init am33xx_clockdomains_init(void);
198extern void __init omap44xx_clockdomains_init(void); 199extern void __init omap44xx_clockdomains_init(void);
199extern void _clkdm_add_autodeps(struct clockdomain *clkdm); 200extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
200extern void _clkdm_del_autodeps(struct clockdomain *clkdm); 201extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
@@ -202,6 +203,7 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
202extern struct clkdm_ops omap2_clkdm_operations; 203extern struct clkdm_ops omap2_clkdm_operations;
203extern struct clkdm_ops omap3_clkdm_operations; 204extern struct clkdm_ops omap3_clkdm_operations;
204extern struct clkdm_ops omap4_clkdm_operations; 205extern struct clkdm_ops omap4_clkdm_operations;
206extern struct clkdm_ops am33xx_clkdm_operations;
205 207
206extern struct clkdm_dep gfx_24xx_wkdeps[]; 208extern struct clkdm_dep gfx_24xx_wkdeps[];
207extern struct clkdm_dep dsp_24xx_wkdeps[]; 209extern struct clkdm_dep dsp_24xx_wkdeps[];
diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c
new file mode 100644
index 000000000000..aca6388fad76
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain33xx.c
@@ -0,0 +1,74 @@
1/*
2 * AM33XX clockdomain control
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20
21#include "clockdomain.h"
22#include "cm33xx.h"
23
24
25static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
26{
27 am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
28 return 0;
29}
30
31static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
32{
33 am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
34 return 0;
35}
36
37static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
38{
39 am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
40}
41
42static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
43{
44 am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
45}
46
47static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
48{
49 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
50 return am33xx_clkdm_wakeup(clkdm);
51
52 return 0;
53}
54
55static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
56{
57 bool hwsup = false;
58
59 hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
60
61 if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
62 am33xx_clkdm_sleep(clkdm);
63
64 return 0;
65}
66
67struct clkdm_ops am33xx_clkdm_operations = {
68 .clkdm_sleep = am33xx_clkdm_sleep,
69 .clkdm_wakeup = am33xx_clkdm_wakeup,
70 .clkdm_allow_idle = am33xx_clkdm_allow_idle,
71 .clkdm_deny_idle = am33xx_clkdm_deny_idle,
72 .clkdm_clk_enable = am33xx_clkdm_clk_enable,
73 .clkdm_clk_disable = am33xx_clkdm_clk_disable,
74};
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
new file mode 100644
index 000000000000..32c90fd9eba2
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
@@ -0,0 +1,196 @@
1/*
2 * AM33XX Clock Domain data.
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19
20#include "clockdomain.h"
21#include "cm.h"
22#include "cm33xx.h"
23#include "cm-regbits-33xx.h"
24
25static struct clockdomain l4ls_am33xx_clkdm = {
26 .name = "l4ls_clkdm",
27 .pwrdm = { .name = "per_pwrdm" },
28 .cm_inst = AM33XX_CM_PER_MOD,
29 .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
30 .flags = CLKDM_CAN_SWSUP,
31};
32
33static struct clockdomain l3s_am33xx_clkdm = {
34 .name = "l3s_clkdm",
35 .pwrdm = { .name = "per_pwrdm" },
36 .cm_inst = AM33XX_CM_PER_MOD,
37 .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
38 .flags = CLKDM_CAN_SWSUP,
39};
40
41static struct clockdomain l4fw_am33xx_clkdm = {
42 .name = "l4fw_clkdm",
43 .pwrdm = { .name = "per_pwrdm" },
44 .cm_inst = AM33XX_CM_PER_MOD,
45 .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
46 .flags = CLKDM_CAN_SWSUP,
47};
48
49static struct clockdomain l3_am33xx_clkdm = {
50 .name = "l3_clkdm",
51 .pwrdm = { .name = "per_pwrdm" },
52 .cm_inst = AM33XX_CM_PER_MOD,
53 .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
54 .flags = CLKDM_CAN_SWSUP,
55};
56
57static struct clockdomain l4hs_am33xx_clkdm = {
58 .name = "l4hs_clkdm",
59 .pwrdm = { .name = "per_pwrdm" },
60 .cm_inst = AM33XX_CM_PER_MOD,
61 .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
62 .flags = CLKDM_CAN_SWSUP,
63};
64
65static struct clockdomain ocpwp_l3_am33xx_clkdm = {
66 .name = "ocpwp_l3_clkdm",
67 .pwrdm = { .name = "per_pwrdm" },
68 .cm_inst = AM33XX_CM_PER_MOD,
69 .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
70 .flags = CLKDM_CAN_SWSUP,
71};
72
73static struct clockdomain pruss_ocp_am33xx_clkdm = {
74 .name = "pruss_ocp_clkdm",
75 .pwrdm = { .name = "per_pwrdm" },
76 .cm_inst = AM33XX_CM_PER_MOD,
77 .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
78 .flags = CLKDM_CAN_SWSUP,
79};
80
81static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
82 .name = "cpsw_125mhz_clkdm",
83 .pwrdm = { .name = "per_pwrdm" },
84 .cm_inst = AM33XX_CM_PER_MOD,
85 .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
86 .flags = CLKDM_CAN_SWSUP,
87};
88
89static struct clockdomain lcdc_am33xx_clkdm = {
90 .name = "lcdc_clkdm",
91 .pwrdm = { .name = "per_pwrdm" },
92 .cm_inst = AM33XX_CM_PER_MOD,
93 .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
94 .flags = CLKDM_CAN_SWSUP,
95};
96
97static struct clockdomain clk_24mhz_am33xx_clkdm = {
98 .name = "clk_24mhz_clkdm",
99 .pwrdm = { .name = "per_pwrdm" },
100 .cm_inst = AM33XX_CM_PER_MOD,
101 .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
102 .flags = CLKDM_CAN_SWSUP,
103};
104
105static struct clockdomain l4_wkup_am33xx_clkdm = {
106 .name = "l4_wkup_clkdm",
107 .pwrdm = { .name = "wkup_pwrdm" },
108 .cm_inst = AM33XX_CM_WKUP_MOD,
109 .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
110 .flags = CLKDM_CAN_SWSUP,
111};
112
113static struct clockdomain l3_aon_am33xx_clkdm = {
114 .name = "l3_aon_clkdm",
115 .pwrdm = { .name = "wkup_pwrdm" },
116 .cm_inst = AM33XX_CM_WKUP_MOD,
117 .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
118 .flags = CLKDM_CAN_SWSUP,
119};
120
121static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
122 .name = "l4_wkup_aon_clkdm",
123 .pwrdm = { .name = "wkup_pwrdm" },
124 .cm_inst = AM33XX_CM_WKUP_MOD,
125 .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
126 .flags = CLKDM_CAN_SWSUP,
127};
128
129static struct clockdomain mpu_am33xx_clkdm = {
130 .name = "mpu_clkdm",
131 .pwrdm = { .name = "mpu_pwrdm" },
132 .cm_inst = AM33XX_CM_MPU_MOD,
133 .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
134 .flags = CLKDM_CAN_SWSUP,
135};
136
137static struct clockdomain l4_rtc_am33xx_clkdm = {
138 .name = "l4_rtc_clkdm",
139 .pwrdm = { .name = "rtc_pwrdm" },
140 .cm_inst = AM33XX_CM_RTC_MOD,
141 .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
142 .flags = CLKDM_CAN_SWSUP,
143};
144
145static struct clockdomain gfx_l3_am33xx_clkdm = {
146 .name = "gfx_l3_clkdm",
147 .pwrdm = { .name = "gfx_pwrdm" },
148 .cm_inst = AM33XX_CM_GFX_MOD,
149 .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
150 .flags = CLKDM_CAN_SWSUP,
151};
152
153static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
154 .name = "gfx_l4ls_gfx_clkdm",
155 .pwrdm = { .name = "gfx_pwrdm" },
156 .cm_inst = AM33XX_CM_GFX_MOD,
157 .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
158 .flags = CLKDM_CAN_SWSUP,
159};
160
161static struct clockdomain l4_cefuse_am33xx_clkdm = {
162 .name = "l4_cefuse_clkdm",
163 .pwrdm = { .name = "cefuse_pwrdm" },
164 .cm_inst = AM33XX_CM_CEFUSE_MOD,
165 .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
166 .flags = CLKDM_CAN_SWSUP,
167};
168
169static struct clockdomain *clockdomains_am33xx[] __initdata = {
170 &l4ls_am33xx_clkdm,
171 &l3s_am33xx_clkdm,
172 &l4fw_am33xx_clkdm,
173 &l3_am33xx_clkdm,
174 &l4hs_am33xx_clkdm,
175 &ocpwp_l3_am33xx_clkdm,
176 &pruss_ocp_am33xx_clkdm,
177 &cpsw_125mhz_am33xx_clkdm,
178 &lcdc_am33xx_clkdm,
179 &clk_24mhz_am33xx_clkdm,
180 &l4_wkup_am33xx_clkdm,
181 &l3_aon_am33xx_clkdm,
182 &l4_wkup_aon_am33xx_clkdm,
183 &mpu_am33xx_clkdm,
184 &l4_rtc_am33xx_clkdm,
185 &gfx_l3_am33xx_clkdm,
186 &gfx_l4ls_gfx_am33xx_clkdm,
187 &l4_cefuse_am33xx_clkdm,
188 NULL,
189};
190
191void __init am33xx_clockdomains_init(void)
192{
193 clkdm_register_platform_funcs(&am33xx_clkdm_operations);
194 clkdm_register_clkdms(clockdomains_am33xx);
195 clkdm_complete_init();
196}
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
new file mode 100644
index 000000000000..532027ee3d8d
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -0,0 +1,687 @@
1/*
2 * AM33XX Power Management register bits
3 *
4 * This file is automatically generated from the AM33XX hardware databases.
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
21#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
22
23/*
24 * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
25 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
26 */
27#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
28#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
29
30/* Used by CM_WKUP_CLKSTCTRL */
31#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
32#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
33
34/* Used by CM_PER_L4LS_CLKSTCTRL */
35#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
36#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
37
38/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
39#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
40#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
41
42/* Used by CM_PER_CPSW_CLKSTCTRL */
43#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
44#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
45
46/* Used by CM_PER_L4HS_CLKSTCTRL */
47#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
48#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
49
50/* Used by CM_PER_L4HS_CLKSTCTRL */
51#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
52#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
53
54/* Used by CM_PER_L4HS_CLKSTCTRL */
55#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
56#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
57
58/* Used by CM_PER_L3_CLKSTCTRL */
59#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
60#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
61
62/* Used by CM_CEFUSE_CLKSTCTRL */
63#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
64#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
65
66/* Used by CM_L3_AON_CLKSTCTRL */
67#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
68#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
69
70/* Used by CM_L3_AON_CLKSTCTRL */
71#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
72#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
73
74/* Used by CM_PER_L3_CLKSTCTRL */
75#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
76#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
77
78/* Used by CM_GFX_L3_CLKSTCTRL */
79#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
80#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
81
82/* Used by CM_GFX_L3_CLKSTCTRL */
83#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
84#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
85
86/* Used by CM_WKUP_CLKSTCTRL */
87#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
88#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
89
90/* Used by CM_PER_L4LS_CLKSTCTRL */
91#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
92#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
93
94/* Used by CM_PER_L4LS_CLKSTCTRL */
95#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
96#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
97
98/* Used by CM_PER_L4LS_CLKSTCTRL */
99#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
100#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
101
102/* Used by CM_PER_L4LS_CLKSTCTRL */
103#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
104#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
105
106/* Used by CM_PER_L4LS_CLKSTCTRL */
107#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
108#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
109
110/* Used by CM_PER_L4LS_CLKSTCTRL */
111#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
112#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
113
114/* Used by CM_WKUP_CLKSTCTRL */
115#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
116#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
117
118/* Used by CM_PER_L4LS_CLKSTCTRL */
119#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
120#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
121
122/* Used by CM_PER_PRUSS_CLKSTCTRL */
123#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
124#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
125
126/* Used by CM_PER_PRUSS_CLKSTCTRL */
127#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
128#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
129
130/* Used by CM_PER_PRUSS_CLKSTCTRL */
131#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
132#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
133
134/* Used by CM_PER_L3S_CLKSTCTRL */
135#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
136#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
137
138/* Used by CM_L3_AON_CLKSTCTRL */
139#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
140#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
141
142/* Used by CM_PER_L3_CLKSTCTRL */
143#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
144#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
145
146/* Used by CM_PER_L4FW_CLKSTCTRL */
147#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
148#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
149
150/* Used by CM_PER_L4HS_CLKSTCTRL */
151#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
152#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
153
154/* Used by CM_PER_L4LS_CLKSTCTRL */
155#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
156#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
157
158/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
159#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
160#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
161
162/* Used by CM_CEFUSE_CLKSTCTRL */
163#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
164#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
165
166/* Used by CM_RTC_CLKSTCTRL */
167#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
168#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
169
170/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
171#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
172#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
173
174/* Used by CM_WKUP_CLKSTCTRL */
175#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
176#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
177
178/* Used by CM_PER_L4LS_CLKSTCTRL */
179#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
180#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
181
182/* Used by CM_PER_LCDC_CLKSTCTRL */
183#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
184#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
185
186/* Used by CM_PER_LCDC_CLKSTCTRL */
187#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
188#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
189
190/* Used by CM_PER_L3_CLKSTCTRL */
191#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
192#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
193
194/* Used by CM_PER_L3_CLKSTCTRL */
195#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
196#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
197
198/* Used by CM_MPU_CLKSTCTRL */
199#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
200#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
201
202/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
203#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
204#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
205
206/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
207#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
208#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
209
210/* Used by CM_RTC_CLKSTCTRL */
211#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
212#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
213
214/* Used by CM_PER_L4LS_CLKSTCTRL */
215#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
216#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
217
218/* Used by CM_WKUP_CLKSTCTRL */
219#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
220#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
221
222/* Used by CM_WKUP_CLKSTCTRL */
223#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
224#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
225
226/* Used by CM_WKUP_CLKSTCTRL */
227#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
228#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
229
230/* Used by CM_PER_L4LS_CLKSTCTRL */
231#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
232#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
233
234/* Used by CM_PER_L4LS_CLKSTCTRL */
235#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
236#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
237
238/* Used by CM_PER_L4LS_CLKSTCTRL */
239#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
240#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
241
242/* Used by CM_PER_L4LS_CLKSTCTRL */
243#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
244#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
245
246/* Used by CM_PER_L4LS_CLKSTCTRL */
247#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
248#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
249
250/* Used by CM_PER_L4LS_CLKSTCTRL */
251#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
252#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
253
254/* Used by CM_WKUP_CLKSTCTRL */
255#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
256#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
257
258/* Used by CM_PER_L4LS_CLKSTCTRL */
259#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
260#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
261
262/* Used by CM_WKUP_CLKSTCTRL */
263#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
264#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
265
266/* Used by CM_WKUP_CLKSTCTRL */
267#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
268#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
269
270/* Used by CLKSEL_GFX_FCLK */
271#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
272#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
273
274/* Used by CM_CLKOUT_CTRL */
275#define AM33XX_CLKOUT2DIV_SHIFT 3
276#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3)
277
278/* Used by CM_CLKOUT_CTRL */
279#define AM33XX_CLKOUT2EN_SHIFT 7
280#define AM33XX_CLKOUT2EN_MASK (1 << 7)
281
282/* Used by CM_CLKOUT_CTRL */
283#define AM33XX_CLKOUT2SOURCE_SHIFT 0
284#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0)
285
286/*
287 * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
288 * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
289 * CLKSEL_TIMER7_CLK
290 */
291#define AM33XX_CLKSEL_SHIFT 0
292#define AM33XX_CLKSEL_MASK (0x01 << 0)
293
294/*
295 * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
296 * CM_CPTS_RFT_CLKSEL
297 */
298#define AM33XX_CLKSEL_0_0_SHIFT 0
299#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
300
301#define AM33XX_CLKSEL_0_1_SHIFT 0
302#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
303
304/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
305#define AM33XX_CLKSEL_0_2_SHIFT 0
306#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
307
308/* Used by CLKSEL_GFX_FCLK */
309#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
310#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
311
312/*
313 * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
314 * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
315 * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
316 * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
317 * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
318 * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
319 */
320#define AM33XX_CLKTRCTRL_SHIFT 0
321#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
322
323/*
324 * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
325 * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
326 * CM_SSC_DELTAMSTEP_DPLL_PER
327 */
328#define AM33XX_DELTAMSTEP_SHIFT 0
329#define AM33XX_DELTAMSTEP_MASK (0x19 << 0)
330
331/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
332#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
333#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
334
335/* Used by CM_CLKDCOLDO_DPLL_PER */
336#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
337#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
338
339/* Used by CM_CLKDCOLDO_DPLL_PER */
340#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
341#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
342
343/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
344#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
345#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
346
347/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
348#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
349#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0)
350
351/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
352#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
353#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
354
355/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
356#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
357#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
358
359/*
360 * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
361 * CM_DIV_M2_DPLL_PER
362 */
363#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
364#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
365
366/*
367 * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
368 * CM_CLKSEL_DPLL_MPU
369 */
370#define AM33XX_DPLL_DIV_SHIFT 0
371#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
372
373#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
374
375/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
376#define AM33XX_DPLL_DIV_0_7_SHIFT 0
377#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0)
378
379/*
380 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
381 * CM_CLKMODE_DPLL_MPU
382 */
383#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
384#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
385
386/*
387 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
388 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
389 */
390#define AM33XX_DPLL_EN_SHIFT 0
391#define AM33XX_DPLL_EN_MASK (0x7 << 0)
392
393/*
394 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
395 * CM_CLKMODE_DPLL_MPU
396 */
397#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
398#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
399
400/*
401 * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
402 * CM_CLKSEL_DPLL_MPU
403 */
404#define AM33XX_DPLL_MULT_SHIFT 8
405#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
406
407/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
408#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
409#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
410
411/*
412 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
413 * CM_CLKMODE_DPLL_MPU
414 */
415#define AM33XX_DPLL_REGM4XEN_SHIFT 11
416#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
417
418/* Used by CM_CLKSEL_DPLL_PERIPH */
419#define AM33XX_DPLL_SD_DIV_SHIFT 24
420#define AM33XX_DPLL_SD_DIV_MASK (24, 31)
421
422/*
423 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
424 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
425 */
426#define AM33XX_DPLL_SSC_ACK_SHIFT 13
427#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
428
429/*
430 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
431 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
432 */
433#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
434#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
435
436/*
437 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
438 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
439 */
440#define AM33XX_DPLL_SSC_EN_SHIFT 12
441#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
442
443/* Used by CM_DIV_M4_DPLL_CORE */
444#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
445#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
446
447/* Used by CM_DIV_M4_DPLL_CORE */
448#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
449#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
450
451/* Used by CM_DIV_M4_DPLL_CORE */
452#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
453#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
454
455/* Used by CM_DIV_M4_DPLL_CORE */
456#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
457#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
458
459/* Used by CM_DIV_M5_DPLL_CORE */
460#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
461#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
462
463/* Used by CM_DIV_M5_DPLL_CORE */
464#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
465#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
466
467/* Used by CM_DIV_M5_DPLL_CORE */
468#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
469#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
470
471/* Used by CM_DIV_M5_DPLL_CORE */
472#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
473#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
474
475/* Used by CM_DIV_M6_DPLL_CORE */
476#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
477#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0)
478
479/* Used by CM_DIV_M6_DPLL_CORE */
480#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
481#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
482
483/* Used by CM_DIV_M6_DPLL_CORE */
484#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
485#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
486
487/* Used by CM_DIV_M6_DPLL_CORE */
488#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
489#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
490
491/*
492 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
493 * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
494 * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
495 * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
496 * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
497 * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
498 * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
499 * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
500 * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
501 * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
502 * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
503 * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
504 * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
505 * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
506 * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
507 * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
508 * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
509 * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
510 * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
511 * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
512 * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
513 * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
514 * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
515 * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
516 * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
517 * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
518 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
519 * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
520 * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
521 * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
522 * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
523 */
524#define AM33XX_IDLEST_SHIFT 16
525#define AM33XX_IDLEST_MASK (0x3 << 16)
526#define AM33XX_IDLEST_VAL 0x3
527
528/* Used by CM_MAC_CLKSEL */
529#define AM33XX_MII_CLK_SEL_SHIFT 2
530#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
531
532/*
533 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
534 * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
535 * CM_SSC_MODFREQDIV_DPLL_PER
536 */
537#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
538#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8)
539
540/*
541 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
542 * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
543 * CM_SSC_MODFREQDIV_DPLL_PER
544 */
545#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
546#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0)
547
548/*
549 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
550 * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
551 * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
552 * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
553 * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
554 * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
555 * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
556 * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
557 * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
558 * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
559 * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
560 * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
561 * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
562 * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
563 * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
564 * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
565 * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
566 * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
567 * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
568 * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
569 * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
570 * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
571 * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
572 * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
573 * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
574 * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
575 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
576 * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
577 * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
578 * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
579 * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
580 * CM_CEFUSE_CEFUSE_CLKCTRL
581 */
582#define AM33XX_MODULEMODE_SHIFT 0
583#define AM33XX_MODULEMODE_MASK (0x3 << 0)
584
585/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
586#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
587#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
588
589/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
590#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
591#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
592
593/* Used by CM_WKUP_GPIO0_CLKCTRL */
594#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
595#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
596
597/* Used by CM_PER_GPIO1_CLKCTRL */
598#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
599#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
600
601/* Used by CM_PER_GPIO2_CLKCTRL */
602#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
603#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
604
605/* Used by CM_PER_GPIO3_CLKCTRL */
606#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
607#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
608
609/* Used by CM_PER_GPIO4_CLKCTRL */
610#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
611#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
612
613/* Used by CM_PER_GPIO5_CLKCTRL */
614#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
615#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
616
617/* Used by CM_PER_GPIO6_CLKCTRL */
618#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
619#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
620
621/*
622 * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
623 * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
624 * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
625 * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
626 * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
627 * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
628 */
629#define AM33XX_STBYST_SHIFT 18
630#define AM33XX_STBYST_MASK (1 << 18)
631
632/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
633#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
634#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27)
635
636/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
637#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
638#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22)
639
640/*
641 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
642 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
643 */
644#define AM33XX_ST_DPLL_CLK_SHIFT 0
645#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
646
647/* Used by CM_CLKDCOLDO_DPLL_PER */
648#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
649#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
650
651/*
652 * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
653 * CM_DIV_M2_DPLL_PER
654 */
655#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
656#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
657
658/* Used by CM_DIV_M4_DPLL_CORE */
659#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
660#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
661
662/* Used by CM_DIV_M5_DPLL_CORE */
663#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
664#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
665
666/* Used by CM_DIV_M6_DPLL_CORE */
667#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
668#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
669
670/*
671 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
672 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
673 */
674#define AM33XX_ST_MN_BYPASS_SHIFT 8
675#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
676
677/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
678#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
679#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24)
680
681/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
682#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
683#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20)
684
685/* Used by CONTROL_SEC_CLK_CTRL */
686#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
687#endif
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
new file mode 100644
index 000000000000..13f56eafef03
--- /dev/null
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -0,0 +1,313 @@
1/*
2 * AM33XX CM functions
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * Reference taken from from OMAP4 cminst44xx.c
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/errno.h>
22#include <linux/err.h>
23#include <linux/io.h>
24
25#include <plat/common.h>
26
27#include "cm.h"
28#include "cm33xx.h"
29#include "cm-regbits-34xx.h"
30#include "cm-regbits-33xx.h"
31#include "prm33xx.h"
32
33/*
34 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
35 *
36 * 0x0 func: Module is fully functional, including OCP
37 * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
38 * abortion
39 * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
40 * using separate functional clock
41 * 0x3 disabled: Module is disabled and cannot be accessed
42 *
43 */
44#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
45#define CLKCTRL_IDLEST_INTRANSITION 0x1
46#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
47#define CLKCTRL_IDLEST_DISABLED 0x3
48
49/* Private functions */
50
51/* Read a register in a CM instance */
52static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
53{
54 return __raw_readl(cm_base + inst + idx);
55}
56
57/* Write into a register in a CM */
58static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
59{
60 __raw_writel(val, cm_base + inst + idx);
61}
62
63/* Read-modify-write a register in CM */
64static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
65{
66 u32 v;
67
68 v = am33xx_cm_read_reg(inst, idx);
69 v &= ~mask;
70 v |= bits;
71 am33xx_cm_write_reg(v, inst, idx);
72
73 return v;
74}
75
76static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
77{
78 return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
79}
80
81static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
82{
83 return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
84}
85
86static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
87{
88 u32 v;
89
90 v = am33xx_cm_read_reg(inst, idx);
91 v &= mask;
92 v >>= __ffs(mask);
93
94 return v;
95}
96
97/**
98 * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
99 * @inst: CM instance register offset (*_INST macro)
100 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
101 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
102 *
103 * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
104 * bit 0.
105 */
106static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
107{
108 u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
109 v &= AM33XX_IDLEST_MASK;
110 v >>= AM33XX_IDLEST_SHIFT;
111 return v;
112}
113
114/**
115 * _is_module_ready - can module registers be accessed without causing an abort?
116 * @inst: CM instance register offset (*_INST macro)
117 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
118 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
119 *
120 * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
121 * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
122 */
123static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
124{
125 u32 v;
126
127 v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
128
129 return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
130 v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
131}
132
133/**
134 * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
135 * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
136 * @inst: CM instance register offset (*_INST macro)
137 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
138 *
139 * @c must be the unshifted value for CLKTRCTRL - i.e., this function
140 * will handle the shift itself.
141 */
142static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
143{
144 u32 v;
145
146 v = am33xx_cm_read_reg(inst, cdoffs);
147 v &= ~AM33XX_CLKTRCTRL_MASK;
148 v |= c << AM33XX_CLKTRCTRL_SHIFT;
149 am33xx_cm_write_reg(v, inst, cdoffs);
150}
151
152/* Public functions */
153
154/**
155 * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
156 * @inst: CM instance register offset (*_INST macro)
157 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
158 *
159 * Returns true if the clockdomain referred to by (@inst, @cdoffs)
160 * is in hardware-supervised idle mode, or 0 otherwise.
161 */
162bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
163{
164 u32 v;
165
166 v = am33xx_cm_read_reg(inst, cdoffs);
167 v &= AM33XX_CLKTRCTRL_MASK;
168 v >>= AM33XX_CLKTRCTRL_SHIFT;
169
170 return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
171}
172
173/**
174 * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
175 * @inst: CM instance register offset (*_INST macro)
176 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
177 *
178 * Put a clockdomain referred to by (@inst, @cdoffs) into
179 * hardware-supervised idle mode. No return value.
180 */
181void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
182{
183 _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
184}
185
186/**
187 * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
188 * @inst: CM instance register offset (*_INST macro)
189 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
190 *
191 * Put a clockdomain referred to by (@inst, @cdoffs) into
192 * software-supervised idle mode, i.e., controlled manually by the
193 * Linux OMAP clockdomain code. No return value.
194 */
195void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
196{
197 _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
198}
199
200/**
201 * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
202 * @inst: CM instance register offset (*_INST macro)
203 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
204 *
205 * Put a clockdomain referred to by (@inst, @cdoffs) into idle
206 * No return value.
207 */
208void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
209{
210 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
211}
212
213/**
214 * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
215 * @inst: CM instance register offset (*_INST macro)
216 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
217 *
218 * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
219 * waking it up. No return value.
220 */
221void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
222{
223 _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
224}
225
226/*
227 *
228 */
229
230/**
231 * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
232 * @inst: CM instance register offset (*_INST macro)
233 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
234 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
235 *
236 * Wait for the module IDLEST to be functional. If the idle state is in any
237 * the non functional state (trans, idle or disabled), module and thus the
238 * sysconfig cannot be accessed and will probably lead to an "imprecise
239 * external abort"
240 */
241int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
242{
243 int i = 0;
244
245 if (!clkctrl_offs)
246 return 0;
247
248 omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
249 MAX_MODULE_READY_TIME, i);
250
251 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
252}
253
254/**
255 * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
256 * state
257 * @inst: CM instance register offset (*_INST macro)
258 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
259 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
260 *
261 * Wait for the module IDLEST to be disabled. Some PRCM transition,
262 * like reset assertion or parent clock de-activation must wait the
263 * module to be fully disabled.
264 */
265int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
266{
267 int i = 0;
268
269 if (!clkctrl_offs)
270 return 0;
271
272 omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
273 CLKCTRL_IDLEST_DISABLED),
274 MAX_MODULE_READY_TIME, i);
275
276 return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
277}
278
279/**
280 * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
281 * @mode: Module mode (SW or HW)
282 * @inst: CM instance register offset (*_INST macro)
283 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
284 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
285 *
286 * No return value.
287 */
288void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
289{
290 u32 v;
291
292 v = am33xx_cm_read_reg(inst, clkctrl_offs);
293 v &= ~AM33XX_MODULEMODE_MASK;
294 v |= mode << AM33XX_MODULEMODE_SHIFT;
295 am33xx_cm_write_reg(v, inst, clkctrl_offs);
296}
297
298/**
299 * am33xx_cm_module_disable - Disable the module inside CLKCTRL
300 * @inst: CM instance register offset (*_INST macro)
301 * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
302 * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
303 *
304 * No return value.
305 */
306void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
307{
308 u32 v;
309
310 v = am33xx_cm_read_reg(inst, clkctrl_offs);
311 v &= ~AM33XX_MODULEMODE_MASK;
312 am33xx_cm_write_reg(v, inst, clkctrl_offs);
313}
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
new file mode 100644
index 000000000000..5fa0b62e1a79
--- /dev/null
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -0,0 +1,420 @@
1/*
2 * AM33XX CM offset macros
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 * Vaibhav Hiremath <hvaibhav@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
18#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
19
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/err.h>
23#include <linux/io.h>
24
25#include "common.h"
26
27#include "cm.h"
28#include "cm-regbits-33xx.h"
29#include "cm33xx.h"
30
31/* CM base address */
32#define AM33XX_CM_BASE 0x44e00000
33
34#define AM33XX_CM_REGADDR(inst, reg) \
35 AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
36
37/* CM instances */
38#define AM33XX_CM_PER_MOD 0x0000
39#define AM33XX_CM_WKUP_MOD 0x0400
40#define AM33XX_CM_DPLL_MOD 0x0500
41#define AM33XX_CM_MPU_MOD 0x0600
42#define AM33XX_CM_DEVICE_MOD 0x0700
43#define AM33XX_CM_RTC_MOD 0x0800
44#define AM33XX_CM_GFX_MOD 0x0900
45#define AM33XX_CM_CEFUSE_MOD 0x0A00
46
47/* CM */
48
49/* CM.PER_CM register offsets */
50#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
51#define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
52#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004
53#define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
54#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008
55#define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
56#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c
57#define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
58#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014
59#define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
60#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018
61#define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
62#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c
63#define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
64#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020
65#define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
66#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024
67#define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
68#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028
69#define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
70#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c
71#define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
72#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030
73#define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
74#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034
75#define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
76#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038
77#define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
78#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c
79#define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
80#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040
81#define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
82#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044
83#define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
84#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048
85#define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
86#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c
87#define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
88#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050
89#define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
90#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054
91#define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
92#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058
93#define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
94#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060
95#define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
96#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064
97#define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
98#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068
99#define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
100#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c
101#define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
102#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070
103#define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
104#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074
105#define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
106#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078
107#define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
108#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c
109#define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
110#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080
111#define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
112#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084
113#define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
114#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088
115#define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
116#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c
117#define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
118#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090
119#define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
120#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094
121#define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
122#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098
123#define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
124#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c
125#define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
126#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0
127#define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
128#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4
129#define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
130#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8
131#define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
132#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac
133#define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
134#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0
135#define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
136#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4
137#define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
138#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8
139#define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
140#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc
141#define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
142#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0
143#define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
144#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4
145#define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
146#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc
147#define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
148#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0
149#define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
150#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4
151#define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
152#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8
153#define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
154#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc
155#define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
156#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0
157#define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
158#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4
159#define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
160#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8
161#define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
162#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec
163#define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
164#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0
165#define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
166#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4
167#define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
168#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8
169#define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
170#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc
171#define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
172#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100
173#define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
174#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104
175#define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
176#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c
177#define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
178#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110
179#define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
180#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c
181#define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
182#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120
183#define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
184#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124
185#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
186#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128
187#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
188#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c
189#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
190#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130
191#define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
192#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134
193#define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
194#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140
195#define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
196#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144
197#define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
198#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148
199#define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
200#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c
201#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
202#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150
203#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
204
205/* CM.WKUP_CM register offsets */
206#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000
207#define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
208#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004
209#define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
210#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008
211#define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
212#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c
213#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
214#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010
215#define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
216#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014
217#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
218#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018
219#define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
220#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c
221#define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
222#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020
223#define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
224#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024
225#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
226#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028
227#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
228#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c
229#define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
230#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030
231#define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
232#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034
233#define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
234#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038
235#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
236#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c
237#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
238#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040
239#define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
240#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044
241#define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
242#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048
243#define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
244#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c
245#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
246#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050
247#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
248#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054
249#define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
250#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058
251#define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
252#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c
253#define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
254#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060
255#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
256#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064
257#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
258#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068
259#define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
260#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c
261#define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
262#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070
263#define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
264#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074
265#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
266#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078
267#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
268#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c
269#define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
270#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080
271#define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
272#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084
273#define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
274#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088
275#define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
276#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c
277#define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
278#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090
279#define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
280#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094
281#define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
282#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098
283#define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
284#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c
285#define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
286#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0
287#define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
288#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4
289#define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
290#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8
291#define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
292#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac
293#define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
294#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0
295#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
296#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4
297#define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
298#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8
299#define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
300#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc
301#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
302#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0
303#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
304#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4
305#define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
306#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8
307#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
308#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc
309#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
310#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0
311#define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
312#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4
313#define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
314#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8
315#define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
316
317/* CM.DPLL_CM register offsets */
318#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004
319#define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
320#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008
321#define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
322#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c
323#define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
324#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010
325#define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
326#define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014
327#define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
328#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018
329#define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
330#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c
331#define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
332#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020
333#define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
334#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028
335#define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
336#define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c
337#define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
338#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030
339#define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
340#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034
341#define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
342#define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038
343#define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
344#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c
345#define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
346
347/* CM.MPU_CM register offsets */
348#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
349#define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
350#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004
351#define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
352
353/* CM.DEVICE_CM register offsets */
354#define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000
355#define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
356
357/* CM.RTC_CM register offsets */
358#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000
359#define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
360#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004
361#define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
362
363/* CM.GFX_CM register offsets */
364#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000
365#define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
366#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004
367#define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
368#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008
369#define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
370#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c
371#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
372#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010
373#define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
374#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014
375#define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
376
377/* CM.CEFUSE_CM register offsets */
378#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
379#define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
380#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
381#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
382
383
384extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
385extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
386extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
387extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
388extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
389
390#ifdef CONFIG_SOC_AM33XX
391extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
392 u16 clkctrl_offs);
393extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
394 u16 clkctrl_offs);
395extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
396 u16 clkctrl_offs);
397extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
398 u16 clkctrl_offs);
399#else
400static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
401 u16 clkctrl_offs)
402{
403 return 0;
404}
405static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
406 u16 clkctrl_offs)
407{
408}
409static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
410 u16 clkctrl_offs)
411{
412}
413static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
414 u16 clkctrl_offs)
415{
416 return 0;
417}
418#endif
419
420#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 56f687bebd0a..5d99c1b2cb48 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -129,6 +129,7 @@ void omap3430_init_early(void);
129void omap35xx_init_early(void); 129void omap35xx_init_early(void);
130void omap3630_init_early(void); 130void omap3630_init_early(void);
131void omap3_init_early(void); /* Do not use this one */ 131void omap3_init_early(void); /* Do not use this one */
132void am33xx_init_early(void);
132void am35xx_init_early(void); 133void am35xx_init_early(void);
133void ti81xx_init_early(void); 134void ti81xx_init_early(void);
134void am33xx_init_early(void); 135void am33xx_init_early(void);
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a406fd045ce1..c43f03cbefc5 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -21,6 +21,8 @@
21#include <mach/ctrl_module_pad_core_44xx.h> 21#include <mach/ctrl_module_pad_core_44xx.h>
22#include <mach/ctrl_module_pad_wkup_44xx.h> 22#include <mach/ctrl_module_pad_wkup_44xx.h>
23 23
24#include <plat/am33xx.h>
25
24#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
25#define OMAP242X_CTRL_REGADDR(reg) \ 27#define OMAP242X_CTRL_REGADDR(reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 28 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -28,6 +30,8 @@
28 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 30 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
29#define OMAP343X_CTRL_REGADDR(reg) \ 31#define OMAP343X_CTRL_REGADDR(reg) \
30 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 32 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
33#define AM33XX_CTRL_REGADDR(reg) \
34 AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
31#else 35#else
32#define OMAP242X_CTRL_REGADDR(reg) \ 36#define OMAP242X_CTRL_REGADDR(reg) \
33 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 37 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -35,6 +39,8 @@
35 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 39 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
36#define OMAP343X_CTRL_REGADDR(reg) \ 40#define OMAP343X_CTRL_REGADDR(reg) \
37 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 41 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
42#define AM33XX_CTRL_REGADDR(reg) \
43 AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
38#endif /* __ASSEMBLY__ */ 44#endif /* __ASSEMBLY__ */
39 45
40/* 46/*
@@ -312,15 +318,15 @@
312 OMAP343X_SCRATCHPAD + reg) 318 OMAP343X_SCRATCHPAD + reg)
313 319
314/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ 320/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
315#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 321#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
316#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 322#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1
317#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 323#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2
318#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 324#define AM35XX_HECC_VBUSP_CLK_SHIFT 3
319#define AM35XX_USBOTG_FCLK_SHIFT 8 325#define AM35XX_USBOTG_FCLK_SHIFT 8
320#define AM35XX_CPGMAC_FCLK_SHIFT 9 326#define AM35XX_CPGMAC_FCLK_SHIFT 9
321#define AM35XX_VPFE_FCLK_SHIFT 10 327#define AM35XX_VPFE_FCLK_SHIFT 10
322 328
323/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ 329/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
324#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) 330#define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
325#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) 331#define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1)
326#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) 332#define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2)
@@ -330,21 +336,22 @@
330#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) 336#define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6)
331#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) 337#define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7)
332 338
333/*AM35XX CONTROL_IP_SW_RESET bits*/ 339/* AM35XX CONTROL_IP_SW_RESET bits */
334#define AM35XX_USBOTGSS_SW_RST BIT(0) 340#define AM35XX_USBOTGSS_SW_RST BIT(0)
335#define AM35XX_CPGMACSS_SW_RST BIT(1) 341#define AM35XX_CPGMACSS_SW_RST BIT(1)
336#define AM35XX_VPFE_VBUSP_SW_RST BIT(2) 342#define AM35XX_VPFE_VBUSP_SW_RST BIT(2)
337#define AM35XX_HECC_SW_RST BIT(3) 343#define AM35XX_HECC_SW_RST BIT(3)
338#define AM35XX_VPFE_PCLK_SW_RST BIT(4) 344#define AM35XX_VPFE_PCLK_SW_RST BIT(4)
339 345
340/* 346/* AM33XX CONTROL_STATUS register */
341 * CONTROL AM33XX STATUS register
342 */
343#define AM33XX_CONTROL_STATUS 0x040 347#define AM33XX_CONTROL_STATUS 0x040
348#define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc
344 349
345/* 350/* AM33XX CONTROL_STATUS bitfields (partial) */
346 * CONTROL OMAP STATUS register to identify OMAP3 features 351#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22
347 */ 352#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22)
353
354/* CONTROL OMAP STATUS register to identify OMAP3 features */
348#define OMAP3_CONTROL_OMAP_STATUS 0x044c 355#define OMAP3_CONTROL_OMAP_STATUS 0x044c
349 356
350#define OMAP3_SGX_SHIFT 13 357#define OMAP3_SGX_SHIFT 13
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5d6b2346bf75..cb6c11cd8df9 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -484,6 +484,9 @@ void __init am33xx_init_early(void)
484 omap3xxx_check_revision(); 484 omap3xxx_check_revision();
485 ti81xx_check_features(); 485 ti81xx_check_features();
486 omap_common_init_early(); 486 omap_common_init_early();
487 am33xx_voltagedomains_init();
488 am33xx_powerdomains_init();
489 am33xx_clockdomains_init();
487} 490}
488#endif 491#endif
489 492
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 8f88d65c46ea..a8a95184243d 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -67,9 +67,9 @@
67 67
68/* 68/*
69 * Maximum number of clockdomains that can be associated with a powerdomain. 69 * Maximum number of clockdomains that can be associated with a powerdomain.
70 * CORE powerdomain on OMAP4 is the worst case 70 * PER powerdomain on AM33XX is the worst case
71 */ 71 */
72#define PWRDM_MAX_CLKDMS 9 72#define PWRDM_MAX_CLKDMS 11
73 73
74/* XXX A completely arbitrary number. What is reasonable here? */ 74/* XXX A completely arbitrary number. What is reasonable here? */
75#define PWRDM_TRANSITION_BAILOUT 100000 75#define PWRDM_TRANSITION_BAILOUT 100000
@@ -92,6 +92,15 @@ struct powerdomain;
92 * @pwrdm_clkdms: Clockdomains in this powerdomain 92 * @pwrdm_clkdms: Clockdomains in this powerdomain
93 * @node: list_head linking all powerdomains 93 * @node: list_head linking all powerdomains
94 * @voltdm_node: list_head linking all powerdomains in a voltagedomain 94 * @voltdm_node: list_head linking all powerdomains in a voltagedomain
95 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
96 * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
97 * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
98 * in @pwrstctrl_offs
99 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
100 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
101 * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
102 * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
103 * in @pwrstctrl_offs
95 * @state: 104 * @state:
96 * @state_counter: 105 * @state_counter:
97 * @timer: 106 * @timer:
@@ -121,6 +130,14 @@ struct powerdomain {
121 unsigned ret_logic_off_counter; 130 unsigned ret_logic_off_counter;
122 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; 131 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
123 132
133 const u8 pwrstctrl_offs;
134 const u8 pwrstst_offs;
135 const u32 logicretstate_mask;
136 const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
137 const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
138 const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
139 const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
140
124#ifdef CONFIG_PM_DEBUG 141#ifdef CONFIG_PM_DEBUG
125 s64 timer; 142 s64 timer;
126 s64 state_timer[PWRDM_MAX_PWRSTS]; 143 s64 state_timer[PWRDM_MAX_PWRSTS];
@@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
222extern void omap242x_powerdomains_init(void); 239extern void omap242x_powerdomains_init(void);
223extern void omap243x_powerdomains_init(void); 240extern void omap243x_powerdomains_init(void);
224extern void omap3xxx_powerdomains_init(void); 241extern void omap3xxx_powerdomains_init(void);
242extern void am33xx_powerdomains_init(void);
225extern void omap44xx_powerdomains_init(void); 243extern void omap44xx_powerdomains_init(void);
226 244
227extern struct pwrdm_ops omap2_pwrdm_operations; 245extern struct pwrdm_ops omap2_pwrdm_operations;
228extern struct pwrdm_ops omap3_pwrdm_operations; 246extern struct pwrdm_ops omap3_pwrdm_operations;
247extern struct pwrdm_ops am33xx_pwrdm_operations;
229extern struct pwrdm_ops omap4_pwrdm_operations; 248extern struct pwrdm_ops omap4_pwrdm_operations;
230 249
231/* Common Internal functions used across OMAP rev's */ 250/* Common Internal functions used across OMAP rev's */
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c
new file mode 100644
index 000000000000..67c5663899b6
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain33xx.c
@@ -0,0 +1,229 @@
1/*
2 * AM33XX Powerdomain control
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
7 * <rnayak@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/io.h>
20#include <linux/errno.h>
21#include <linux/delay.h>
22
23#include <plat/prcm.h>
24
25#include "powerdomain.h"
26#include "prm33xx.h"
27#include "prm-regbits-33xx.h"
28
29
30static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
31{
32 am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
33 (pwrst << OMAP_POWERSTATE_SHIFT),
34 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
35 return 0;
36}
37
38static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
39{
40 u32 v;
41
42 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
43 v &= OMAP_POWERSTATE_MASK;
44 v >>= OMAP_POWERSTATE_SHIFT;
45
46 return v;
47}
48
49static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
50{
51 u32 v;
52
53 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
54 v &= OMAP_POWERSTATEST_MASK;
55 v >>= OMAP_POWERSTATEST_SHIFT;
56
57 return v;
58}
59
60static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
61{
62 u32 v;
63
64 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
65 v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
66 v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
67
68 return v;
69}
70
71static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
72{
73 am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
74 (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
75 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
76 return 0;
77}
78
79static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
80{
81 am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
82 AM33XX_LASTPOWERSTATEENTERED_MASK,
83 pwrdm->prcm_offs, pwrdm->pwrstst_offs);
84 return 0;
85}
86
87static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
88{
89 u32 m;
90
91 m = pwrdm->logicretstate_mask;
92 if (!m)
93 return -EINVAL;
94
95 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
96 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
97
98 return 0;
99}
100
101static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
102{
103 u32 v;
104
105 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
106 v &= AM33XX_LOGICSTATEST_MASK;
107 v >>= AM33XX_LOGICSTATEST_SHIFT;
108
109 return v;
110}
111
112static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
113{
114 u32 v, m;
115
116 m = pwrdm->logicretstate_mask;
117 if (!m)
118 return -EINVAL;
119
120 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
121 v &= m;
122 v >>= __ffs(m);
123
124 return v;
125}
126
127static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
128 u8 pwrst)
129{
130 u32 m;
131
132 m = pwrdm->mem_on_mask[bank];
133 if (!m)
134 return -EINVAL;
135
136 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
137 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
138
139 return 0;
140}
141
142static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
143 u8 pwrst)
144{
145 u32 m;
146
147 m = pwrdm->mem_ret_mask[bank];
148 if (!m)
149 return -EINVAL;
150
151 am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
152 pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
153
154 return 0;
155}
156
157static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
158{
159 u32 m, v;
160
161 m = pwrdm->mem_pwrst_mask[bank];
162 if (!m)
163 return -EINVAL;
164
165 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
166 v &= m;
167 v >>= __ffs(m);
168
169 return v;
170}
171
172static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
173{
174 u32 m, v;
175
176 m = pwrdm->mem_retst_mask[bank];
177 if (!m)
178 return -EINVAL;
179
180 v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
181 v &= m;
182 v >>= __ffs(m);
183
184 return v;
185}
186
187static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
188{
189 u32 c = 0;
190
191 /*
192 * REVISIT: pwrdm_wait_transition() may be better implemented
193 * via a callback and a periodic timer check -- how long do we expect
194 * powerdomain transitions to take?
195 */
196
197 /* XXX Is this udelay() value meaningful? */
198 while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
199 & OMAP_INTRANSITION_MASK) &&
200 (c++ < PWRDM_TRANSITION_BAILOUT))
201 udelay(1);
202
203 if (c > PWRDM_TRANSITION_BAILOUT) {
204 pr_err("powerdomain: %s: waited too long to complete transition\n",
205 pwrdm->name);
206 return -EAGAIN;
207 }
208
209 pr_debug("powerdomain: completed transition in %d loops\n", c);
210
211 return 0;
212}
213
214struct pwrdm_ops am33xx_pwrdm_operations = {
215 .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
216 .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
217 .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
218 .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
219 .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
220 .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
221 .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
222 .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
223 .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
224 .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
225 .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
226 .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
227 .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
228 .pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
229};
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
new file mode 100644
index 000000000000..869adb82569e
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -0,0 +1,185 @@
1/*
2 * AM33XX Power domain data
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include "powerdomain.h"
20#include "prcm-common.h"
21#include "prm-regbits-33xx.h"
22#include "prm33xx.h"
23
24static struct powerdomain gfx_33xx_pwrdm = {
25 .name = "gfx_pwrdm",
26 .voltdm = { .name = "core" },
27 .prcm_offs = AM33XX_PRM_GFX_MOD,
28 .pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
29 .pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET,
30 .pwrsts = PWRSTS_OFF_RET_ON,
31 .pwrsts_logic_ret = PWRSTS_OFF_RET,
32 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
33 .banks = 1,
34 .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
35 .mem_on_mask = {
36 [0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */
37 },
38 .mem_ret_mask = {
39 [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
40 },
41 .mem_pwrst_mask = {
42 [0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */
43 },
44 .mem_retst_mask = {
45 [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
46 },
47 .pwrsts_mem_ret = {
48 [0] = PWRSTS_OFF_RET, /* gfx_mem */
49 },
50 .pwrsts_mem_on = {
51 [0] = PWRSTS_ON, /* gfx_mem */
52 },
53};
54
55static struct powerdomain rtc_33xx_pwrdm = {
56 .name = "rtc_pwrdm",
57 .voltdm = { .name = "rtc" },
58 .prcm_offs = AM33XX_PRM_RTC_MOD,
59 .pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
60 .pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET,
61 .pwrsts = PWRSTS_ON,
62 .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
63};
64
65static struct powerdomain wkup_33xx_pwrdm = {
66 .name = "wkup_pwrdm",
67 .voltdm = { .name = "core" },
68 .prcm_offs = AM33XX_PRM_WKUP_MOD,
69 .pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
70 .pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET,
71 .pwrsts = PWRSTS_ON,
72 .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
73};
74
75static struct powerdomain per_33xx_pwrdm = {
76 .name = "per_pwrdm",
77 .voltdm = { .name = "core" },
78 .prcm_offs = AM33XX_PRM_PER_MOD,
79 .pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
80 .pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET,
81 .pwrsts = PWRSTS_OFF_RET_ON,
82 .pwrsts_logic_ret = PWRSTS_OFF_RET,
83 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
84 .banks = 3,
85 .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK,
86 .mem_on_mask = {
87 [0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
88 [1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */
89 [2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */
90 },
91 .mem_ret_mask = {
92 [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
93 [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
94 [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
95 },
96 .mem_pwrst_mask = {
97 [0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
98 [1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */
99 [2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */
100 },
101 .mem_retst_mask = {
102 [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
103 [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
104 [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
105 },
106 .pwrsts_mem_ret = {
107 [0] = PWRSTS_OFF_RET, /* pruss_mem */
108 [1] = PWRSTS_OFF_RET, /* per_mem */
109 [2] = PWRSTS_OFF_RET, /* ram_mem */
110 },
111 .pwrsts_mem_on = {
112 [0] = PWRSTS_ON, /* pruss_mem */
113 [1] = PWRSTS_ON, /* per_mem */
114 [2] = PWRSTS_ON, /* ram_mem */
115 },
116};
117
118static struct powerdomain mpu_33xx_pwrdm = {
119 .name = "mpu_pwrdm",
120 .voltdm = { .name = "mpu" },
121 .prcm_offs = AM33XX_PRM_MPU_MOD,
122 .pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
123 .pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET,
124 .pwrsts = PWRSTS_OFF_RET_ON,
125 .pwrsts_logic_ret = PWRSTS_OFF_RET,
126 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
127 .banks = 3,
128 .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK,
129 .mem_on_mask = {
130 [0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */
131 [1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */
132 [2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */
133 },
134 .mem_ret_mask = {
135 [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
136 [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
137 [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
138 },
139 .mem_pwrst_mask = {
140 [0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */
141 [1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */
142 [2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */
143 },
144 .mem_retst_mask = {
145 [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */
146 [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */
147 [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
148 },
149 .pwrsts_mem_ret = {
150 [0] = PWRSTS_OFF_RET, /* mpu_l1 */
151 [1] = PWRSTS_OFF_RET, /* mpu_l2 */
152 [2] = PWRSTS_OFF_RET, /* mpu_ram */
153 },
154 .pwrsts_mem_on = {
155 [0] = PWRSTS_ON, /* mpu_l1 */
156 [1] = PWRSTS_ON, /* mpu_l2 */
157 [2] = PWRSTS_ON, /* mpu_ram */
158 },
159};
160
161static struct powerdomain cefuse_33xx_pwrdm = {
162 .name = "cefuse_pwrdm",
163 .voltdm = { .name = "core" },
164 .prcm_offs = AM33XX_PRM_CEFUSE_MOD,
165 .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
166 .pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
167 .pwrsts = PWRSTS_OFF_ON,
168};
169
170static struct powerdomain *powerdomains_am33xx[] __initdata = {
171 &gfx_33xx_pwrdm,
172 &rtc_33xx_pwrdm,
173 &wkup_33xx_pwrdm,
174 &per_33xx_pwrdm,
175 &mpu_33xx_pwrdm,
176 &cefuse_33xx_pwrdm,
177 NULL,
178};
179
180void __init am33xx_powerdomains_init(void)
181{
182 pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
183 pwrdm_register_pwrdms(powerdomains_am33xx);
184 pwrdm_complete_init();
185}
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
new file mode 100644
index 000000000000..0221b5c20e87
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -0,0 +1,357 @@
1/*
2 * AM33XX PRM_XXX register bits
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
17#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
18
19#include "prm.h"
20
21/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
22#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1
23#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1)
24
25/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
26#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2
27#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
28
29/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
30#define AM33XX_AIPOFF_SHIFT 8
31#define AM33XX_AIPOFF_MASK (1 << 8)
32
33/* Used by PM_WKUP_PWRSTST */
34#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17
35#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17)
36
37/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
38#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0
39#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0)
40
41/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
42#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12
43#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12)
44
45/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
46#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12
47#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12)
48
49/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
50#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14
51#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14)
52
53/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
54#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14
55#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14)
56
57/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
58#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15
59#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15)
60
61/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
62#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13
63#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13)
64
65/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
66#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11
67#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11)
68
69/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
70#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11
71#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11)
72
73/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
74#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13
75#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13)
76
77/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
78#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15
79#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15)
80
81/* Used by RM_WKUP_RSTST */
82#define AM33XX_EMULATION_M3_RST_SHIFT 6
83#define AM33XX_EMULATION_M3_RST_MASK (1 << 6)
84
85/* Used by RM_MPU_RSTST */
86#define AM33XX_EMULATION_MPU_RST_SHIFT 5
87#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5)
88
89/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
90#define AM33XX_ENFUNC1_EXPORT_SHIFT 3
91#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3)
92
93/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
94#define AM33XX_ENFUNC3_EXPORT_SHIFT 5
95#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5)
96
97/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
98#define AM33XX_ENFUNC4_SHIFT 6
99#define AM33XX_ENFUNC4_MASK (1 << 6)
100
101/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
102#define AM33XX_ENFUNC5_SHIFT 7
103#define AM33XX_ENFUNC5_MASK (1 << 7)
104
105/* Used by PRM_RSTST */
106#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5
107#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5)
108
109/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
110#define AM33XX_FORCEWKUP_EN_SHIFT 10
111#define AM33XX_FORCEWKUP_EN_MASK (1 << 10)
112
113/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
114#define AM33XX_FORCEWKUP_ST_SHIFT 10
115#define AM33XX_FORCEWKUP_ST_MASK (1 << 10)
116
117/* Used by PM_GFX_PWRSTCTRL */
118#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17
119#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
120
121/* Used by PM_GFX_PWRSTCTRL */
122#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6
123#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6)
124
125/* Used by PM_GFX_PWRSTST */
126#define AM33XX_GFX_MEM_STATEST_SHIFT 4
127#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
128
129/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
130#define AM33XX_GFX_RST_SHIFT 0
131#define AM33XX_GFX_RST_MASK (1 << 0)
132
133/* Used by PRM_RSTST */
134#define AM33XX_GLOBAL_COLD_RST_SHIFT 0
135#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0)
136
137/* Used by PRM_RSTST */
138#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1
139#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
140
141/* Used by RM_WKUP_RSTST */
142#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7
143#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7)
144
145/* Used by RM_MPU_RSTST */
146#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6
147#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6)
148
149/* Used by PRM_RSTST */
150#define AM33XX_ICEPICK_RST_SHIFT 9
151#define AM33XX_ICEPICK_RST_MASK (1 << 9)
152
153/* Used by RM_PER_RSTCTRL */
154#define AM33XX_PRUSS_LRST_SHIFT 1
155#define AM33XX_PRUSS_LRST_MASK (1 << 1)
156
157/* Used by PM_PER_PWRSTCTRL */
158#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5
159#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
160
161/* Used by PM_PER_PWRSTCTRL */
162#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7
163#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7)
164
165/* Used by PM_PER_PWRSTST */
166#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23
167#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
168
169/*
170 * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
171 * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
172 */
173#define AM33XX_INTRANSITION_SHIFT 20
174#define AM33XX_INTRANSITION_MASK (1 << 20)
175
176/* Used by PM_CEFUSE_PWRSTST */
177#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24
178#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
179
180/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
181#define AM33XX_LOGICRETSTATE_SHIFT 2
182#define AM33XX_LOGICRETSTATE_MASK (1 << 2)
183
184/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
185#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3
186#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3)
187
188/*
189 * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
190 * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
191 */
192#define AM33XX_LOGICSTATEST_SHIFT 2
193#define AM33XX_LOGICSTATEST_MASK (1 << 2)
194
195/*
196 * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
197 * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
198 */
199#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4
200#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
201
202/* Used by PM_MPU_PWRSTCTRL */
203#define AM33XX_MPU_L1_ONSTATE_SHIFT 18
204#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
205
206/* Used by PM_MPU_PWRSTCTRL */
207#define AM33XX_MPU_L1_RETSTATE_SHIFT 22
208#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22)
209
210/* Used by PM_MPU_PWRSTST */
211#define AM33XX_MPU_L1_STATEST_SHIFT 6
212#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
213
214/* Used by PM_MPU_PWRSTCTRL */
215#define AM33XX_MPU_L2_ONSTATE_SHIFT 20
216#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
217
218/* Used by PM_MPU_PWRSTCTRL */
219#define AM33XX_MPU_L2_RETSTATE_SHIFT 23
220#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23)
221
222/* Used by PM_MPU_PWRSTST */
223#define AM33XX_MPU_L2_STATEST_SHIFT 8
224#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
225
226/* Used by PM_MPU_PWRSTCTRL */
227#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16
228#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16)
229
230/* Used by PM_MPU_PWRSTCTRL */
231#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24
232#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24)
233
234/* Used by PM_MPU_PWRSTST */
235#define AM33XX_MPU_RAM_STATEST_SHIFT 4
236#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4)
237
238/* Used by PRM_RSTST */
239#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2
240#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
241
242/* Used by PRM_SRAM_COUNT */
243#define AM33XX_PCHARGECNT_VALUE_SHIFT 0
244#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
245
246/* Used by RM_PER_RSTCTRL */
247#define AM33XX_PCI_LRST_SHIFT 0
248#define AM33XX_PCI_LRST_MASK (1 << 0)
249
250/* Renamed from PCI_LRST Used by RM_PER_RSTST */
251#define AM33XX_PCI_LRST_5_5_SHIFT 5
252#define AM33XX_PCI_LRST_5_5_MASK (1 << 5)
253
254/* Used by PM_PER_PWRSTCTRL */
255#define AM33XX_PER_MEM_ONSTATE_SHIFT 25
256#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25)
257
258/* Used by PM_PER_PWRSTCTRL */
259#define AM33XX_PER_MEM_RETSTATE_SHIFT 29
260#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29)
261
262/* Used by PM_PER_PWRSTST */
263#define AM33XX_PER_MEM_STATEST_SHIFT 17
264#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17)
265
266/*
267 * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
268 * PM_MPU_PWRSTCTRL
269 */
270#define AM33XX_POWERSTATE_SHIFT 0
271#define AM33XX_POWERSTATE_MASK (0x3 << 0)
272
273/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
274#define AM33XX_POWERSTATEST_SHIFT 0
275#define AM33XX_POWERSTATEST_MASK (0x3 << 0)
276
277/* Used by PM_PER_PWRSTCTRL */
278#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30
279#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30)
280
281/* Used by PM_PER_PWRSTCTRL */
282#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27
283#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27)
284
285/* Used by PM_PER_PWRSTST */
286#define AM33XX_RAM_MEM_STATEST_SHIFT 21
287#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21)
288
289/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
290#define AM33XX_RETMODE_ENABLE_SHIFT 0
291#define AM33XX_RETMODE_ENABLE_MASK (1 << 0)
292
293/* Used by REVISION_PRM */
294#define AM33XX_REV_SHIFT 0
295#define AM33XX_REV_MASK (0xff << 0)
296
297/* Used by PRM_RSTTIME */
298#define AM33XX_RSTTIME1_SHIFT 0
299#define AM33XX_RSTTIME1_MASK (0xff << 0)
300
301/* Used by PRM_RSTTIME */
302#define AM33XX_RSTTIME2_SHIFT 8
303#define AM33XX_RSTTIME2_MASK (0x1f << 8)
304
305/* Used by PRM_RSTCTRL */
306#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1
307#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
308
309/* Used by PRM_RSTCTRL */
310#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0
311#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
312
313/* Used by PRM_SRAM_COUNT */
314#define AM33XX_SLPCNT_VALUE_SHIFT 16
315#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16)
316
317/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
318#define AM33XX_SRAMLDO_STATUS_SHIFT 8
319#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8)
320
321/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
322#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9
323#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9)
324
325/* Used by PRM_SRAM_COUNT */
326#define AM33XX_STARTUP_COUNT_SHIFT 24
327#define AM33XX_STARTUP_COUNT_MASK (0xff << 24)
328
329/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
330#define AM33XX_TRANSITION_EN_SHIFT 8
331#define AM33XX_TRANSITION_EN_MASK (1 << 8)
332
333/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
334#define AM33XX_TRANSITION_ST_SHIFT 8
335#define AM33XX_TRANSITION_ST_MASK (1 << 8)
336
337/* Used by PRM_SRAM_COUNT */
338#define AM33XX_VSETUPCNT_VALUE_SHIFT 8
339#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8)
340
341/* Used by PRM_RSTST */
342#define AM33XX_WDT0_RST_SHIFT 3
343#define AM33XX_WDT0_RST_MASK (1 << 3)
344
345/* Used by PRM_RSTST */
346#define AM33XX_WDT1_RST_SHIFT 4
347#define AM33XX_WDT1_RST_MASK (1 << 4)
348
349/* Used by RM_WKUP_RSTCTRL */
350#define AM33XX_WKUP_M3_LRST_SHIFT 3
351#define AM33XX_WKUP_M3_LRST_MASK (1 << 3)
352
353/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
354#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5
355#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5)
356
357#endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
new file mode 100644
index 000000000000..e7dbb6cf1255
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -0,0 +1,135 @@
1/*
2 * AM33XX PRM functions
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/err.h>
20#include <linux/io.h>
21
22#include <plat/common.h>
23
24#include "common.h"
25#include "prm33xx.h"
26#include "prm-regbits-33xx.h"
27
28/* Read a register in a PRM instance */
29u32 am33xx_prm_read_reg(s16 inst, u16 idx)
30{
31 return __raw_readl(prm_base + inst + idx);
32}
33
34/* Write into a register in a PRM instance */
35void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
36{
37 __raw_writel(val, prm_base + inst + idx);
38}
39
40/* Read-modify-write a register in PRM. Caller must lock */
41u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
42{
43 u32 v;
44
45 v = am33xx_prm_read_reg(inst, idx);
46 v &= ~mask;
47 v |= bits;
48 am33xx_prm_write_reg(v, inst, idx);
49
50 return v;
51}
52
53/**
54 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
55 * submodules contained in the hwmod module
56 * @shift: register bit shift corresponding to the reset line to check
57 * @inst: CM instance register offset (*_INST macro)
58 * @rstctrl_offs: RM_RSTCTRL register address offset for this module
59 *
60 * Returns 1 if the (sub)module hardreset line is currently asserted,
61 * 0 if the (sub)module hardreset line is not currently asserted, or
62 * -EINVAL upon parameter error.
63 */
64int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
65{
66 u32 v;
67
68 v = am33xx_prm_read_reg(inst, rstctrl_offs);
69 v &= 1 << shift;
70 v >>= shift;
71
72 return v;
73}
74
75/**
76 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
77 * @shift: register bit shift corresponding to the reset line to assert
78 * @inst: CM instance register offset (*_INST macro)
79 * @rstctrl_reg: RM_RSTCTRL register address for this module
80 *
81 * Some IPs like dsp, ipu or iva contain processors that require an HW
82 * reset line to be asserted / deasserted in order to fully enable the
83 * IP. These modules may have multiple hard-reset lines that reset
84 * different 'submodules' inside the IP block. This function will
85 * place the submodule into reset. Returns 0 upon success or -EINVAL
86 * upon an argument error.
87 */
88int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
89{
90 u32 mask = 1 << shift;
91
92 am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
93
94 return 0;
95}
96
97/**
98 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
99 * wait
100 * @shift: register bit shift corresponding to the reset line to deassert
101 * @inst: CM instance register offset (*_INST macro)
102 * @rstctrl_reg: RM_RSTCTRL register address for this module
103 * @rstst_reg: RM_RSTST register address for this module
104 *
105 * Some IPs like dsp, ipu or iva contain processors that require an HW
106 * reset line to be asserted / deasserted in order to fully enable the
107 * IP. These modules may have multiple hard-reset lines that reset
108 * different 'submodules' inside the IP block. This function will
109 * take the submodule out of reset and wait until the PRCM indicates
110 * that the reset has completed before returning. Returns 0 upon success or
111 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
112 * of reset, or -EBUSY if the submodule did not exit reset promptly.
113 */
114int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
115 u16 rstctrl_offs, u16 rstst_offs)
116{
117 int c;
118 u32 mask = 1 << shift;
119
120 /* Check the current status to avoid de-asserting the line twice */
121 if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
122 return -EEXIST;
123
124 /* Clear the reset status by writing 1 to the status bit */
125 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
126 /* de-assert the reset control line */
127 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
128 /* wait the status to be set */
129
130 omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
131 rstst_offs),
132 MAX_MODULE_HARDRESET_WAIT, c);
133
134 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
135}
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
new file mode 100644
index 000000000000..3f25c563a821
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -0,0 +1,129 @@
1/*
2 * AM33XX PRM instance offset macros
3 *
4 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
17#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
18
19#include "prcm-common.h"
20#include "prm.h"
21
22#define AM33XX_PRM_BASE 0x44E00000
23
24#define AM33XX_PRM_REGADDR(inst, reg) \
25 AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
26
27
28/* PRM instances */
29#define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
30#define AM33XX_PRM_PER_MOD 0x0C00
31#define AM33XX_PRM_WKUP_MOD 0x0D00
32#define AM33XX_PRM_MPU_MOD 0x0E00
33#define AM33XX_PRM_DEVICE_MOD 0x0F00
34#define AM33XX_PRM_RTC_MOD 0x1000
35#define AM33XX_PRM_GFX_MOD 0x1100
36#define AM33XX_PRM_CEFUSE_MOD 0x1200
37
38/* PRM */
39
40/* PRM.OCP_SOCKET_PRM register offsets */
41#define AM33XX_REVISION_PRM_OFFSET 0x0000
42#define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
43#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004
44#define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
45#define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008
46#define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
47#define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c
48#define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
49#define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010
50#define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
51
52/* PRM.PER_PRM register offsets */
53#define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000
54#define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
55#define AM33XX_RM_PER_RSTST_OFFSET 0x0004
56#define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
57#define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
58#define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
59#define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c
60#define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
61
62/* PRM.WKUP_PRM register offsets */
63#define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000
64#define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
65#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004
66#define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
67#define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008
68#define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
69#define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c
70#define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
71
72/* PRM.MPU_PRM register offsets */
73#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
74#define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
75#define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004
76#define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
77#define AM33XX_RM_MPU_RSTST_OFFSET 0x0008
78#define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
79
80/* PRM.DEVICE_PRM register offsets */
81#define AM33XX_PRM_RSTCTRL_OFFSET 0x0000
82#define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
83#define AM33XX_PRM_RSTTIME_OFFSET 0x0004
84#define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
85#define AM33XX_PRM_RSTST_OFFSET 0x0008
86#define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
87#define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c
88#define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
89#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010
90#define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
91#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014
92#define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
93#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018
94#define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
95#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c
96#define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
97
98/* PRM.RTC_PRM register offsets */
99#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000
100#define AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
101#define AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004
102#define AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
103
104/* PRM.GFX_PRM register offsets */
105#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000
106#define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
107#define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004
108#define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
109#define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010
110#define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
111#define AM33XX_RM_GFX_RSTST_OFFSET 0x0014
112#define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
113
114/* PRM.CEFUSE_PRM register offsets */
115#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000
116#define AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
117#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
119
120extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
121extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
122extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
123extern void am33xx_prm_global_warm_sw_reset(void);
124extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
125 u16 rstctrl_offs);
126extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
127extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
128 u16 rstctrl_offs, u16 rstst_offs);
129#endif
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 16a1b092cf36..a7c43c1042be 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -156,6 +156,7 @@ int omap_voltage_late_init(void);
156 156
157extern void omap2xxx_voltagedomains_init(void); 157extern void omap2xxx_voltagedomains_init(void);
158extern void omap3xxx_voltagedomains_init(void); 158extern void omap3xxx_voltagedomains_init(void);
159extern void am33xx_voltagedomains_init(void);
159extern void omap44xx_voltagedomains_init(void); 160extern void omap44xx_voltagedomains_init(void);
160 161
161struct voltagedomain *voltdm_lookup(const char *name); 162struct voltagedomain *voltdm_lookup(const char *name);
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
new file mode 100644
index 000000000000..965458dc0cb9
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c
@@ -0,0 +1,43 @@
1/*
2 * AM33XX voltage domain data
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include "voltage.h"
20
21static struct voltagedomain am33xx_voltdm_mpu = {
22 .name = "mpu",
23};
24
25static struct voltagedomain am33xx_voltdm_core = {
26 .name = "core",
27};
28
29static struct voltagedomain am33xx_voltdm_rtc = {
30 .name = "rtc",
31};
32
33static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
34 &am33xx_voltdm_mpu,
35 &am33xx_voltdm_core,
36 &am33xx_voltdm_rtc,
37 NULL,
38};
39
40void __init am33xx_voltagedomains_init(void)
41{
42 voltdm_init(voltagedomains_am33xx);
43}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-12 03:32:44 -0400