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authorAlex Deucher <alexdeucher@gmail.com>2010-12-15 11:01:56 -0500
committerDave Airlie <airlied@redhat.com>2010-12-15 19:08:26 -0500
commit6f2f48a9a061a94d059f89c69472f467839cc616 (patch)
tree980b2ea58eb2fe24bd52125da8d512c58dd54b79
parenta1a8213392b29c2b427567b86e2ccfe88ded58cc (diff)
drm/radeon/kms/evergreen: flush hdp cache when flushing gart tlb
Make sure vram changes hit memory. This mirrors the 6xx/7xx behavior. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c2
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h1
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 4dc5b4714c5a..39fa75bf7c4f 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -748,6 +748,8 @@ void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
748 unsigned i; 748 unsigned i;
749 u32 tmp; 749 u32 tmp;
750 750
751 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
752
751 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); 753 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
752 for (i = 0; i < rdev->usec_timeout; i++) { 754 for (i = 0; i < rdev->usec_timeout; i++) {
753 /* read MC_STATUS */ 755 /* read MC_STATUS */
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 113c70cc8b39..a73b53c44359 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -174,6 +174,7 @@
174#define HDP_NONSURFACE_BASE 0x2C04 174#define HDP_NONSURFACE_BASE 0x2C04
175#define HDP_NONSURFACE_INFO 0x2C08 175#define HDP_NONSURFACE_INFO 0x2C08
176#define HDP_NONSURFACE_SIZE 0x2C0C 176#define HDP_NONSURFACE_SIZE 0x2C0C
177#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
177#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 178#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
178#define HDP_TILING_CONFIG 0x2F3C 179#define HDP_TILING_CONFIG 0x2F3C
179 180