diff options
| author | Jarkko Nikula <jarkko.nikula@linux.intel.com> | 2014-02-24 10:26:56 -0500 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-02-24 23:44:27 -0500 |
| commit | 6ef20de726bd68b68a925cc63f12e0ed655c6b56 (patch) | |
| tree | 400b9d67602a24dbb2b1afa9f3ae0c568c496814 | |
| parent | 90931b9eaed9aaf772784a93da320cf10713effa (diff) | |
ASoC: Intel: Add Baytrail SST ID and Baytrail specific register bits
While the SHIM register addresses in Baytrail are the same than Haswell and
Broadwell their register size is 64-bit and some bits are different.
This patch adds the SST device ID for Baytrail and Baytrail specific
SHIM bit definitions.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Acked-by: Liam Girdwood <liam.r.girdwood@intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
| -rw-r--r-- | sound/soc/intel/sst-dsp.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sound/soc/intel/sst-dsp.h b/sound/soc/intel/sst-dsp.h index 608418c1181a..74052b59485c 100644 --- a/sound/soc/intel/sst-dsp.h +++ b/sound/soc/intel/sst-dsp.h | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | /* SST Device IDs */ | 24 | /* SST Device IDs */ |
| 25 | #define SST_DEV_ID_LYNX_POINT 0x33C8 | 25 | #define SST_DEV_ID_LYNX_POINT 0x33C8 |
| 26 | #define SST_DEV_ID_WILDCAT_POINT 0x3438 | 26 | #define SST_DEV_ID_WILDCAT_POINT 0x3438 |
| 27 | #define SST_DEV_ID_BYT 0x0F28 | ||
| 27 | 28 | ||
| 28 | /* Supported SST DMA Devices */ | 29 | /* Supported SST DMA Devices */ |
| 29 | #define SST_DMA_TYPE_DW 1 | 30 | #define SST_DMA_TYPE_DW 1 |
| @@ -72,10 +73,15 @@ | |||
| 72 | #define SST_CSR_S0IOCS (0x1 << 21) | 73 | #define SST_CSR_S0IOCS (0x1 << 21) |
| 73 | #define SST_CSR_S1IOCS (0x1 << 23) | 74 | #define SST_CSR_S1IOCS (0x1 << 23) |
| 74 | #define SST_CSR_LPCS (0x1 << 31) | 75 | #define SST_CSR_LPCS (0x1 << 31) |
| 76 | #define SST_BYT_CSR_RST (0x1 << 0) | ||
| 77 | #define SST_BYT_CSR_VECTOR_SEL (0x1 << 1) | ||
| 78 | #define SST_BYT_CSR_STALL (0x1 << 2) | ||
| 79 | #define SST_BYT_CSR_PWAITMODE (0x1 << 3) | ||
| 75 | 80 | ||
| 76 | /* ISRX / ISC */ | 81 | /* ISRX / ISC */ |
| 77 | #define SST_ISRX_BUSY (0x1 << 1) | 82 | #define SST_ISRX_BUSY (0x1 << 1) |
| 78 | #define SST_ISRX_DONE (0x1 << 0) | 83 | #define SST_ISRX_DONE (0x1 << 0) |
| 84 | #define SST_BYT_ISRX_REQUEST (0x1 << 1) | ||
| 79 | 85 | ||
| 80 | /* ISRD / ISD */ | 86 | /* ISRD / ISD */ |
| 81 | #define SST_ISRD_BUSY (0x1 << 1) | 87 | #define SST_ISRD_BUSY (0x1 << 1) |
| @@ -84,14 +90,19 @@ | |||
| 84 | /* IMRX / IMC */ | 90 | /* IMRX / IMC */ |
| 85 | #define SST_IMRX_BUSY (0x1 << 1) | 91 | #define SST_IMRX_BUSY (0x1 << 1) |
| 86 | #define SST_IMRX_DONE (0x1 << 0) | 92 | #define SST_IMRX_DONE (0x1 << 0) |
| 93 | #define SST_BYT_IMRX_REQUEST (0x1 << 1) | ||
| 87 | 94 | ||
| 88 | /* IPCX / IPCC */ | 95 | /* IPCX / IPCC */ |
| 89 | #define SST_IPCX_DONE (0x1 << 30) | 96 | #define SST_IPCX_DONE (0x1 << 30) |
| 90 | #define SST_IPCX_BUSY (0x1 << 31) | 97 | #define SST_IPCX_BUSY (0x1 << 31) |
| 98 | #define SST_BYT_IPCX_DONE ((u64)0x1 << 62) | ||
| 99 | #define SST_BYT_IPCX_BUSY ((u64)0x1 << 63) | ||
| 91 | 100 | ||
| 92 | /* IPCD */ | 101 | /* IPCD */ |
| 93 | #define SST_IPCD_DONE (0x1 << 30) | 102 | #define SST_IPCD_DONE (0x1 << 30) |
| 94 | #define SST_IPCD_BUSY (0x1 << 31) | 103 | #define SST_IPCD_BUSY (0x1 << 31) |
| 104 | #define SST_BYT_IPCD_DONE ((u64)0x1 << 62) | ||
| 105 | #define SST_BYT_IPCD_BUSY ((u64)0x1 << 63) | ||
| 95 | 106 | ||
| 96 | /* CLKCTL */ | 107 | /* CLKCTL */ |
| 97 | #define SST_CLKCTL_SMOS(x) (x << 24) | 108 | #define SST_CLKCTL_SMOS(x) (x << 24) |