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authorArnd Bergmann <arnd@arndb.de>2014-09-25 18:15:09 -0400
committerArnd Bergmann <arnd@arndb.de>2014-09-25 18:15:09 -0400
commit6d50424a390966e0afdf4d28c2713c8312645bc9 (patch)
treee11b046bb3c9e89ed5bc6d9021595a8c87fb6984
parent0c18acc110c5d582327f78aa2d5d061d2e67af68 (diff)
parent02037a9719fa89b7e5dc25cb22afc06c4eae406e (diff)
Merge tag 'at91-soc2' of git://github.com/at91linux/linux-at91 into next/soc
Pull "Second SoC batch for 3.18" from Nicolas Ferre: - introduction of the new SAMA5D4 SoC and associated Evaluation Kit - low level soc detection and early printk code - taking advantage of this, documentation of all AT91 SoC DT strings Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'at91-soc2' of git://github.com/at91linux/linux-at91: ARM: at91: document Atmel SMART compatibles ARM: at91: add sama5d4 support to sama5_defconfig ARM: at91: dt: add device tree file for SAMA5D4ek board ARM: at91: dt: add device tree file for SAMA5D4 SoC ARM: at91: SAMA5D4 SoC detection code and low level routines ARM: at91: introduce basic SAMA5D4 support clk: at91: add a driver for the h32mx clock
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/atmel-at91.txt37
-rw-r--r--Documentation/devicetree/bindings/clock/at91-clock.txt14
-rw-r--r--arch/arm/Kconfig.debug4
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/at91-sama5d4ek.dts260
-rw-r--r--arch/arm/boot/dts/sama5d4.dtsi1240
-rw-r--r--arch/arm/configs/sama5_defconfig1
-rw-r--r--arch/arm/mach-at91/Kconfig21
-rw-r--r--arch/arm/mach-at91/Makefile1
-rw-r--r--arch/arm/mach-at91/board-dt-sama5.c16
-rw-r--r--arch/arm/mach-at91/generic.h1
-rw-r--r--arch/arm/mach-at91/include/mach/cpu.h22
-rw-r--r--arch/arm/mach-at91/include/mach/debug-macro.S5
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h19
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d4.h33
-rw-r--r--arch/arm/mach-at91/include/mach/uncompress.h21
-rw-r--r--arch/arm/mach-at91/sama5d4.c64
-rw-r--r--arch/arm/mach-at91/setup.c97
-rw-r--r--arch/arm/mach-at91/soc.h5
-rw-r--r--drivers/clk/at91/Makefile1
-rw-r--r--drivers/clk/at91/clk-h32mx.c123
-rw-r--r--drivers/clk/at91/pmc.c6
-rw-r--r--drivers/clk/at91/pmc.h5
-rw-r--r--include/linux/clk/at91_pmc.h1
24 files changed, 1987 insertions, 12 deletions
diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt
index 16f60b41c147..4949e805f7fc 100644
--- a/Documentation/devicetree/bindings/arm/atmel-at91.txt
+++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt
@@ -1,6 +1,43 @@
1Atmel AT91 device tree bindings. 1Atmel AT91 device tree bindings.
2================================ 2================================
3 3
4Boards with a SoC of the Atmel AT91 or SMART family shall have the following
5properties:
6
7Required root node properties:
8compatible: must be one of:
9 * "atmel,at91rm9200"
10
11 * "atmel,at91sam9" for SoCs using an ARM926EJ-S core, shall be extended with
12 the specific SoC family or compatible:
13 o "atmel,at91sam9260"
14 o "atmel,at91sam9261"
15 o "atmel,at91sam9263"
16 o "atmel,at91sam9x5" for the 5 series, shall be extended with the specific
17 SoC compatible:
18 - "atmel,at91sam9g15"
19 - "atmel,at91sam9g25"
20 - "atmel,at91sam9g35"
21 - "atmel,at91sam9x25"
22 - "atmel,at91sam9x35"
23 o "atmel,at91sam9g20"
24 o "atmel,at91sam9g45"
25 o "atmel,at91sam9n12"
26 o "atmel,at91sam9rl"
27 * "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
28 SoC family:
29 o "atmel,sama5d3" shall be extended with the specific SoC compatible:
30 - "atmel,sama5d31"
31 - "atmel,sama5d33"
32 - "atmel,sama5d34"
33 - "atmel,sama5d35"
34 - "atmel,sama5d36"
35 o "atmel,sama5d4" shall be extended with the specific SoC compatible:
36 - "atmel,sama5d41"
37 - "atmel,sama5d42"
38 - "atmel,sama5d43"
39 - "atmel,sama5d44"
40
4PIT Timer required properties: 41PIT Timer required properties:
5- compatible: Should be "atmel,at91sam9260-pit" 42- compatible: Should be "atmel,at91sam9260-pit"
6- reg: Should contain registers location and length 43- reg: Should contain registers location and length
diff --git a/Documentation/devicetree/bindings/clock/at91-clock.txt b/Documentation/devicetree/bindings/clock/at91-clock.txt
index b3d544ca522a..7a4d4926f44e 100644
--- a/Documentation/devicetree/bindings/clock/at91-clock.txt
+++ b/Documentation/devicetree/bindings/clock/at91-clock.txt
@@ -74,6 +74,9 @@ Required properties:
74 "atmel,at91sam9x5-clk-utmi": 74 "atmel,at91sam9x5-clk-utmi":
75 at91 utmi clock 75 at91 utmi clock
76 76
77 "atmel,sama5d4-clk-h32mx":
78 at91 h32mx clock
79
77Required properties for SCKC node: 80Required properties for SCKC node:
78- reg : defines the IO memory reserved for the SCKC. 81- reg : defines the IO memory reserved for the SCKC.
79- #size-cells : shall be 0 (reg is used to encode clk id). 82- #size-cells : shall be 0 (reg is used to encode clk id).
@@ -447,3 +450,14 @@ For example:
447 #clock-cells = <0>; 450 #clock-cells = <0>;
448 clocks = <&main>; 451 clocks = <&main>;
449 }; 452 };
453
454Required properties for 32 bits bus Matrix clock (h32mx clock):
455- #clock-cells : from common clock binding; shall be set to 0.
456- clocks : shall be the master clock source phandle.
457
458For example:
459 h32ck: h32mxck {
460 #clock-cells = <0>;
461 compatible = "atmel,sama5d4-clk-h32mx";
462 clocks = <&mck>;
463 };
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 22ebff9d781d..ebce6e2c8390 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -101,6 +101,10 @@ choice
101 bool "Kernel low-level debugging on 9263 and 9g45" 101 bool "Kernel low-level debugging on 9263 and 9g45"
102 depends on HAVE_AT91_DBGU1 102 depends on HAVE_AT91_DBGU1
103 103
104 config AT91_DEBUG_LL_DBGU2
105 bool "Kernel low-level debugging on sama5d4"
106 depends on HAVE_AT91_DBGU2
107
104 config DEBUG_BCM2835 108 config DEBUG_BCM2835
105 bool "Kernel low-level debugging on BCM2835 PL011 UART" 109 bool "Kernel low-level debugging on BCM2835 PL011 UART"
106 depends on ARCH_BCM2835 110 depends on ARCH_BCM2835
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1a471d7c61ce..76fafb666c3c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -48,6 +48,8 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb
48dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb 48dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
49dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb 49dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
50dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb 50dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
51# sama5d4
52dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
51 53
52dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb 54dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
53dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb 55dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
new file mode 100644
index 000000000000..b5b84006469e
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -0,0 +1,260 @@
1/*
2 * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This library is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45/dts-v1/;
46#include "sama5d4.dtsi"
47
48/ {
49 model = "Atmel SAMA5D4-EK";
50 compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
51
52 chosen {
53 bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
54 };
55
56 memory {
57 reg = <0x20000000 0x20000000>;
58 };
59
60 clocks {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 main_clock: clock@0 {
66 compatible = "atmel,osc", "fixed-clock";
67 clock-frequency = <12000000>;
68 };
69
70 slow_xtal {
71 clock-frequency = <32768>;
72 };
73
74 main_xtal {
75 clock-frequency = <12000000>;
76 };
77 };
78
79 ahb {
80 apb {
81 lcd_bus@f0000000 {
82 status = "okay";
83
84 lcd@f0000000 {
85 status = "okay";
86 };
87
88 lcdovl1@f0000140 {
89 status = "okay";
90 };
91
92 lcdovl2@f0000240 {
93 status = "okay";
94 };
95
96 lcdheo1@f0000340 {
97 status = "okay";
98 };
99 };
100
101 adc0: adc@fc034000 {
102 /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
103 atmel,adc-vref = <3300>;
104 /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */
105 status = "okay"; /* Enable ADC IIO support */
106 };
107
108 mmc0: mmc@f8000000 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
111 slot@1 {
112 reg = <1>;
113 bus-width = <4>;
114 cd-gpios = <&pioE 5 0>;
115 };
116 };
117
118 spi0: spi@f8010000 {
119 cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
120 status = "okay";
121 m25p80@0 {
122 compatible = "atmel,at25df321a";
123 spi-max-frequency = <50000000>;
124 reg = <0>;
125 };
126 };
127
128 i2c0: i2c@f8014000 {
129 status = "okay";
130 };
131
132 macb0: ethernet@f8020000 {
133 phy-mode = "rmii";
134 status = "okay";
135 };
136
137 mmc1: mmc@fc000000 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
140 status = "okay";
141 slot@0 {
142 reg = <0>;
143 bus-width = <4>;
144 cd-gpios = <&pioE 6 0>;
145 };
146 };
147
148 usart2: serial@fc008000 {
149 status = "okay";
150 };
151
152 usart3: serial@fc00c000 {
153 status = "okay";
154 };
155
156 usart4: serial@fc010000 {
157 status = "okay";
158 };
159
160 watchdog@fc068640 {
161 status = "okay";
162 };
163
164 pinctrl@fc06a000 {
165 board {
166 pinctrl_mmc0_cd: mmc0_cd {
167 atmel,pins =
168 <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
169 };
170 pinctrl_mmc1_cd: mmc1_cd {
171 atmel,pins =
172 <AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
173 };
174 pinctrl_usba_vbus: usba_vbus {
175 atmel,pins =
176 <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
177 };
178 pinctrl_key_gpio: key_gpio_0 {
179 atmel,pins =
180 <AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */
181 };
182 };
183 };
184 };
185
186 usb0: gadget@00400000 {
187 atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_usba_vbus>;
190 status = "okay";
191 };
192
193 usb1: ohci@00500000 {
194 num-ports = <3>;
195 atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */
196 &pioE 11 GPIO_ACTIVE_LOW
197 &pioE 12 GPIO_ACTIVE_LOW
198 >;
199 status = "okay";
200 };
201
202 usb2: ehci@00600000 {
203 status = "okay";
204 };
205
206 nand0: nand@80000000 {
207 nand-bus-width = <8>;
208 nand-ecc-mode = "hw";
209 nand-on-flash-bbt;
210 atmel,has-pmecc;
211 status = "okay";
212
213 at91bootstrap@0 {
214 label = "at91bootstrap";
215 reg = <0x0 0x40000>;
216 };
217
218 bootloader@40000 {
219 label = "bootloader";
220 reg = <0x40000 0x80000>;
221 };
222
223 bootloaderenv@c0000 {
224 label = "bootloader env";
225 reg = <0xc0000 0xc0000>;
226 };
227
228 dtb@180000 {
229 label = "device tree";
230 reg = <0x180000 0x80000>;
231 };
232
233 kernel@200000 {
234 label = "kernel";
235 reg = <0x200000 0x600000>;
236 };
237
238 rootfs@800000 {
239 label = "rootfs";
240 reg = <0x800000 0x0f800000>;
241 };
242 };
243 };
244
245 gpio_keys {
246 compatible = "gpio-keys";
247 #address-cells = <1>;
248 #size-cells = <0>;
249
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_key_gpio>;
252
253 pb_user1 {
254 label = "pb_user1";
255 gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
256 linux,code = <0x100>;
257 gpio-key,wakeup;
258 };
259 };
260};
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
new file mode 100644
index 000000000000..e0157b0f075c
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -0,0 +1,1240 @@
1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This library is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This library is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
48#include <dt-bindings/pinctrl/at91.h>
49#include <dt-bindings/interrupt-controller/irq.h>
50#include <dt-bindings/gpio/gpio.h>
51
52/ {
53 model = "Atmel SAMA5D4 family SoC";
54 compatible = "atmel,sama5d4";
55 interrupt-parent = <&aic>;
56
57 aliases {
58 serial0 = &usart3;
59 serial1 = &usart4;
60 serial2 = &usart2;
61 gpio0 = &pioA;
62 gpio1 = &pioB;
63 gpio2 = &pioC;
64 gpio4 = &pioE;
65 tcb0 = &tcb0;
66 tcb1 = &tcb1;
67 i2c2 = &i2c2;
68 };
69 cpus {
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 cpu@0 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a5";
76 reg = <0>;
77 next-level-cache = <&L2>;
78 };
79 };
80
81 memory {
82 reg = <0x20000000 0x20000000>;
83 };
84
85 clocks {
86 slow_xtal: slow_xtal {
87 compatible = "fixed-clock";
88 #clock-cells = <0>;
89 clock-frequency = <0>;
90 };
91
92 main_xtal: main_xtal {
93 compatible = "fixed-clock";
94 #clock-cells = <0>;
95 clock-frequency = <0>;
96 };
97
98 adc_op_clk: adc_op_clk{
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <1000000>;
102 };
103 };
104
105 ahb {
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
109 ranges;
110
111 usb0: gadget@00400000 {
112 #address-cells = <1>;
113 #size-cells = <0>;
114 compatible = "atmel,at91sam9rl-udc";
115 reg = <0x00400000 0x100000
116 0xfc02c000 0x4000>;
117 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
118 clocks = <&udphs_clk>, <&utmi>;
119 clock-names = "pclk", "hclk";
120 status = "disabled";
121
122 ep0 {
123 reg = <0>;
124 atmel,fifo-size = <64>;
125 atmel,nb-banks = <1>;
126 };
127
128 ep1 {
129 reg = <1>;
130 atmel,fifo-size = <1024>;
131 atmel,nb-banks = <3>;
132 atmel,can-dma;
133 atmel,can-isoc;
134 };
135
136 ep2 {
137 reg = <2>;
138 atmel,fifo-size = <1024>;
139 atmel,nb-banks = <3>;
140 atmel,can-dma;
141 atmel,can-isoc;
142 };
143
144 ep3 {
145 reg = <3>;
146 atmel,fifo-size = <1024>;
147 atmel,nb-banks = <2>;
148 atmel,can-dma;
149 atmel,can-isoc;
150 };
151
152 ep4 {
153 reg = <4>;
154 atmel,fifo-size = <1024>;
155 atmel,nb-banks = <2>;
156 atmel,can-dma;
157 atmel,can-isoc;
158 };
159
160 ep5 {
161 reg = <5>;
162 atmel,fifo-size = <1024>;
163 atmel,nb-banks = <2>;
164 atmel,can-dma;
165 atmel,can-isoc;
166 };
167
168 ep6 {
169 reg = <6>;
170 atmel,fifo-size = <1024>;
171 atmel,nb-banks = <2>;
172 atmel,can-dma;
173 atmel,can-isoc;
174 };
175
176 ep7 {
177 reg = <7>;
178 atmel,fifo-size = <1024>;
179 atmel,nb-banks = <2>;
180 atmel,can-dma;
181 atmel,can-isoc;
182 };
183
184 ep8 {
185 reg = <8>;
186 atmel,fifo-size = <1024>;
187 atmel,nb-banks = <2>;
188 atmel,can-isoc;
189 };
190
191 ep9 {
192 reg = <9>;
193 atmel,fifo-size = <1024>;
194 atmel,nb-banks = <2>;
195 atmel,can-isoc;
196 };
197
198 ep10 {
199 reg = <10>;
200 atmel,fifo-size = <1024>;
201 atmel,nb-banks = <2>;
202 atmel,can-isoc;
203 };
204
205 ep11 {
206 reg = <11>;
207 atmel,fifo-size = <1024>;
208 atmel,nb-banks = <2>;
209 atmel,can-isoc;
210 };
211
212 ep12 {
213 reg = <12>;
214 atmel,fifo-size = <1024>;
215 atmel,nb-banks = <2>;
216 atmel,can-isoc;
217 };
218
219 ep13 {
220 reg = <13>;
221 atmel,fifo-size = <1024>;
222 atmel,nb-banks = <2>;
223 atmel,can-isoc;
224 };
225
226 ep14 {
227 reg = <14>;
228 atmel,fifo-size = <1024>;
229 atmel,nb-banks = <2>;
230 atmel,can-isoc;
231 };
232
233 ep15 {
234 reg = <15>;
235 atmel,fifo-size = <1024>;
236 atmel,nb-banks = <2>;
237 atmel,can-isoc;
238 };
239 };
240
241 usb1: ohci@00500000 {
242 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
243 reg = <0x00500000 0x100000>;
244 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
245 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
246 <&uhpck>;
247 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
248 status = "disabled";
249 };
250
251 usb2: ehci@00600000 {
252 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
253 reg = <0x00600000 0x100000>;
254 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
255 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
256 clock-names = "usb_clk", "ehci_clk", "uhpck";
257 status = "disabled";
258 };
259
260 L2: cache-controller@00a00000 {
261 compatible = "arm,pl310-cache";
262 reg = <0x00a00000 0x1000>;
263 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
264 cache-unified;
265 cache-level = <2>;
266 };
267
268 nand0: nand@80000000 {
269 compatible = "atmel,at91rm9200-nand";
270 #address-cells = <1>;
271 #size-cells = <1>;
272 ranges;
273 reg = < 0x80000000 0x08000000 /* EBI CS3 */
274 0xfc05c070 0x00000490 /* SMC PMECC regs */
275 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
276 >;
277 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
278 atmel,nand-addr-offset = <21>;
279 atmel,nand-cmd-offset = <22>;
280 atmel,nand-has-dma;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_nand>;
283 status = "disabled";
284
285 nfc@90000000 {
286 compatible = "atmel,sama5d3-nfc";
287 #address-cells = <1>;
288 #size-cells = <1>;
289 reg = <
290 0x90000000 0x10000000 /* NFC Command Registers */
291 0xfc05c000 0x00000070 /* NFC HSMC regs */
292 0x00100000 0x00100000 /* NFC SRAM banks */
293 >;
294 clocks = <&hsmc_clk>;
295 atmel,write-by-sram;
296 };
297 };
298
299 apb {
300 compatible = "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
303 ranges;
304
305 ramc0: ramc@f0010000 {
306 compatible = "atmel,sama5d3-ddramc";
307 reg = <0xf0010000 0x200>;
308 clocks = <&ddrck>, <&mpddr_clk>;
309 clock-names = "ddrck", "mpddr";
310 };
311
312 pmc: pmc@f0018000 {
313 compatible = "atmel,sama5d3-pmc";
314 reg = <0xf0018000 0x120>;
315 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
316 interrupt-controller;
317 #address-cells = <1>;
318 #size-cells = <0>;
319 #interrupt-cells = <1>;
320
321 main_rc_osc: main_rc_osc {
322 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
323 #clock-cells = <0>;
324 interrupt-parent = <&pmc>;
325 interrupts = <AT91_PMC_MOSCRCS>;
326 clock-frequency = <12000000>;
327 clock-accuracy = <100000000>;
328 };
329
330 main_osc: main_osc {
331 compatible = "atmel,at91rm9200-clk-main-osc";
332 #clock-cells = <0>;
333 interrupt-parent = <&pmc>;
334 interrupts = <AT91_PMC_MOSCS>;
335 clocks = <&main_xtal>;
336 };
337
338 main: mainck {
339 compatible = "atmel,at91sam9x5-clk-main";
340 #clock-cells = <0>;
341 interrupt-parent = <&pmc>;
342 interrupts = <AT91_PMC_MOSCSELS>;
343 clocks = <&main_rc_osc &main_osc>;
344 };
345
346 plla: pllack {
347 compatible = "atmel,sama5d3-clk-pll";
348 #clock-cells = <0>;
349 interrupt-parent = <&pmc>;
350 interrupts = <AT91_PMC_LOCKA>;
351 clocks = <&main>;
352 reg = <0>;
353 atmel,clk-input-range = <12000000 12000000>;
354 #atmel,pll-clk-output-range-cells = <4>;
355 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
356 };
357
358 plladiv: plladivck {
359 compatible = "atmel,at91sam9x5-clk-plldiv";
360 #clock-cells = <0>;
361 clocks = <&plla>;
362 };
363
364 utmi: utmick {
365 compatible = "atmel,at91sam9x5-clk-utmi";
366 #clock-cells = <0>;
367 interrupt-parent = <&pmc>;
368 interrupts = <AT91_PMC_LOCKU>;
369 clocks = <&main>;
370 };
371
372 mck: masterck {
373 compatible = "atmel,at91sam9x5-clk-master";
374 #clock-cells = <0>;
375 interrupt-parent = <&pmc>;
376 interrupts = <AT91_PMC_MCKRDY>;
377 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
378 atmel,clk-output-range = <125000000 177000000>;
379 atmel,clk-divisors = <1 2 4 3>;
380 };
381
382 h32ck: h32mxck {
383 #clock-cells = <0>;
384 compatible = "atmel,sama5d4-clk-h32mx";
385 clocks = <&mck>;
386 };
387
388 usb: usbck {
389 compatible = "atmel,at91sam9x5-clk-usb";
390 #clock-cells = <0>;
391 clocks = <&plladiv>, <&utmi>;
392 };
393
394 prog: progck {
395 compatible = "atmel,at91sam9x5-clk-programmable";
396 #address-cells = <1>;
397 #size-cells = <0>;
398 interrupt-parent = <&pmc>;
399 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
400
401 prog0: prog0 {
402 #clock-cells = <0>;
403 reg = <0>;
404 interrupts = <AT91_PMC_PCKRDY(0)>;
405 };
406
407 prog1: prog1 {
408 #clock-cells = <0>;
409 reg = <1>;
410 interrupts = <AT91_PMC_PCKRDY(1)>;
411 };
412
413 prog2: prog2 {
414 #clock-cells = <0>;
415 reg = <2>;
416 interrupts = <AT91_PMC_PCKRDY(2)>;
417 };
418 };
419
420 smd: smdclk {
421 compatible = "atmel,at91sam9x5-clk-smd";
422 #clock-cells = <0>;
423 clocks = <&plladiv>, <&utmi>;
424 };
425
426 systemck {
427 compatible = "atmel,at91rm9200-clk-system";
428 #address-cells = <1>;
429 #size-cells = <0>;
430
431 ddrck: ddrck {
432 #clock-cells = <0>;
433 reg = <2>;
434 clocks = <&mck>;
435 };
436
437 lcdck: lcdck {
438 #clock-cells = <0>;
439 reg = <4>;
440 clocks = <&smd>;
441 };
442
443 smdck: smdck {
444 #clock-cells = <0>;
445 reg = <4>;
446 clocks = <&smd>;
447 };
448
449 uhpck: uhpck {
450 #clock-cells = <0>;
451 reg = <6>;
452 clocks = <&usb>;
453 };
454
455 udpck: udpck {
456 #clock-cells = <0>;
457 reg = <7>;
458 clocks = <&usb>;
459 };
460
461 pck0: pck0 {
462 #clock-cells = <0>;
463 reg = <8>;
464 clocks = <&prog0>;
465 };
466
467 pck1: pck1 {
468 #clock-cells = <0>;
469 reg = <9>;
470 clocks = <&prog1>;
471 };
472
473 pck2: pck2 {
474 #clock-cells = <0>;
475 reg = <10>;
476 clocks = <&prog2>;
477 };
478 };
479
480 periph32ck {
481 compatible = "atmel,at91sam9x5-clk-peripheral";
482 #address-cells = <1>;
483 #size-cells = <0>;
484 clocks = <&h32ck>;
485
486 pioD_clk: pioD_clk {
487 #clock-cells = <0>;
488 reg = <5>;
489 };
490
491 usart0_clk: usart0_clk {
492 #clock-cells = <0>;
493 reg = <6>;
494 };
495
496 usart1_clk: usart1_clk {
497 #clock-cells = <0>;
498 reg = <7>;
499 };
500
501 icm_clk: icm_clk {
502 #clock-cells = <0>;
503 reg = <9>;
504 };
505
506 aes_clk: aes_clk {
507 #clock-cells = <0>;
508 reg = <12>;
509 };
510
511 tdes_clk: tdes_clk {
512 #clock-cells = <0>;
513 reg = <14>;
514 };
515
516 sha_clk: sha_clk {
517 #clock-cells = <0>;
518 reg = <15>;
519 };
520
521 matrix1_clk: matrix1_clk {
522 #clock-cells = <0>;
523 reg = <17>;
524 };
525
526 hsmc_clk: hsmc_clk {
527 #clock-cells = <0>;
528 reg = <22>;
529 };
530
531 pioA_clk: pioA_clk {
532 #clock-cells = <0>;
533 reg = <23>;
534 };
535
536 pioB_clk: pioB_clk {
537 #clock-cells = <0>;
538 reg = <24>;
539 };
540
541 pioC_clk: pioC_clk {
542 #clock-cells = <0>;
543 reg = <25>;
544 };
545
546 pioE_clk: pioE_clk {
547 #clock-cells = <0>;
548 reg = <26>;
549 };
550
551 uart0_clk: uart0_clk {
552 #clock-cells = <0>;
553 reg = <27>;
554 };
555
556 uart1_clk: uart1_clk {
557 #clock-cells = <0>;
558 reg = <28>;
559 };
560
561 usart2_clk: usart2_clk {
562 #clock-cells = <0>;
563 reg = <29>;
564 };
565
566 usart3_clk: usart3_clk {
567 #clock-cells = <0>;
568 reg = <30>;
569 };
570
571 usart4_clk: usart4_clk {
572 #clock-cells = <0>;
573 reg = <31>;
574 };
575
576 twi0_clk: twi0_clk {
577 reg = <32>;
578 #clock-cells = <0>;
579 };
580
581 twi1_clk: twi1_clk {
582 #clock-cells = <0>;
583 reg = <33>;
584 };
585
586 twi2_clk: twi2_clk {
587 #clock-cells = <0>;
588 reg = <34>;
589 };
590
591 mci0_clk: mci0_clk {
592 #clock-cells = <0>;
593 reg = <35>;
594 };
595
596 mci1_clk: mci1_clk {
597 #clock-cells = <0>;
598 reg = <36>;
599 };
600
601 spi0_clk: spi0_clk {
602 #clock-cells = <0>;
603 reg = <37>;
604 };
605
606 spi1_clk: spi1_clk {
607 #clock-cells = <0>;
608 reg = <38>;
609 };
610
611 spi2_clk: spi2_clk {
612 #clock-cells = <0>;
613 reg = <39>;
614 };
615
616 tcb0_clk: tcb0_clk {
617 #clock-cells = <0>;
618 reg = <40>;
619 };
620
621 tcb1_clk: tcb1_clk {
622 #clock-cells = <0>;
623 reg = <41>;
624 };
625
626 tcb2_clk: tcb2_clk {
627 #clock-cells = <0>;
628 reg = <42>;
629 };
630
631 pwm_clk: pwm_clk {
632 #clock-cells = <0>;
633 reg = <43>;
634 };
635
636 adc_clk: adc_clk {
637 #clock-cells = <0>;
638 reg = <44>;
639 };
640
641 dbgu_clk: dbgu_clk {
642 #clock-cells = <0>;
643 reg = <45>;
644 };
645
646 uhphs_clk: uhphs_clk {
647 #clock-cells = <0>;
648 reg = <46>;
649 };
650
651 udphs_clk: udphs_clk {
652 #clock-cells = <0>;
653 reg = <47>;
654 };
655
656 ssc0_clk: ssc0_clk {
657 #clock-cells = <0>;
658 reg = <48>;
659 };
660
661 ssc1_clk: ssc1_clk {
662 #clock-cells = <0>;
663 reg = <49>;
664 };
665
666 trng_clk: trng_clk {
667 #clock-cells = <0>;
668 reg = <53>;
669 };
670
671 macb0_clk: macb0_clk {
672 #clock-cells = <0>;
673 reg = <54>;
674 };
675
676 macb1_clk: macb1_clk {
677 #clock-cells = <0>;
678 reg = <55>;
679 };
680
681 fuse_clk: fuse_clk {
682 #clock-cells = <0>;
683 reg = <57>;
684 };
685
686 securam_clk: securam_clk {
687 #clock-cells = <0>;
688 reg = <59>;
689 };
690
691 smd_clk: smd_clk {
692 #clock-cells = <0>;
693 reg = <61>;
694 };
695
696 twi3_clk: twi3_clk {
697 #clock-cells = <0>;
698 reg = <62>;
699 };
700
701 catb_clk: catb_clk {
702 #clock-cells = <0>;
703 reg = <63>;
704 };
705 };
706
707 periph64ck {
708 compatible = "atmel,at91sam9x5-clk-peripheral";
709 #address-cells = <1>;
710 #size-cells = <0>;
711 clocks = <&mck>;
712
713 dma0_clk: dma0_clk {
714 #clock-cells = <0>;
715 reg = <8>;
716 };
717
718 cpkcc_clk: cpkcc_clk {
719 #clock-cells = <0>;
720 reg = <10>;
721 };
722
723 aesb_clk: aesb_clk {
724 #clock-cells = <0>;
725 reg = <13>;
726 };
727
728 mpddr_clk: mpddr_clk {
729 #clock-cells = <0>;
730 reg = <16>;
731 };
732
733 matrix0_clk: matrix0_clk {
734 #clock-cells = <0>;
735 reg = <18>;
736 };
737
738 vdec_clk: vdec_clk {
739 #clock-cells = <0>;
740 reg = <19>;
741 };
742
743 dma1_clk: dma1_clk {
744 #clock-cells = <0>;
745 reg = <50>;
746 };
747
748 lcd_clk: lcd_clk {
749 #clock-cells = <0>;
750 reg = <51>;
751 };
752
753 isi_clk: isi_clk {
754 #clock-cells = <0>;
755 reg = <52>;
756 };
757 };
758 };
759
760 mmc0: mmc@f8000000 {
761 compatible = "atmel,hsmci";
762 reg = <0xf8000000 0x600>;
763 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
766 status = "disabled";
767 #address-cells = <1>;
768 #size-cells = <0>;
769 clocks = <&mci0_clk>;
770 clock-names = "mci_clk";
771 };
772
773 spi0: spi@f8010000 {
774 #address-cells = <1>;
775 #size-cells = <0>;
776 compatible = "atmel,at91rm9200-spi";
777 reg = <0xf8010000 0x100>;
778 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
779 pinctrl-names = "default";
780 pinctrl-0 = <&pinctrl_spi0>;
781 clocks = <&spi0_clk>;
782 clock-names = "spi_clk";
783 status = "disabled";
784 };
785
786 i2c0: i2c@f8014000 {
787 compatible = "atmel,at91sam9x5-i2c";
788 reg = <0xf8014000 0x4000>;
789 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
790 pinctrl-names = "default";
791 pinctrl-0 = <&pinctrl_i2c0>;
792 #address-cells = <1>;
793 #size-cells = <0>;
794 clocks = <&twi0_clk>;
795 status = "disabled";
796 };
797
798 tcb0: timer@f801c000 {
799 compatible = "atmel,at91sam9x5-tcb";
800 reg = <0xf801c000 0x100>;
801 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
802 clocks = <&tcb0_clk>;
803 clock-names = "t0_clk";
804 };
805
806 macb0: ethernet@f8020000 {
807 compatible = "atmel,sama5d4-gem";
808 reg = <0xf8020000 0x100>;
809 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
810 pinctrl-names = "default";
811 pinctrl-0 = <&pinctrl_macb0_rmii>;
812 clocks = <&macb0_clk>, <&macb0_clk>;
813 clock-names = "hclk", "pclk";
814 status = "disabled";
815 };
816
817 i2c2: i2c@f8024000 {
818 compatible = "atmel,at91sam9x5-i2c";
819 reg = <0xf8024000 0x4000>;
820 interrupts = <34 4 6>;
821 pinctrl-names = "default";
822 pinctrl-0 = <&pinctrl_i2c2>;
823 #address-cells = <1>;
824 #size-cells = <0>;
825 clocks = <&twi2_clk>;
826 status = "disabled";
827 };
828
829 mmc1: mmc@fc000000 {
830 compatible = "atmel,hsmci";
831 reg = <0xfc000000 0x600>;
832 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
833 pinctrl-names = "default";
834 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
835 status = "disabled";
836 #address-cells = <1>;
837 #size-cells = <0>;
838 clocks = <&mci1_clk>;
839 clock-names = "mci_clk";
840 };
841
842 usart2: serial@fc008000 {
843 compatible = "atmel,at91sam9260-usart";
844 reg = <0xfc008000 0x100>;
845 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
846 pinctrl-names = "default";
847 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
848 clocks = <&usart2_clk>;
849 clock-names = "usart";
850 status = "disabled";
851 };
852
853 usart3: serial@fc00c000 {
854 compatible = "atmel,at91sam9260-usart";
855 reg = <0xfc00c000 0x100>;
856 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
857 pinctrl-names = "default";
858 pinctrl-0 = <&pinctrl_usart3>;
859 clocks = <&usart3_clk>;
860 clock-names = "usart";
861 status = "disabled";
862 };
863
864 usart4: serial@fc010000 {
865 compatible = "atmel,at91sam9260-usart";
866 reg = <0xfc010000 0x100>;
867 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
868 pinctrl-names = "default";
869 pinctrl-0 = <&pinctrl_usart4>;
870 clocks = <&usart4_clk>;
871 clock-names = "usart";
872 status = "disabled";
873 };
874
875 tcb1: timer@fc020000 {
876 compatible = "atmel,at91sam9x5-tcb";
877 reg = <0xfc020000 0x100>;
878 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
879 clocks = <&tcb1_clk>;
880 clock-names = "t0_clk";
881 };
882
883 adc0: adc@fc034000 {
884 compatible = "atmel,at91sam9x5-adc";
885 reg = <0xfc034000 0x100>;
886 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
887 pinctrl-names = "default";
888 pinctrl-0 = <
889 /* external trigger is conflict with USBA_VBUS */
890 &pinctrl_adc0_ad0
891 &pinctrl_adc0_ad1
892 &pinctrl_adc0_ad2
893 &pinctrl_adc0_ad3
894 &pinctrl_adc0_ad4
895 >;
896 clocks = <&adc_clk>,
897 <&adc_op_clk>;
898 clock-names = "adc_clk", "adc_op_clk";
899 atmel,adc-channels-used = <0x01f>;
900 atmel,adc-startup-time = <40>;
901 atmel,adc-use-external;
902 atmel,adc-vref = <3000>;
903 atmel,adc-res = <8 10>;
904 atmel,adc-sample-hold-time = <11>;
905 atmel,adc-res-names = "lowres", "highres";
906 atmel,adc-ts-pressure-threshold = <10000>;
907 status = "disabled";
908
909 trigger@0 {
910 trigger-name = "external-rising";
911 trigger-value = <0x1>;
912 trigger-external;
913 };
914 trigger@1 {
915 trigger-name = "external-falling";
916 trigger-value = <0x2>;
917 trigger-external;
918 };
919 trigger@2 {
920 trigger-name = "external-any";
921 trigger-value = <0x3>;
922 trigger-external;
923 };
924 trigger@3 {
925 trigger-name = "continuous";
926 trigger-value = <0x6>;
927 };
928 };
929
930 rstc@fc068600 {
931 compatible = "atmel,at91sam9g45-rstc";
932 reg = <0xfc068600 0x10>;
933 };
934
935 shdwc@fc068610 {
936 compatible = "atmel,at91sam9x5-shdwc";
937 reg = <0xfc068610 0x10>;
938 };
939
940 pit: timer@fc068630 {
941 compatible = "atmel,at91sam9260-pit";
942 reg = <0xfc068630 0xf>;
943 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
944 clocks = <&h32ck>;
945 };
946
947 watchdog@fc068640 {
948 compatible = "atmel,at91sam9260-wdt";
949 reg = <0xfc068640 0x10>;
950 status = "disabled";
951 };
952
953 sckc@fc068650 {
954 compatible = "atmel,at91sam9x5-sckc";
955 reg = <0xfc068650 0x4>;
956
957 slow_rc_osc: slow_rc_osc {
958 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
959 #clock-cells = <0>;
960 clock-frequency = <32768>;
961 clock-accuracy = <250000000>;
962 atmel,startup-time-usec = <75>;
963 };
964
965 slow_osc: slow_osc {
966 compatible = "atmel,at91sam9x5-clk-slow-osc";
967 #clock-cells = <0>;
968 clocks = <&slow_xtal>;
969 atmel,startup-time-usec = <1200000>;
970 };
971
972 clk32k: slowck {
973 compatible = "atmel,at91sam9x5-clk-slow";
974 #clock-cells = <0>;
975 clocks = <&slow_rc_osc &slow_osc>;
976 };
977 };
978
979 rtc@fc0686b0 {
980 compatible = "atmel,at91rm9200-rtc";
981 reg = <0xfc0686b0 0x30>;
982 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
983 };
984
985 dbgu: serial@fc069000 {
986 compatible = "atmel,at91sam9260-usart";
987 reg = <0xfc069000 0x200>;
988 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
989 pinctrl-names = "default";
990 pinctrl-0 = <&pinctrl_dbgu>;
991 clocks = <&dbgu_clk>;
992 clock-names = "usart";
993 status = "disabled";
994 };
995
996
997 pinctrl@fc06a000 {
998 #address-cells = <1>;
999 #size-cells = <1>;
1000 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1001 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1002 /* WARNING: revisit as pin spec has changed */
1003 atmel,mux-mask = <
1004 /* A B C */
1005 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1006 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1007 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1008 0x00000000 0x00000000 0x00000000 /* pioD */
1009 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1010 >;
1011
1012 pioA: gpio@fc06a000 {
1013 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1014 reg = <0xfc06a000 0x100>;
1015 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1016 #gpio-cells = <2>;
1017 gpio-controller;
1018 interrupt-controller;
1019 #interrupt-cells = <2>;
1020 clocks = <&pioA_clk>;
1021 };
1022
1023 pioB: gpio@fc06b000 {
1024 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1025 reg = <0xfc06b000 0x100>;
1026 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1027 #gpio-cells = <2>;
1028 gpio-controller;
1029 interrupt-controller;
1030 #interrupt-cells = <2>;
1031 clocks = <&pioB_clk>;
1032 };
1033
1034 pioC: gpio@fc06c000 {
1035 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1036 reg = <0xfc06c000 0x100>;
1037 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1038 #gpio-cells = <2>;
1039 gpio-controller;
1040 interrupt-controller;
1041 #interrupt-cells = <2>;
1042 clocks = <&pioC_clk>;
1043 };
1044
1045 pioE: gpio@fc06d000 {
1046 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1047 reg = <0xfc06d000 0x100>;
1048 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1049 #gpio-cells = <2>;
1050 gpio-controller;
1051 interrupt-controller;
1052 #interrupt-cells = <2>;
1053 clocks = <&pioE_clk>;
1054 };
1055
1056 /* pinctrl pin settings */
1057 adc0 {
1058 pinctrl_adc0_adtrg: adc0_adtrg {
1059 atmel,pins =
1060 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1061 };
1062 pinctrl_adc0_ad0: adc0_ad0 {
1063 atmel,pins =
1064 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1065 };
1066 pinctrl_adc0_ad1: adc0_ad1 {
1067 atmel,pins =
1068 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1069 };
1070 pinctrl_adc0_ad2: adc0_ad2 {
1071 atmel,pins =
1072 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1073 };
1074 pinctrl_adc0_ad3: adc0_ad3 {
1075 atmel,pins =
1076 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1077 };
1078 pinctrl_adc0_ad4: adc0_ad4 {
1079 atmel,pins =
1080 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1081 };
1082 };
1083
1084 dbgu {
1085 pinctrl_dbgu: dbgu-0 {
1086 atmel,pins =
1087 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1088 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1089 };
1090 };
1091
1092 i2c0 {
1093 pinctrl_i2c0: i2c0-0 {
1094 atmel,pins =
1095 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1096 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1097 };
1098 };
1099
1100 i2c2 {
1101 pinctrl_i2c2: i2c2-0 {
1102 atmel,pins =
1103 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1104 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1105 };
1106 };
1107
1108 macb0 {
1109 pinctrl_macb0_rmii: macb0_rmii-0 {
1110 atmel,pins =
1111 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1112 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1113 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1114 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1115 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1116 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1117 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1118 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1119 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1120 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1121 >;
1122 };
1123 };
1124
1125 mmc0 {
1126 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1127 atmel,pins =
1128 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1129 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1130 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1131 >;
1132 };
1133 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1134 atmel,pins =
1135 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1136 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1137 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1138 >;
1139 };
1140 };
1141
1142 mmc1 {
1143 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1144 atmel,pins =
1145 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1146 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1147 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1148 >;
1149 };
1150 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1151 atmel,pins =
1152 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1153 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1154 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1155 >;
1156 };
1157 };
1158
1159 nand0 {
1160 pinctrl_nand: nand-0 {
1161 atmel,pins =
1162 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1163 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1164
1165 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1166 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1167
1168 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1169 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1170 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1171 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1172 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1173 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1174 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1175 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1176 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1177 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1178 };
1179 };
1180
1181 spi0 {
1182 pinctrl_spi0: spi0-0 {
1183 atmel,pins =
1184 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1185 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1186 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1187 >;
1188 };
1189 };
1190
1191 usart2 {
1192 pinctrl_usart2: usart2-0 {
1193 atmel,pins =
1194 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1195 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1196 >;
1197 };
1198 pinctrl_usart2_rts: usart2_rts-0 {
1199 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1200 };
1201 pinctrl_usart2_cts: usart2_cts-0 {
1202 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1203 };
1204 };
1205
1206 usart3 {
1207 pinctrl_usart3: usart3-0 {
1208 atmel,pins =
1209 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1210 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1211 >;
1212 };
1213 };
1214
1215 usart4 {
1216 pinctrl_usart4: usart4-0 {
1217 atmel,pins =
1218 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1219 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1220 >;
1221 };
1222 pinctrl_usart4_rts: usart4_rts-0 {
1223 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1224 };
1225 pinctrl_usart4_cts: usart4_cts-0 {
1226 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1227 };
1228 };
1229 };
1230
1231 aic: interrupt-controller@fc06e000 {
1232 #interrupt-cells = <3>;
1233 compatible = "atmel,sama5d4-aic";
1234 interrupt-controller;
1235 reg = <0xfc06e000 0x200>;
1236 atmel,external-irqs = <56>;
1237 };
1238 };
1239 };
1240};
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 4414990521d3..12007282b557 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -19,6 +19,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y
19CONFIG_ARCH_AT91=y 19CONFIG_ARCH_AT91=y
20CONFIG_SOC_SAM_V7=y 20CONFIG_SOC_SAM_V7=y
21CONFIG_SOC_SAMA5D3=y 21CONFIG_SOC_SAMA5D3=y
22CONFIG_SOC_SAMA5D4=y
22CONFIG_MACH_SAMA5_DT=y 23CONFIG_MACH_SAMA5_DT=y
23CONFIG_AEABI=y 24CONFIG_AEABI=y
24# CONFIG_OABI_COMPAT is not set 25# CONFIG_OABI_COMPAT is not set
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6cc6f7aebdae..807b22dadcb6 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -12,6 +12,9 @@ config HAVE_AT91_DBGU0
12config HAVE_AT91_DBGU1 12config HAVE_AT91_DBGU1
13 bool 13 bool
14 14
15config HAVE_AT91_DBGU2
16 bool
17
15config AT91_USE_OLD_CLK 18config AT91_USE_OLD_CLK
16 bool 19 bool
17 20
@@ -42,6 +45,9 @@ config AT91_SAM9_TIME
42config HAVE_AT91_SMD 45config HAVE_AT91_SMD
43 bool 46 bool
44 47
48config HAVE_AT91_H32MX
49 bool
50
45config SOC_AT91SAM9 51config SOC_AT91SAM9
46 bool 52 bool
47 select AT91_SAM9_TIME 53 select AT91_SAM9_TIME
@@ -103,6 +109,21 @@ config SOC_SAMA5D3
103 help 109 help
104 Select this if you are using one of Atmel's SAMA5D3 family SoC. 110 Select this if you are using one of Atmel's SAMA5D3 family SoC.
105 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36. 111 This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36.
112
113config SOC_SAMA5D4
114 bool "SAMA5D4 family"
115 select SOC_SAMA5
116 select HAVE_AT91_DBGU2
117 select CLKSRC_MMIO
118 select CACHE_L2X0
119 select CACHE_PL310
120 select HAVE_FB_ATMEL
121 select HAVE_AT91_UTMI
122 select HAVE_AT91_SMD
123 select HAVE_AT91_USB_CLK
124 select HAVE_AT91_H32MX
125 help
126 Select this if you are using one of Atmel's SAMA5D4 family SoC.
106endif 127endif
107 128
108if SOC_SAM_V4_V5 129if SOC_SAM_V4_V5
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c677f9688ffe..3e9f01ca142a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o
23obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o 23obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o
24obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o 24obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
25obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o 25obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
26obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
26 27
27obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o 28obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
28obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o 29obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 075ec0576ada..514956336025 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -73,7 +73,7 @@ static void __init sama5_dt_device_init(void)
73 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 73 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
74} 74}
75 75
76static const char *sama5_dt_board_compat[] __initdata = { 76static const char *sama5_dt_board_compat[] __initconst = {
77 "atmel,sama5", 77 "atmel,sama5",
78 NULL 78 NULL
79}; 79};
@@ -88,3 +88,17 @@ DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)")
88 .init_machine = sama5_dt_device_init, 88 .init_machine = sama5_dt_device_init,
89 .dt_compat = sama5_dt_board_compat, 89 .dt_compat = sama5_dt_board_compat,
90MACHINE_END 90MACHINE_END
91
92static const char *sama5_alt_dt_board_compat[] __initconst = {
93 "atmel,sama5d4",
94 NULL
95};
96
97DT_MACHINE_START(sama5_alt_dt, "Atmel SAMA5 (Device Tree)")
98 /* Maintainer: Atmel */
99 .map_io = at91_alt_map_io,
100 .init_early = at91_dt_initialize,
101 .init_machine = sama5_dt_device_init,
102 .dt_compat = sama5_alt_dt_board_compat,
103 .l2c_aux_mask = ~0UL,
104MACHINE_END
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 631fa3b8c16d..cddf1e51c50e 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -14,6 +14,7 @@
14 14
15 /* Map io */ 15 /* Map io */
16extern void __init at91_map_io(void); 16extern void __init at91_map_io(void);
17extern void __init at91_alt_map_io(void);
17extern void __init at91_init_sram(int bank, unsigned long base, 18extern void __init at91_init_sram(int bank, unsigned long base,
18 unsigned int length); 19 unsigned int length);
19 20
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 86c71debab5b..b27e9ca65653 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -36,7 +36,7 @@
36#define ARCH_ID_AT91M40807 0x14080745 36#define ARCH_ID_AT91M40807 0x14080745
37#define ARCH_ID_AT91R40008 0x44000840 37#define ARCH_ID_AT91R40008 0x44000840
38 38
39#define ARCH_ID_SAMA5D3 0x8A5C07C0 39#define ARCH_ID_SAMA5 0x8A5C07C0
40 40
41#define ARCH_EXID_AT91SAM9M11 0x00000001 41#define ARCH_EXID_AT91SAM9M11 0x00000001
42#define ARCH_EXID_AT91SAM9M10 0x00000002 42#define ARCH_EXID_AT91SAM9M10 0x00000002
@@ -49,12 +49,19 @@
49#define ARCH_EXID_AT91SAM9G25 0x00000003 49#define ARCH_EXID_AT91SAM9G25 0x00000003
50#define ARCH_EXID_AT91SAM9X25 0x00000004 50#define ARCH_EXID_AT91SAM9X25 0x00000004
51 51
52#define ARCH_EXID_SAMA5D3 0x00004300
52#define ARCH_EXID_SAMA5D31 0x00444300 53#define ARCH_EXID_SAMA5D31 0x00444300
53#define ARCH_EXID_SAMA5D33 0x00414300 54#define ARCH_EXID_SAMA5D33 0x00414300
54#define ARCH_EXID_SAMA5D34 0x00414301 55#define ARCH_EXID_SAMA5D34 0x00414301
55#define ARCH_EXID_SAMA5D35 0x00584300 56#define ARCH_EXID_SAMA5D35 0x00584300
56#define ARCH_EXID_SAMA5D36 0x00004301 57#define ARCH_EXID_SAMA5D36 0x00004301
57 58
59#define ARCH_EXID_SAMA5D4 0x00000007
60#define ARCH_EXID_SAMA5D41 0x00000001
61#define ARCH_EXID_SAMA5D42 0x00000002
62#define ARCH_EXID_SAMA5D43 0x00000003
63#define ARCH_EXID_SAMA5D44 0x00000004
64
58#define ARCH_FAMILY_AT91X92 0x09200000 65#define ARCH_FAMILY_AT91X92 0x09200000
59#define ARCH_FAMILY_AT91SAM9 0x01900000 66#define ARCH_FAMILY_AT91SAM9 0x01900000
60#define ARCH_FAMILY_AT91SAM9XE 0x02900000 67#define ARCH_FAMILY_AT91SAM9XE 0x02900000
@@ -86,6 +93,9 @@ enum at91_soc_type {
86 /* SAMA5D3 */ 93 /* SAMA5D3 */
87 AT91_SOC_SAMA5D3, 94 AT91_SOC_SAMA5D3,
88 95
96 /* SAMA5D4 */
97 AT91_SOC_SAMA5D4,
98
89 /* Unknown type */ 99 /* Unknown type */
90 AT91_SOC_UNKNOWN, 100 AT91_SOC_UNKNOWN,
91}; 101};
@@ -108,6 +118,10 @@ enum at91_soc_subtype {
108 AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, 118 AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34,
109 AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36, 119 AT91_SOC_SAMA5D35, AT91_SOC_SAMA5D36,
110 120
121 /* SAMA5D4 */
122 AT91_SOC_SAMA5D41, AT91_SOC_SAMA5D42, AT91_SOC_SAMA5D43,
123 AT91_SOC_SAMA5D44,
124
111 /* No subtype for this SoC */ 125 /* No subtype for this SoC */
112 AT91_SOC_SUBTYPE_NONE, 126 AT91_SOC_SUBTYPE_NONE,
113 127
@@ -211,6 +225,12 @@ static inline int at91_soc_is_detected(void)
211#define cpu_is_sama5d3() (0) 225#define cpu_is_sama5d3() (0)
212#endif 226#endif
213 227
228#ifdef CONFIG_SOC_SAMA5D4
229#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4)
230#else
231#define cpu_is_sama5d4() (0)
232#endif
233
214/* 234/*
215 * Since this is ARM, we will never run on any AVR32 CPU. But these 235 * Since this is ARM, we will never run on any AVR32 CPU. But these
216 * definitions may reduce clutter in common drivers. 236 * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index c6bb9e2d9baa..2103a90f2261 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -16,8 +16,11 @@
16 16
17#if defined(CONFIG_AT91_DEBUG_LL_DBGU0) 17#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
18#define AT91_DBGU AT91_BASE_DBGU0 18#define AT91_DBGU AT91_BASE_DBGU0
19#else 19#elif defined(CONFIG_AT91_DEBUG_LL_DBGU1)
20#define AT91_DBGU AT91_BASE_DBGU1 20#define AT91_DBGU AT91_BASE_DBGU1
21#else
22/* On sama5d4, use USART3 as low level serial console */
23#define AT91_DBGU SAMA5D4_BASE_USART3
21#endif 24#endif
22 25
23 .macro addruart, rp, rv, tmp 26 .macro addruart, rp, rv, tmp
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 56338245653a..d84776f6b8ac 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -19,8 +19,10 @@
19/* DBGU base */ 19/* DBGU base */
20/* rm9200, 9260/9g20, 9261/9g10, 9rl */ 20/* rm9200, 9260/9g20, 9261/9g10, 9rl */
21#define AT91_BASE_DBGU0 0xfffff200 21#define AT91_BASE_DBGU0 0xfffff200
22/* 9263, 9g45 */ 22/* 9263, 9g45, sama5d3 */
23#define AT91_BASE_DBGU1 0xffffee00 23#define AT91_BASE_DBGU1 0xffffee00
24/* sama5d4 */
25#define AT91_BASE_DBGU2 0xfc069000
24 26
25#if defined(CONFIG_ARCH_AT91X40) 27#if defined(CONFIG_ARCH_AT91X40)
26#include <mach/at91x40.h> 28#include <mach/at91x40.h>
@@ -34,6 +36,7 @@
34#include <mach/at91sam9x5.h> 36#include <mach/at91sam9x5.h>
35#include <mach/at91sam9n12.h> 37#include <mach/at91sam9n12.h>
36#include <mach/sama5d3.h> 38#include <mach/sama5d3.h>
39#include <mach/sama5d4.h>
37 40
38/* 41/*
39 * On all at91 except rm9200 and x40 have the System Controller starts 42 * On all at91 except rm9200 and x40 have the System Controller starts
@@ -47,6 +50,11 @@
47 * and map the same memory space 50 * and map the same memory space
48 */ 51 */
49#define AT91_BASE_SYS 0xffffc000 52#define AT91_BASE_SYS 0xffffc000
53
54/*
55 * On sama5d4 there is no system controller, we map some needed peripherals
56 */
57#define AT91_ALT_BASE_SYS 0xfc069000
50#endif 58#endif
51 59
52/* 60/*
@@ -69,6 +77,13 @@
69 */ 77 */
70#define AT91_IO_PHYS_BASE 0xFFF78000 78#define AT91_IO_PHYS_BASE 0xFFF78000
71#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE) 79#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE)
80
81/*
82 * On sama5d4, remap the peripherals from address 0xFC069000 .. 0xFC06F000
83 * to 0xFB069000 .. 0xFB06F000. (24Kb)
84 */
85#define AT91_ALT_IO_PHYS_BASE AT91_ALT_BASE_SYS
86#define AT91_ALT_IO_VIRT_BASE IOMEM(0xFB069000)
72#else 87#else
73/* 88/*
74 * Identity mapping for the non MMU case. 89 * Identity mapping for the non MMU case.
@@ -81,11 +96,13 @@
81 96
82 /* Convert a physical IO address to virtual IO address */ 97 /* Convert a physical IO address to virtual IO address */
83#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE) 98#define AT91_IO_P2V(x) ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
99#define AT91_ALT_IO_P2V(x) ((x) - AT91_ALT_IO_PHYS_BASE + AT91_ALT_IO_VIRT_BASE)
84 100
85/* 101/*
86 * Virtual to Physical Address mapping for IO devices. 102 * Virtual to Physical Address mapping for IO devices.
87 */ 103 */
88#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) 104#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
105#define AT91_ALT_VA_BASE_SYS AT91_ALT_IO_P2V(AT91_ALT_BASE_SYS)
89 106
90 /* Internal SRAM is mapped below the IO devices */ 107 /* Internal SRAM is mapped below the IO devices */
91#define AT91_SRAM_MAX SZ_1M 108#define AT91_SRAM_MAX SZ_1M
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
new file mode 100644
index 000000000000..f256a45d9854
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -0,0 +1,33 @@
1/*
2 * Chip-specific header file for the SAMA5D4 family
3 *
4 * Copyright (C) 2013 Atmel Corporation,
5 * Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Common definitions.
8 * Based on SAMA5D4 datasheet.
9 *
10 * Licensed under GPLv2 or later.
11 */
12
13#ifndef SAMA5D4_H
14#define SAMA5D4_H
15
16/*
17 * User Peripheral physical base addresses.
18 */
19#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3 non-secure) Base Address */
20#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */
21#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */
22#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */
23
24/* Some other peripherals */
25#define SAMA5D4_BASE_SYS2 SAMA5D4_BASE_PIOD
26
27/*
28 * Internal Memory.
29 */
30#define SAMA5D4_NS_SRAM_BASE 0x00210000 /* Internal SRAM base address Non-Secure */
31#define SAMA5D4_NS_SRAM_SIZE (64 * SZ_1K) /* Internal SRAM size Non-Secure part (64Kb) */
32
33#endif
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 4bb644f8e87c..acb2d890ad7e 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = {
94 0, 94 0,
95}; 95};
96 96
97static const u32 uarts_sama5[] = { 97static const u32 uarts_sama5d3[] = {
98 AT91_BASE_DBGU1, 98 AT91_BASE_DBGU1,
99 SAMA5D3_BASE_USART0, 99 SAMA5D3_BASE_USART0,
100 SAMA5D3_BASE_USART1, 100 SAMA5D3_BASE_USART1,
@@ -103,6 +103,12 @@ static const u32 uarts_sama5[] = {
103 0, 103 0,
104}; 104};
105 105
106static const u32 uarts_sama5d4[] = {
107 AT91_BASE_DBGU2,
108 SAMA5D4_BASE_USART3,
109 0,
110};
111
106static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) 112static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
107{ 113{
108 u32 cidr, socid; 114 u32 cidr, socid;
@@ -134,8 +140,14 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
134 case ARCH_ID_AT91SAM9X5: 140 case ARCH_ID_AT91SAM9X5:
135 return uarts_sam9x5; 141 return uarts_sam9x5;
136 142
137 case ARCH_ID_SAMA5D3: 143 case ARCH_ID_SAMA5:
138 return uarts_sama5; 144 cidr = __raw_readl(dbgu_base + AT91_DBGU_EXID);
145 if (cidr & ARCH_EXID_SAMA5D3)
146 return uarts_sama5d3;
147 else if (cidr & ARCH_EXID_SAMA5D4)
148 return uarts_sama5d4;
149
150 break;
139 } 151 }
140 152
141 /* at91sam9g10 */ 153 /* at91sam9g10 */
@@ -156,9 +168,10 @@ static inline void arch_decomp_setup(void)
156 const u32* usarts; 168 const u32* usarts;
157 169
158 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0); 170 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
159
160 if (!usarts) 171 if (!usarts)
161 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1); 172 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
173 if (!usarts)
174 usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU2);
162 if (!usarts) { 175 if (!usarts) {
163 at91_uart = NULL; 176 at91_uart = NULL;
164 return; 177 return;
diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c
new file mode 100644
index 000000000000..7638509639f4
--- /dev/null
+++ b/arch/arm/mach-at91/sama5d4.c
@@ -0,0 +1,64 @@
1/*
2 * Chip-specific setup code for the SAMA5D4 family
3 *
4 * Copyright (C) 2013 Atmel Corporation,
5 * Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10#include <linux/module.h>
11#include <linux/dma-mapping.h>
12#include <linux/clk/at91_pmc.h>
13
14#include <asm/irq.h>
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <mach/sama5d4.h>
18#include <mach/cpu.h>
19#include <mach/hardware.h>
20
21#include "soc.h"
22#include "generic.h"
23#include "sam9_smc.h"
24
25/* --------------------------------------------------------------------
26 * Processor initialization
27 * -------------------------------------------------------------------- */
28static struct map_desc at91_io_desc[] __initdata = {
29 {
30 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_MPDDRC),
31 .pfn = __phys_to_pfn(SAMA5D4_BASE_MPDDRC),
32 .length = SZ_512,
33 .type = MT_DEVICE,
34 },
35 {
36 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_PMC),
37 .pfn = __phys_to_pfn(SAMA5D4_BASE_PMC),
38 .length = SZ_512,
39 .type = MT_DEVICE,
40 },
41 { /* On sama5d4, we use USART3 as serial console */
42 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_USART3),
43 .pfn = __phys_to_pfn(SAMA5D4_BASE_USART3),
44 .length = SZ_256,
45 .type = MT_DEVICE,
46 },
47 { /* A bunch of peripheral with fine grained IO space */
48 .virtual = (unsigned long)AT91_ALT_IO_P2V(SAMA5D4_BASE_SYS2),
49 .pfn = __phys_to_pfn(SAMA5D4_BASE_SYS2),
50 .length = SZ_2K,
51 .type = MT_DEVICE,
52 },
53};
54
55
56static void __init sama5d4_map_io(void)
57{
58 iotable_init(at91_io_desc, ARRAY_SIZE(at91_io_desc));
59 at91_init_sram(0, SAMA5D4_NS_SRAM_BASE, SAMA5D4_NS_SRAM_SIZE);
60}
61
62AT91_SOC_START(sama5d4)
63 .map_io = sama5d4_map_io,
64AT91_SOC_END
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index f7a07a58ebb6..535a6e70f4ef 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -96,6 +96,13 @@ static struct map_desc at91_io_desc __initdata __maybe_unused = {
96 .type = MT_DEVICE, 96 .type = MT_DEVICE,
97}; 97};
98 98
99static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
100 .virtual = (unsigned long)AT91_ALT_VA_BASE_SYS,
101 .pfn = __phys_to_pfn(AT91_ALT_BASE_SYS),
102 .length = 24 * SZ_1K,
103 .type = MT_DEVICE,
104};
105
99static void __init soc_detect(u32 dbgu_base) 106static void __init soc_detect(u32 dbgu_base)
100{ 107{
101 u32 cidr, socid; 108 u32 cidr, socid;
@@ -158,9 +165,12 @@ static void __init soc_detect(u32 dbgu_base)
158 at91_boot_soc = at91sam9n12_soc; 165 at91_boot_soc = at91sam9n12_soc;
159 break; 166 break;
160 167
161 case ARCH_ID_SAMA5D3: 168 case ARCH_ID_SAMA5:
162 at91_soc_initdata.type = AT91_SOC_SAMA5D3; 169 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
163 at91_boot_soc = sama5d3_soc; 170 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
171 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
172 at91_boot_soc = sama5d3_soc;
173 }
164 break; 174 break;
165 } 175 }
166 176
@@ -183,7 +193,8 @@ static void __init soc_detect(u32 dbgu_base)
183 at91_soc_initdata.cidr = cidr; 193 at91_soc_initdata.cidr = cidr;
184 194
185 /* sub version of soc */ 195 /* sub version of soc */
186 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID); 196 if (!at91_soc_initdata.exid)
197 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
187 198
188 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) { 199 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
189 switch (at91_soc_initdata.exid) { 200 switch (at91_soc_initdata.exid) {
@@ -240,6 +251,54 @@ static void __init soc_detect(u32 dbgu_base)
240 } 251 }
241} 252}
242 253
254static void __init alt_soc_detect(u32 dbgu_base)
255{
256 u32 cidr, socid;
257
258 /* SoC ID */
259 cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
260 socid = cidr & ~AT91_CIDR_VERSION;
261
262 switch (socid) {
263 case ARCH_ID_SAMA5:
264 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
265 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
266 at91_soc_initdata.type = AT91_SOC_SAMA5D3;
267 at91_boot_soc = sama5d3_soc;
268 } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
269 at91_soc_initdata.type = AT91_SOC_SAMA5D4;
270 at91_boot_soc = sama5d4_soc;
271 }
272 break;
273 }
274
275 if (!at91_soc_is_detected())
276 return;
277
278 at91_soc_initdata.cidr = cidr;
279
280 /* sub version of soc */
281 if (!at91_soc_initdata.exid)
282 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
283
284 if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
285 switch (at91_soc_initdata.exid) {
286 case ARCH_EXID_SAMA5D41:
287 at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
288 break;
289 case ARCH_EXID_SAMA5D42:
290 at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
291 break;
292 case ARCH_EXID_SAMA5D43:
293 at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
294 break;
295 case ARCH_EXID_SAMA5D44:
296 at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
297 break;
298 }
299 }
300}
301
243static const char *soc_name[] = { 302static const char *soc_name[] = {
244 [AT91_SOC_RM9200] = "at91rm9200", 303 [AT91_SOC_RM9200] = "at91rm9200",
245 [AT91_SOC_SAM9260] = "at91sam9260", 304 [AT91_SOC_SAM9260] = "at91sam9260",
@@ -252,6 +311,7 @@ static const char *soc_name[] = {
252 [AT91_SOC_SAM9X5] = "at91sam9x5", 311 [AT91_SOC_SAM9X5] = "at91sam9x5",
253 [AT91_SOC_SAM9N12] = "at91sam9n12", 312 [AT91_SOC_SAM9N12] = "at91sam9n12",
254 [AT91_SOC_SAMA5D3] = "sama5d3", 313 [AT91_SOC_SAMA5D3] = "sama5d3",
314 [AT91_SOC_SAMA5D4] = "sama5d4",
255 [AT91_SOC_UNKNOWN] = "Unknown", 315 [AT91_SOC_UNKNOWN] = "Unknown",
256}; 316};
257 317
@@ -279,6 +339,10 @@ static const char *soc_subtype_name[] = {
279 [AT91_SOC_SAMA5D34] = "sama5d34", 339 [AT91_SOC_SAMA5D34] = "sama5d34",
280 [AT91_SOC_SAMA5D35] = "sama5d35", 340 [AT91_SOC_SAMA5D35] = "sama5d35",
281 [AT91_SOC_SAMA5D36] = "sama5d36", 341 [AT91_SOC_SAMA5D36] = "sama5d36",
342 [AT91_SOC_SAMA5D41] = "sama5d41",
343 [AT91_SOC_SAMA5D42] = "sama5d42",
344 [AT91_SOC_SAMA5D43] = "sama5d43",
345 [AT91_SOC_SAMA5D44] = "sama5d44",
282 [AT91_SOC_SUBTYPE_NONE] = "None", 346 [AT91_SOC_SUBTYPE_NONE] = "None",
283 [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown", 347 [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
284}; 348};
@@ -341,6 +405,31 @@ void __init at91_ioremap_rstc(u32 base_addr)
341 panic("Impossible to ioremap at91_rstc_base\n"); 405 panic("Impossible to ioremap at91_rstc_base\n");
342} 406}
343 407
408void __init at91_alt_map_io(void)
409{
410 /* Map peripherals */
411 iotable_init(&at91_alt_io_desc, 1);
412
413 at91_soc_initdata.type = AT91_SOC_UNKNOWN;
414 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
415
416 alt_soc_detect(AT91_BASE_DBGU2);
417 if (!at91_soc_is_detected())
418 panic("AT91: Impossible to detect the SOC type");
419
420 pr_info("AT91: Detected soc type: %s\n",
421 at91_get_soc_type(&at91_soc_initdata));
422 if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
423 pr_info("AT91: Detected soc subtype: %s\n",
424 at91_get_soc_subtype(&at91_soc_initdata));
425
426 if (!at91_soc_is_enabled())
427 panic("AT91: Soc not enabled");
428
429 if (at91_boot_soc.map_io)
430 at91_boot_soc.map_io();
431}
432
344void __iomem *at91_matrix_base; 433void __iomem *at91_matrix_base;
345EXPORT_SYMBOL_GPL(at91_matrix_base); 434EXPORT_SYMBOL_GPL(at91_matrix_base);
346 435
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index a1e1482c6da8..8ecaee67f953 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -24,6 +24,7 @@ extern struct at91_init_soc at91sam9rl_soc;
24extern struct at91_init_soc at91sam9x5_soc; 24extern struct at91_init_soc at91sam9x5_soc;
25extern struct at91_init_soc at91sam9n12_soc; 25extern struct at91_init_soc at91sam9n12_soc;
26extern struct at91_init_soc sama5d3_soc; 26extern struct at91_init_soc sama5d3_soc;
27extern struct at91_init_soc sama5d4_soc;
27 28
28#define AT91_SOC_START(_name) \ 29#define AT91_SOC_START(_name) \
29struct at91_init_soc __initdata _name##_soc \ 30struct at91_init_soc __initdata _name##_soc \
@@ -74,3 +75,7 @@ static inline int at91_soc_is_enabled(void)
74#if !defined(CONFIG_SOC_SAMA5D3) 75#if !defined(CONFIG_SOC_SAMA5D3)
75#define sama5d3_soc at91_boot_soc 76#define sama5d3_soc at91_boot_soc
76#endif 77#endif
78
79#if !defined(CONFIG_SOC_SAMA5D4)
80#define sama5d4_soc at91_boot_soc
81#endif
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 4998aee59267..89a48a7bd5df 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -9,3 +9,4 @@ obj-y += clk-system.o clk-peripheral.o clk-programmable.o
9obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o 9obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
10obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o 10obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
11obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o 11obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
12obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c
new file mode 100644
index 000000000000..152dcb3f7b5f
--- /dev/null
+++ b/drivers/clk/at91/clk-h32mx.c
@@ -0,0 +1,123 @@
1/*
2 * clk-h32mx.c
3 *
4 * Copyright (C) 2014 Atmel
5 *
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/clkdev.h>
17#include <linux/clk/at91_pmc.h>
18#include <linux/delay.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22#include <linux/io.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/sched.h>
26#include <linux/wait.h>
27
28#include "pmc.h"
29
30#define H32MX_MAX_FREQ 90000000
31
32struct clk_sama5d4_h32mx {
33 struct clk_hw hw;
34 struct at91_pmc *pmc;
35};
36
37#define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw)
38
39static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
40 unsigned long parent_rate)
41{
42 struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
43
44 if (pmc_read(h32mxclk->pmc, AT91_PMC_MCKR) & AT91_PMC_H32MXDIV)
45 return parent_rate / 2;
46
47 if (parent_rate > H32MX_MAX_FREQ)
48 pr_warn("H32MX clock is too fast\n");
49 return parent_rate;
50}
51
52static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
53 unsigned long *parent_rate)
54{
55 unsigned long div;
56
57 if (rate > *parent_rate)
58 return *parent_rate;
59 div = *parent_rate / 2;
60 if (rate < div)
61 return div;
62
63 if (rate - div < *parent_rate - rate)
64 return div;
65
66 return *parent_rate;
67}
68
69static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate,
70 unsigned long parent_rate)
71{
72 struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
73 struct at91_pmc *pmc = h32mxclk->pmc;
74 u32 tmp;
75
76 if (parent_rate != rate && (parent_rate / 2) != rate)
77 return -EINVAL;
78
79 pmc_lock(pmc);
80 tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_H32MXDIV;
81 if ((parent_rate / 2) == rate)
82 tmp |= AT91_PMC_H32MXDIV;
83 pmc_write(pmc, AT91_PMC_MCKR, tmp);
84 pmc_unlock(pmc);
85
86 return 0;
87}
88
89static const struct clk_ops h32mx_ops = {
90 .recalc_rate = clk_sama5d4_h32mx_recalc_rate,
91 .round_rate = clk_sama5d4_h32mx_round_rate,
92 .set_rate = clk_sama5d4_h32mx_set_rate,
93};
94
95void __init of_sama5d4_clk_h32mx_setup(struct device_node *np,
96 struct at91_pmc *pmc)
97{
98 struct clk_sama5d4_h32mx *h32mxclk;
99 struct clk_init_data init;
100 const char *parent_name;
101 struct clk *clk;
102
103 h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
104 if (!h32mxclk)
105 return;
106
107 parent_name = of_clk_get_parent_name(np, 0);
108
109 init.name = np->name;
110 init.ops = &h32mx_ops;
111 init.parent_names = parent_name ? &parent_name : NULL;
112 init.num_parents = parent_name ? 1 : 0;
113 init.flags = CLK_SET_RATE_GATE;
114
115 h32mxclk->hw.init = &init;
116 h32mxclk->pmc = pmc;
117
118 clk = clk_register(NULL, &h32mxclk->hw);
119 if (!clk)
120 return;
121
122 of_clk_add_provider(np, of_clk_src_simple_get, clk);
123}
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 524196bb35a5..386999b4f8eb 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -337,6 +337,12 @@ static const struct of_device_id pmc_clk_ids[] __initconst = {
337 .data = of_at91sam9x5_clk_smd_setup, 337 .data = of_at91sam9x5_clk_smd_setup,
338 }, 338 },
339#endif 339#endif
340#if defined(CONFIG_HAVE_AT91_H32MX)
341 {
342 .compatible = "atmel,sama5d4-clk-h32mx",
343 .data = of_sama5d4_clk_h32mx_setup,
344 },
345#endif
340 { /*sentinel*/ } 346 { /*sentinel*/ }
341}; 347};
342 348
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 6c7625976113..52d2041fa3f6 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -120,4 +120,9 @@ extern void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
120 struct at91_pmc *pmc); 120 struct at91_pmc *pmc);
121#endif 121#endif
122 122
123#if defined(CONFIG_HAVE_AT91_SMD)
124extern void __init of_sama5d4_clk_h32mx_setup(struct device_node *np,
125 struct at91_pmc *pmc);
126#endif
127
123#endif /* __PMC_H_ */ 128#endif /* __PMC_H_ */
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index de4268d4987a..c8e3b3d1eded 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -125,6 +125,7 @@ extern void __iomem *at91_pmc_base;
125#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ 125#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
126#define AT91_PMC_PLLADIV2_OFF (0 << 12) 126#define AT91_PMC_PLLADIV2_OFF (0 << 12)
127#define AT91_PMC_PLLADIV2_ON (1 << 12) 127#define AT91_PMC_PLLADIV2_ON (1 << 12)
128#define AT91_PMC_H32MXDIV BIT(24)
128 129
129#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ 130#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
130#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ 131#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-24 08:15:12 -0400