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authorAndreas Larsson <andreas@gaisler.com>2012-11-15 02:47:14 -0500
committerMarc Kleine-Budde <mkl@pengutronix.de>2012-11-15 14:47:26 -0500
commit6cec9b07fe6a0c4dfbcdcee7c6283529f087c521 (patch)
treea7c45d677c49ee428f519bf3ed83865011c12431
parentc70edb9e8a30c7bd8eae347b9a7d83984e2b5ae3 (diff)
can: grcan: Add device driver for GRCAN and GRHCAN cores
This driver supports GRCAN and CRHCAN CAN controllers available in the GRLIB VHDL IP core library. Signed-off-by: Andreas Larsson <andreas@gaisler.com> Acked-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat
-rw-r--r--Documentation/ABI/testing/sysfs-class-net-grcan35
-rw-r--r--Documentation/devicetree/bindings/net/can/grcan.txt28
-rw-r--r--Documentation/kernel-parameters.txt18
-rw-r--r--drivers/net/can/Kconfig9
-rw-r--r--drivers/net/can/Makefile1
-rw-r--r--drivers/net/can/grcan.c1756
6 files changed, 1847 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-class-net-grcan b/Documentation/ABI/testing/sysfs-class-net-grcan
new file mode 100644
index 000000000000..f418c92ca555
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-net-grcan
@@ -0,0 +1,35 @@
1
2What: /sys/class/net/<iface>/grcan/enable0
3Date: October 2012
4KernelVersion: 3.8
5Contact: Andreas Larsson <andreas@gaisler.com>
6Description:
7 Hardware configuration of physical interface 0. This file reads
8 and writes the "Enable 0" bit of the configuration register.
9 Possible values: 0 or 1. See the GRCAN chapter of the GRLIB IP
10 core library documentation for details. The default value is 0
11 or set by the module parameter grcan.enable0 and can be read at
12 /sys/module/grcan/parameters/enable0.
13
14What: /sys/class/net/<iface>/grcan/enable1
15Date: October 2012
16KernelVersion: 3.8
17Contact: Andreas Larsson <andreas@gaisler.com>
18Description:
19 Hardware configuration of physical interface 1. This file reads
20 and writes the "Enable 1" bit of the configuration register.
21 Possible values: 0 or 1. See the GRCAN chapter of the GRLIB IP
22 core library documentation for details. The default value is 0
23 or set by the module parameter grcan.enable1 and can be read at
24 /sys/module/grcan/parameters/enable1.
25
26What: /sys/class/net/<iface>/grcan/select
27Date: October 2012
28KernelVersion: 3.8
29Contact: Andreas Larsson <andreas@gaisler.com>
30Description:
31 Configuration of which physical interface to be used. Possible
32 values: 0 or 1. See the GRCAN chapter of the GRLIB IP core
33 library documentation for details. The default value is 0 or is
34 set by the module parameter grcan.select and can be read at
35 /sys/module/grcan/parameters/select.
diff --git a/Documentation/devicetree/bindings/net/can/grcan.txt b/Documentation/devicetree/bindings/net/can/grcan.txt
new file mode 100644
index 000000000000..34ef3498f887
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/grcan.txt
@@ -0,0 +1,28 @@
1Aeroflex Gaisler GRCAN and GRHCAN CAN controllers.
2
3The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core
4library.
5
6Note: These properties are built from the AMBA plug&play in a Leon SPARC system
7(the ordinary environment for GRCAN and GRHCAN). There are no dts files for
8sparc.
9
10Required properties:
11
12- name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034"
13
14- reg : Address and length of the register set for the device
15
16- freq : Frequency of the external oscillator clock in Hz (the frequency of
17 the amba bus in the ordinary case)
18
19- interrupts : Interrupt number for this device
20
21Optional properties:
22
23- systemid : If not present or if the value of the least significant 16 bits
24 of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION
25 a bug workaround is activated.
26
27For further information look in the documentation for the GLIB IP core library:
28http://www.gaisler.com/products/grlib/grip.pdf
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 9776f068306b..3da4f9670d8b 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -905,6 +905,24 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
905 gpt [EFI] Forces disk with valid GPT signature but 905 gpt [EFI] Forces disk with valid GPT signature but
906 invalid Protective MBR to be treated as GPT. 906 invalid Protective MBR to be treated as GPT.
907 907
908 grcan.enable0= [HW] Configuration of physical interface 0. Determines
909 the "Enable 0" bit of the configuration register.
910 Format: 0 | 1
911 Default: 0
912 grcan.enable1= [HW] Configuration of physical interface 1. Determines
913 the "Enable 0" bit of the configuration register.
914 Format: 0 | 1
915 Default: 0
916 grcan.select= [HW] Select which physical interface to use.
917 Format: 0 | 1
918 Default: 0
919 grcan.txsize= [HW] Sets the size of the tx buffer.
920 Format: <unsigned int> such that (txsize & ~0x1fffc0) == 0.
921 Default: 1024
922 grcan.rxsize= [HW] Sets the size of the rx buffer.
923 Format: <unsigned int> such that (rxsize & ~0x1fffc0) == 0.
924 Default: 1024
925
908 hashdist= [KNL,NUMA] Large hashes allocated during boot 926 hashdist= [KNL,NUMA] Large hashes allocated during boot
909 are distributed across NUMA nodes. Defaults on 927 are distributed across NUMA nodes. Defaults on
910 for 64-bit NUMA, off otherwise. 928 for 64-bit NUMA, off otherwise.
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index bb709fd66993..b56bd9e80957 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -110,6 +110,15 @@ config PCH_CAN
110 is an IOH for x86 embedded processor (Intel Atom E6xx series). 110 is an IOH for x86 embedded processor (Intel Atom E6xx series).
111 This driver can access CAN bus. 111 This driver can access CAN bus.
112 112
113config CAN_GRCAN
114 tristate "Aeroflex Gaisler GRCAN and GRHCAN CAN devices"
115 depends on CAN_DEV && OF
116 ---help---
117 Say Y here if you want to use Aeroflex Gaisler GRCAN or GRHCAN.
118 Note that the driver supports little endian, even though little
119 endian syntheses of the cores would need some modifications on
120 the hardware level to work.
121
113source "drivers/net/can/mscan/Kconfig" 122source "drivers/net/can/mscan/Kconfig"
114 123
115source "drivers/net/can/sja1000/Kconfig" 124source "drivers/net/can/sja1000/Kconfig"
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 938be37b670c..7de59862bbe9 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -22,5 +22,6 @@ obj-$(CONFIG_CAN_BFIN) += bfin_can.o
22obj-$(CONFIG_CAN_JANZ_ICAN3) += janz-ican3.o 22obj-$(CONFIG_CAN_JANZ_ICAN3) += janz-ican3.o
23obj-$(CONFIG_CAN_FLEXCAN) += flexcan.o 23obj-$(CONFIG_CAN_FLEXCAN) += flexcan.o
24obj-$(CONFIG_PCH_CAN) += pch_can.o 24obj-$(CONFIG_PCH_CAN) += pch_can.o
25obj-$(CONFIG_CAN_GRCAN) += grcan.o
25 26
26ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG 27ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/grcan.c b/drivers/net/can/grcan.c
new file mode 100644
index 000000000000..391f484fccb7
--- /dev/null
+++ b/drivers/net/can/grcan.c
@@ -0,0 +1,1756 @@
1/*
2 * Socket CAN driver for Aeroflex Gaisler GRCAN and GRHCAN.
3 *
4 * 2012 (c) Aeroflex Gaisler AB
5 *
6 * This driver supports GRCAN and GRHCAN CAN controllers available in the GRLIB
7 * VHDL IP core library.
8 *
9 * Full documentation of the GRCAN core can be found here:
10 * http://www.gaisler.com/products/grlib/grip.pdf
11 *
12 * See "Documentation/devicetree/bindings/net/can/grcan.txt" for information on
13 * open firmware properties.
14 *
15 * See "Documentation/ABI/testing/sysfs-class-net-grcan" for information on the
16 * sysfs interface.
17 *
18 * See "Documentation/kernel-parameters.txt" for information on the module
19 * parameters.
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 *
26 * Contributors: Andreas Larsson <andreas@gaisler.com>
27 */
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/interrupt.h>
32#include <linux/netdevice.h>
33#include <linux/delay.h>
34#include <linux/io.h>
35#include <linux/can/dev.h>
36#include <linux/spinlock.h>
37
38#include <linux/of_platform.h>
39#include <asm/prom.h>
40
41#include <linux/of_irq.h>
42
43#include <linux/dma-mapping.h>
44
45#define DRV_NAME "grcan"
46
47#define GRCAN_NAPI_WEIGHT 32
48
49#define GRCAN_RESERVE_SIZE(slot1, slot2) (((slot2) - (slot1)) / 4 - 1)
50
51struct grcan_registers {
52 u32 conf; /* 0x00 */
53 u32 stat; /* 0x04 */
54 u32 ctrl; /* 0x08 */
55 u32 __reserved1[GRCAN_RESERVE_SIZE(0x08, 0x18)];
56 u32 smask; /* 0x18 - CanMASK */
57 u32 scode; /* 0x1c - CanCODE */
58 u32 __reserved2[GRCAN_RESERVE_SIZE(0x1c, 0x100)];
59 u32 pimsr; /* 0x100 */
60 u32 pimr; /* 0x104 */
61 u32 pisr; /* 0x108 */
62 u32 pir; /* 0x10C */
63 u32 imr; /* 0x110 */
64 u32 picr; /* 0x114 */
65 u32 __reserved3[GRCAN_RESERVE_SIZE(0x114, 0x200)];
66 u32 txctrl; /* 0x200 */
67 u32 txaddr; /* 0x204 */
68 u32 txsize; /* 0x208 */
69 u32 txwr; /* 0x20C */
70 u32 txrd; /* 0x210 */
71 u32 txirq; /* 0x214 */
72 u32 __reserved4[GRCAN_RESERVE_SIZE(0x214, 0x300)];
73 u32 rxctrl; /* 0x300 */
74 u32 rxaddr; /* 0x304 */
75 u32 rxsize; /* 0x308 */
76 u32 rxwr; /* 0x30C */
77 u32 rxrd; /* 0x310 */
78 u32 rxirq; /* 0x314 */
79 u32 rxmask; /* 0x318 */
80 u32 rxcode; /* 0x31C */
81};
82
83#define GRCAN_CONF_ABORT 0x00000001
84#define GRCAN_CONF_ENABLE0 0x00000002
85#define GRCAN_CONF_ENABLE1 0x00000004
86#define GRCAN_CONF_SELECT 0x00000008
87#define GRCAN_CONF_SILENT 0x00000010
88#define GRCAN_CONF_SAM 0x00000020 /* Available in some hardware */
89#define GRCAN_CONF_BPR 0x00000300 /* Note: not BRP */
90#define GRCAN_CONF_RSJ 0x00007000
91#define GRCAN_CONF_PS1 0x00f00000
92#define GRCAN_CONF_PS2 0x000f0000
93#define GRCAN_CONF_SCALER 0xff000000
94#define GRCAN_CONF_OPERATION \
95 (GRCAN_CONF_ABORT | GRCAN_CONF_ENABLE0 | GRCAN_CONF_ENABLE1 \
96 | GRCAN_CONF_SELECT | GRCAN_CONF_SILENT | GRCAN_CONF_SAM)
97#define GRCAN_CONF_TIMING \
98 (GRCAN_CONF_BPR | GRCAN_CONF_RSJ | GRCAN_CONF_PS1 \
99 | GRCAN_CONF_PS2 | GRCAN_CONF_SCALER)
100
101#define GRCAN_CONF_RSJ_MIN 1
102#define GRCAN_CONF_RSJ_MAX 4
103#define GRCAN_CONF_PS1_MIN 1
104#define GRCAN_CONF_PS1_MAX 15
105#define GRCAN_CONF_PS2_MIN 2
106#define GRCAN_CONF_PS2_MAX 8
107#define GRCAN_CONF_SCALER_MIN 0
108#define GRCAN_CONF_SCALER_MAX 255
109#define GRCAN_CONF_SCALER_INC 1
110
111#define GRCAN_CONF_BPR_BIT 8
112#define GRCAN_CONF_RSJ_BIT 12
113#define GRCAN_CONF_PS1_BIT 20
114#define GRCAN_CONF_PS2_BIT 16
115#define GRCAN_CONF_SCALER_BIT 24
116
117#define GRCAN_STAT_PASS 0x000001
118#define GRCAN_STAT_OFF 0x000002
119#define GRCAN_STAT_OR 0x000004
120#define GRCAN_STAT_AHBERR 0x000008
121#define GRCAN_STAT_ACTIVE 0x000010
122#define GRCAN_STAT_RXERRCNT 0x00ff00
123#define GRCAN_STAT_TXERRCNT 0xff0000
124
125#define GRCAN_STAT_ERRCTR_RELATED (GRCAN_STAT_PASS | GRCAN_STAT_OFF)
126
127#define GRCAN_STAT_RXERRCNT_BIT 8
128#define GRCAN_STAT_TXERRCNT_BIT 16
129
130#define GRCAN_STAT_ERRCNT_WARNING_LIMIT 96
131#define GRCAN_STAT_ERRCNT_PASSIVE_LIMIT 127
132
133#define GRCAN_CTRL_RESET 0x2
134#define GRCAN_CTRL_ENABLE 0x1
135
136#define GRCAN_TXCTRL_ENABLE 0x1
137#define GRCAN_TXCTRL_ONGOING 0x2
138#define GRCAN_TXCTRL_SINGLE 0x4
139
140#define GRCAN_RXCTRL_ENABLE 0x1
141#define GRCAN_RXCTRL_ONGOING 0x2
142
143/* Relative offset of IRQ sources to AMBA Plug&Play */
144#define GRCAN_IRQIX_IRQ 0
145#define GRCAN_IRQIX_TXSYNC 1
146#define GRCAN_IRQIX_RXSYNC 2
147
148#define GRCAN_IRQ_PASS 0x00001
149#define GRCAN_IRQ_OFF 0x00002
150#define GRCAN_IRQ_OR 0x00004
151#define GRCAN_IRQ_RXAHBERR 0x00008
152#define GRCAN_IRQ_TXAHBERR 0x00010
153#define GRCAN_IRQ_RXIRQ 0x00020
154#define GRCAN_IRQ_TXIRQ 0x00040
155#define GRCAN_IRQ_RXFULL 0x00080
156#define GRCAN_IRQ_TXEMPTY 0x00100
157#define GRCAN_IRQ_RX 0x00200
158#define GRCAN_IRQ_TX 0x00400
159#define GRCAN_IRQ_RXSYNC 0x00800
160#define GRCAN_IRQ_TXSYNC 0x01000
161#define GRCAN_IRQ_RXERRCTR 0x02000
162#define GRCAN_IRQ_TXERRCTR 0x04000
163#define GRCAN_IRQ_RXMISS 0x08000
164#define GRCAN_IRQ_TXLOSS 0x10000
165
166#define GRCAN_IRQ_NONE 0
167#define GRCAN_IRQ_ALL \
168 (GRCAN_IRQ_PASS | GRCAN_IRQ_OFF | GRCAN_IRQ_OR \
169 | GRCAN_IRQ_RXAHBERR | GRCAN_IRQ_TXAHBERR \
170 | GRCAN_IRQ_RXIRQ | GRCAN_IRQ_TXIRQ \
171 | GRCAN_IRQ_RXFULL | GRCAN_IRQ_TXEMPTY \
172 | GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_RXSYNC \
173 | GRCAN_IRQ_TXSYNC | GRCAN_IRQ_RXERRCTR \
174 | GRCAN_IRQ_TXERRCTR | GRCAN_IRQ_RXMISS \
175 | GRCAN_IRQ_TXLOSS)
176
177#define GRCAN_IRQ_ERRCTR_RELATED (GRCAN_IRQ_RXERRCTR | GRCAN_IRQ_TXERRCTR \
178 | GRCAN_IRQ_PASS | GRCAN_IRQ_OFF)
179#define GRCAN_IRQ_ERRORS (GRCAN_IRQ_ERRCTR_RELATED | GRCAN_IRQ_OR \
180 | GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR \
181 | GRCAN_IRQ_TXLOSS)
182#define GRCAN_IRQ_DEFAULT (GRCAN_IRQ_RX | GRCAN_IRQ_TX | GRCAN_IRQ_ERRORS)
183
184#define GRCAN_MSG_SIZE 16
185
186#define GRCAN_MSG_IDE 0x80000000
187#define GRCAN_MSG_RTR 0x40000000
188#define GRCAN_MSG_BID 0x1ffc0000
189#define GRCAN_MSG_EID 0x1fffffff
190#define GRCAN_MSG_IDE_BIT 31
191#define GRCAN_MSG_RTR_BIT 30
192#define GRCAN_MSG_BID_BIT 18
193#define GRCAN_MSG_EID_BIT 0
194
195#define GRCAN_MSG_DLC 0xf0000000
196#define GRCAN_MSG_TXERRC 0x00ff0000
197#define GRCAN_MSG_RXERRC 0x0000ff00
198#define GRCAN_MSG_DLC_BIT 28
199#define GRCAN_MSG_TXERRC_BIT 16
200#define GRCAN_MSG_RXERRC_BIT 8
201#define GRCAN_MSG_AHBERR 0x00000008
202#define GRCAN_MSG_OR 0x00000004
203#define GRCAN_MSG_OFF 0x00000002
204#define GRCAN_MSG_PASS 0x00000001
205
206#define GRCAN_MSG_DATA_SLOT_INDEX(i) (2 + (i) / 4)
207#define GRCAN_MSG_DATA_SHIFT(i) ((3 - (i) % 4) * 8)
208
209#define GRCAN_BUFFER_ALIGNMENT 1024
210#define GRCAN_DEFAULT_BUFFER_SIZE 1024
211#define GRCAN_VALID_TR_SIZE_MASK 0x001fffc0
212
213#define GRCAN_INVALID_BUFFER_SIZE(s) \
214 ((s) == 0 || ((s) & ~GRCAN_VALID_TR_SIZE_MASK))
215
216#if GRCAN_INVALID_BUFFER_SIZE(GRCAN_DEFAULT_BUFFER_SIZE)
217#error "Invalid default buffer size"
218#endif
219
220struct grcan_dma_buffer {
221 size_t size;
222 void *buf;
223 dma_addr_t handle;
224};
225
226struct grcan_dma {
227 size_t base_size;
228 void *base_buf;
229 dma_addr_t base_handle;
230 struct grcan_dma_buffer tx;
231 struct grcan_dma_buffer rx;
232};
233
234/* GRCAN configuration parameters */
235struct grcan_device_config {
236 unsigned short enable0;
237 unsigned short enable1;
238 unsigned short select;
239 unsigned int txsize;
240 unsigned int rxsize;
241};
242
243#define GRCAN_DEFAULT_DEVICE_CONFIG { \
244 .enable0 = 0, \
245 .enable1 = 0, \
246 .select = 0, \
247 .txsize = GRCAN_DEFAULT_BUFFER_SIZE, \
248 .rxsize = GRCAN_DEFAULT_BUFFER_SIZE, \
249 }
250
251#define GRCAN_TXBUG_SAFE_GRLIB_VERSION 0x4100
252#define GRLIB_VERSION_MASK 0xffff
253
254/* GRCAN private data structure */
255struct grcan_priv {
256 struct can_priv can; /* must be the first member */
257 struct net_device *dev;
258 struct napi_struct napi;
259
260 struct grcan_registers __iomem *regs; /* ioremap'ed registers */
261 struct grcan_device_config config;
262 struct grcan_dma dma;
263
264 struct sk_buff **echo_skb; /* We allocate this on our own */
265 u8 *txdlc; /* Length of queued frames */
266
267 /* The echo skb pointer, pointing into echo_skb and indicating which
268 * frames can be echoed back. See the "Notes on the tx cyclic buffer
269 * handling"-comment for grcan_start_xmit for more details.
270 */
271 u32 eskbp;
272
273 /* Lock for controlling changes to the netif tx queue state, accesses to
274 * the echo_skb pointer eskbp and for making sure that a running reset
275 * and/or a close of the interface is done without interference from
276 * other parts of the code.
277 *
278 * The echo_skb pointer, eskbp, should only be accessed under this lock
279 * as it can be changed in several places and together with decisions on
280 * whether to wake up the tx queue.
281 *
282 * The tx queue must never be woken up if there is a running reset or
283 * close in progress.
284 *
285 * A running reset (see below on need_txbug_workaround) should never be
286 * done if the interface is closing down and several running resets
287 * should never be scheduled simultaneously.
288 */
289 spinlock_t lock;
290
291 /* Whether a workaround is needed due to a bug in older hardware. In
292 * this case, the driver both tries to prevent the bug from being
293 * triggered and recovers, if the bug nevertheless happens, by doing a
294 * running reset. A running reset, resets the device and continues from
295 * where it were without being noticeable from outside the driver (apart
296 * from slight delays).
297 */
298 bool need_txbug_workaround;
299
300 /* To trigger initization of running reset and to trigger running reset
301 * respectively in the case of a hanged device due to a txbug.
302 */
303 struct timer_list hang_timer;
304 struct timer_list rr_timer;
305
306 /* To avoid waking up the netif queue and restarting timers
307 * when a reset is scheduled or when closing of the device is
308 * undergoing
309 */
310 bool resetting;
311 bool closing;
312};
313
314/* Wait time for a short wait for ongoing to clear */
315#define GRCAN_SHORTWAIT_USECS 10
316
317/* Limit on the number of transmitted bits of an eff frame according to the CAN
318 * specification: 1 bit start of frame, 32 bits arbitration field, 6 bits
319 * control field, 8 bytes data field, 16 bits crc field, 2 bits ACK field and 7
320 * bits end of frame
321 */
322#define GRCAN_EFF_FRAME_MAX_BITS (1+32+6+8*8+16+2+7)
323
324#if defined(__BIG_ENDIAN)
325static inline u32 grcan_read_reg(u32 __iomem *reg)
326{
327 return ioread32be(reg);
328}
329
330static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
331{
332 iowrite32be(val, reg);
333}
334#else
335static inline u32 grcan_read_reg(u32 __iomem *reg)
336{
337 return ioread32(reg);
338}
339
340static inline void grcan_write_reg(u32 __iomem *reg, u32 val)
341{
342 iowrite32(val, reg);
343}
344#endif
345
346static inline void grcan_clear_bits(u32 __iomem *reg, u32 mask)
347{
348 grcan_write_reg(reg, grcan_read_reg(reg) & ~mask);
349}
350
351static inline void grcan_set_bits(u32 __iomem *reg, u32 mask)
352{
353 grcan_write_reg(reg, grcan_read_reg(reg) | mask);
354}
355
356static inline u32 grcan_read_bits(u32 __iomem *reg, u32 mask)
357{
358 return grcan_read_reg(reg) & mask;
359}
360
361static inline void grcan_write_bits(u32 __iomem *reg, u32 value, u32 mask)
362{
363 u32 old = grcan_read_reg(reg);
364
365 grcan_write_reg(reg, (old & ~mask) | (value & mask));
366}
367
368/* a and b should both be in [0,size] and a == b == size should not hold */
369static inline u32 grcan_ring_add(u32 a, u32 b, u32 size)
370{
371 u32 sum = a + b;
372
373 if (sum < size)
374 return sum;
375 else
376 return sum - size;
377}
378
379/* a and b should both be in [0,size) */
380static inline u32 grcan_ring_sub(u32 a, u32 b, u32 size)
381{
382 return grcan_ring_add(a, size - b, size);
383}
384
385/* Available slots for new transmissions */
386static inline u32 grcan_txspace(size_t txsize, u32 txwr, u32 eskbp)
387{
388 u32 slots = txsize / GRCAN_MSG_SIZE - 1;
389 u32 used = grcan_ring_sub(txwr, eskbp, txsize) / GRCAN_MSG_SIZE;
390
391 return slots - used;
392}
393
394/* Configuration parameters that can be set via module parameters */
395static struct grcan_device_config grcan_module_config =
396 GRCAN_DEFAULT_DEVICE_CONFIG;
397
398static const struct can_bittiming_const grcan_bittiming_const = {
399 .name = DRV_NAME,
400 .tseg1_min = GRCAN_CONF_PS1_MIN + 1,
401 .tseg1_max = GRCAN_CONF_PS1_MAX + 1,
402 .tseg2_min = GRCAN_CONF_PS2_MIN,
403 .tseg2_max = GRCAN_CONF_PS2_MAX,
404 .sjw_max = GRCAN_CONF_RSJ_MAX,
405 .brp_min = GRCAN_CONF_SCALER_MIN + 1,
406 .brp_max = GRCAN_CONF_SCALER_MAX + 1,
407 .brp_inc = GRCAN_CONF_SCALER_INC,
408};
409
410static int grcan_set_bittiming(struct net_device *dev)
411{
412 struct grcan_priv *priv = netdev_priv(dev);
413 struct grcan_registers __iomem *regs = priv->regs;
414 struct can_bittiming *bt = &priv->can.bittiming;
415 u32 timing = 0;
416 int bpr, rsj, ps1, ps2, scaler;
417
418 /* Should never happen - function will not be called when
419 * device is up
420 */
421 if (grcan_read_bits(&regs->ctrl, GRCAN_CTRL_ENABLE))
422 return -EBUSY;
423
424 bpr = 0; /* Note bpr and brp are different concepts */
425 rsj = bt->sjw;
426 ps1 = (bt->prop_seg + bt->phase_seg1) - 1; /* tseg1 - 1 */
427 ps2 = bt->phase_seg2;
428 scaler = (bt->brp - 1);
429 netdev_dbg(dev, "Request for BPR=%d, RSJ=%d, PS1=%d, PS2=%d, SCALER=%d",
430 bpr, rsj, ps1, ps2, scaler);
431 if (!(ps1 > ps2)) {
432 netdev_err(dev, "PS1 > PS2 must hold: PS1=%d, PS2=%d\n",
433 ps1, ps2);
434 return -EINVAL;
435 }
436 if (!(ps2 >= rsj)) {
437 netdev_err(dev, "PS2 >= RSJ must hold: PS2=%d, RSJ=%d\n",
438 ps2, rsj);
439 return -EINVAL;
440 }
441
442 timing |= (bpr << GRCAN_CONF_BPR_BIT) & GRCAN_CONF_BPR;
443 timing |= (rsj << GRCAN_CONF_RSJ_BIT) & GRCAN_CONF_RSJ;
444 timing |= (ps1 << GRCAN_CONF_PS1_BIT) & GRCAN_CONF_PS1;
445 timing |= (ps2 << GRCAN_CONF_PS2_BIT) & GRCAN_CONF_PS2;
446 timing |= (scaler << GRCAN_CONF_SCALER_BIT) & GRCAN_CONF_SCALER;
447 netdev_info(dev, "setting timing=0x%x\n", timing);
448 grcan_write_bits(&regs->conf, timing, GRCAN_CONF_TIMING);
449
450 return 0;
451}
452
453static int grcan_get_berr_counter(const struct net_device *dev,
454 struct can_berr_counter *bec)
455{
456 struct grcan_priv *priv = netdev_priv(dev);
457 struct grcan_registers __iomem *regs = priv->regs;
458 u32 status = grcan_read_reg(&regs->stat);
459
460 bec->txerr = (status & GRCAN_STAT_TXERRCNT) >> GRCAN_STAT_TXERRCNT_BIT;
461 bec->rxerr = (status & GRCAN_STAT_RXERRCNT) >> GRCAN_STAT_RXERRCNT_BIT;
462 return 0;
463}
464
465static int grcan_poll(struct napi_struct *napi, int budget);
466
467/* Reset device, but keep configuration information */
468static void grcan_reset(struct net_device *dev)
469{
470 struct grcan_priv *priv = netdev_priv(dev);
471 struct grcan_registers __iomem *regs = priv->regs;
472 u32 config = grcan_read_reg(&regs->conf);
473
474 grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
475 grcan_write_reg(&regs->conf, config);
476
477 priv->eskbp = grcan_read_reg(&regs->txrd);
478 priv->can.state = CAN_STATE_STOPPED;
479
480 /* Turn off hardware filtering - regs->rxcode set to 0 by reset */
481 grcan_write_reg(&regs->rxmask, 0);
482}
483
484/* stop device without changing any configurations */
485static void grcan_stop_hardware(struct net_device *dev)
486{
487 struct grcan_priv *priv = netdev_priv(dev);
488 struct grcan_registers __iomem *regs = priv->regs;
489
490 grcan_write_reg(&regs->imr, GRCAN_IRQ_NONE);
491 grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
492 grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
493 grcan_clear_bits(&regs->ctrl, GRCAN_CTRL_ENABLE);
494}
495
496/* Let priv->eskbp catch up to regs->txrd and echo back the skbs if echo
497 * is true and free them otherwise.
498 *
499 * If budget is >= 0, stop after handling at most budget skbs. Otherwise,
500 * continue until priv->eskbp catches up to regs->txrd.
501 *
502 * priv->lock *must* be held when calling this function
503 */
504static int catch_up_echo_skb(struct net_device *dev, int budget, bool echo)
505{
506 struct grcan_priv *priv = netdev_priv(dev);
507 struct grcan_registers __iomem *regs = priv->regs;
508 struct grcan_dma *dma = &priv->dma;
509 struct net_device_stats *stats = &dev->stats;
510 int i, work_done;
511
512 /* Updates to priv->eskbp and wake-ups of the queue needs to
513 * be atomic towards the reads of priv->eskbp and shut-downs
514 * of the queue in grcan_start_xmit.
515 */
516 u32 txrd = grcan_read_reg(&regs->txrd);
517
518 for (work_done = 0; work_done < budget || budget < 0; work_done++) {
519 if (priv->eskbp == txrd)
520 break;
521 i = priv->eskbp / GRCAN_MSG_SIZE;
522 if (echo) {
523 /* Normal echo of messages */
524 stats->tx_packets++;
525 stats->tx_bytes += priv->txdlc[i];
526 priv->txdlc[i] = 0;
527 can_get_echo_skb(dev, i);
528 } else {
529 /* For cleanup of untransmitted messages */
530 can_free_echo_skb(dev, i);
531 }
532
533 priv->eskbp = grcan_ring_add(priv->eskbp, GRCAN_MSG_SIZE,
534 dma->tx.size);
535 txrd = grcan_read_reg(&regs->txrd);
536 }
537 return work_done;
538}
539
540static void grcan_lost_one_shot_frame(struct net_device *dev)
541{
542 struct grcan_priv *priv = netdev_priv(dev);
543 struct grcan_registers __iomem *regs = priv->regs;
544 struct grcan_dma *dma = &priv->dma;
545 u32 txrd;
546 unsigned long flags;
547
548 spin_lock_irqsave(&priv->lock, flags);
549
550 catch_up_echo_skb(dev, -1, true);
551
552 if (unlikely(grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE))) {
553 /* Should never happen */
554 netdev_err(dev, "TXCTRL enabled at TXLOSS in one shot mode\n");
555 } else {
556 /* By the time an GRCAN_IRQ_TXLOSS is generated in
557 * one-shot mode there is no problem in writing
558 * to TXRD even in versions of the hardware in
559 * which GRCAN_TXCTRL_ONGOING is not cleared properly
560 * in one-shot mode.
561 */
562
563 /* Skip message and discard echo-skb */
564 txrd = grcan_read_reg(&regs->txrd);
565 txrd = grcan_ring_add(txrd, GRCAN_MSG_SIZE, dma->tx.size);
566 grcan_write_reg(&regs->txrd, txrd);
567 catch_up_echo_skb(dev, -1, false);
568
569 if (!priv->resetting && !priv->closing &&
570 !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)) {
571 netif_wake_queue(dev);
572 grcan_set_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
573 }
574 }
575
576 spin_unlock_irqrestore(&priv->lock, flags);
577}
578
579static void grcan_err(struct net_device *dev, u32 sources, u32 status)
580{
581 struct grcan_priv *priv = netdev_priv(dev);
582 struct grcan_registers __iomem *regs = priv->regs;
583 struct grcan_dma *dma = &priv->dma;
584 struct net_device_stats *stats = &dev->stats;
585 struct can_frame cf;
586
587 /* Zero potential error_frame */
588 memset(&cf, 0, sizeof(cf));
589
590 /* Message lost interrupt. This might be due to arbitration error, but
591 * is also triggered when there is no one else on the can bus or when
592 * there is a problem with the hardware interface or the bus itself. As
593 * arbitration errors can not be singled out, no error frames are
594 * generated reporting this event as an arbitration error.
595 */
596 if (sources & GRCAN_IRQ_TXLOSS) {
597 /* Take care of failed one-shot transmit */
598 if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
599 grcan_lost_one_shot_frame(dev);
600
601 /* Stop printing as soon as error passive or bus off is in
602 * effect to limit the amount of txloss debug printouts.
603 */
604 if (!(status & GRCAN_STAT_ERRCTR_RELATED)) {
605 netdev_dbg(dev, "tx message lost\n");
606 stats->tx_errors++;
607 }
608 }
609
610 /* Conditions dealing with the error counters. There is no interrupt for
611 * error warning, but there are interrupts for increases of the error
612 * counters.
613 */
614 if ((sources & GRCAN_IRQ_ERRCTR_RELATED) ||
615 (status & GRCAN_STAT_ERRCTR_RELATED)) {
616 enum can_state state = priv->can.state;
617 enum can_state oldstate = state;
618 u32 txerr = (status & GRCAN_STAT_TXERRCNT)
619 >> GRCAN_STAT_TXERRCNT_BIT;
620 u32 rxerr = (status & GRCAN_STAT_RXERRCNT)
621 >> GRCAN_STAT_RXERRCNT_BIT;
622
623 /* Figure out current state */
624 if (status & GRCAN_STAT_OFF) {
625 state = CAN_STATE_BUS_OFF;
626 } else if (status & GRCAN_STAT_PASS) {
627 state = CAN_STATE_ERROR_PASSIVE;
628 } else if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT ||
629 rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT) {
630 state = CAN_STATE_ERROR_WARNING;
631 } else {
632 state = CAN_STATE_ERROR_ACTIVE;
633 }
634
635 /* Handle and report state changes */
636 if (state != oldstate) {
637 switch (state) {
638 case CAN_STATE_BUS_OFF:
639 netdev_dbg(dev, "bus-off\n");
640 netif_carrier_off(dev);
641 priv->can.can_stats.bus_off++;
642
643 /* Prevent the hardware from recovering from bus
644 * off on its own if restart is disabled.
645 */
646 if (!priv->can.restart_ms)
647 grcan_stop_hardware(dev);
648
649 cf.can_id |= CAN_ERR_BUSOFF;
650 break;
651
652 case CAN_STATE_ERROR_PASSIVE:
653 netdev_dbg(dev, "Error passive condition\n");
654 priv->can.can_stats.error_passive++;
655
656 cf.can_id |= CAN_ERR_CRTL;
657 if (txerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
658 cf.data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
659 if (rxerr >= GRCAN_STAT_ERRCNT_PASSIVE_LIMIT)
660 cf.data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
661 break;
662
663 case CAN_STATE_ERROR_WARNING:
664 netdev_dbg(dev, "Error warning condition\n");
665 priv->can.can_stats.error_warning++;
666
667 cf.can_id |= CAN_ERR_CRTL;
668 if (txerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
669 cf.data[1] |= CAN_ERR_CRTL_TX_WARNING;
670 if (rxerr >= GRCAN_STAT_ERRCNT_WARNING_LIMIT)
671 cf.data[1] |= CAN_ERR_CRTL_RX_WARNING;
672 break;
673
674 case CAN_STATE_ERROR_ACTIVE:
675 netdev_dbg(dev, "Error active condition\n");
676 cf.can_id |= CAN_ERR_CRTL;
677 break;
678
679 default:
680 /* There are no others at this point */
681 break;
682 }
683 cf.data[6] = txerr;
684 cf.data[7] = rxerr;
685 priv->can.state = state;
686 }
687
688 /* Report automatic restarts */
689 if (priv->can.restart_ms && oldstate == CAN_STATE_BUS_OFF) {
690 unsigned long flags;
691
692 cf.can_id |= CAN_ERR_RESTARTED;
693 netdev_dbg(dev, "restarted\n");
694 priv->can.can_stats.restarts++;
695 netif_carrier_on(dev);
696
697 spin_lock_irqsave(&priv->lock, flags);
698
699 if (!priv->resetting && !priv->closing) {
700 u32 txwr = grcan_read_reg(&regs->txwr);
701
702 if (grcan_txspace(dma->tx.size, txwr,
703 priv->eskbp))
704 netif_wake_queue(dev);
705 }
706
707 spin_unlock_irqrestore(&priv->lock, flags);
708 }
709 }
710
711 /* Data overrun interrupt */
712 if ((sources & GRCAN_IRQ_OR) || (status & GRCAN_STAT_OR)) {
713 netdev_dbg(dev, "got data overrun interrupt\n");
714 stats->rx_over_errors++;
715 stats->rx_errors++;
716
717 cf.can_id |= CAN_ERR_CRTL;
718 cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
719 }
720
721 /* AHB bus error interrupts (not CAN bus errors) - shut down the
722 * device.
723 */
724 if (sources & (GRCAN_IRQ_TXAHBERR | GRCAN_IRQ_RXAHBERR) ||
725 (status & GRCAN_STAT_AHBERR)) {
726 char *txrx = "";
727 unsigned long flags;
728
729 if (sources & GRCAN_IRQ_TXAHBERR) {
730 txrx = "on tx ";
731 stats->tx_errors++;
732 } else if (sources & GRCAN_IRQ_RXAHBERR) {
733 txrx = "on rx ";
734 stats->rx_errors++;
735 }
736 netdev_err(dev, "Fatal AHB buss error %s- halting device\n",
737 txrx);
738
739 spin_lock_irqsave(&priv->lock, flags);
740
741 /* Prevent anything to be enabled again and halt device */
742 priv->closing = true;
743 netif_stop_queue(dev);
744 grcan_stop_hardware(dev);
745 priv->can.state = CAN_STATE_STOPPED;
746
747 spin_unlock_irqrestore(&priv->lock, flags);
748 }
749
750 /* Pass on error frame if something to report,
751 * i.e. id contains some information
752 */
753 if (cf.can_id) {
754 struct can_frame *skb_cf;
755 struct sk_buff *skb = alloc_can_err_skb(dev, &skb_cf);
756
757 if (skb == NULL) {
758 netdev_dbg(dev, "could not allocate error frame\n");
759 return;
760 }
761 skb_cf->can_id |= cf.can_id;
762 memcpy(skb_cf->data, cf.data, sizeof(cf.data));
763
764 netif_rx(skb);
765 }
766}
767
768static irqreturn_t grcan_interrupt(int irq, void *dev_id)
769{
770 struct net_device *dev = dev_id;
771 struct grcan_priv *priv = netdev_priv(dev);
772 struct grcan_registers __iomem *regs = priv->regs;
773 u32 sources, status;
774
775 /* Find out the source */
776 sources = grcan_read_reg(&regs->pimsr);
777 if (!sources)
778 return IRQ_NONE;
779 grcan_write_reg(&regs->picr, sources);
780 status = grcan_read_reg(&regs->stat);
781
782 /* If we got TX progress, the device has not hanged,
783 * so disable the hang timer
784 */
785 if (priv->need_txbug_workaround &&
786 (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_TXLOSS))) {
787 del_timer(&priv->hang_timer);
788 }
789
790 /* Frame(s) received or transmitted */
791 if (sources & (GRCAN_IRQ_TX | GRCAN_IRQ_RX)) {
792 /* Disable tx/rx interrupts and schedule poll(). No need for
793 * locking as interference from a running reset at worst leads
794 * to an extra interrupt.
795 */
796 grcan_clear_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
797 napi_schedule(&priv->napi);
798 }
799
800 /* (Potential) error conditions to take care of */
801 if (sources & GRCAN_IRQ_ERRORS)
802 grcan_err(dev, sources, status);
803
804 return IRQ_HANDLED;
805}
806
807/* Reset device and restart operations from where they were.
808 *
809 * This assumes that RXCTRL & RXCTRL is properly disabled and that RX
810 * is not ONGOING (TX might be stuck in ONGOING due to a harwrware bug
811 * for single shot)
812 */
813static void grcan_running_reset(unsigned long data)
814{
815 struct net_device *dev = (struct net_device *)data;
816 struct grcan_priv *priv = netdev_priv(dev);
817 struct grcan_registers __iomem *regs = priv->regs;
818 unsigned long flags;
819
820 /* This temporarily messes with eskbp, so we need to lock
821 * priv->lock
822 */
823 spin_lock_irqsave(&priv->lock, flags);
824
825 priv->resetting = false;
826 del_timer(&priv->hang_timer);
827 del_timer(&priv->rr_timer);
828
829 if (!priv->closing) {
830 /* Save and reset - config register preserved by grcan_reset */
831 u32 imr = grcan_read_reg(&regs->imr);
832
833 u32 txaddr = grcan_read_reg(&regs->txaddr);
834 u32 txsize = grcan_read_reg(&regs->txsize);
835 u32 txwr = grcan_read_reg(&regs->txwr);
836 u32 txrd = grcan_read_reg(&regs->txrd);
837 u32 eskbp = priv->eskbp;
838
839 u32 rxaddr = grcan_read_reg(&regs->rxaddr);
840 u32 rxsize = grcan_read_reg(&regs->rxsize);
841 u32 rxwr = grcan_read_reg(&regs->rxwr);
842 u32 rxrd = grcan_read_reg(&regs->rxrd);
843
844 grcan_reset(dev);
845
846 /* Restore */
847 grcan_write_reg(&regs->txaddr, txaddr);
848 grcan_write_reg(&regs->txsize, txsize);
849 grcan_write_reg(&regs->txwr, txwr);
850 grcan_write_reg(&regs->txrd, txrd);
851 priv->eskbp = eskbp;
852
853 grcan_write_reg(&regs->rxaddr, rxaddr);
854 grcan_write_reg(&regs->rxsize, rxsize);
855 grcan_write_reg(&regs->rxwr, rxwr);
856 grcan_write_reg(&regs->rxrd, rxrd);
857
858 /* Turn on device again */
859 grcan_write_reg(&regs->imr, imr);
860 priv->can.state = CAN_STATE_ERROR_ACTIVE;
861 grcan_write_reg(&regs->txctrl, GRCAN_TXCTRL_ENABLE
862 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
863 ? GRCAN_TXCTRL_SINGLE : 0));
864 grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
865 grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
866
867 /* Start queue if there is size and listen-onle mode is not
868 * enabled
869 */
870 if (grcan_txspace(priv->dma.tx.size, txwr, priv->eskbp) &&
871 !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
872 netif_wake_queue(dev);
873 }
874
875 spin_unlock_irqrestore(&priv->lock, flags);
876
877 netdev_err(dev, "Device reset and restored\n");
878}
879
880/* Waiting time in usecs corresponding to the transmission of three maximum
881 * sized can frames in the given bitrate (in bits/sec). Waiting for this amount
882 * of time makes sure that the can controller have time to finish sending or
883 * receiving a frame with a good margin.
884 *
885 * usecs/sec * number of frames * bits/frame / bits/sec
886 */
887static inline u32 grcan_ongoing_wait_usecs(__u32 bitrate)
888{
889 return 1000000 * 3 * GRCAN_EFF_FRAME_MAX_BITS / bitrate;
890}
891
892/* Set timer so that it will not fire until after a period in which the can
893 * controller have a good margin to finish transmitting a frame unless it has
894 * hanged
895 */
896static inline void grcan_reset_timer(struct timer_list *timer, __u32 bitrate)
897{
898 u32 wait_jiffies = usecs_to_jiffies(grcan_ongoing_wait_usecs(bitrate));
899
900 mod_timer(timer, jiffies + wait_jiffies);
901}
902
903/* Disable channels and schedule a running reset */
904static void grcan_initiate_running_reset(unsigned long data)
905{
906 struct net_device *dev = (struct net_device *)data;
907 struct grcan_priv *priv = netdev_priv(dev);
908 struct grcan_registers __iomem *regs = priv->regs;
909 unsigned long flags;
910
911 netdev_err(dev, "Device seems hanged - reset scheduled\n");
912
913 spin_lock_irqsave(&priv->lock, flags);
914
915 /* The main body of this function must never be executed again
916 * until after an execution of grcan_running_reset
917 */
918 if (!priv->resetting && !priv->closing) {
919 priv->resetting = true;
920 netif_stop_queue(dev);
921 grcan_clear_bits(&regs->txctrl, GRCAN_TXCTRL_ENABLE);
922 grcan_clear_bits(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
923 grcan_reset_timer(&priv->rr_timer, priv->can.bittiming.bitrate);
924 }
925
926 spin_unlock_irqrestore(&priv->lock, flags);
927}
928
929static void grcan_free_dma_buffers(struct net_device *dev)
930{
931 struct grcan_priv *priv = netdev_priv(dev);
932 struct grcan_dma *dma = &priv->dma;
933
934 dma_free_coherent(&dev->dev, dma->base_size, dma->base_buf,
935 dma->base_handle);
936 memset(dma, 0, sizeof(*dma));
937}
938
939static int grcan_allocate_dma_buffers(struct net_device *dev,
940 size_t tsize, size_t rsize)
941{
942 struct grcan_priv *priv = netdev_priv(dev);
943 struct grcan_dma *dma = &priv->dma;
944 struct grcan_dma_buffer *large = rsize > tsize ? &dma->rx : &dma->tx;
945 struct grcan_dma_buffer *small = rsize > tsize ? &dma->tx : &dma->rx;
946 size_t shift;
947
948 /* Need a whole number of GRCAN_BUFFER_ALIGNMENT for the large,
949 * i.e. first buffer
950 */
951 size_t maxs = max(tsize, rsize);
952 size_t lsize = ALIGN(maxs, GRCAN_BUFFER_ALIGNMENT);
953
954 /* Put the small buffer after that */
955 size_t ssize = min(tsize, rsize);
956
957 /* Extra GRCAN_BUFFER_ALIGNMENT to allow for alignment */
958 dma->base_size = lsize + ssize + GRCAN_BUFFER_ALIGNMENT;
959 dma->base_buf = dma_alloc_coherent(&dev->dev,
960 dma->base_size,
961 &dma->base_handle,
962 GFP_KERNEL);
963
964 if (!dma->base_buf)
965 return -ENOMEM;
966
967 dma->tx.size = tsize;
968 dma->rx.size = rsize;
969
970 large->handle = ALIGN(dma->base_handle, GRCAN_BUFFER_ALIGNMENT);
971 small->handle = large->handle + lsize;
972 shift = large->handle - dma->base_handle;
973
974 large->buf = dma->base_buf + shift;
975 small->buf = large->buf + lsize;
976
977 return 0;
978}
979
980/* priv->lock *must* be held when calling this function */
981static int grcan_start(struct net_device *dev)
982{
983 struct grcan_priv *priv = netdev_priv(dev);
984 struct grcan_registers __iomem *regs = priv->regs;
985 u32 confop, txctrl;
986
987 grcan_reset(dev);
988
989 grcan_write_reg(&regs->txaddr, priv->dma.tx.handle);
990 grcan_write_reg(&regs->txsize, priv->dma.tx.size);
991 /* regs->txwr, regs->txrd and priv->eskbp already set to 0 by reset */
992
993 grcan_write_reg(&regs->rxaddr, priv->dma.rx.handle);
994 grcan_write_reg(&regs->rxsize, priv->dma.rx.size);
995 /* regs->rxwr and regs->rxrd already set to 0 by reset */
996
997 /* Enable interrupts */
998 grcan_read_reg(&regs->pir);
999 grcan_write_reg(&regs->imr, GRCAN_IRQ_DEFAULT);
1000
1001 /* Enable interfaces, channels and device */
1002 confop = GRCAN_CONF_ABORT
1003 | (priv->config.enable0 ? GRCAN_CONF_ENABLE0 : 0)
1004 | (priv->config.enable1 ? GRCAN_CONF_ENABLE1 : 0)
1005 | (priv->config.select ? GRCAN_CONF_SELECT : 0)
1006 | (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY ?
1007 GRCAN_CONF_SILENT : 0)
1008 | (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
1009 GRCAN_CONF_SAM : 0);
1010 grcan_write_bits(&regs->conf, confop, GRCAN_CONF_OPERATION);
1011 txctrl = GRCAN_TXCTRL_ENABLE
1012 | (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT
1013 ? GRCAN_TXCTRL_SINGLE : 0);
1014 grcan_write_reg(&regs->txctrl, txctrl);
1015 grcan_write_reg(&regs->rxctrl, GRCAN_RXCTRL_ENABLE);
1016 grcan_write_reg(&regs->ctrl, GRCAN_CTRL_ENABLE);
1017
1018 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1019
1020 return 0;
1021}
1022
1023static int grcan_set_mode(struct net_device *dev, enum can_mode mode)
1024{
1025 struct grcan_priv *priv = netdev_priv(dev);
1026 unsigned long flags;
1027 int err = 0;
1028
1029 if (mode == CAN_MODE_START) {
1030 /* This might be called to restart the device to recover from
1031 * bus off errors
1032 */
1033 spin_lock_irqsave(&priv->lock, flags);
1034 if (priv->closing || priv->resetting) {
1035 err = -EBUSY;
1036 } else {
1037 netdev_info(dev, "Restarting device\n");
1038 grcan_start(dev);
1039 if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1040 netif_wake_queue(dev);
1041 }
1042 spin_unlock_irqrestore(&priv->lock, flags);
1043 return err;
1044 }
1045 return -EOPNOTSUPP;
1046}
1047
1048static int grcan_open(struct net_device *dev)
1049{
1050 struct grcan_priv *priv = netdev_priv(dev);
1051 struct grcan_dma *dma = &priv->dma;
1052 unsigned long flags;
1053 int err;
1054
1055 /* Allocate memory */
1056 err = grcan_allocate_dma_buffers(dev, priv->config.txsize,
1057 priv->config.rxsize);
1058 if (err) {
1059 netdev_err(dev, "could not allocate DMA buffers\n");
1060 return err;
1061 }
1062
1063 priv->echo_skb = kzalloc(dma->tx.size * sizeof(*priv->echo_skb),
1064 GFP_KERNEL);
1065 if (!priv->echo_skb) {
1066 err = -ENOMEM;
1067 goto exit_free_dma_buffers;
1068 }
1069 priv->can.echo_skb_max = dma->tx.size;
1070 priv->can.echo_skb = priv->echo_skb;
1071
1072 priv->txdlc = kzalloc(dma->tx.size * sizeof(*priv->txdlc), GFP_KERNEL);
1073 if (!priv->txdlc) {
1074 err = -ENOMEM;
1075 goto exit_free_echo_skb;
1076 }
1077
1078 /* Get can device up */
1079 err = open_candev(dev);
1080 if (err)
1081 goto exit_free_txdlc;
1082
1083 err = request_irq(dev->irq, grcan_interrupt, IRQF_SHARED,
1084 dev->name, dev);
1085 if (err)
1086 goto exit_close_candev;
1087
1088 spin_lock_irqsave(&priv->lock, flags);
1089
1090 napi_enable(&priv->napi);
1091 grcan_start(dev);
1092 if (!(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1093 netif_start_queue(dev);
1094 priv->resetting = false;
1095 priv->closing = false;
1096
1097 spin_unlock_irqrestore(&priv->lock, flags);
1098
1099 return 0;
1100
1101exit_close_candev:
1102 close_candev(dev);
1103exit_free_txdlc:
1104 kfree(priv->txdlc);
1105exit_free_echo_skb:
1106 kfree(priv->echo_skb);
1107exit_free_dma_buffers:
1108 grcan_free_dma_buffers(dev);
1109 return err;
1110}
1111
1112static int grcan_close(struct net_device *dev)
1113{
1114 struct grcan_priv *priv = netdev_priv(dev);
1115 unsigned long flags;
1116
1117 napi_disable(&priv->napi);
1118
1119 spin_lock_irqsave(&priv->lock, flags);
1120
1121 priv->closing = true;
1122 if (priv->need_txbug_workaround) {
1123 del_timer_sync(&priv->hang_timer);
1124 del_timer_sync(&priv->rr_timer);
1125 }
1126 netif_stop_queue(dev);
1127 grcan_stop_hardware(dev);
1128 priv->can.state = CAN_STATE_STOPPED;
1129
1130 spin_unlock_irqrestore(&priv->lock, flags);
1131
1132 free_irq(dev->irq, dev);
1133 close_candev(dev);
1134
1135 grcan_free_dma_buffers(dev);
1136 priv->can.echo_skb_max = 0;
1137 priv->can.echo_skb = NULL;
1138 kfree(priv->echo_skb);
1139 kfree(priv->txdlc);
1140
1141 return 0;
1142}
1143
1144static int grcan_transmit_catch_up(struct net_device *dev, int budget)
1145{
1146 struct grcan_priv *priv = netdev_priv(dev);
1147 unsigned long flags;
1148 int work_done;
1149
1150 spin_lock_irqsave(&priv->lock, flags);
1151
1152 work_done = catch_up_echo_skb(dev, budget, true);
1153 if (work_done) {
1154 if (!priv->resetting && !priv->closing &&
1155 !(priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY))
1156 netif_wake_queue(dev);
1157
1158 /* With napi we don't get TX interrupts for a while,
1159 * so prevent a running reset while catching up
1160 */
1161 if (priv->need_txbug_workaround)
1162 del_timer(&priv->hang_timer);
1163 }
1164
1165 spin_unlock_irqrestore(&priv->lock, flags);
1166
1167 return work_done;
1168}
1169
1170static int grcan_receive(struct net_device *dev, int budget)
1171{
1172 struct grcan_priv *priv = netdev_priv(dev);
1173 struct grcan_registers __iomem *regs = priv->regs;
1174 struct grcan_dma *dma = &priv->dma;
1175 struct net_device_stats *stats = &dev->stats;
1176 struct can_frame *cf;
1177 struct sk_buff *skb;
1178 u32 wr, rd, startrd;
1179 u32 *slot;
1180 u32 i, rtr, eff, j, shift;
1181 int work_done = 0;
1182
1183 rd = grcan_read_reg(&regs->rxrd);
1184 startrd = rd;
1185 for (work_done = 0; work_done < budget; work_done++) {
1186 /* Check for packet to receive */
1187 wr = grcan_read_reg(&regs->rxwr);
1188 if (rd == wr)
1189 break;
1190
1191 /* Take care of packet */
1192 skb = alloc_can_skb(dev, &cf);
1193 if (skb == NULL) {
1194 netdev_err(dev,
1195 "dropping frame: skb allocation failed\n");
1196 stats->rx_dropped++;
1197 continue;
1198 }
1199
1200 slot = dma->rx.buf + rd;
1201 eff = slot[0] & GRCAN_MSG_IDE;
1202 rtr = slot[0] & GRCAN_MSG_RTR;
1203 if (eff) {
1204 cf->can_id = ((slot[0] & GRCAN_MSG_EID)
1205 >> GRCAN_MSG_EID_BIT);
1206 cf->can_id |= CAN_EFF_FLAG;
1207 } else {
1208 cf->can_id = ((slot[0] & GRCAN_MSG_BID)
1209 >> GRCAN_MSG_BID_BIT);
1210 }
1211 cf->can_dlc = get_can_dlc((slot[1] & GRCAN_MSG_DLC)
1212 >> GRCAN_MSG_DLC_BIT);
1213 if (rtr) {
1214 cf->can_id |= CAN_RTR_FLAG;
1215 } else {
1216 for (i = 0; i < cf->can_dlc; i++) {
1217 j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1218 shift = GRCAN_MSG_DATA_SHIFT(i);
1219 cf->data[i] = (u8)(slot[j] >> shift);
1220 }
1221 }
1222 netif_receive_skb(skb);
1223
1224 /* Update statistics and read pointer */
1225 stats->rx_packets++;
1226 stats->rx_bytes += cf->can_dlc;
1227 rd = grcan_ring_add(rd, GRCAN_MSG_SIZE, dma->rx.size);
1228 }
1229
1230 /* Make sure everything is read before allowing hardware to
1231 * use the memory
1232 */
1233 mb();
1234
1235 /* Update read pointer - no need to check for ongoing */
1236 if (likely(rd != startrd))
1237 grcan_write_reg(&regs->rxrd, rd);
1238
1239 return work_done;
1240}
1241
1242static int grcan_poll(struct napi_struct *napi, int budget)
1243{
1244 struct grcan_priv *priv = container_of(napi, struct grcan_priv, napi);
1245 struct net_device *dev = priv->dev;
1246 struct grcan_registers __iomem *regs = priv->regs;
1247 unsigned long flags;
1248 int tx_work_done, rx_work_done;
1249 int rx_budget = budget / 2;
1250 int tx_budget = budget - rx_budget;
1251
1252 /* Half of the budget for receiveing messages */
1253 rx_work_done = grcan_receive(dev, rx_budget);
1254
1255 /* Half of the budget for transmitting messages as that can trigger echo
1256 * frames being received
1257 */
1258 tx_work_done = grcan_transmit_catch_up(dev, tx_budget);
1259
1260 if (rx_work_done < rx_budget && tx_work_done < tx_budget) {
1261 napi_complete(napi);
1262
1263 /* Guarantee no interference with a running reset that otherwise
1264 * could turn off interrupts.
1265 */
1266 spin_lock_irqsave(&priv->lock, flags);
1267
1268 /* Enable tx and rx interrupts again. No need to check
1269 * priv->closing as napi_disable in grcan_close is waiting for
1270 * scheduled napi calls to finish.
1271 */
1272 grcan_set_bits(&regs->imr, GRCAN_IRQ_TX | GRCAN_IRQ_RX);
1273
1274 spin_unlock_irqrestore(&priv->lock, flags);
1275 }
1276
1277 return rx_work_done + tx_work_done;
1278}
1279
1280/* Work tx bug by waiting while for the risky situation to clear. If that fails,
1281 * drop a frame in one-shot mode or indicate a busy device otherwise.
1282 *
1283 * Returns 0 on successful wait. Otherwise it sets *netdev_tx_status to the
1284 * value that should be returned by grcan_start_xmit when aborting the xmit.
1285 */
1286static int grcan_txbug_workaround(struct net_device *dev, struct sk_buff *skb,
1287 u32 txwr, u32 oneshotmode,
1288 netdev_tx_t *netdev_tx_status)
1289{
1290 struct grcan_priv *priv = netdev_priv(dev);
1291 struct grcan_registers __iomem *regs = priv->regs;
1292 struct grcan_dma *dma = &priv->dma;
1293 int i;
1294 unsigned long flags;
1295
1296 /* Wait a while for ongoing to be cleared or read pointer to catch up to
1297 * write pointer. The latter is needed due to a bug in older versions of
1298 * GRCAN in which ONGOING is not cleared properly one-shot mode when a
1299 * transmission fails.
1300 */
1301 for (i = 0; i < GRCAN_SHORTWAIT_USECS; i++) {
1302 udelay(1);
1303 if (!grcan_read_bits(&regs->txctrl, GRCAN_TXCTRL_ONGOING) ||
1304 grcan_read_reg(&regs->txrd) == txwr) {
1305 return 0;
1306 }
1307 }
1308
1309 /* Clean up, in case the situation was not resolved */
1310 spin_lock_irqsave(&priv->lock, flags);
1311 if (!priv->resetting && !priv->closing) {
1312 /* Queue might have been stopped earlier in grcan_start_xmit */
1313 if (grcan_txspace(dma->tx.size, txwr, priv->eskbp))
1314 netif_wake_queue(dev);
1315 /* Set a timer to resolve a hanged tx controller */
1316 if (!timer_pending(&priv->hang_timer))
1317 grcan_reset_timer(&priv->hang_timer,
1318 priv->can.bittiming.bitrate);
1319 }
1320 spin_unlock_irqrestore(&priv->lock, flags);
1321
1322 if (oneshotmode) {
1323 /* In one-shot mode we should never end up here because
1324 * then the interrupt handler increases txrd on TXLOSS,
1325 * but it is consistent with one-shot mode to drop the
1326 * frame in this case.
1327 */
1328 kfree_skb(skb);
1329 *netdev_tx_status = NETDEV_TX_OK;
1330 } else {
1331 /* In normal mode the socket-can transmission queue get
1332 * to keep the frame so that it can be retransmitted
1333 * later
1334 */
1335 *netdev_tx_status = NETDEV_TX_BUSY;
1336 }
1337 return -EBUSY;
1338}
1339
1340/* Notes on the tx cyclic buffer handling:
1341 *
1342 * regs->txwr - the next slot for the driver to put data to be sent
1343 * regs->txrd - the next slot for the device to read data
1344 * priv->eskbp - the next slot for the driver to call can_put_echo_skb for
1345 *
1346 * grcan_start_xmit can enter more messages as long as regs->txwr does
1347 * not reach priv->eskbp (within 1 message gap)
1348 *
1349 * The device sends messages until regs->txrd reaches regs->txwr
1350 *
1351 * The interrupt calls handler calls can_put_echo_skb until
1352 * priv->eskbp reaches regs->txrd
1353 */
1354static netdev_tx_t grcan_start_xmit(struct sk_buff *skb,
1355 struct net_device *dev)
1356{
1357 struct grcan_priv *priv = netdev_priv(dev);
1358 struct grcan_registers __iomem *regs = priv->regs;
1359 struct grcan_dma *dma = &priv->dma;
1360 struct can_frame *cf = (struct can_frame *)skb->data;
1361 u32 id, txwr, txrd, space, txctrl;
1362 int slotindex;
1363 u32 *slot;
1364 u32 i, rtr, eff, dlc, tmp, err;
1365 int j, shift;
1366 unsigned long flags;
1367 u32 oneshotmode = priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT;
1368
1369 if (can_dropped_invalid_skb(dev, skb))
1370 return NETDEV_TX_OK;
1371
1372 /* Trying to transmit in silent mode will generate error interrupts, but
1373 * this should never happen - the queue should not have been started.
1374 */
1375 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
1376 return NETDEV_TX_BUSY;
1377
1378 /* Reads of priv->eskbp and shut-downs of the queue needs to
1379 * be atomic towards the updates to priv->eskbp and wake-ups
1380 * of the queue in the interrupt handler.
1381 */
1382 spin_lock_irqsave(&priv->lock, flags);
1383
1384 txwr = grcan_read_reg(&regs->txwr);
1385 space = grcan_txspace(dma->tx.size, txwr, priv->eskbp);
1386
1387 slotindex = txwr / GRCAN_MSG_SIZE;
1388 slot = dma->tx.buf + txwr;
1389
1390 if (unlikely(space == 1))
1391 netif_stop_queue(dev);
1392
1393 spin_unlock_irqrestore(&priv->lock, flags);
1394 /* End of critical section*/
1395
1396 /* This should never happen. If circular buffer is full, the
1397 * netif_stop_queue should have been stopped already.
1398 */
1399 if (unlikely(!space)) {
1400 netdev_err(dev, "No buffer space, but queue is non-stopped.\n");
1401 return NETDEV_TX_BUSY;
1402 }
1403
1404 /* Convert and write CAN message to DMA buffer */
1405 eff = cf->can_id & CAN_EFF_FLAG;
1406 rtr = cf->can_id & CAN_RTR_FLAG;
1407 id = cf->can_id & (eff ? CAN_EFF_MASK : CAN_SFF_MASK);
1408 dlc = cf->can_dlc;
1409 if (eff)
1410 tmp = (id << GRCAN_MSG_EID_BIT) & GRCAN_MSG_EID;
1411 else
1412 tmp = (id << GRCAN_MSG_BID_BIT) & GRCAN_MSG_BID;
1413 slot[0] = (eff ? GRCAN_MSG_IDE : 0) | (rtr ? GRCAN_MSG_RTR : 0) | tmp;
1414
1415 slot[1] = ((dlc << GRCAN_MSG_DLC_BIT) & GRCAN_MSG_DLC);
1416 slot[2] = 0;
1417 slot[3] = 0;
1418 for (i = 0; i < dlc; i++) {
1419 j = GRCAN_MSG_DATA_SLOT_INDEX(i);
1420 shift = GRCAN_MSG_DATA_SHIFT(i);
1421 slot[j] |= cf->data[i] << shift;
1422 }
1423
1424 /* Checking that channel has not been disabled. These cases
1425 * should never happen
1426 */
1427 txctrl = grcan_read_reg(&regs->txctrl);
1428 if (!(txctrl & GRCAN_TXCTRL_ENABLE))
1429 netdev_err(dev, "tx channel spuriously disabled\n");
1430
1431 if (oneshotmode && !(txctrl & GRCAN_TXCTRL_SINGLE))
1432 netdev_err(dev, "one-shot mode spuriously disabled\n");
1433
1434 /* Bug workaround for old version of grcan where updating txwr
1435 * in the same clock cycle as the controller updates txrd to
1436 * the current txwr could hang the can controller
1437 */
1438 if (priv->need_txbug_workaround) {
1439 txrd = grcan_read_reg(&regs->txrd);
1440 if (unlikely(grcan_ring_sub(txwr, txrd, dma->tx.size) == 1)) {
1441 netdev_tx_t txstatus;
1442
1443 err = grcan_txbug_workaround(dev, skb, txwr,
1444 oneshotmode, &txstatus);
1445 if (err)
1446 return txstatus;
1447 }
1448 }
1449
1450 /* Prepare skb for echoing. This must be after the bug workaround above
1451 * as ownership of the skb is passed on by calling can_put_echo_skb.
1452 * Returning NETDEV_TX_BUSY or accessing skb or cf after a call to
1453 * can_put_echo_skb would be an error unless other measures are
1454 * taken.
1455 */
1456 priv->txdlc[slotindex] = cf->can_dlc; /* Store dlc for statistics */
1457 can_put_echo_skb(skb, dev, slotindex);
1458
1459 /* Make sure everything is written before allowing hardware to
1460 * read from the memory
1461 */
1462 wmb();
1463
1464 /* Update write pointer to start transmission */
1465 grcan_write_reg(&regs->txwr,
1466 grcan_ring_add(txwr, GRCAN_MSG_SIZE, dma->tx.size));
1467
1468 return NETDEV_TX_OK;
1469}
1470
1471/* ========== Setting up sysfs interface and module parameters ========== */
1472
1473#define GRCAN_NOT_BOOL(unsigned_val) ((unsigned_val) > 1)
1474
1475#define GRCAN_MODULE_PARAM(name, mtype, valcheckf, desc) \
1476 static void grcan_sanitize_##name(struct platform_device *pd) \
1477 { \
1478 struct grcan_device_config grcan_default_config \
1479 = GRCAN_DEFAULT_DEVICE_CONFIG; \
1480 if (valcheckf(grcan_module_config.name)) { \
1481 dev_err(&pd->dev, \
1482 "Invalid module parameter value for " \
1483 #name " - setting default\n"); \
1484 grcan_module_config.name = \
1485 grcan_default_config.name; \
1486 } \
1487 } \
1488 module_param_named(name, grcan_module_config.name, \
1489 mtype, S_IRUGO); \
1490 MODULE_PARM_DESC(name, desc)
1491
1492#define GRCAN_CONFIG_ATTR(name, desc) \
1493 static ssize_t grcan_store_##name(struct device *sdev, \
1494 struct device_attribute *att, \
1495 const char *buf, \
1496 size_t count) \
1497 { \
1498 struct net_device *dev = to_net_dev(sdev); \
1499 struct grcan_priv *priv = netdev_priv(dev); \
1500 u8 val; \
1501 int ret; \
1502 if (dev->flags & IFF_UP) \
1503 return -EBUSY; \
1504 ret = kstrtou8(buf, 0, &val); \
1505 if (ret < 0 || val > 1) \
1506 return -EINVAL; \
1507 priv->config.name = val; \
1508 return count; \
1509 } \
1510 static ssize_t grcan_show_##name(struct device *sdev, \
1511 struct device_attribute *att, \
1512 char *buf) \
1513 { \
1514 struct net_device *dev = to_net_dev(sdev); \
1515 struct grcan_priv *priv = netdev_priv(dev); \
1516 return sprintf(buf, "%d\n", priv->config.name); \
1517 } \
1518 static DEVICE_ATTR(name, S_IRUGO | S_IWUSR, \
1519 grcan_show_##name, \
1520 grcan_store_##name); \
1521 GRCAN_MODULE_PARAM(name, ushort, GRCAN_NOT_BOOL, desc)
1522
1523/* The following configuration options are made available both via module
1524 * parameters and writable sysfs files. See the chapter about GRCAN in the
1525 * documentation for the GRLIB VHDL library for further details.
1526 */
1527GRCAN_CONFIG_ATTR(enable0,
1528 "Configuration of physical interface 0. Determines\n" \
1529 "the \"Enable 0\" bit of the configuration register.\n" \
1530 "Format: 0 | 1\nDefault: 0\n");
1531
1532GRCAN_CONFIG_ATTR(enable1,
1533 "Configuration of physical interface 1. Determines\n" \
1534 "the \"Enable 1\" bit of the configuration register.\n" \
1535 "Format: 0 | 1\nDefault: 0\n");
1536
1537GRCAN_CONFIG_ATTR(select,
1538 "Select which physical interface to use.\n" \
1539 "Format: 0 | 1\nDefault: 0\n");
1540
1541/* The tx and rx buffer size configuration options are only available via module
1542 * parameters.
1543 */
1544GRCAN_MODULE_PARAM(txsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1545 "Sets the size of the tx buffer.\n" \
1546 "Format: <unsigned int> where (txsize & ~0x1fffc0) == 0\n" \
1547 "Default: 1024\n");
1548GRCAN_MODULE_PARAM(rxsize, uint, GRCAN_INVALID_BUFFER_SIZE,
1549 "Sets the size of the rx buffer.\n" \
1550 "Format: <unsigned int> where (size & ~0x1fffc0) == 0\n" \
1551 "Default: 1024\n");
1552
1553/* Function that makes sure that configuration done using
1554 * module parameters are set to valid values
1555 */
1556static void grcan_sanitize_module_config(struct platform_device *ofdev)
1557{
1558 grcan_sanitize_enable0(ofdev);
1559 grcan_sanitize_enable1(ofdev);
1560 grcan_sanitize_select(ofdev);
1561 grcan_sanitize_txsize(ofdev);
1562 grcan_sanitize_rxsize(ofdev);
1563}
1564
1565static const struct attribute *const sysfs_grcan_attrs[] = {
1566 /* Config attrs */
1567 &dev_attr_enable0.attr,
1568 &dev_attr_enable1.attr,
1569 &dev_attr_select.attr,
1570 NULL,
1571};
1572
1573static const struct attribute_group sysfs_grcan_group = {
1574 .name = "grcan",
1575 .attrs = (struct attribute **)sysfs_grcan_attrs,
1576};
1577
1578/* ========== Setting up the driver ========== */
1579
1580static const struct net_device_ops grcan_netdev_ops = {
1581 .ndo_open = grcan_open,
1582 .ndo_stop = grcan_close,
1583 .ndo_start_xmit = grcan_start_xmit,
1584};
1585
1586static int grcan_setup_netdev(struct platform_device *ofdev,
1587 void __iomem *base,
1588 int irq, u32 ambafreq, bool txbug)
1589{
1590 struct net_device *dev;
1591 struct grcan_priv *priv;
1592 struct grcan_registers __iomem *regs;
1593 int err;
1594
1595 dev = alloc_candev(sizeof(struct grcan_priv), 0);
1596 if (!dev)
1597 return -ENOMEM;
1598
1599 dev->irq = irq;
1600 dev->flags |= IFF_ECHO;
1601 dev->netdev_ops = &grcan_netdev_ops;
1602 dev->sysfs_groups[0] = &sysfs_grcan_group;
1603
1604 priv = netdev_priv(dev);
1605 memcpy(&priv->config, &grcan_module_config,
1606 sizeof(struct grcan_device_config));
1607 priv->dev = dev;
1608 priv->regs = base;
1609 priv->can.bittiming_const = &grcan_bittiming_const;
1610 priv->can.do_set_bittiming = grcan_set_bittiming;
1611 priv->can.do_set_mode = grcan_set_mode;
1612 priv->can.do_get_berr_counter = grcan_get_berr_counter;
1613 priv->can.clock.freq = ambafreq;
1614 priv->can.ctrlmode_supported =
1615 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_ONE_SHOT;
1616 priv->need_txbug_workaround = txbug;
1617
1618 /* Discover if triple sampling is supported by hardware */
1619 regs = priv->regs;
1620 grcan_set_bits(&regs->ctrl, GRCAN_CTRL_RESET);
1621 grcan_set_bits(&regs->conf, GRCAN_CONF_SAM);
1622 if (grcan_read_bits(&regs->conf, GRCAN_CONF_SAM)) {
1623 priv->can.ctrlmode_supported |= CAN_CTRLMODE_3_SAMPLES;
1624 dev_dbg(&ofdev->dev, "Hardware supports triple-sampling\n");
1625 }
1626
1627 spin_lock_init(&priv->lock);
1628
1629 if (priv->need_txbug_workaround) {
1630 init_timer(&priv->rr_timer);
1631 priv->rr_timer.function = grcan_running_reset;
1632 priv->rr_timer.data = (unsigned long)dev;
1633
1634 init_timer(&priv->hang_timer);
1635 priv->hang_timer.function = grcan_initiate_running_reset;
1636 priv->hang_timer.data = (unsigned long)dev;
1637 }
1638
1639 netif_napi_add(dev, &priv->napi, grcan_poll, GRCAN_NAPI_WEIGHT);
1640
1641 SET_NETDEV_DEV(dev, &ofdev->dev);
1642 dev_info(&ofdev->dev, "regs=0x%p, irq=%d, clock=%d\n",
1643 priv->regs, dev->irq, priv->can.clock.freq);
1644
1645 err = register_candev(dev);
1646 if (err)
1647 goto exit_free_candev;
1648
1649 dev_set_drvdata(&ofdev->dev, dev);
1650
1651 /* Reset device to allow bit-timing to be set. No need to call
1652 * grcan_reset at this stage. That is done in grcan_open.
1653 */
1654 grcan_write_reg(&regs->ctrl, GRCAN_CTRL_RESET);
1655
1656 return 0;
1657exit_free_candev:
1658 free_candev(dev);
1659 return err;
1660}
1661
1662static int __devinit grcan_probe(struct platform_device *ofdev)
1663{
1664 struct device_node *np = ofdev->dev.of_node;
1665 struct resource *res;
1666 u32 sysid, ambafreq;
1667 int irq, err;
1668 void __iomem *base;
1669 bool txbug = true;
1670
1671 /* Compare GRLIB version number with the first that does not
1672 * have the tx bug (see start_xmit)
1673 */
1674 err = of_property_read_u32(np, "systemid", &sysid);
1675 if (!err && ((sysid & GRLIB_VERSION_MASK)
1676 >= GRCAN_TXBUG_SAFE_GRLIB_VERSION))
1677 txbug = false;
1678
1679 err = of_property_read_u32(np, "freq", &ambafreq);
1680 if (err) {
1681 dev_err(&ofdev->dev, "unable to fetch \"freq\" property\n");
1682 goto exit_error;
1683 }
1684
1685 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1686 base = devm_request_and_ioremap(&ofdev->dev, res);
1687 if (!base) {
1688 dev_err(&ofdev->dev, "couldn't map IO resource\n");
1689 err = -EADDRNOTAVAIL;
1690 goto exit_error;
1691 }
1692
1693 irq = irq_of_parse_and_map(np, GRCAN_IRQIX_IRQ);
1694 if (!irq) {
1695 dev_err(&ofdev->dev, "no irq found\n");
1696 err = -ENODEV;
1697 goto exit_error;
1698 }
1699
1700 grcan_sanitize_module_config(ofdev);
1701
1702 err = grcan_setup_netdev(ofdev, base, irq, ambafreq, txbug);
1703 if (err)
1704 goto exit_dispose_irq;
1705
1706 return 0;
1707
1708exit_dispose_irq:
1709 irq_dispose_mapping(irq);
1710exit_error:
1711 dev_err(&ofdev->dev,
1712 "%s socket CAN driver initialization failed with error %d\n",
1713 DRV_NAME, err);
1714 return err;
1715}
1716
1717static int __devexit grcan_remove(struct platform_device *ofdev)
1718{
1719 struct net_device *dev = dev_get_drvdata(&ofdev->dev);
1720 struct grcan_priv *priv = netdev_priv(dev);
1721
1722 unregister_candev(dev); /* Will in turn call grcan_close */
1723
1724 irq_dispose_mapping(dev->irq);
1725 dev_set_drvdata(&ofdev->dev, NULL);
1726 netif_napi_del(&priv->napi);
1727 free_candev(dev);
1728
1729 return 0;
1730}
1731
1732static struct of_device_id grcan_match[] __devinitconst = {
1733 {.name = "GAISLER_GRCAN"},
1734 {.name = "01_03d"},
1735 {.name = "GAISLER_GRHCAN"},
1736 {.name = "01_034"},
1737 {},
1738};
1739
1740MODULE_DEVICE_TABLE(of, grcan_match);
1741
1742static struct platform_driver grcan_driver = {
1743 .driver = {
1744 .name = DRV_NAME,
1745 .owner = THIS_MODULE,
1746 .of_match_table = grcan_match,
1747 },
1748 .probe = grcan_probe,
1749 .remove = __devexit_p(grcan_remove),
1750};
1751
1752module_platform_driver(grcan_driver);
1753
1754MODULE_AUTHOR("Aeroflex Gaisler AB.");
1755MODULE_DESCRIPTION("Socket CAN driver for Aeroflex Gaisler GRCAN");
1756MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 21:35:00 -0500