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authorDave Airlie <airlied@redhat.com>2014-06-09 18:51:19 -0400
committerDave Airlie <airlied@redhat.com>2014-06-09 18:51:19 -0400
commit6c8a02bba826b52af1da3447af8acdc49eddad66 (patch)
tree95cee89a36954c3868347f06720860d3523cbe04
parentecb889e6205171ecbf80b15d903549aa6b15d23b (diff)
parent1f64ae7c5af0d65b2491af30ce7a295569e452c9 (diff)
Merge tag 'drm/tegra/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v3.16-rc1 The majority of these changes are a slew of cleanups across the board. A more noteworthy change is the addition of drm_dev_set_unique() and the conversion of the Tegra DRM driver to use it. This allows us to get rid of the host1x drm_bus implementation. Other USB and platform drivers can be changed in a similar way. Unfortunately for most PCI devices there is some userspace that relies on the old functionality and cannot be as easily converted. HDMI and hardware cursor support is added for Tegra124. The SOR output gains support for exposing CRCs via debugfs, which can be used for automated testing. Many values that were hardcoded in the SOR/eDP code are now computed at runtime to increase compatibility with more devices. * tag 'drm/tegra/for-3.16-rc1' of git://anongit.freedesktop.org/tegra/linux: (47 commits) drm/tegra: sor - Remove obsolete comment drm/tegra: sor - Enable only the necessary number of lanes drm/tegra: sor - Power on only the necessary lanes drm/tegra: sor - Do not program interlaced mode registers drm/tegra: sor - Do not hardcode link speed drm/tegra: sor - Do not hardcode number of blank symbols drm/tegra: sor - Don't hardcode link parameters drm/tegra: sor - Change power down ordering drm/tegra: sor - Fix copy/paste error drm/tegra: sor - Remove pixel clock rounding drm/tegra: sor - Make debugfs setup consistent drm/tegra: sor - Recursively remove debugfs tree drm/tegra: dp - Mark the connector as hotplug capable drm/tegra: dp - Implement hotplug detection in work queue drm/tegra: Add hardware cursor support drm/tegra: Remove host1x drm_bus implementation drm: Document how to register devices without struct drm_bus drm: Add device registration documentation drm: Introduce drm_dev_set_unique() gpu: host1x: Rename internal functions for clarity ...
Diffstat
-rw-r--r--Documentation/DocBook/drm.tmpl36
-rw-r--r--Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt2
-rw-r--r--drivers/gpu/drm/drm_ioctl.c24
-rw-r--r--drivers/gpu/drm/drm_pci.c80
-rw-r--r--drivers/gpu/drm/drm_platform.c15
-rw-r--r--drivers/gpu/drm/drm_stub.c48
-rw-r--r--drivers/gpu/drm/drm_usb.c20
-rw-r--r--drivers/gpu/drm/tegra/Makefile1
-rw-r--r--drivers/gpu/drm/tegra/bus.c64
-rw-r--r--drivers/gpu/drm/tegra/dc.c657
-rw-r--r--drivers/gpu/drm/tegra/dc.h33
-rw-r--r--drivers/gpu/drm/tegra/dpaux.c31
-rw-r--r--drivers/gpu/drm/tegra/drm.c36
-rw-r--r--drivers/gpu/drm/tegra/drm.h58
-rw-r--r--drivers/gpu/drm/tegra/dsi.c250
-rw-r--r--drivers/gpu/drm/tegra/dsi.h10
-rw-r--r--drivers/gpu/drm/tegra/gem.c3
-rw-r--r--drivers/gpu/drm/tegra/gr2d.c8
-rw-r--r--drivers/gpu/drm/tegra/gr3d.c8
-rw-r--r--drivers/gpu/drm/tegra/hdmi.c202
-rw-r--r--drivers/gpu/drm/tegra/hdmi.h5
-rw-r--r--drivers/gpu/drm/tegra/rgb.c31
-rw-r--r--drivers/gpu/drm/tegra/sor.c478
-rw-r--r--drivers/gpu/drm/tegra/sor.h4
-rw-r--r--drivers/gpu/host1x/bus.c12
-rw-r--r--include/drm/drmP.h2
26 files changed, 1438 insertions, 680 deletions
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
index efef63717ef6..d95027f6e977 100644
--- a/Documentation/DocBook/drm.tmpl
+++ b/Documentation/DocBook/drm.tmpl
@@ -142,6 +142,12 @@
142 to register it with the DRM subsystem. 142 to register it with the DRM subsystem.
143 </para> 143 </para>
144 <para> 144 <para>
145 Newer drivers that no longer require a <structname>drm_bus</structname>
146 structure can alternatively use the low-level device initialization and
147 registration functions such as <function>drm_dev_alloc()</function> and
148 <function>drm_dev_register()</function> directly.
149 </para>
150 <para>
145 The <structname>drm_driver</structname> structure contains static 151 The <structname>drm_driver</structname> structure contains static
146 information that describes the driver and features it supports, and 152 information that describes the driver and features it supports, and
147 pointers to methods that the DRM core will call to implement the DRM API. 153 pointers to methods that the DRM core will call to implement the DRM API.
@@ -282,6 +288,36 @@ char *date;</synopsis>
282 </sect3> 288 </sect3>
283 </sect2> 289 </sect2>
284 <sect2> 290 <sect2>
291 <title>Device Registration</title>
292 <para>
293 A number of functions are provided to help with device registration.
294 The functions deal with PCI, USB and platform devices, respectively.
295 </para>
296!Edrivers/gpu/drm/drm_pci.c
297!Edrivers/gpu/drm/drm_usb.c
298!Edrivers/gpu/drm/drm_platform.c
299 <para>
300 New drivers that no longer rely on the services provided by the
301 <structname>drm_bus</structname> structure can call the low-level
302 device registration functions directly. The
303 <function>drm_dev_alloc()</function> function can be used to allocate
304 and initialize a new <structname>drm_device</structname> structure.
305 Drivers will typically want to perform some additional setup on this
306 structure, such as allocating driver-specific data and storing a
307 pointer to it in the DRM device's <structfield>dev_private</structfield>
308 field. Drivers should also set the device's unique name using the
309 <function>drm_dev_set_unique()</function> function. After it has been
310 set up a device can be registered with the DRM subsystem by calling
311 <function>drm_dev_register()</function>. This will cause the device to
312 be exposed to userspace and will call the driver's
313 <structfield>.load()</structfield> implementation. When a device is
314 removed, the DRM device can safely be unregistered and freed by calling
315 <function>drm_dev_unregister()</function> followed by a call to
316 <function>drm_dev_unref()</function>.
317 </para>
318!Edrivers/gpu/drm/drm_stub.c
319 </sect2>
320 <sect2>
285 <title>Driver Load</title> 321 <title>Driver Load</title>
286 <para> 322 <para>
287 The <methodname>load</methodname> method is the driver and device 323 The <methodname>load</methodname> method is the driver and device
diff --git a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
index efa8b8451f93..b48f4ef31d93 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
@@ -136,6 +136,7 @@ of the following host1x client modules:
136 - compatible: "nvidia,tegra<chip>-hdmi" 136 - compatible: "nvidia,tegra<chip>-hdmi"
137 - reg: Physical base address and length of the controller's registers. 137 - reg: Physical base address and length of the controller's registers.
138 - interrupts: The interrupt outputs from the controller. 138 - interrupts: The interrupt outputs from the controller.
139 - hdmi-supply: supply for the +5V HDMI connector pin
139 - vdd-supply: regulator for supply voltage 140 - vdd-supply: regulator for supply voltage
140 - pll-supply: regulator for PLL 141 - pll-supply: regulator for PLL
141 - clocks: Must contain an entry for each entry in clock-names. 142 - clocks: Must contain an entry for each entry in clock-names.
@@ -180,6 +181,7 @@ of the following host1x client modules:
180 See ../reset/reset.txt for details. 181 See ../reset/reset.txt for details.
181 - reset-names: Must include the following entries: 182 - reset-names: Must include the following entries:
182 - dsi 183 - dsi
184 - avdd-dsi-supply: phandle of a supply that powers the DSI controller
183 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying 185 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
184 which pads are used by this DSI output and need to be calibrated. See also 186 which pads are used by this DSI output and need to be calibrated. See also
185 ../mipi/nvidia,tegra114-mipi.txt. 187 ../mipi/nvidia,tegra114-mipi.txt.
diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c
index 38269d5aa333..69c61f392e66 100644
--- a/drivers/gpu/drm/drm_ioctl.c
+++ b/drivers/gpu/drm/drm_ioctl.c
@@ -131,13 +131,25 @@ static int drm_set_busid(struct drm_device *dev, struct drm_file *file_priv)
131 if (master->unique != NULL) 131 if (master->unique != NULL)
132 drm_unset_busid(dev, master); 132 drm_unset_busid(dev, master);
133 133
134 ret = dev->driver->bus->set_busid(dev, master); 134 if (dev->driver->bus && dev->driver->bus->set_busid) {
135 if (ret) 135 ret = dev->driver->bus->set_busid(dev, master);
136 goto err; 136 if (ret) {
137 drm_unset_busid(dev, master);
138 return ret;
139 }
140 } else {
141 if (WARN(dev->unique == NULL,
142 "No drm_bus.set_busid() implementation provided by "
143 "%ps. Use drm_dev_set_unique() to set the unique "
144 "name explicitly.", dev->driver))
145 return -EINVAL;
146
147 master->unique = kstrdup(dev->unique, GFP_KERNEL);
148 if (master->unique)
149 master->unique_len = strlen(dev->unique);
150 }
151
137 return 0; 152 return 0;
138err:
139 drm_unset_busid(dev, master);
140 return ret;
141} 153}
142 154
143/** 155/**
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index d237de36a07a..020cfd934854 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -1,17 +1,3 @@
1/* drm_pci.h -- PCI DMA memory management wrappers for DRM -*- linux-c -*- */
2/**
3 * \file drm_pci.c
4 * \brief Functions and ioctls to manage PCI memory
5 *
6 * \warning These interfaces aren't stable yet.
7 *
8 * \todo Implement the remaining ioctl's for the PCI pools.
9 * \todo The wrappers here are so thin that they would be better off inlined..
10 *
11 * \author José Fonseca <jrfonseca@tungstengraphics.com>
12 * \author Leif Delgass <ldelgass@retinalburn.net>
13 */
14
15/* 1/*
16 * Copyright 2003 José Fonseca. 2 * Copyright 2003 José Fonseca.
17 * Copyright 2003 Leif Delgass. 3 * Copyright 2003 Leif Delgass.
@@ -42,12 +28,14 @@
42#include <linux/export.h> 28#include <linux/export.h>
43#include <drm/drmP.h> 29#include <drm/drmP.h>
44 30
45/**********************************************************************/
46/** \name PCI memory */
47/*@{*/
48
49/** 31/**
50 * \brief Allocate a PCI consistent memory block, for DMA. 32 * drm_pci_alloc - Allocate a PCI consistent memory block, for DMA.
33 * @dev: DRM device
34 * @size: size of block to allocate
35 * @align: alignment of block
36 *
37 * Return: A handle to the allocated memory block on success or NULL on
38 * failure.
51 */ 39 */
52drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t align) 40drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t align)
53{ 41{
@@ -88,8 +76,8 @@ drm_dma_handle_t *drm_pci_alloc(struct drm_device * dev, size_t size, size_t ali
88 76
89EXPORT_SYMBOL(drm_pci_alloc); 77EXPORT_SYMBOL(drm_pci_alloc);
90 78
91/** 79/*
92 * \brief Free a PCI consistent memory block without freeing its descriptor. 80 * Free a PCI consistent memory block without freeing its descriptor.
93 * 81 *
94 * This function is for internal use in the Linux-specific DRM core code. 82 * This function is for internal use in the Linux-specific DRM core code.
95 */ 83 */
@@ -111,7 +99,9 @@ void __drm_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
111} 99}
112 100
113/** 101/**
114 * \brief Free a PCI consistent memory block 102 * drm_pci_free - Free a PCI consistent memory block
103 * @dev: DRM device
104 * @dmah: handle to memory block
115 */ 105 */
116void drm_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah) 106void drm_pci_free(struct drm_device * dev, drm_dma_handle_t * dmah)
117{ 107{
@@ -226,17 +216,16 @@ static int drm_pci_irq_by_busid(struct drm_device *dev, struct drm_irq_busid *p)
226} 216}
227 217
228/** 218/**
229 * Get interrupt from bus id. 219 * drm_irq_by_busid - Get interrupt from bus ID
230 * 220 * @dev: DRM device
231 * \param inode device inode. 221 * @data: IOCTL parameter pointing to a drm_irq_busid structure
232 * \param file_priv DRM file private. 222 * @file_priv: DRM file private.
233 * \param cmd command.
234 * \param arg user argument, pointing to a drm_irq_busid structure.
235 * \return zero on success or a negative number on failure.
236 * 223 *
237 * Finds the PCI device with the specified bus id and gets its IRQ number. 224 * Finds the PCI device with the specified bus id and gets its IRQ number.
238 * This IOCTL is deprecated, and will now return EINVAL for any busid not equal 225 * This IOCTL is deprecated, and will now return EINVAL for any busid not equal
239 * to that of the device that this DRM instance attached to. 226 * to that of the device that this DRM instance attached to.
227 *
228 * Return: 0 on success or a negative error code on failure.
240 */ 229 */
241int drm_irq_by_busid(struct drm_device *dev, void *data, 230int drm_irq_by_busid(struct drm_device *dev, void *data,
242 struct drm_file *file_priv) 231 struct drm_file *file_priv)
@@ -285,15 +274,16 @@ static struct drm_bus drm_pci_bus = {
285}; 274};
286 275
287/** 276/**
288 * Register. 277 * drm_get_pci_dev - Register a PCI device with the DRM subsystem
289 * 278 * @pdev: PCI device
290 * \param pdev - PCI device structure 279 * @ent: entry from the PCI ID table that matches @pdev
291 * \param ent entry from the PCI ID table with device type flags 280 * @driver: DRM device driver
292 * \return zero on success or a negative number on failure.
293 * 281 *
294 * Attempt to gets inter module "drm" information. If we are first 282 * Attempt to gets inter module "drm" information. If we are first
295 * then register the character device and inter module information. 283 * then register the character device and inter module information.
296 * Try and register, if we fail to register, backout previous work. 284 * Try and register, if we fail to register, backout previous work.
285 *
286 * Return: 0 on success or a negative error code on failure.
297 */ 287 */
298int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent, 288int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
299 struct drm_driver *driver) 289 struct drm_driver *driver)
@@ -346,15 +336,14 @@ err_free:
346EXPORT_SYMBOL(drm_get_pci_dev); 336EXPORT_SYMBOL(drm_get_pci_dev);
347 337
348/** 338/**
349 * PCI device initialization. Called direct from modules at load time. 339 * drm_pci_init - Register matching PCI devices with the DRM subsystem
340 * @driver: DRM device driver
341 * @pdriver: PCI device driver
350 * 342 *
351 * \return zero on success or a negative number on failure. 343 * Initializes a drm_device structures, registering the stubs and initializing
344 * the AGP device.
352 * 345 *
353 * Initializes a drm_device structures,registering the 346 * Return: 0 on success or a negative error code on failure.
354 * stubs and initializing the AGP device.
355 *
356 * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and
357 * after the initialization for driver customization.
358 */ 347 */
359int drm_pci_init(struct drm_driver *driver, struct pci_driver *pdriver) 348int drm_pci_init(struct drm_driver *driver, struct pci_driver *pdriver)
360{ 349{
@@ -458,7 +447,14 @@ int drm_pci_set_unique(struct drm_device *dev,
458 447
459EXPORT_SYMBOL(drm_pci_init); 448EXPORT_SYMBOL(drm_pci_init);
460 449
461/*@}*/ 450/**
451 * drm_pci_exit - Unregister matching PCI devices from the DRM subsystem
452 * @driver: DRM device driver
453 * @pdriver: PCI device driver
454 *
455 * Unregisters one or more devices matched by a PCI driver from the DRM
456 * subsystem.
457 */
462void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver) 458void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver)
463{ 459{
464 struct drm_device *dev, *tmp; 460 struct drm_device *dev, *tmp;
diff --git a/drivers/gpu/drm/drm_platform.c b/drivers/gpu/drm/drm_platform.c
index 234e0bc1ae51..d5b76f148c12 100644
--- a/drivers/gpu/drm/drm_platform.c
+++ b/drivers/gpu/drm/drm_platform.c
@@ -106,17 +106,16 @@ static struct drm_bus drm_platform_bus = {
106}; 106};
107 107
108/** 108/**
109 * Platform device initialization. Called direct from modules. 109 * drm_platform_init - Register a platform device with the DRM subsystem
110 * @driver: DRM device driver
111 * @platform_device: platform device to register
110 * 112 *
111 * \return zero on success or a negative number on failure. 113 * Registers the specified DRM device driver and platform device with the DRM
112 * 114 * subsystem, initializing a drm_device structure and calling the driver's
113 * Initializes a drm_device structures,registering the 115 * .load() function.
114 * stubs
115 * 116 *
116 * Expands the \c DRIVER_PREINIT and \c DRIVER_POST_INIT macros before and 117 * Return: 0 on success or a negative error code on failure.
117 * after the initialization for driver customization.
118 */ 118 */
119
120int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device) 119int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device)
121{ 120{
122 DRM_DEBUG("\n"); 121 DRM_DEBUG("\n");
diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
index 3727ac8bc310..14d16464000a 100644
--- a/drivers/gpu/drm/drm_stub.c
+++ b/drivers/gpu/drm/drm_stub.c
@@ -1,16 +1,11 @@
1/**
2 * \file drm_stub.h
3 * Stub support
4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 */
7
8/* 1/*
9 * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org 2 * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org
10 * 3 *
11 * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. 4 * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California.
12 * All Rights Reserved. 5 * All Rights Reserved.
13 * 6 *
7 * Author Rickard E. (Rik) Faith <faith@valinux.com>
8 *
14 * Permission is hereby granted, free of charge, to any person obtaining a 9 * Permission is hereby granted, free of charge, to any person obtaining a
15 * copy of this software and associated documentation files (the "Software"), 10 * copy of this software and associated documentation files (the "Software"),
16 * to deal in the Software without restriction, including without limitation 11 * to deal in the Software without restriction, including without limitation
@@ -425,11 +420,15 @@ void drm_minor_release(struct drm_minor *minor)
425} 420}
426 421
427/** 422/**
428 * Called via drm_exit() at module unload time or when pci device is 423 * drm_put_dev - Unregister and release a DRM device
429 * unplugged. 424 * @dev: DRM device
430 * 425 *
431 * Cleans up all DRM device, calling drm_lastclose(). 426 * Called at module unload time or when a PCI device is unplugged.
427 *
428 * Use of this function is discouraged. It will eventually go away completely.
429 * Please use drm_dev_unregister() and drm_dev_unref() explicitly instead.
432 * 430 *
431 * Cleans up all DRM device, calling drm_lastclose().
433 */ 432 */
434void drm_put_dev(struct drm_device *dev) 433void drm_put_dev(struct drm_device *dev)
435{ 434{
@@ -536,7 +535,7 @@ static void drm_fs_inode_free(struct inode *inode)
536} 535}
537 536
538/** 537/**
539 * drm_dev_alloc - Allocate new drm device 538 * drm_dev_alloc - Allocate new DRM device
540 * @driver: DRM driver to allocate device for 539 * @driver: DRM driver to allocate device for
541 * @parent: Parent device object 540 * @parent: Parent device object
542 * 541 *
@@ -650,6 +649,7 @@ static void drm_dev_release(struct kref *ref)
650 drm_minor_free(dev, DRM_MINOR_CONTROL); 649 drm_minor_free(dev, DRM_MINOR_CONTROL);
651 650
652 mutex_destroy(&dev->master_mutex); 651 mutex_destroy(&dev->master_mutex);
652 kfree(dev->unique);
653 kfree(dev); 653 kfree(dev);
654} 654}
655 655
@@ -689,6 +689,7 @@ EXPORT_SYMBOL(drm_dev_unref);
689/** 689/**
690 * drm_dev_register - Register DRM device 690 * drm_dev_register - Register DRM device
691 * @dev: Device to register 691 * @dev: Device to register
692 * @flags: Flags passed to the driver's .load() function
692 * 693 *
693 * Register the DRM device @dev with the system, advertise device to user-space 694 * Register the DRM device @dev with the system, advertise device to user-space
694 * and start normal device operation. @dev must be allocated via drm_dev_alloc() 695 * and start normal device operation. @dev must be allocated via drm_dev_alloc()
@@ -777,3 +778,28 @@ void drm_dev_unregister(struct drm_device *dev)
777 drm_minor_unregister(dev, DRM_MINOR_CONTROL); 778 drm_minor_unregister(dev, DRM_MINOR_CONTROL);
778} 779}
779EXPORT_SYMBOL(drm_dev_unregister); 780EXPORT_SYMBOL(drm_dev_unregister);
781
782/**
783 * drm_dev_set_unique - Set the unique name of a DRM device
784 * @dev: device of which to set the unique name
785 * @fmt: format string for unique name
786 *
787 * Sets the unique name of a DRM device using the specified format string and
788 * a variable list of arguments. Drivers can use this at driver probe time if
789 * the unique name of the devices they drive is static.
790 *
791 * Return: 0 on success or a negative error code on failure.
792 */
793int drm_dev_set_unique(struct drm_device *dev, const char *fmt, ...)
794{
795 va_list ap;
796
797 kfree(dev->unique);
798
799 va_start(ap, fmt);
800 dev->unique = kvasprintf(GFP_KERNEL, fmt, ap);
801 va_end(ap);
802
803 return dev->unique ? 0 : -ENOMEM;
804}
805EXPORT_SYMBOL(drm_dev_set_unique);
diff --git a/drivers/gpu/drm/drm_usb.c b/drivers/gpu/drm/drm_usb.c
index c6c7c29ad46f..f2fe94aab901 100644
--- a/drivers/gpu/drm/drm_usb.c
+++ b/drivers/gpu/drm/drm_usb.c
@@ -45,7 +45,17 @@ static int drm_usb_set_busid(struct drm_device *dev,
45static struct drm_bus drm_usb_bus = { 45static struct drm_bus drm_usb_bus = {
46 .set_busid = drm_usb_set_busid, 46 .set_busid = drm_usb_set_busid,
47}; 47};
48 48
49/**
50 * drm_usb_init - Register matching USB devices with the DRM subsystem
51 * @driver: DRM device driver
52 * @udriver: USB device driver
53 *
54 * Registers one or more devices matched by a USB driver with the DRM
55 * subsystem.
56 *
57 * Return: 0 on success or a negative error code on failure.
58 */
49int drm_usb_init(struct drm_driver *driver, struct usb_driver *udriver) 59int drm_usb_init(struct drm_driver *driver, struct usb_driver *udriver)
50{ 60{
51 int res; 61 int res;
@@ -58,6 +68,14 @@ int drm_usb_init(struct drm_driver *driver, struct usb_driver *udriver)
58} 68}
59EXPORT_SYMBOL(drm_usb_init); 69EXPORT_SYMBOL(drm_usb_init);
60 70
71/**
72 * drm_usb_exit - Unregister matching USB devices from the DRM subsystem
73 * @driver: DRM device driver
74 * @udriver: USB device driver
75 *
76 * Unregisters one or more devices matched by a USB driver from the DRM
77 * subsystem.
78 */
61void drm_usb_exit(struct drm_driver *driver, 79void drm_usb_exit(struct drm_driver *driver,
62 struct usb_driver *udriver) 80 struct usb_driver *udriver)
63{ 81{
diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile
index d43f21bb4596..2c66a8db9da4 100644
--- a/drivers/gpu/drm/tegra/Makefile
+++ b/drivers/gpu/drm/tegra/Makefile
@@ -1,7 +1,6 @@
1ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG 1ccflags-$(CONFIG_DRM_TEGRA_DEBUG) += -DDEBUG
2 2
3tegra-drm-y := \ 3tegra-drm-y := \
4 bus.o \
5 drm.o \ 4 drm.o \
6 gem.o \ 5 gem.o \
7 fb.o \ 6 fb.o \
diff --git a/drivers/gpu/drm/tegra/bus.c b/drivers/gpu/drm/tegra/bus.c
deleted file mode 100644
index b3a66d65cb53..000000000000
--- a/drivers/gpu/drm/tegra/bus.c
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include "drm.h"
10
11static int drm_host1x_set_busid(struct drm_device *dev,
12 struct drm_master *master)
13{
14 const char *device = dev_name(dev->dev);
15 const char *bus = dev->dev->bus->name;
16
17 master->unique_len = strlen(bus) + 1 + strlen(device);
18 master->unique_size = master->unique_len;
19
20 master->unique = kmalloc(master->unique_len + 1, GFP_KERNEL);
21 if (!master->unique)
22 return -ENOMEM;
23
24 snprintf(master->unique, master->unique_len + 1, "%s:%s", bus, device);
25
26 return 0;
27}
28
29static struct drm_bus drm_host1x_bus = {
30 .set_busid = drm_host1x_set_busid,
31};
32
33int drm_host1x_init(struct drm_driver *driver, struct host1x_device *device)
34{
35 struct drm_device *drm;
36 int ret;
37
38 driver->bus = &drm_host1x_bus;
39
40 drm = drm_dev_alloc(driver, &device->dev);
41 if (!drm)
42 return -ENOMEM;
43
44 ret = drm_dev_register(drm, 0);
45 if (ret)
46 goto err_free;
47
48 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name,
49 driver->major, driver->minor, driver->patchlevel,
50 driver->date, drm->primary->index);
51
52 return 0;
53
54err_free:
55 drm_dev_unref(drm);
56 return ret;
57}
58
59void drm_host1x_exit(struct drm_driver *driver, struct host1x_device *device)
60{
61 struct tegra_drm *tegra = dev_get_drvdata(&device->dev);
62
63 drm_put_dev(tegra->drm);
64}
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index edb871d7d395..ef40381f3909 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -17,6 +17,7 @@
17 17
18struct tegra_dc_soc_info { 18struct tegra_dc_soc_info {
19 bool supports_interlacing; 19 bool supports_interlacing;
20 bool supports_cursor;
20}; 21};
21 22
22struct tegra_plane { 23struct tegra_plane {
@@ -29,6 +30,254 @@ static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
29 return container_of(plane, struct tegra_plane, base); 30 return container_of(plane, struct tegra_plane, base);
30} 31}
31 32
33static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
34{
35 /* assume no swapping of fetched data */
36 if (swap)
37 *swap = BYTE_SWAP_NOSWAP;
38
39 switch (format) {
40 case DRM_FORMAT_XBGR8888:
41 return WIN_COLOR_DEPTH_R8G8B8A8;
42
43 case DRM_FORMAT_XRGB8888:
44 return WIN_COLOR_DEPTH_B8G8R8A8;
45
46 case DRM_FORMAT_RGB565:
47 return WIN_COLOR_DEPTH_B5G6R5;
48
49 case DRM_FORMAT_UYVY:
50 return WIN_COLOR_DEPTH_YCbCr422;
51
52 case DRM_FORMAT_YUYV:
53 if (swap)
54 *swap = BYTE_SWAP_SWAP2;
55
56 return WIN_COLOR_DEPTH_YCbCr422;
57
58 case DRM_FORMAT_YUV420:
59 return WIN_COLOR_DEPTH_YCbCr420P;
60
61 case DRM_FORMAT_YUV422:
62 return WIN_COLOR_DEPTH_YCbCr422P;
63
64 default:
65 break;
66 }
67
68 WARN(1, "unsupported pixel format %u, using default\n", format);
69 return WIN_COLOR_DEPTH_B8G8R8A8;
70}
71
72static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
73{
74 switch (format) {
75 case WIN_COLOR_DEPTH_YCbCr422:
76 case WIN_COLOR_DEPTH_YUV422:
77 if (planar)
78 *planar = false;
79
80 return true;
81
82 case WIN_COLOR_DEPTH_YCbCr420P:
83 case WIN_COLOR_DEPTH_YUV420P:
84 case WIN_COLOR_DEPTH_YCbCr422P:
85 case WIN_COLOR_DEPTH_YUV422P:
86 case WIN_COLOR_DEPTH_YCbCr422R:
87 case WIN_COLOR_DEPTH_YUV422R:
88 case WIN_COLOR_DEPTH_YCbCr422RA:
89 case WIN_COLOR_DEPTH_YUV422RA:
90 if (planar)
91 *planar = true;
92
93 return true;
94 }
95
96 return false;
97}
98
99static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
100 unsigned int bpp)
101{
102 fixed20_12 outf = dfixed_init(out);
103 fixed20_12 inf = dfixed_init(in);
104 u32 dda_inc;
105 int max;
106
107 if (v)
108 max = 15;
109 else {
110 switch (bpp) {
111 case 2:
112 max = 8;
113 break;
114
115 default:
116 WARN_ON_ONCE(1);
117 /* fallthrough */
118 case 4:
119 max = 4;
120 break;
121 }
122 }
123
124 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
125 inf.full -= dfixed_const(1);
126
127 dda_inc = dfixed_div(inf, outf);
128 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
129
130 return dda_inc;
131}
132
133static inline u32 compute_initial_dda(unsigned int in)
134{
135 fixed20_12 inf = dfixed_init(in);
136 return dfixed_frac(inf);
137}
138
139static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
140 const struct tegra_dc_window *window)
141{
142 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
143 unsigned long value;
144 bool yuv, planar;
145
146 /*
147 * For YUV planar modes, the number of bytes per pixel takes into
148 * account only the luma component and therefore is 1.
149 */
150 yuv = tegra_dc_format_is_yuv(window->format, &planar);
151 if (!yuv)
152 bpp = window->bits_per_pixel / 8;
153 else
154 bpp = planar ? 1 : 2;
155
156 value = WINDOW_A_SELECT << index;
157 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
158
159 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
160 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
161
162 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
163 tegra_dc_writel(dc, value, DC_WIN_POSITION);
164
165 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
166 tegra_dc_writel(dc, value, DC_WIN_SIZE);
167
168 h_offset = window->src.x * bpp;
169 v_offset = window->src.y;
170 h_size = window->src.w * bpp;
171 v_size = window->src.h;
172
173 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
174 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
175
176 /*
177 * For DDA computations the number of bytes per pixel for YUV planar
178 * modes needs to take into account all Y, U and V components.
179 */
180 if (yuv && planar)
181 bpp = 2;
182
183 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
184 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
185
186 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
187 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
188
189 h_dda = compute_initial_dda(window->src.x);
190 v_dda = compute_initial_dda(window->src.y);
191
192 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
193 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
194
195 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
196 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
197
198 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
199
200 if (yuv && planar) {
201 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
202 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
203 value = window->stride[1] << 16 | window->stride[0];
204 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
205 } else {
206 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
207 }
208
209 if (window->bottom_up)
210 v_offset += window->src.h - 1;
211
212 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
213 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
214
215 if (window->tiled) {
216 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
217 DC_WIN_BUFFER_ADDR_MODE_TILE;
218 } else {
219 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
220 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
221 }
222
223 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
224
225 value = WIN_ENABLE;
226
227 if (yuv) {
228 /* setup default colorspace conversion coefficients */
229 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
230 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
231 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
232 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
233 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
234 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
235 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
236 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
237
238 value |= CSC_ENABLE;
239 } else if (window->bits_per_pixel < 24) {
240 value |= COLOR_EXPAND;
241 }
242
243 if (window->bottom_up)
244 value |= V_DIRECTION;
245
246 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
247
248 /*
249 * Disable blending and assume Window A is the bottom-most window,
250 * Window C is the top-most window and Window B is in the middle.
251 */
252 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
253 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
254
255 switch (index) {
256 case 0:
257 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
258 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
259 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
260 break;
261
262 case 1:
263 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
264 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
265 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
266 break;
267
268 case 2:
269 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
270 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
271 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
272 break;
273 }
274
275 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
276 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
277
278 return 0;
279}
280
32static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, 281static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
33 struct drm_framebuffer *fb, int crtc_x, 282 struct drm_framebuffer *fb, int crtc_x,
34 int crtc_y, unsigned int crtc_w, 283 int crtc_y, unsigned int crtc_w,
@@ -49,7 +298,7 @@ static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
49 window.dst.y = crtc_y; 298 window.dst.y = crtc_y;
50 window.dst.w = crtc_w; 299 window.dst.w = crtc_w;
51 window.dst.h = crtc_h; 300 window.dst.h = crtc_h;
52 window.format = tegra_dc_format(fb->pixel_format); 301 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
53 window.bits_per_pixel = fb->bits_per_pixel; 302 window.bits_per_pixel = fb->bits_per_pixel;
54 window.bottom_up = tegra_fb_is_bottom_up(fb); 303 window.bottom_up = tegra_fb_is_bottom_up(fb);
55 window.tiled = tegra_fb_is_tiled(fb); 304 window.tiled = tegra_fb_is_tiled(fb);
@@ -117,6 +366,7 @@ static const uint32_t plane_formats[] = {
117 DRM_FORMAT_XRGB8888, 366 DRM_FORMAT_XRGB8888,
118 DRM_FORMAT_RGB565, 367 DRM_FORMAT_RGB565,
119 DRM_FORMAT_UYVY, 368 DRM_FORMAT_UYVY,
369 DRM_FORMAT_YUYV,
120 DRM_FORMAT_YUV420, 370 DRM_FORMAT_YUV420,
121 DRM_FORMAT_YUV422, 371 DRM_FORMAT_YUV422,
122}; 372};
@@ -150,9 +400,9 @@ static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
150static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, 400static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
151 struct drm_framebuffer *fb) 401 struct drm_framebuffer *fb)
152{ 402{
153 unsigned int format = tegra_dc_format(fb->pixel_format);
154 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); 403 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
155 unsigned int h_offset = 0, v_offset = 0; 404 unsigned int h_offset = 0, v_offset = 0;
405 unsigned int format, swap;
156 unsigned long value; 406 unsigned long value;
157 407
158 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); 408 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
@@ -162,7 +412,10 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
162 412
163 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR); 413 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
164 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE); 414 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
415
416 format = tegra_dc_format(fb->pixel_format, &swap);
165 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH); 417 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
418 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
166 419
167 if (tegra_fb_is_tiled(fb)) { 420 if (tegra_fb_is_tiled(fb)) {
168 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | 421 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
@@ -177,13 +430,13 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
177 /* make sure bottom-up buffers are properly displayed */ 430 /* make sure bottom-up buffers are properly displayed */
178 if (tegra_fb_is_bottom_up(fb)) { 431 if (tegra_fb_is_bottom_up(fb)) {
179 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); 432 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
180 value |= INVERT_V; 433 value |= V_DIRECTION;
181 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); 434 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
182 435
183 v_offset += fb->height - 1; 436 v_offset += fb->height - 1;
184 } else { 437 } else {
185 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); 438 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
186 value &= ~INVERT_V; 439 value &= ~V_DIRECTION;
187 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); 440 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
188 } 441 }
189 442
@@ -225,6 +478,109 @@ void tegra_dc_disable_vblank(struct tegra_dc *dc)
225 spin_unlock_irqrestore(&dc->lock, flags); 478 spin_unlock_irqrestore(&dc->lock, flags);
226} 479}
227 480
481static int tegra_dc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file,
482 uint32_t handle, uint32_t width,
483 uint32_t height, int32_t hot_x, int32_t hot_y)
484{
485 unsigned long value = CURSOR_CLIP_DISPLAY;
486 struct tegra_dc *dc = to_tegra_dc(crtc);
487 struct drm_gem_object *gem;
488 struct tegra_bo *bo = NULL;
489
490 if (!dc->soc->supports_cursor)
491 return -ENXIO;
492
493 if (width != height)
494 return -EINVAL;
495
496 switch (width) {
497 case 32:
498 value |= CURSOR_SIZE_32x32;
499 break;
500
501 case 64:
502 value |= CURSOR_SIZE_64x64;
503 break;
504
505 case 128:
506 value |= CURSOR_SIZE_128x128;
507
508 case 256:
509 value |= CURSOR_SIZE_256x256;
510 break;
511
512 default:
513 return -EINVAL;
514 }
515
516 if (handle) {
517 gem = drm_gem_object_lookup(crtc->dev, file, handle);
518 if (!gem)
519 return -ENOENT;
520
521 bo = to_tegra_bo(gem);
522 }
523
524 if (bo) {
525 unsigned long addr = (bo->paddr & 0xfffffc00) >> 10;
526#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
527 unsigned long high = (bo->paddr & 0xfffffffc) >> 32;
528#endif
529
530 tegra_dc_writel(dc, value | addr, DC_DISP_CURSOR_START_ADDR);
531
532#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
533 tegra_dc_writel(dc, high, DC_DISP_CURSOR_START_ADDR_HI);
534#endif
535
536 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
537 value |= CURSOR_ENABLE;
538 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
539
540 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
541 value &= ~CURSOR_DST_BLEND_MASK;
542 value &= ~CURSOR_SRC_BLEND_MASK;
543 value |= CURSOR_MODE_NORMAL;
544 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
545 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
546 value |= CURSOR_ALPHA;
547 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
548 } else {
549 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
550 value &= ~CURSOR_ENABLE;
551 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
552 }
553
554 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
555 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
556
557 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
558 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
559
560 return 0;
561}
562
563static int tegra_dc_cursor_move(struct drm_crtc *crtc, int x, int y)
564{
565 struct tegra_dc *dc = to_tegra_dc(crtc);
566 unsigned long value;
567
568 if (!dc->soc->supports_cursor)
569 return -ENXIO;
570
571 value = ((y & 0x3fff) << 16) | (x & 0x3fff);
572 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
573
574 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
575 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
576
577 /* XXX: only required on generations earlier than Tegra124? */
578 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
579 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
580
581 return 0;
582}
583
228static void tegra_dc_finish_page_flip(struct tegra_dc *dc) 584static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
229{ 585{
230 struct drm_device *drm = dc->base.dev; 586 struct drm_device *drm = dc->base.dev;
@@ -301,6 +657,8 @@ static void tegra_dc_destroy(struct drm_crtc *crtc)
301} 657}
302 658
303static const struct drm_crtc_funcs tegra_crtc_funcs = { 659static const struct drm_crtc_funcs tegra_crtc_funcs = {
660 .cursor_set2 = tegra_dc_cursor_set2,
661 .cursor_move = tegra_dc_cursor_move,
304 .page_flip = tegra_dc_page_flip, 662 .page_flip = tegra_dc_page_flip,
305 .set_config = drm_crtc_helper_set_config, 663 .set_config = drm_crtc_helper_set_config,
306 .destroy = tegra_dc_destroy, 664 .destroy = tegra_dc_destroy,
@@ -334,52 +692,11 @@ static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
334 return true; 692 return true;
335} 693}
336 694
337static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
338 unsigned int bpp)
339{
340 fixed20_12 outf = dfixed_init(out);
341 fixed20_12 inf = dfixed_init(in);
342 u32 dda_inc;
343 int max;
344
345 if (v)
346 max = 15;
347 else {
348 switch (bpp) {
349 case 2:
350 max = 8;
351 break;
352
353 default:
354 WARN_ON_ONCE(1);
355 /* fallthrough */
356 case 4:
357 max = 4;
358 break;
359 }
360 }
361
362 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
363 inf.full -= dfixed_const(1);
364
365 dda_inc = dfixed_div(inf, outf);
366 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
367
368 return dda_inc;
369}
370
371static inline u32 compute_initial_dda(unsigned int in)
372{
373 fixed20_12 inf = dfixed_init(in);
374 return dfixed_frac(inf);
375}
376
377static int tegra_dc_set_timings(struct tegra_dc *dc, 695static int tegra_dc_set_timings(struct tegra_dc *dc,
378 struct drm_display_mode *mode) 696 struct drm_display_mode *mode)
379{ 697{
380 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */ 698 unsigned int h_ref_to_sync = 1;
381 unsigned int h_ref_to_sync = 0; 699 unsigned int v_ref_to_sync = 1;
382 unsigned int v_ref_to_sync = 0;
383 unsigned long value; 700 unsigned long value;
384 701
385 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 702 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
@@ -406,13 +723,14 @@ static int tegra_dc_set_timings(struct tegra_dc *dc,
406} 723}
407 724
408static int tegra_crtc_setup_clk(struct drm_crtc *crtc, 725static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
409 struct drm_display_mode *mode, 726 struct drm_display_mode *mode)
410 unsigned long *div)
411{ 727{
412 unsigned long pclk = mode->clock * 1000, rate; 728 unsigned long pclk = mode->clock * 1000;
413 struct tegra_dc *dc = to_tegra_dc(crtc); 729 struct tegra_dc *dc = to_tegra_dc(crtc);
414 struct tegra_output *output = NULL; 730 struct tegra_output *output = NULL;
415 struct drm_encoder *encoder; 731 struct drm_encoder *encoder;
732 unsigned int div;
733 u32 value;
416 long err; 734 long err;
417 735
418 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head) 736 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
@@ -425,221 +743,23 @@ static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
425 return -ENODEV; 743 return -ENODEV;
426 744
427 /* 745 /*
428 * This assumes that the display controller will divide its parent 746 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
429 * clock by 2 to generate the pixel clock. 747 * respectively, each of which divides the base pll_d by 2.
430 */ 748 */
431 err = tegra_output_setup_clock(output, dc->clk, pclk * 2); 749 err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
432 if (err < 0) { 750 if (err < 0) {
433 dev_err(dc->dev, "failed to setup clock: %ld\n", err); 751 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
434 return err; 752 return err;
435 } 753 }
436 754
437 rate = clk_get_rate(dc->clk); 755 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
438 *div = (rate * 2 / pclk) - 2;
439
440 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
441
442 return 0;
443}
444
445static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
446{
447 switch (format) {
448 case WIN_COLOR_DEPTH_YCbCr422:
449 case WIN_COLOR_DEPTH_YUV422:
450 if (planar)
451 *planar = false;
452
453 return true;
454
455 case WIN_COLOR_DEPTH_YCbCr420P:
456 case WIN_COLOR_DEPTH_YUV420P:
457 case WIN_COLOR_DEPTH_YCbCr422P:
458 case WIN_COLOR_DEPTH_YUV422P:
459 case WIN_COLOR_DEPTH_YCbCr422R:
460 case WIN_COLOR_DEPTH_YUV422R:
461 case WIN_COLOR_DEPTH_YCbCr422RA:
462 case WIN_COLOR_DEPTH_YUV422RA:
463 if (planar)
464 *planar = true;
465
466 return true;
467 }
468
469 return false;
470}
471
472int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
473 const struct tegra_dc_window *window)
474{
475 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
476 unsigned long value;
477 bool yuv, planar;
478
479 /*
480 * For YUV planar modes, the number of bytes per pixel takes into
481 * account only the luma component and therefore is 1.
482 */
483 yuv = tegra_dc_format_is_yuv(window->format, &planar);
484 if (!yuv)
485 bpp = window->bits_per_pixel / 8;
486 else
487 bpp = planar ? 1 : 2;
488
489 value = WINDOW_A_SELECT << index;
490 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
491
492 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
493 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
494
495 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
496 tegra_dc_writel(dc, value, DC_WIN_POSITION);
497
498 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
499 tegra_dc_writel(dc, value, DC_WIN_SIZE);
500
501 h_offset = window->src.x * bpp;
502 v_offset = window->src.y;
503 h_size = window->src.w * bpp;
504 v_size = window->src.h;
505
506 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
507 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
508
509 /*
510 * For DDA computations the number of bytes per pixel for YUV planar
511 * modes needs to take into account all Y, U and V components.
512 */
513 if (yuv && planar)
514 bpp = 2;
515
516 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
517 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
518
519 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
520 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
521
522 h_dda = compute_initial_dda(window->src.x);
523 v_dda = compute_initial_dda(window->src.y);
524
525 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
526 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
527
528 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
529 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
530
531 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
532
533 if (yuv && planar) {
534 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
535 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
536 value = window->stride[1] << 16 | window->stride[0];
537 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
538 } else {
539 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
540 }
541
542 if (window->bottom_up)
543 v_offset += window->src.h - 1;
544 756
545 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); 757 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
546 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); 758 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
547
548 if (window->tiled) {
549 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
550 DC_WIN_BUFFER_ADDR_MODE_TILE;
551 } else {
552 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
553 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
554 }
555
556 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
557
558 value = WIN_ENABLE;
559
560 if (yuv) {
561 /* setup default colorspace conversion coefficients */
562 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
563 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
564 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
565 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
566 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
567 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
568 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
569 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
570
571 value |= CSC_ENABLE;
572 } else if (window->bits_per_pixel < 24) {
573 value |= COLOR_EXPAND;
574 }
575
576 if (window->bottom_up)
577 value |= INVERT_V;
578
579 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
580
581 /*
582 * Disable blending and assume Window A is the bottom-most window,
583 * Window C is the top-most window and Window B is in the middle.
584 */
585 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
586 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
587
588 switch (index) {
589 case 0:
590 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
591 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
592 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
593 break;
594
595 case 1:
596 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
597 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
598 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
599 break;
600
601 case 2:
602 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
603 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
604 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
605 break;
606 }
607
608 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
609 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
610 759
611 return 0; 760 return 0;
612} 761}
613 762
614unsigned int tegra_dc_format(uint32_t format)
615{
616 switch (format) {
617 case DRM_FORMAT_XBGR8888:
618 return WIN_COLOR_DEPTH_R8G8B8A8;
619
620 case DRM_FORMAT_XRGB8888:
621 return WIN_COLOR_DEPTH_B8G8R8A8;
622
623 case DRM_FORMAT_RGB565:
624 return WIN_COLOR_DEPTH_B5G6R5;
625
626 case DRM_FORMAT_UYVY:
627 return WIN_COLOR_DEPTH_YCbCr422;
628
629 case DRM_FORMAT_YUV420:
630 return WIN_COLOR_DEPTH_YCbCr420P;
631
632 case DRM_FORMAT_YUV422:
633 return WIN_COLOR_DEPTH_YCbCr422P;
634
635 default:
636 break;
637 }
638
639 WARN(1, "unsupported pixel format %u, using default\n", format);
640 return WIN_COLOR_DEPTH_B8G8R8A8;
641}
642
643static int tegra_crtc_mode_set(struct drm_crtc *crtc, 763static int tegra_crtc_mode_set(struct drm_crtc *crtc,
644 struct drm_display_mode *mode, 764 struct drm_display_mode *mode,
645 struct drm_display_mode *adjusted, 765 struct drm_display_mode *adjusted,
@@ -648,12 +768,12 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc,
648 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0); 768 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
649 struct tegra_dc *dc = to_tegra_dc(crtc); 769 struct tegra_dc *dc = to_tegra_dc(crtc);
650 struct tegra_dc_window window; 770 struct tegra_dc_window window;
651 unsigned long div, value; 771 u32 value;
652 int err; 772 int err;
653 773
654 drm_vblank_pre_modeset(crtc->dev, dc->pipe); 774 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
655 775
656 err = tegra_crtc_setup_clk(crtc, mode, &div); 776 err = tegra_crtc_setup_clk(crtc, mode);
657 if (err) { 777 if (err) {
658 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err); 778 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
659 return err; 779 return err;
@@ -669,9 +789,6 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc,
669 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); 789 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
670 } 790 }
671 791
672 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
673 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
674
675 /* setup window parameters */ 792 /* setup window parameters */
676 memset(&window, 0, sizeof(window)); 793 memset(&window, 0, sizeof(window));
677 window.src.x = 0; 794 window.src.x = 0;
@@ -682,7 +799,8 @@ static int tegra_crtc_mode_set(struct drm_crtc *crtc,
682 window.dst.y = 0; 799 window.dst.y = 0;
683 window.dst.w = mode->hdisplay; 800 window.dst.w = mode->hdisplay;
684 window.dst.h = mode->vdisplay; 801 window.dst.h = mode->vdisplay;
685 window.format = tegra_dc_format(crtc->primary->fb->pixel_format); 802 window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
803 &window.swap);
686 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel; 804 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
687 window.stride[0] = crtc->primary->fb->pitches[0]; 805 window.stride[0] = crtc->primary->fb->pitches[0];
688 window.base[0] = bo->paddr; 806 window.base[0] = bo->paddr;
@@ -728,10 +846,6 @@ static void tegra_crtc_prepare(struct drm_crtc *crtc)
728 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 846 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
729 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 847 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
730 848
731 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
732 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
733 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
734
735 /* initialize timer */ 849 /* initialize timer */
736 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 850 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
737 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 851 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
@@ -991,6 +1105,8 @@ static int tegra_dc_show_regs(struct seq_file *s, void *data)
991 DUMP_REG(DC_DISP_SD_BL_CONTROL); 1105 DUMP_REG(DC_DISP_SD_BL_CONTROL);
992 DUMP_REG(DC_DISP_SD_HW_K_VALUES); 1106 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
993 DUMP_REG(DC_DISP_SD_MAN_K_VALUES); 1107 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1108 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1109 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
994 DUMP_REG(DC_WIN_WIN_OPTIONS); 1110 DUMP_REG(DC_WIN_WIN_OPTIONS);
995 DUMP_REG(DC_WIN_BYTE_SWAP); 1111 DUMP_REG(DC_WIN_BYTE_SWAP);
996 DUMP_REG(DC_WIN_BUFFER_CONTROL); 1112 DUMP_REG(DC_WIN_BUFFER_CONTROL);
@@ -1096,26 +1212,26 @@ static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1096 1212
1097static int tegra_dc_init(struct host1x_client *client) 1213static int tegra_dc_init(struct host1x_client *client)
1098{ 1214{
1099 struct tegra_drm *tegra = dev_get_drvdata(client->parent); 1215 struct drm_device *drm = dev_get_drvdata(client->parent);
1100 struct tegra_dc *dc = host1x_client_to_dc(client); 1216 struct tegra_dc *dc = host1x_client_to_dc(client);
1101 int err; 1217 int err;
1102 1218
1103 drm_crtc_init(tegra->drm, &dc->base, &tegra_crtc_funcs); 1219 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
1104 drm_mode_crtc_set_gamma_size(&dc->base, 256); 1220 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1105 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); 1221 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1106 1222
1107 err = tegra_dc_rgb_init(tegra->drm, dc); 1223 err = tegra_dc_rgb_init(drm, dc);
1108 if (err < 0 && err != -ENODEV) { 1224 if (err < 0 && err != -ENODEV) {
1109 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); 1225 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1110 return err; 1226 return err;
1111 } 1227 }
1112 1228
1113 err = tegra_dc_add_planes(tegra->drm, dc); 1229 err = tegra_dc_add_planes(drm, dc);
1114 if (err < 0) 1230 if (err < 0)
1115 return err; 1231 return err;
1116 1232
1117 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1233 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1118 err = tegra_dc_debugfs_init(dc, tegra->drm->primary); 1234 err = tegra_dc_debugfs_init(dc, drm->primary);
1119 if (err < 0) 1235 if (err < 0)
1120 dev_err(dc->dev, "debugfs setup failed: %d\n", err); 1236 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1121 } 1237 }
@@ -1160,14 +1276,17 @@ static const struct host1x_client_ops dc_client_ops = {
1160 1276
1161static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 1277static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1162 .supports_interlacing = false, 1278 .supports_interlacing = false,
1279 .supports_cursor = false,
1163}; 1280};
1164 1281
1165static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 1282static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1166 .supports_interlacing = false, 1283 .supports_interlacing = false,
1284 .supports_cursor = false,
1167}; 1285};
1168 1286
1169static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 1287static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1170 .supports_interlacing = true, 1288 .supports_interlacing = true,
1289 .supports_cursor = true,
1171}; 1290};
1172 1291
1173static const struct of_device_id tegra_dc_of_match[] = { 1292static const struct of_device_id tegra_dc_of_match[] = {
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h
index c94101494826..78c5feff95d2 100644
--- a/drivers/gpu/drm/tegra/dc.h
+++ b/drivers/gpu/drm/tegra/dc.h
@@ -67,10 +67,12 @@
67#define WIN_A_ACT_REQ (1 << 1) 67#define WIN_A_ACT_REQ (1 << 1)
68#define WIN_B_ACT_REQ (1 << 2) 68#define WIN_B_ACT_REQ (1 << 2)
69#define WIN_C_ACT_REQ (1 << 3) 69#define WIN_C_ACT_REQ (1 << 3)
70#define CURSOR_ACT_REQ (1 << 7)
70#define GENERAL_UPDATE (1 << 8) 71#define GENERAL_UPDATE (1 << 8)
71#define WIN_A_UPDATE (1 << 9) 72#define WIN_A_UPDATE (1 << 9)
72#define WIN_B_UPDATE (1 << 10) 73#define WIN_B_UPDATE (1 << 10)
73#define WIN_C_UPDATE (1 << 11) 74#define WIN_C_UPDATE (1 << 11)
75#define CURSOR_UPDATE (1 << 15)
74#define NC_HOST_TRIG (1 << 24) 76#define NC_HOST_TRIG (1 << 24)
75 77
76#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 78#define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
@@ -116,9 +118,10 @@
116#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 118#define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
117 119
118#define DC_DISP_DISP_WIN_OPTIONS 0x402 120#define DC_DISP_DISP_WIN_OPTIONS 0x402
119#define HDMI_ENABLE (1 << 30) 121#define HDMI_ENABLE (1 << 30)
120#define DSI_ENABLE (1 << 29) 122#define DSI_ENABLE (1 << 29)
121#define SOR_ENABLE (1 << 25) 123#define SOR_ENABLE (1 << 25)
124#define CURSOR_ENABLE (1 << 16)
122 125
123#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 126#define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
124#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) 127#define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
@@ -266,6 +269,14 @@
266#define DC_DISP_CURSOR_BACKGROUND 0x43d 269#define DC_DISP_CURSOR_BACKGROUND 0x43d
267 270
268#define DC_DISP_CURSOR_START_ADDR 0x43e 271#define DC_DISP_CURSOR_START_ADDR 0x43e
272#define CURSOR_CLIP_DISPLAY (0 << 28)
273#define CURSOR_CLIP_WIN_A (1 << 28)
274#define CURSOR_CLIP_WIN_B (2 << 28)
275#define CURSOR_CLIP_WIN_C (3 << 28)
276#define CURSOR_SIZE_32x32 (0 << 24)
277#define CURSOR_SIZE_64x64 (1 << 24)
278#define CURSOR_SIZE_128x128 (2 << 24)
279#define CURSOR_SIZE_256x256 (3 << 24)
269#define DC_DISP_CURSOR_START_ADDR_NS 0x43f 280#define DC_DISP_CURSOR_START_ADDR_NS 0x43f
270 281
271#define DC_DISP_CURSOR_POSITION 0x440 282#define DC_DISP_CURSOR_POSITION 0x440
@@ -302,6 +313,19 @@
302#define INTERLACE_START (1 << 1) 313#define INTERLACE_START (1 << 1)
303#define INTERLACE_ENABLE (1 << 0) 314#define INTERLACE_ENABLE (1 << 0)
304 315
316#define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
317#define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
318#define CURSOR_MODE_LEGACY (0 << 24)
319#define CURSOR_MODE_NORMAL (1 << 24)
320#define CURSOR_DST_BLEND_ZERO (0 << 16)
321#define CURSOR_DST_BLEND_K1 (1 << 16)
322#define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16)
323#define CURSOR_DST_BLEND_MASK (3 << 16)
324#define CURSOR_SRC_BLEND_K1 (0 << 8)
325#define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8)
326#define CURSOR_SRC_BLEND_MASK (3 << 8)
327#define CURSOR_ALPHA 0xff
328
305#define DC_WIN_CSC_YOF 0x611 329#define DC_WIN_CSC_YOF 0x611
306#define DC_WIN_CSC_KYRGB 0x612 330#define DC_WIN_CSC_KYRGB 0x612
307#define DC_WIN_CSC_KUR 0x613 331#define DC_WIN_CSC_KUR 0x613
@@ -312,7 +336,8 @@
312#define DC_WIN_CSC_KVB 0x618 336#define DC_WIN_CSC_KVB 0x618
313 337
314#define DC_WIN_WIN_OPTIONS 0x700 338#define DC_WIN_WIN_OPTIONS 0x700
315#define INVERT_V (1 << 2) 339#define H_DIRECTION (1 << 0)
340#define V_DIRECTION (1 << 2)
316#define COLOR_EXPAND (1 << 6) 341#define COLOR_EXPAND (1 << 6)
317#define CSC_ENABLE (1 << 18) 342#define CSC_ENABLE (1 << 18)
318#define WIN_ENABLE (1 << 30) 343#define WIN_ENABLE (1 << 30)
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c
index 2b725ba7facc..3f132e356e9c 100644
--- a/drivers/gpu/drm/tegra/dpaux.c
+++ b/drivers/gpu/drm/tegra/dpaux.c
@@ -15,6 +15,7 @@
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/reset.h> 16#include <linux/reset.h>
17#include <linux/regulator/consumer.h> 17#include <linux/regulator/consumer.h>
18#include <linux/workqueue.h>
18 19
19#include <drm/drm_dp_helper.h> 20#include <drm/drm_dp_helper.h>
20#include <drm/drm_panel.h> 21#include <drm/drm_panel.h>
@@ -41,6 +42,7 @@ struct tegra_dpaux {
41 struct regulator *vdd; 42 struct regulator *vdd;
42 43
43 struct completion complete; 44 struct completion complete;
45 struct work_struct work;
44 struct list_head list; 46 struct list_head list;
45}; 47};
46 48
@@ -49,6 +51,11 @@ static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux)
49 return container_of(aux, struct tegra_dpaux, aux); 51 return container_of(aux, struct tegra_dpaux, aux);
50} 52}
51 53
54static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work)
55{
56 return container_of(work, struct tegra_dpaux, work);
57}
58
52static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux, 59static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux,
53 unsigned long offset) 60 unsigned long offset)
54{ 61{
@@ -231,6 +238,14 @@ static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux,
231 return ret; 238 return ret;
232} 239}
233 240
241static void tegra_dpaux_hotplug(struct work_struct *work)
242{
243 struct tegra_dpaux *dpaux = work_to_dpaux(work);
244
245 if (dpaux->output)
246 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
247}
248
234static irqreturn_t tegra_dpaux_irq(int irq, void *data) 249static irqreturn_t tegra_dpaux_irq(int irq, void *data)
235{ 250{
236 struct tegra_dpaux *dpaux = data; 251 struct tegra_dpaux *dpaux = data;
@@ -241,16 +256,8 @@ static irqreturn_t tegra_dpaux_irq(int irq, void *data)
241 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX); 256 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX);
242 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); 257 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX);
243 258
244 if (value & DPAUX_INTR_PLUG_EVENT) { 259 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT))
245 if (dpaux->output) { 260 schedule_work(&dpaux->work);
246 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
247 }
248 }
249
250 if (value & DPAUX_INTR_UNPLUG_EVENT) {
251 if (dpaux->output)
252 drm_helper_hpd_irq_event(dpaux->output->connector.dev);
253 }
254 261
255 if (value & DPAUX_INTR_IRQ_EVENT) { 262 if (value & DPAUX_INTR_IRQ_EVENT) {
256 /* TODO: handle this */ 263 /* TODO: handle this */
@@ -273,6 +280,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
273 if (!dpaux) 280 if (!dpaux)
274 return -ENOMEM; 281 return -ENOMEM;
275 282
283 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug);
276 init_completion(&dpaux->complete); 284 init_completion(&dpaux->complete);
277 INIT_LIST_HEAD(&dpaux->list); 285 INIT_LIST_HEAD(&dpaux->list);
278 dpaux->dev = &pdev->dev; 286 dpaux->dev = &pdev->dev;
@@ -361,6 +369,8 @@ static int tegra_dpaux_remove(struct platform_device *pdev)
361 list_del(&dpaux->list); 369 list_del(&dpaux->list);
362 mutex_unlock(&dpaux_lock); 370 mutex_unlock(&dpaux_lock);
363 371
372 cancel_work_sync(&dpaux->work);
373
364 clk_disable_unprepare(dpaux->clk_parent); 374 clk_disable_unprepare(dpaux->clk_parent);
365 reset_control_assert(dpaux->rst); 375 reset_control_assert(dpaux->rst);
366 clk_disable_unprepare(dpaux->clk); 376 clk_disable_unprepare(dpaux->clk);
@@ -404,6 +414,7 @@ int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output)
404 unsigned long timeout; 414 unsigned long timeout;
405 int err; 415 int err;
406 416
417 output->connector.polled = DRM_CONNECTOR_POLL_HPD;
407 dpaux->output = output; 418 dpaux->output = output;
408 419
409 err = regulator_enable(dpaux->vdd); 420 err = regulator_enable(dpaux->vdd);
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
index 6f5b6e2f552e..3396f9f6a9f7 100644
--- a/drivers/gpu/drm/tegra/drm.c
+++ b/drivers/gpu/drm/tegra/drm.c
@@ -33,7 +33,6 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
33 if (!tegra) 33 if (!tegra)
34 return -ENOMEM; 34 return -ENOMEM;
35 35
36 dev_set_drvdata(drm->dev, tegra);
37 mutex_init(&tegra->clients_lock); 36 mutex_init(&tegra->clients_lock);
38 INIT_LIST_HEAD(&tegra->clients); 37 INIT_LIST_HEAD(&tegra->clients);
39 drm->dev_private = tegra; 38 drm->dev_private = tegra;
@@ -640,14 +639,40 @@ int tegra_drm_unregister_client(struct tegra_drm *tegra,
640 return 0; 639 return 0;
641} 640}
642 641
643static int host1x_drm_probe(struct host1x_device *device) 642static int host1x_drm_probe(struct host1x_device *dev)
644{ 643{
645 return drm_host1x_init(&tegra_drm_driver, device); 644 struct drm_driver *driver = &tegra_drm_driver;
645 struct drm_device *drm;
646 int err;
647
648 drm = drm_dev_alloc(driver, &dev->dev);
649 if (!drm)
650 return -ENOMEM;
651
652 drm_dev_set_unique(drm, dev_name(&dev->dev));
653 dev_set_drvdata(&dev->dev, drm);
654
655 err = drm_dev_register(drm, 0);
656 if (err < 0)
657 goto unref;
658
659 DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n", driver->name,
660 driver->major, driver->minor, driver->patchlevel,
661 driver->date, drm->primary->index);
662
663 return 0;
664
665unref:
666 drm_dev_unref(drm);
667 return err;
646} 668}
647 669
648static int host1x_drm_remove(struct host1x_device *device) 670static int host1x_drm_remove(struct host1x_device *dev)
649{ 671{
650 drm_host1x_exit(&tegra_drm_driver, device); 672 struct drm_device *drm = dev_get_drvdata(&dev->dev);
673
674 drm_dev_unregister(drm);
675 drm_dev_unref(drm);
651 676
652 return 0; 677 return 0;
653} 678}
@@ -666,6 +691,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
666 { .compatible = "nvidia,tegra114-gr3d", }, 691 { .compatible = "nvidia,tegra114-gr3d", },
667 { .compatible = "nvidia,tegra124-dc", }, 692 { .compatible = "nvidia,tegra124-dc", },
668 { .compatible = "nvidia,tegra124-sor", }, 693 { .compatible = "nvidia,tegra124-sor", },
694 { .compatible = "nvidia,tegra124-hdmi", },
669 { /* sentinel */ } 695 { /* sentinel */ }
670}; 696};
671 697
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 126332c3ecbb..6b8fe9d86ed4 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -80,13 +80,13 @@ host1x_to_drm_client(struct host1x_client *client)
80 return container_of(client, struct tegra_drm_client, base); 80 return container_of(client, struct tegra_drm_client, base);
81} 81}
82 82
83extern int tegra_drm_register_client(struct tegra_drm *tegra, 83int tegra_drm_register_client(struct tegra_drm *tegra,
84 struct tegra_drm_client *client); 84 struct tegra_drm_client *client);
85extern int tegra_drm_unregister_client(struct tegra_drm *tegra, 85int tegra_drm_unregister_client(struct tegra_drm *tegra,
86 struct tegra_drm_client *client); 86 struct tegra_drm_client *client);
87 87
88extern int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); 88int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm);
89extern int tegra_drm_exit(struct tegra_drm *tegra); 89int tegra_drm_exit(struct tegra_drm *tegra);
90 90
91struct tegra_dc_soc_info; 91struct tegra_dc_soc_info;
92struct tegra_output; 92struct tegra_output;
@@ -156,6 +156,7 @@ struct tegra_dc_window {
156 } dst; 156 } dst;
157 unsigned int bits_per_pixel; 157 unsigned int bits_per_pixel;
158 unsigned int format; 158 unsigned int format;
159 unsigned int swap;
159 unsigned int stride[2]; 160 unsigned int stride[2];
160 unsigned long base[3]; 161 unsigned long base[3];
161 bool bottom_up; 162 bool bottom_up;
@@ -163,19 +164,15 @@ struct tegra_dc_window {
163}; 164};
164 165
165/* from dc.c */ 166/* from dc.c */
166extern unsigned int tegra_dc_format(uint32_t format); 167void tegra_dc_enable_vblank(struct tegra_dc *dc);
167extern int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, 168void tegra_dc_disable_vblank(struct tegra_dc *dc);
168 const struct tegra_dc_window *window); 169void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file);
169extern void tegra_dc_enable_vblank(struct tegra_dc *dc);
170extern void tegra_dc_disable_vblank(struct tegra_dc *dc);
171extern void tegra_dc_cancel_page_flip(struct drm_crtc *crtc,
172 struct drm_file *file);
173 170
174struct tegra_output_ops { 171struct tegra_output_ops {
175 int (*enable)(struct tegra_output *output); 172 int (*enable)(struct tegra_output *output);
176 int (*disable)(struct tegra_output *output); 173 int (*disable)(struct tegra_output *output);
177 int (*setup_clock)(struct tegra_output *output, struct clk *clk, 174 int (*setup_clock)(struct tegra_output *output, struct clk *clk,
178 unsigned long pclk); 175 unsigned long pclk, unsigned int *div);
179 int (*check_mode)(struct tegra_output *output, 176 int (*check_mode)(struct tegra_output *output,
180 struct drm_display_mode *mode, 177 struct drm_display_mode *mode,
181 enum drm_mode_status *status); 178 enum drm_mode_status *status);
@@ -233,10 +230,11 @@ static inline int tegra_output_disable(struct tegra_output *output)
233} 230}
234 231
235static inline int tegra_output_setup_clock(struct tegra_output *output, 232static inline int tegra_output_setup_clock(struct tegra_output *output,
236 struct clk *clk, unsigned long pclk) 233 struct clk *clk, unsigned long pclk,
234 unsigned int *div)
237{ 235{
238 if (output && output->ops && output->ops->setup_clock) 236 if (output && output->ops && output->ops->setup_clock)
239 return output->ops->setup_clock(output, clk, pclk); 237 return output->ops->setup_clock(output, clk, pclk, div);
240 238
241 return output ? -ENOSYS : -EINVAL; 239 return output ? -ENOSYS : -EINVAL;
242} 240}
@@ -251,27 +249,21 @@ static inline int tegra_output_check_mode(struct tegra_output *output,
251 return output ? -ENOSYS : -EINVAL; 249 return output ? -ENOSYS : -EINVAL;
252} 250}
253 251
254/* from bus.c */
255int drm_host1x_init(struct drm_driver *driver, struct host1x_device *device);
256void drm_host1x_exit(struct drm_driver *driver, struct host1x_device *device);
257
258/* from rgb.c */ 252/* from rgb.c */
259extern int tegra_dc_rgb_probe(struct tegra_dc *dc); 253int tegra_dc_rgb_probe(struct tegra_dc *dc);
260extern int tegra_dc_rgb_remove(struct tegra_dc *dc); 254int tegra_dc_rgb_remove(struct tegra_dc *dc);
261extern int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); 255int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc);
262extern int tegra_dc_rgb_exit(struct tegra_dc *dc); 256int tegra_dc_rgb_exit(struct tegra_dc *dc);
263 257
264/* from output.c */ 258/* from output.c */
265extern int tegra_output_probe(struct tegra_output *output); 259int tegra_output_probe(struct tegra_output *output);
266extern int tegra_output_remove(struct tegra_output *output); 260int tegra_output_remove(struct tegra_output *output);
267extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output); 261int tegra_output_init(struct drm_device *drm, struct tegra_output *output);
268extern int tegra_output_exit(struct tegra_output *output); 262int tegra_output_exit(struct tegra_output *output);
269 263
270/* from dpaux.c */ 264/* from dpaux.c */
271
272struct tegra_dpaux; 265struct tegra_dpaux;
273struct drm_dp_link; 266struct drm_dp_link;
274struct drm_dp_aux;
275 267
276struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np); 268struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np);
277enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux); 269enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux);
@@ -288,10 +280,10 @@ struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer,
288 unsigned int index); 280 unsigned int index);
289bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer); 281bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer);
290bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer); 282bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer);
291extern int tegra_drm_fb_init(struct drm_device *drm); 283int tegra_drm_fb_init(struct drm_device *drm);
292extern void tegra_drm_fb_exit(struct drm_device *drm); 284void tegra_drm_fb_exit(struct drm_device *drm);
293#ifdef CONFIG_DRM_TEGRA_FBDEV 285#ifdef CONFIG_DRM_TEGRA_FBDEV
294extern void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); 286void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev);
295#endif 287#endif
296 288
297extern struct platform_driver tegra_dc_driver; 289extern struct platform_driver tegra_dc_driver;
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 0e599f0417c0..bd56f2affa78 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -14,6 +14,8 @@
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/reset.h> 15#include <linux/reset.h>
16 16
17#include <linux/regulator/consumer.h>
18
17#include <drm/drm_mipi_dsi.h> 19#include <drm/drm_mipi_dsi.h>
18#include <drm/drm_panel.h> 20#include <drm/drm_panel.h>
19 21
@@ -43,11 +45,15 @@ struct tegra_dsi {
43 struct drm_minor *minor; 45 struct drm_minor *minor;
44 struct dentry *debugfs; 46 struct dentry *debugfs;
45 47
48 unsigned long flags;
46 enum mipi_dsi_pixel_format format; 49 enum mipi_dsi_pixel_format format;
47 unsigned int lanes; 50 unsigned int lanes;
48 51
49 struct tegra_mipi_device *mipi; 52 struct tegra_mipi_device *mipi;
50 struct mipi_dsi_host host; 53 struct mipi_dsi_host host;
54
55 struct regulator *vdd;
56 bool enabled;
51}; 57};
52 58
53static inline struct tegra_dsi * 59static inline struct tegra_dsi *
@@ -244,8 +250,10 @@ static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
244#define PKT_LP (1 << 30) 250#define PKT_LP (1 << 30)
245#define NUM_PKT_SEQ 12 251#define NUM_PKT_SEQ 12
246 252
247/* non-burst mode with sync-end */ 253/*
248static const u32 pkt_seq_vnb_syne[NUM_PKT_SEQ] = { 254 * non-burst mode with sync pulses
255 */
256static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
249 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 257 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
250 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 258 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
251 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 259 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
@@ -280,6 +288,36 @@ static const u32 pkt_seq_vnb_syne[NUM_PKT_SEQ] = {
280 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 288 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
281}; 289};
282 290
291/*
292 * non-burst mode with sync events
293 */
294static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
295 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
296 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
297 PKT_LP,
298 [ 1] = 0,
299 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
300 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
301 PKT_LP,
302 [ 3] = 0,
303 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
304 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
305 PKT_LP,
306 [ 5] = 0,
307 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
308 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
309 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
310 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
311 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
312 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
313 PKT_LP,
314 [ 9] = 0,
315 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
316 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
317 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
318 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
319};
320
283static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi) 321static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
284{ 322{
285 struct mipi_dphy_timing timing; 323 struct mipi_dphy_timing timing;
@@ -361,28 +399,70 @@ static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
361 return 0; 399 return 0;
362} 400}
363 401
402static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
403 enum tegra_dsi_format *fmt)
404{
405 switch (format) {
406 case MIPI_DSI_FMT_RGB888:
407 *fmt = TEGRA_DSI_FORMAT_24P;
408 break;
409
410 case MIPI_DSI_FMT_RGB666:
411 *fmt = TEGRA_DSI_FORMAT_18NP;
412 break;
413
414 case MIPI_DSI_FMT_RGB666_PACKED:
415 *fmt = TEGRA_DSI_FORMAT_18P;
416 break;
417
418 case MIPI_DSI_FMT_RGB565:
419 *fmt = TEGRA_DSI_FORMAT_16P;
420 break;
421
422 default:
423 return -EINVAL;
424 }
425
426 return 0;
427}
428
364static int tegra_output_dsi_enable(struct tegra_output *output) 429static int tegra_output_dsi_enable(struct tegra_output *output)
365{ 430{
366 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 431 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
367 struct drm_display_mode *mode = &dc->base.mode; 432 struct drm_display_mode *mode = &dc->base.mode;
368 unsigned int hact, hsw, hbp, hfp, i, mul, div; 433 unsigned int hact, hsw, hbp, hfp, i, mul, div;
369 struct tegra_dsi *dsi = to_dsi(output); 434 struct tegra_dsi *dsi = to_dsi(output);
370 /* FIXME: don't hardcode this */ 435 enum tegra_dsi_format format;
371 const u32 *pkt_seq = pkt_seq_vnb_syne;
372 unsigned long value; 436 unsigned long value;
437 const u32 *pkt_seq;
373 int err; 438 int err;
374 439
440 if (dsi->enabled)
441 return 0;
442
443 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
444 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
445 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
446 } else {
447 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
448 pkt_seq = pkt_seq_video_non_burst_sync_events;
449 }
450
375 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); 451 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
376 if (err < 0) 452 if (err < 0)
377 return err; 453 return err;
378 454
455 err = tegra_dsi_get_format(dsi->format, &format);
456 if (err < 0)
457 return err;
458
379 err = clk_enable(dsi->clk); 459 err = clk_enable(dsi->clk);
380 if (err < 0) 460 if (err < 0)
381 return err; 461 return err;
382 462
383 reset_control_deassert(dsi->rst); 463 reset_control_deassert(dsi->rst);
384 464
385 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(dsi->format) | 465 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
386 DSI_CONTROL_LANES(dsi->lanes - 1) | 466 DSI_CONTROL_LANES(dsi->lanes - 1) |
387 DSI_CONTROL_SOURCE(dc->pipe); 467 DSI_CONTROL_SOURCE(dc->pipe);
388 tegra_dsi_writel(dsi, value, DSI_CONTROL); 468 tegra_dsi_writel(dsi, value, DSI_CONTROL);
@@ -454,6 +534,8 @@ static int tegra_output_dsi_enable(struct tegra_output *output)
454 value |= DSI_POWER_CONTROL_ENABLE; 534 value |= DSI_POWER_CONTROL_ENABLE;
455 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 535 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
456 536
537 dsi->enabled = true;
538
457 return 0; 539 return 0;
458} 540}
459 541
@@ -463,9 +545,12 @@ static int tegra_output_dsi_disable(struct tegra_output *output)
463 struct tegra_dsi *dsi = to_dsi(output); 545 struct tegra_dsi *dsi = to_dsi(output);
464 unsigned long value; 546 unsigned long value;
465 547
548 if (!dsi->enabled)
549 return 0;
550
466 /* disable DSI controller */ 551 /* disable DSI controller */
467 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 552 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
468 value &= DSI_POWER_CONTROL_ENABLE; 553 value &= ~DSI_POWER_CONTROL_ENABLE;
469 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 554 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
470 555
471 /* 556 /*
@@ -492,30 +577,44 @@ static int tegra_output_dsi_disable(struct tegra_output *output)
492 577
493 clk_disable(dsi->clk); 578 clk_disable(dsi->clk);
494 579
580 dsi->enabled = false;
581
495 return 0; 582 return 0;
496} 583}
497 584
498static int tegra_output_dsi_setup_clock(struct tegra_output *output, 585static int tegra_output_dsi_setup_clock(struct tegra_output *output,
499 struct clk *clk, unsigned long pclk) 586 struct clk *clk, unsigned long pclk,
587 unsigned int *divp)
500{ 588{
501 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 589 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
502 struct drm_display_mode *mode = &dc->base.mode; 590 struct drm_display_mode *mode = &dc->base.mode;
503 unsigned int timeout, mul, div, vrefresh; 591 unsigned int timeout, mul, div, vrefresh;
504 struct tegra_dsi *dsi = to_dsi(output); 592 struct tegra_dsi *dsi = to_dsi(output);
505 unsigned long bclk, plld, value; 593 unsigned long bclk, plld, value;
506 struct clk *base;
507 int err; 594 int err;
508 595
509 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); 596 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
510 if (err < 0) 597 if (err < 0)
511 return err; 598 return err;
512 599
600 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, dsi->lanes);
513 vrefresh = drm_mode_vrefresh(mode); 601 vrefresh = drm_mode_vrefresh(mode);
602 DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh);
514 603
515 pclk = mode->htotal * mode->vtotal * vrefresh; 604 /* compute byte clock */
516 bclk = (pclk * mul) / (div * dsi->lanes); 605 bclk = (pclk * mul) / (div * dsi->lanes);
517 plld = DIV_ROUND_UP(bclk * 8, 1000000); 606
518 pclk = (plld * 1000000) / 2; 607 /*
608 * Compute bit clock and round up to the next MHz.
609 */
610 plld = DIV_ROUND_UP(bclk * 8, 1000000) * 1000000;
611
612 /*
613 * We divide the frequency by two here, but we make up for that by
614 * setting the shift clock divider (further below) to half of the
615 * correct value.
616 */
617 plld /= 2;
519 618
520 err = clk_set_parent(clk, dsi->clk_parent); 619 err = clk_set_parent(clk, dsi->clk_parent);
521 if (err < 0) { 620 if (err < 0) {
@@ -523,20 +622,26 @@ static int tegra_output_dsi_setup_clock(struct tegra_output *output,
523 return err; 622 return err;
524 } 623 }
525 624
526 base = clk_get_parent(dsi->clk_parent); 625 err = clk_set_rate(dsi->clk_parent, plld);
527
528 /*
529 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
530 * respectively, each of which divides the base pll_d by 2.
531 */
532 err = clk_set_rate(base, pclk * 2);
533 if (err < 0) { 626 if (err < 0) {
534 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n", 627 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n",
535 pclk * 2); 628 plld);
536 return err; 629 return err;
537 } 630 }
538 631
539 /* 632 /*
633 * Derive pixel clock from bit clock using the shift clock divider.
634 * Note that this is only half of what we would expect, but we need
635 * that to make up for the fact that we divided the bit clock by a
636 * factor of two above.
637 *
638 * It's not clear exactly why this is necessary, but the display is
639 * not working properly otherwise. Perhaps the PLLs cannot generate
640 * frequencies sufficiently high.
641 */
642 *divp = ((8 * mul) / (div * dsi->lanes)) - 2;
643
644 /*
540 * XXX: Move the below somewhere else so that we don't need to have 645 * XXX: Move the below somewhere else so that we don't need to have
541 * access to the vrefresh in this function? 646 * access to the vrefresh in this function?
542 */ 647 */
@@ -610,61 +715,32 @@ static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
610 715
611static int tegra_dsi_init(struct host1x_client *client) 716static int tegra_dsi_init(struct host1x_client *client)
612{ 717{
613 struct tegra_drm *tegra = dev_get_drvdata(client->parent); 718 struct drm_device *drm = dev_get_drvdata(client->parent);
614 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 719 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
615 unsigned long value, i;
616 int err; 720 int err;
617 721
618 dsi->output.type = TEGRA_OUTPUT_DSI; 722 dsi->output.type = TEGRA_OUTPUT_DSI;
619 dsi->output.dev = client->dev; 723 dsi->output.dev = client->dev;
620 dsi->output.ops = &dsi_ops; 724 dsi->output.ops = &dsi_ops;
621 725
622 err = tegra_output_init(tegra->drm, &dsi->output); 726 err = tegra_output_init(drm, &dsi->output);
623 if (err < 0) { 727 if (err < 0) {
624 dev_err(client->dev, "output setup failed: %d\n", err); 728 dev_err(client->dev, "output setup failed: %d\n", err);
625 return err; 729 return err;
626 } 730 }
627 731
628 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 732 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
629 err = tegra_dsi_debugfs_init(dsi, tegra->drm->primary); 733 err = tegra_dsi_debugfs_init(dsi, drm->primary);
630 if (err < 0) 734 if (err < 0)
631 dev_err(dsi->dev, "debugfs setup failed: %d\n", err); 735 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
632 } 736 }
633 737
634 /*
635 * enable high-speed mode, checksum generation, ECC generation and
636 * disable raw mode
637 */
638 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
639 value |= DSI_HOST_CONTROL_ECC | DSI_HOST_CONTROL_CS |
640 DSI_HOST_CONTROL_HS;
641 value &= ~DSI_HOST_CONTROL_RAW;
642 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
643
644 tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY);
645 tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD);
646
647 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
648
649 for (i = 0; i < 8; i++) {
650 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i);
651 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i);
652 }
653
654 for (i = 0; i < 12; i++)
655 tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i);
656
657 tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS);
658
659 err = tegra_dsi_pad_calibrate(dsi); 738 err = tegra_dsi_pad_calibrate(dsi);
660 if (err < 0) { 739 if (err < 0) {
661 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); 740 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
662 return err; 741 return err;
663 } 742 }
664 743
665 tegra_dsi_writel(dsi, DSI_POWER_CONTROL_ENABLE, DSI_POWER_CONTROL);
666 usleep_range(300, 1000);
667
668 return 0; 744 return 0;
669} 745}
670 746
@@ -715,66 +791,13 @@ static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
715 return 0; 791 return 0;
716} 792}
717 793
718static void tegra_dsi_initialize(struct tegra_dsi *dsi)
719{
720 unsigned int i;
721
722 tegra_dsi_writel(dsi, 0, DSI_POWER_CONTROL);
723
724 tegra_dsi_writel(dsi, 0, DSI_INT_ENABLE);
725 tegra_dsi_writel(dsi, 0, DSI_INT_STATUS);
726 tegra_dsi_writel(dsi, 0, DSI_INT_MASK);
727
728 tegra_dsi_writel(dsi, 0, DSI_HOST_CONTROL);
729 tegra_dsi_writel(dsi, 0, DSI_CONTROL);
730
731 tegra_dsi_writel(dsi, 0, DSI_SOL_DELAY);
732 tegra_dsi_writel(dsi, 0, DSI_MAX_THRESHOLD);
733
734 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL);
735
736 for (i = 0; i < 8; i++) {
737 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + i);
738 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_8 + i);
739 }
740
741 for (i = 0; i < 12; i++)
742 tegra_dsi_writel(dsi, 0, DSI_PKT_SEQ_0_LO + i);
743
744 tegra_dsi_writel(dsi, 0, DSI_DCS_CMDS);
745
746 for (i = 0; i < 4; i++)
747 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1 + i);
748
749 tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_0);
750 tegra_dsi_writel(dsi, 0x00000000, DSI_PHY_TIMING_1);
751 tegra_dsi_writel(dsi, 0x000000ff, DSI_PHY_TIMING_2);
752 tegra_dsi_writel(dsi, 0x00000000, DSI_BTA_TIMING);
753
754 tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_0);
755 tegra_dsi_writel(dsi, 0, DSI_TIMEOUT_1);
756 tegra_dsi_writel(dsi, 0, DSI_TO_TALLY);
757
758 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
759 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_CD);
760 tegra_dsi_writel(dsi, 0, DSI_PAD_CD_STATUS);
761 tegra_dsi_writel(dsi, 0, DSI_VIDEO_MODE_CONTROL);
762 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
763 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
764 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
765 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
766
767 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
768 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
769 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
770}
771
772static int tegra_dsi_host_attach(struct mipi_dsi_host *host, 794static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
773 struct mipi_dsi_device *device) 795 struct mipi_dsi_device *device)
774{ 796{
775 struct tegra_dsi *dsi = host_to_tegra(host); 797 struct tegra_dsi *dsi = host_to_tegra(host);
776 struct tegra_output *output = &dsi->output; 798 struct tegra_output *output = &dsi->output;
777 799
800 dsi->flags = device->mode_flags;
778 dsi->format = device->format; 801 dsi->format = device->format;
779 dsi->lanes = device->lanes; 802 dsi->lanes = device->lanes;
780 803
@@ -829,6 +852,7 @@ static int tegra_dsi_probe(struct platform_device *pdev)
829 * attaches to the DSI host, the parameters will be taken from 852 * attaches to the DSI host, the parameters will be taken from
830 * the attached device. 853 * the attached device.
831 */ 854 */
855 dsi->flags = MIPI_DSI_MODE_VIDEO;
832 dsi->format = MIPI_DSI_FMT_RGB888; 856 dsi->format = MIPI_DSI_FMT_RGB888;
833 dsi->lanes = 4; 857 dsi->lanes = 4;
834 858
@@ -872,6 +896,18 @@ static int tegra_dsi_probe(struct platform_device *pdev)
872 return err; 896 return err;
873 } 897 }
874 898
899 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
900 if (IS_ERR(dsi->vdd)) {
901 dev_err(&pdev->dev, "cannot get VDD supply\n");
902 return PTR_ERR(dsi->vdd);
903 }
904
905 err = regulator_enable(dsi->vdd);
906 if (err < 0) {
907 dev_err(&pdev->dev, "cannot enable VDD supply\n");
908 return err;
909 }
910
875 err = tegra_dsi_setup_clocks(dsi); 911 err = tegra_dsi_setup_clocks(dsi);
876 if (err < 0) { 912 if (err < 0) {
877 dev_err(&pdev->dev, "cannot setup clocks\n"); 913 dev_err(&pdev->dev, "cannot setup clocks\n");
@@ -883,8 +919,6 @@ static int tegra_dsi_probe(struct platform_device *pdev)
883 if (IS_ERR(dsi->regs)) 919 if (IS_ERR(dsi->regs))
884 return PTR_ERR(dsi->regs); 920 return PTR_ERR(dsi->regs);
885 921
886 tegra_dsi_initialize(dsi);
887
888 dsi->mipi = tegra_mipi_request(&pdev->dev); 922 dsi->mipi = tegra_mipi_request(&pdev->dev);
889 if (IS_ERR(dsi->mipi)) 923 if (IS_ERR(dsi->mipi))
890 return PTR_ERR(dsi->mipi); 924 return PTR_ERR(dsi->mipi);
@@ -929,9 +963,11 @@ static int tegra_dsi_remove(struct platform_device *pdev)
929 mipi_dsi_host_unregister(&dsi->host); 963 mipi_dsi_host_unregister(&dsi->host);
930 tegra_mipi_free(dsi->mipi); 964 tegra_mipi_free(dsi->mipi);
931 965
966 regulator_disable(dsi->vdd);
932 clk_disable_unprepare(dsi->clk_parent); 967 clk_disable_unprepare(dsi->clk_parent);
933 clk_disable_unprepare(dsi->clk_lp); 968 clk_disable_unprepare(dsi->clk_lp);
934 clk_disable_unprepare(dsi->clk); 969 clk_disable_unprepare(dsi->clk);
970 reset_control_assert(dsi->rst);
935 971
936 err = tegra_output_remove(&dsi->output); 972 err = tegra_output_remove(&dsi->output);
937 if (err < 0) { 973 if (err < 0) {
diff --git a/drivers/gpu/drm/tegra/dsi.h b/drivers/gpu/drm/tegra/dsi.h
index 1db5cc24ea91..5ce610d08d77 100644
--- a/drivers/gpu/drm/tegra/dsi.h
+++ b/drivers/gpu/drm/tegra/dsi.h
@@ -117,4 +117,14 @@
117#define DSI_INIT_SEQ_DATA_14 0x5e 117#define DSI_INIT_SEQ_DATA_14 0x5e
118#define DSI_INIT_SEQ_DATA_15 0x5f 118#define DSI_INIT_SEQ_DATA_15 0x5f
119 119
120/*
121 * pixel format as used in the DSI_CONTROL_FORMAT field
122 */
123enum tegra_dsi_format {
124 TEGRA_DSI_FORMAT_16P,
125 TEGRA_DSI_FORMAT_18NP,
126 TEGRA_DSI_FORMAT_18P,
127 TEGRA_DSI_FORMAT_24P,
128};
129
120#endif 130#endif
diff --git a/drivers/gpu/drm/tegra/gem.c b/drivers/gpu/drm/tegra/gem.c
index bcf9895cef9f..aa85b7b26f10 100644
--- a/drivers/gpu/drm/tegra/gem.c
+++ b/drivers/gpu/drm/tegra/gem.c
@@ -169,7 +169,8 @@ err:
169 return ERR_PTR(ret); 169 return ERR_PTR(ret);
170} 170}
171 171
172struct tegra_bo *tegra_bo_import(struct drm_device *drm, struct dma_buf *buf) 172static struct tegra_bo *tegra_bo_import(struct drm_device *drm,
173 struct dma_buf *buf)
173{ 174{
174 struct dma_buf_attachment *attach; 175 struct dma_buf_attachment *attach;
175 struct tegra_bo *bo; 176 struct tegra_bo *bo;
diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers/gpu/drm/tegra/gr2d.c
index 2c7ca748edf5..7c53941f2a9e 100644
--- a/drivers/gpu/drm/tegra/gr2d.c
+++ b/drivers/gpu/drm/tegra/gr2d.c
@@ -28,7 +28,7 @@ static inline struct gr2d *to_gr2d(struct tegra_drm_client *client)
28static int gr2d_init(struct host1x_client *client) 28static int gr2d_init(struct host1x_client *client)
29{ 29{
30 struct tegra_drm_client *drm = host1x_to_drm_client(client); 30 struct tegra_drm_client *drm = host1x_to_drm_client(client);
31 struct tegra_drm *tegra = dev_get_drvdata(client->parent); 31 struct drm_device *dev = dev_get_drvdata(client->parent);
32 unsigned long flags = HOST1X_SYNCPT_HAS_BASE; 32 unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
33 struct gr2d *gr2d = to_gr2d(drm); 33 struct gr2d *gr2d = to_gr2d(drm);
34 34
@@ -42,17 +42,17 @@ static int gr2d_init(struct host1x_client *client)
42 return -ENOMEM; 42 return -ENOMEM;
43 } 43 }
44 44
45 return tegra_drm_register_client(tegra, drm); 45 return tegra_drm_register_client(dev->dev_private, drm);
46} 46}
47 47
48static int gr2d_exit(struct host1x_client *client) 48static int gr2d_exit(struct host1x_client *client)
49{ 49{
50 struct tegra_drm_client *drm = host1x_to_drm_client(client); 50 struct tegra_drm_client *drm = host1x_to_drm_client(client);
51 struct tegra_drm *tegra = dev_get_drvdata(client->parent); 51 struct drm_device *dev = dev_get_drvdata(client->parent);
52 struct gr2d *gr2d = to_gr2d(drm); 52 struct gr2d *gr2d = to_gr2d(drm);
53 int err; 53 int err;
54 54
55 err = tegra_drm_unregister_client(tegra, drm); 55 err = tegra_drm_unregister_client(dev->dev_private, drm);
56 if (err < 0) 56 if (err < 0)
57 return err; 57 return err;
58 58
diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c
index 0cbb24b1ae04..30f5ba9bd6d0 100644
--- a/drivers/gpu/drm/tegra/gr3d.c
+++ b/drivers/gpu/drm/tegra/gr3d.c
@@ -37,7 +37,7 @@ static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
37static int gr3d_init(struct host1x_client *client) 37static int gr3d_init(struct host1x_client *client)
38{ 38{
39 struct tegra_drm_client *drm = host1x_to_drm_client(client); 39 struct tegra_drm_client *drm = host1x_to_drm_client(client);
40 struct tegra_drm *tegra = dev_get_drvdata(client->parent); 40 struct drm_device *dev = dev_get_drvdata(client->parent);
41 unsigned long flags = HOST1X_SYNCPT_HAS_BASE; 41 unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
42 struct gr3d *gr3d = to_gr3d(drm); 42 struct gr3d *gr3d = to_gr3d(drm);
43 43
@@ -51,17 +51,17 @@ static int gr3d_init(struct host1x_client *client)
51 return -ENOMEM; 51 return -ENOMEM;
52 } 52 }
53 53
54 return tegra_drm_register_client(tegra, drm); 54 return tegra_drm_register_client(dev->dev_private, drm);
55} 55}
56 56
57static int gr3d_exit(struct host1x_client *client) 57static int gr3d_exit(struct host1x_client *client)
58{ 58{
59 struct tegra_drm_client *drm = host1x_to_drm_client(client); 59 struct tegra_drm_client *drm = host1x_to_drm_client(client);
60 struct tegra_drm *tegra = dev_get_drvdata(client->parent); 60 struct drm_device *dev = dev_get_drvdata(client->parent);
61 struct gr3d *gr3d = to_gr3d(drm); 61 struct gr3d *gr3d = to_gr3d(drm);
62 int err; 62 int err;
63 63
64 err = tegra_drm_unregister_client(tegra, drm); 64 err = tegra_drm_unregister_client(dev->dev_private, drm);
65 if (err < 0) 65 if (err < 0)
66 return err; 66 return err;
67 67
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 6928015d11a4..ba067bb767e3 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -42,8 +42,9 @@ struct tegra_hdmi {
42 struct device *dev; 42 struct device *dev;
43 bool enabled; 43 bool enabled;
44 44
45 struct regulator *vdd; 45 struct regulator *hdmi;
46 struct regulator *pll; 46 struct regulator *pll;
47 struct regulator *vdd;
47 48
48 void __iomem *regs; 49 void __iomem *regs;
49 unsigned int irq; 50 unsigned int irq;
@@ -317,6 +318,85 @@ static const struct tmds_config tegra114_tmds_config[] = {
317 }, 318 },
318}; 319};
319 320
321static const struct tmds_config tegra124_tmds_config[] = {
322 { /* 480p/576p / 25.2MHz/27MHz modes */
323 .pclk = 27000000,
324 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
325 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
326 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
327 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
328 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
329 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
330 PE_CURRENT3(PE_CURRENT_0_mA_T114),
331 .drive_current =
332 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
333 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
334 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
335 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
336 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
337 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
338 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
339 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
340 }, { /* 720p / 74.25MHz modes */
341 .pclk = 74250000,
342 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
343 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
344 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
345 SOR_PLL_TMDS_TERMADJ(0),
346 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
347 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
348 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
349 PE_CURRENT3(PE_CURRENT_15_mA_T114),
350 .drive_current =
351 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
352 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
353 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
354 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
355 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
356 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
357 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
358 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
359 }, { /* 1080p / 148.5MHz modes */
360 .pclk = 148500000,
361 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
362 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
363 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
364 SOR_PLL_TMDS_TERMADJ(0),
365 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
366 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
367 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
368 PE_CURRENT3(PE_CURRENT_10_mA_T114),
369 .drive_current =
370 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
371 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
372 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
373 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
374 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
375 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
376 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
377 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
378 }, { /* 225/297MHz modes */
379 .pclk = UINT_MAX,
380 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
381 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
382 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
383 | SOR_PLL_TMDS_TERM_ENABLE,
384 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
385 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
386 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
387 PE_CURRENT3(PE_CURRENT_0_mA_T114),
388 .drive_current =
389 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
390 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
391 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
392 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
393 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
394 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
395 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
396 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
397 },
398};
399
320static const struct tegra_hdmi_audio_config * 400static const struct tegra_hdmi_audio_config *
321tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk) 401tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
322{ 402{
@@ -716,13 +796,9 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
716 return err; 796 return err;
717 } 797 }
718 798
719 /* 799 err = regulator_enable(hdmi->vdd);
720 * This assumes that the display controller will divide its parent
721 * clock by 2 to generate the pixel clock.
722 */
723 err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
724 if (err < 0) { 800 if (err < 0) {
725 dev_err(hdmi->dev, "failed to setup clock: %d\n", err); 801 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
726 return err; 802 return err;
727 } 803 }
728 804
@@ -730,7 +806,7 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
730 if (err < 0) 806 if (err < 0)
731 return err; 807 return err;
732 808
733 err = clk_enable(hdmi->clk); 809 err = clk_prepare_enable(hdmi->clk);
734 if (err < 0) { 810 if (err < 0) {
735 dev_err(hdmi->dev, "failed to enable clock: %d\n", err); 811 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
736 return err; 812 return err;
@@ -740,6 +816,17 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
740 usleep_range(1000, 2000); 816 usleep_range(1000, 2000);
741 reset_control_deassert(hdmi->rst); 817 reset_control_deassert(hdmi->rst);
742 818
819 /* power up sequence */
820 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
821 value &= ~SOR_PLL_PDBG;
822 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
823
824 usleep_range(10, 20);
825
826 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
827 value &= ~SOR_PLL_PWR;
828 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
829
743 tegra_dc_writel(dc, VSYNC_H_POSITION(1), 830 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
744 DC_DISP_DISP_TIMING_OPTIONS); 831 DC_DISP_DISP_TIMING_OPTIONS);
745 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888, 832 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
@@ -838,9 +925,13 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
838 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0)); 925 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
839 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8)); 926 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
840 927
841 value = 0x1c800; 928 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
842 value &= ~SOR_CSTM_ROTCLK(~0); 929 value &= ~SOR_CSTM_ROTCLK(~0);
843 value |= SOR_CSTM_ROTCLK(2); 930 value |= SOR_CSTM_ROTCLK(2);
931 value |= SOR_CSTM_PLLDIV;
932 value &= ~SOR_CSTM_LVDS_ENABLE;
933 value &= ~SOR_CSTM_MODE_MASK;
934 value |= SOR_CSTM_MODE_TMDS;
844 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM); 935 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
845 936
846 /* start SOR */ 937 /* start SOR */
@@ -930,10 +1021,18 @@ static int tegra_output_hdmi_disable(struct tegra_output *output)
930 * sure it's only executed when the output is attached to one. 1021 * sure it's only executed when the output is attached to one.
931 */ 1022 */
932 if (dc) { 1023 if (dc) {
1024 /*
1025 * XXX: We can't do this here because it causes HDMI to go
1026 * into an erroneous state with the result that HDMI won't
1027 * properly work once disabled. See also a similar symptom
1028 * for the SOR output.
1029 */
1030 /*
933 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 1031 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
934 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 1032 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
935 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 1033 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
936 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 1034 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1035 */
937 1036
938 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1037 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
939 value &= ~DISP_CTRL_MODE_MASK; 1038 value &= ~DISP_CTRL_MODE_MASK;
@@ -947,8 +1046,9 @@ static int tegra_output_hdmi_disable(struct tegra_output *output)
947 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 1046 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
948 } 1047 }
949 1048
1049 clk_disable_unprepare(hdmi->clk);
950 reset_control_assert(hdmi->rst); 1050 reset_control_assert(hdmi->rst);
951 clk_disable(hdmi->clk); 1051 regulator_disable(hdmi->vdd);
952 regulator_disable(hdmi->pll); 1052 regulator_disable(hdmi->pll);
953 1053
954 hdmi->enabled = false; 1054 hdmi->enabled = false;
@@ -957,10 +1057,10 @@ static int tegra_output_hdmi_disable(struct tegra_output *output)
957} 1057}
958 1058
959static int tegra_output_hdmi_setup_clock(struct tegra_output *output, 1059static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
960 struct clk *clk, unsigned long pclk) 1060 struct clk *clk, unsigned long pclk,
1061 unsigned int *div)
961{ 1062{
962 struct tegra_hdmi *hdmi = to_hdmi(output); 1063 struct tegra_hdmi *hdmi = to_hdmi(output);
963 struct clk *base;
964 int err; 1064 int err;
965 1065
966 err = clk_set_parent(clk, hdmi->clk_parent); 1066 err = clk_set_parent(clk, hdmi->clk_parent);
@@ -969,17 +1069,12 @@ static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
969 return err; 1069 return err;
970 } 1070 }
971 1071
972 base = clk_get_parent(hdmi->clk_parent); 1072 err = clk_set_rate(hdmi->clk_parent, pclk);
973
974 /*
975 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
976 * respectively, each of which divides the base pll_d by 2.
977 */
978 err = clk_set_rate(base, pclk * 2);
979 if (err < 0) 1073 if (err < 0)
980 dev_err(output->dev, 1074 dev_err(output->dev, "failed to set clock rate to %lu Hz\n",
981 "failed to set base clock rate to %lu Hz\n", 1075 pclk);
982 pclk * 2); 1076
1077 *div = 0;
983 1078
984 return 0; 1079 return 0;
985} 1080}
@@ -1017,7 +1112,7 @@ static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1017 struct tegra_hdmi *hdmi = node->info_ent->data; 1112 struct tegra_hdmi *hdmi = node->info_ent->data;
1018 int err; 1113 int err;
1019 1114
1020 err = clk_enable(hdmi->clk); 1115 err = clk_prepare_enable(hdmi->clk);
1021 if (err) 1116 if (err)
1022 return err; 1117 return err;
1023 1118
@@ -1186,7 +1281,7 @@ static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1186 1281
1187#undef DUMP_REG 1282#undef DUMP_REG
1188 1283
1189 clk_disable(hdmi->clk); 1284 clk_disable_unprepare(hdmi->clk);
1190 1285
1191 return 0; 1286 return 0;
1192} 1287}
@@ -1252,33 +1347,33 @@ static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1252 1347
1253static int tegra_hdmi_init(struct host1x_client *client) 1348static int tegra_hdmi_init(struct host1x_client *client)
1254{ 1349{
1255 struct tegra_drm *tegra = dev_get_drvdata(client->parent); 1350 struct drm_device *drm = dev_get_drvdata(client->parent);
1256 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1351 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1257 int err; 1352 int err;
1258 1353
1259 err = regulator_enable(hdmi->vdd);
1260 if (err < 0) {
1261 dev_err(client->dev, "failed to enable VDD regulator: %d\n",
1262 err);
1263 return err;
1264 }
1265
1266 hdmi->output.type = TEGRA_OUTPUT_HDMI; 1354 hdmi->output.type = TEGRA_OUTPUT_HDMI;
1267 hdmi->output.dev = client->dev; 1355 hdmi->output.dev = client->dev;
1268 hdmi->output.ops = &hdmi_ops; 1356 hdmi->output.ops = &hdmi_ops;
1269 1357
1270 err = tegra_output_init(tegra->drm, &hdmi->output); 1358 err = tegra_output_init(drm, &hdmi->output);
1271 if (err < 0) { 1359 if (err < 0) {
1272 dev_err(client->dev, "output setup failed: %d\n", err); 1360 dev_err(client->dev, "output setup failed: %d\n", err);
1273 return err; 1361 return err;
1274 } 1362 }
1275 1363
1276 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1364 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1277 err = tegra_hdmi_debugfs_init(hdmi, tegra->drm->primary); 1365 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1278 if (err < 0) 1366 if (err < 0)
1279 dev_err(client->dev, "debugfs setup failed: %d\n", err); 1367 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1280 } 1368 }
1281 1369
1370 err = regulator_enable(hdmi->hdmi);
1371 if (err < 0) {
1372 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1373 err);
1374 return err;
1375 }
1376
1282 return 0; 1377 return 0;
1283} 1378}
1284 1379
@@ -1287,6 +1382,8 @@ static int tegra_hdmi_exit(struct host1x_client *client)
1287 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client); 1382 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1288 int err; 1383 int err;
1289 1384
1385 regulator_disable(hdmi->hdmi);
1386
1290 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1387 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1291 err = tegra_hdmi_debugfs_exit(hdmi); 1388 err = tegra_hdmi_debugfs_exit(hdmi);
1292 if (err < 0) 1389 if (err < 0)
@@ -1306,8 +1403,6 @@ static int tegra_hdmi_exit(struct host1x_client *client)
1306 return err; 1403 return err;
1307 } 1404 }
1308 1405
1309 regulator_disable(hdmi->vdd);
1310
1311 return 0; 1406 return 0;
1312} 1407}
1313 1408
@@ -1340,7 +1435,16 @@ static const struct tegra_hdmi_config tegra114_hdmi_config = {
1340 .has_sor_io_peak_current = true, 1435 .has_sor_io_peak_current = true,
1341}; 1436};
1342 1437
1438static const struct tegra_hdmi_config tegra124_hdmi_config = {
1439 .tmds = tegra124_tmds_config,
1440 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1441 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1442 .fuse_override_value = 1 << 31,
1443 .has_sor_io_peak_current = true,
1444};
1445
1343static const struct of_device_id tegra_hdmi_of_match[] = { 1446static const struct of_device_id tegra_hdmi_of_match[] = {
1447 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1344 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config }, 1448 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1345 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config }, 1449 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1346 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config }, 1450 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
@@ -1381,28 +1485,20 @@ static int tegra_hdmi_probe(struct platform_device *pdev)
1381 return PTR_ERR(hdmi->rst); 1485 return PTR_ERR(hdmi->rst);
1382 } 1486 }
1383 1487
1384 err = clk_prepare(hdmi->clk);
1385 if (err < 0)
1386 return err;
1387
1388 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1488 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1389 if (IS_ERR(hdmi->clk_parent)) 1489 if (IS_ERR(hdmi->clk_parent))
1390 return PTR_ERR(hdmi->clk_parent); 1490 return PTR_ERR(hdmi->clk_parent);
1391 1491
1392 err = clk_prepare(hdmi->clk_parent);
1393 if (err < 0)
1394 return err;
1395
1396 err = clk_set_parent(hdmi->clk, hdmi->clk_parent); 1492 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1397 if (err < 0) { 1493 if (err < 0) {
1398 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err); 1494 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1399 return err; 1495 return err;
1400 } 1496 }
1401 1497
1402 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd"); 1498 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1403 if (IS_ERR(hdmi->vdd)) { 1499 if (IS_ERR(hdmi->hdmi)) {
1404 dev_err(&pdev->dev, "failed to get VDD regulator\n"); 1500 dev_err(&pdev->dev, "failed to get HDMI regulator\n");
1405 return PTR_ERR(hdmi->vdd); 1501 return PTR_ERR(hdmi->hdmi);
1406 } 1502 }
1407 1503
1408 hdmi->pll = devm_regulator_get(&pdev->dev, "pll"); 1504 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
@@ -1411,6 +1507,12 @@ static int tegra_hdmi_probe(struct platform_device *pdev)
1411 return PTR_ERR(hdmi->pll); 1507 return PTR_ERR(hdmi->pll);
1412 } 1508 }
1413 1509
1510 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1511 if (IS_ERR(hdmi->vdd)) {
1512 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1513 return PTR_ERR(hdmi->vdd);
1514 }
1515
1414 hdmi->output.dev = &pdev->dev; 1516 hdmi->output.dev = &pdev->dev;
1415 1517
1416 err = tegra_output_probe(&hdmi->output); 1518 err = tegra_output_probe(&hdmi->output);
@@ -1462,8 +1564,8 @@ static int tegra_hdmi_remove(struct platform_device *pdev)
1462 return err; 1564 return err;
1463 } 1565 }
1464 1566
1465 clk_unprepare(hdmi->clk_parent); 1567 clk_disable_unprepare(hdmi->clk_parent);
1466 clk_unprepare(hdmi->clk); 1568 clk_disable_unprepare(hdmi->clk);
1467 1569
1468 return 0; 1570 return 0;
1469} 1571}
diff --git a/drivers/gpu/drm/tegra/hdmi.h b/drivers/gpu/drm/tegra/hdmi.h
index 0aebc485f7fa..919a19df4e1b 100644
--- a/drivers/gpu/drm/tegra/hdmi.h
+++ b/drivers/gpu/drm/tegra/hdmi.h
@@ -190,6 +190,11 @@
190 190
191#define HDMI_NV_PDISP_SOR_CSTM 0x5a 191#define HDMI_NV_PDISP_SOR_CSTM 0x5a
192#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24) 192#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
193#define SOR_CSTM_PLLDIV (1 << 21)
194#define SOR_CSTM_LVDS_ENABLE (1 << 16)
195#define SOR_CSTM_MODE_LVDS (0 << 12)
196#define SOR_CSTM_MODE_TMDS (1 << 12)
197#define SOR_CSTM_MODE_MASK (3 << 12)
193 198
194#define HDMI_NV_PDISP_SOR_LVDS 0x5b 199#define HDMI_NV_PDISP_SOR_LVDS 0x5b
195#define HDMI_NV_PDISP_SOR_CRCA 0x5c 200#define HDMI_NV_PDISP_SOR_CRCA 0x5c
diff --git a/drivers/gpu/drm/tegra/rgb.c b/drivers/gpu/drm/tegra/rgb.c
index 0266fb40479e..d6af9be48f42 100644
--- a/drivers/gpu/drm/tegra/rgb.c
+++ b/drivers/gpu/drm/tegra/rgb.c
@@ -159,11 +159,38 @@ static int tegra_output_rgb_disable(struct tegra_output *output)
159} 159}
160 160
161static int tegra_output_rgb_setup_clock(struct tegra_output *output, 161static int tegra_output_rgb_setup_clock(struct tegra_output *output,
162 struct clk *clk, unsigned long pclk) 162 struct clk *clk, unsigned long pclk,
163 unsigned int *div)
163{ 164{
164 struct tegra_rgb *rgb = to_rgb(output); 165 struct tegra_rgb *rgb = to_rgb(output);
166 int err;
167
168 err = clk_set_parent(clk, rgb->clk_parent);
169 if (err < 0) {
170 dev_err(output->dev, "failed to set parent: %d\n", err);
171 return err;
172 }
165 173
166 return clk_set_parent(clk, rgb->clk_parent); 174 /*
175 * We may not want to change the frequency of the parent clock, since
176 * it may be a parent for other peripherals. This is due to the fact
177 * that on Tegra20 there's only a single clock dedicated to display
178 * (pll_d_out0), whereas later generations have a second one that can
179 * be used to independently drive a second output (pll_d2_out0).
180 *
181 * As a way to support multiple outputs on Tegra20 as well, pll_p is
182 * typically used as the parent clock for the display controllers.
183 * But this comes at a cost: pll_p is the parent of several other
184 * peripherals, so its frequency shouldn't change out of the blue.
185 *
186 * The best we can do at this point is to use the shift clock divider
187 * and hope that the desired frequency can be matched (or at least
188 * matched sufficiently close that the panel will still work).
189 */
190
191 *div = ((clk_get_rate(clk) * 2) / pclk) - 2;
192
193 return 0;
167} 194}
168 195
169static int tegra_output_rgb_check_mode(struct tegra_output *output, 196static int tegra_output_rgb_check_mode(struct tegra_output *output,
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index 49ef5729f435..27c979b50111 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -7,6 +7,7 @@
7 */ 7 */
8 8
9#include <linux/clk.h> 9#include <linux/clk.h>
10#include <linux/debugfs.h>
10#include <linux/io.h> 11#include <linux/io.h>
11#include <linux/platform_device.h> 12#include <linux/platform_device.h>
12#include <linux/reset.h> 13#include <linux/reset.h>
@@ -33,7 +34,23 @@ struct tegra_sor {
33 34
34 struct tegra_dpaux *dpaux; 35 struct tegra_dpaux *dpaux;
35 36
37 struct mutex lock;
36 bool enabled; 38 bool enabled;
39
40 struct dentry *debugfs;
41};
42
43struct tegra_sor_config {
44 u32 bits_per_pixel;
45
46 u32 active_polarity;
47 u32 active_count;
48 u32 tu_size;
49 u32 active_frac;
50 u32 watermark;
51
52 u32 hblank_symbols;
53 u32 vblank_symbols;
37}; 54};
38 55
39static inline struct tegra_sor * 56static inline struct tegra_sor *
@@ -289,34 +306,232 @@ static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
289 return -ETIMEDOUT; 306 return -ETIMEDOUT;
290} 307}
291 308
309struct tegra_sor_params {
310 /* number of link clocks per line */
311 unsigned int num_clocks;
312 /* ratio between input and output */
313 u64 ratio;
314 /* precision factor */
315 u64 precision;
316
317 unsigned int active_polarity;
318 unsigned int active_count;
319 unsigned int active_frac;
320 unsigned int tu_size;
321 unsigned int error;
322};
323
324static int tegra_sor_compute_params(struct tegra_sor *sor,
325 struct tegra_sor_params *params,
326 unsigned int tu_size)
327{
328 u64 active_sym, active_count, frac, approx;
329 u32 active_polarity, active_frac = 0;
330 const u64 f = params->precision;
331 s64 error;
332
333 active_sym = params->ratio * tu_size;
334 active_count = div_u64(active_sym, f) * f;
335 frac = active_sym - active_count;
336
337 /* fraction < 0.5 */
338 if (frac >= (f / 2)) {
339 active_polarity = 1;
340 frac = f - frac;
341 } else {
342 active_polarity = 0;
343 }
344
345 if (frac != 0) {
346 frac = div_u64(f * f, frac); /* 1/fraction */
347 if (frac <= (15 * f)) {
348 active_frac = div_u64(frac, f);
349
350 /* round up */
351 if (active_polarity)
352 active_frac++;
353 } else {
354 active_frac = active_polarity ? 1 : 15;
355 }
356 }
357
358 if (active_frac == 1)
359 active_polarity = 0;
360
361 if (active_polarity == 1) {
362 if (active_frac) {
363 approx = active_count + (active_frac * (f - 1)) * f;
364 approx = div_u64(approx, active_frac * f);
365 } else {
366 approx = active_count + f;
367 }
368 } else {
369 if (active_frac)
370 approx = active_count + div_u64(f, active_frac);
371 else
372 approx = active_count;
373 }
374
375 error = div_s64(active_sym - approx, tu_size);
376 error *= params->num_clocks;
377
378 if (error <= 0 && abs64(error) < params->error) {
379 params->active_count = div_u64(active_count, f);
380 params->active_polarity = active_polarity;
381 params->active_frac = active_frac;
382 params->error = abs64(error);
383 params->tu_size = tu_size;
384
385 if (error == 0)
386 return true;
387 }
388
389 return false;
390}
391
392static int tegra_sor_calc_config(struct tegra_sor *sor,
393 struct drm_display_mode *mode,
394 struct tegra_sor_config *config,
395 struct drm_dp_link *link)
396{
397 const u64 f = 100000, link_rate = link->rate * 1000;
398 const u64 pclk = mode->clock * 1000;
399 u64 input, output, watermark, num;
400 struct tegra_sor_params params;
401 u32 num_syms_per_line;
402 unsigned int i;
403
404 if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
405 return -EINVAL;
406
407 output = link_rate * 8 * link->num_lanes;
408 input = pclk * config->bits_per_pixel;
409
410 if (input >= output)
411 return -ERANGE;
412
413 memset(&params, 0, sizeof(params));
414 params.ratio = div64_u64(input * f, output);
415 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
416 params.precision = f;
417 params.error = 64 * f;
418 params.tu_size = 64;
419
420 for (i = params.tu_size; i >= 32; i--)
421 if (tegra_sor_compute_params(sor, &params, i))
422 break;
423
424 if (params.active_frac == 0) {
425 config->active_polarity = 0;
426 config->active_count = params.active_count;
427
428 if (!params.active_polarity)
429 config->active_count--;
430
431 config->tu_size = params.tu_size;
432 config->active_frac = 1;
433 } else {
434 config->active_polarity = params.active_polarity;
435 config->active_count = params.active_count;
436 config->active_frac = params.active_frac;
437 config->tu_size = params.tu_size;
438 }
439
440 dev_dbg(sor->dev,
441 "polarity: %d active count: %d tu size: %d active frac: %d\n",
442 config->active_polarity, config->active_count,
443 config->tu_size, config->active_frac);
444
445 watermark = params.ratio * config->tu_size * (f - params.ratio);
446 watermark = div_u64(watermark, f);
447
448 watermark = div_u64(watermark + params.error, f);
449 config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
450 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
451 (link->num_lanes * 8);
452
453 if (config->watermark > 30) {
454 config->watermark = 30;
455 dev_err(sor->dev,
456 "unable to compute TU size, forcing watermark to %u\n",
457 config->watermark);
458 } else if (config->watermark > num_syms_per_line) {
459 config->watermark = num_syms_per_line;
460 dev_err(sor->dev, "watermark too high, forcing to %u\n",
461 config->watermark);
462 }
463
464 /* compute the number of symbols per horizontal blanking interval */
465 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
466 config->hblank_symbols = div_u64(num, pclk);
467
468 if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
469 config->hblank_symbols -= 3;
470
471 config->hblank_symbols -= 12 / link->num_lanes;
472
473 /* compute the number of symbols per vertical blanking interval */
474 num = (mode->hdisplay - 25) * link_rate;
475 config->vblank_symbols = div_u64(num, pclk);
476 config->vblank_symbols -= 36 / link->num_lanes + 4;
477
478 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
479 config->vblank_symbols);
480
481 return 0;
482}
483
292static int tegra_output_sor_enable(struct tegra_output *output) 484static int tegra_output_sor_enable(struct tegra_output *output)
293{ 485{
294 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 486 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
295 struct drm_display_mode *mode = &dc->base.mode; 487 struct drm_display_mode *mode = &dc->base.mode;
296 unsigned int vbe, vse, hbe, hse, vbs, hbs, i; 488 unsigned int vbe, vse, hbe, hse, vbs, hbs, i;
297 struct tegra_sor *sor = to_sor(output); 489 struct tegra_sor *sor = to_sor(output);
490 struct tegra_sor_config config;
491 struct drm_dp_link link;
492 struct drm_dp_aux *aux;
298 unsigned long value; 493 unsigned long value;
299 int err; 494 int err = 0;
495
496 mutex_lock(&sor->lock);
300 497
301 if (sor->enabled) 498 if (sor->enabled)
302 return 0; 499 goto unlock;
303 500
304 err = clk_prepare_enable(sor->clk); 501 err = clk_prepare_enable(sor->clk);
305 if (err < 0) 502 if (err < 0)
306 return err; 503 goto unlock;
307 504
308 reset_control_deassert(sor->rst); 505 reset_control_deassert(sor->rst);
309 506
507 /* FIXME: properly convert to struct drm_dp_aux */
508 aux = (struct drm_dp_aux *)sor->dpaux;
509
310 if (sor->dpaux) { 510 if (sor->dpaux) {
311 err = tegra_dpaux_enable(sor->dpaux); 511 err = tegra_dpaux_enable(sor->dpaux);
312 if (err < 0) 512 if (err < 0)
313 dev_err(sor->dev, "failed to enable DP: %d\n", err); 513 dev_err(sor->dev, "failed to enable DP: %d\n", err);
514
515 err = drm_dp_link_probe(aux, &link);
516 if (err < 0) {
517 dev_err(sor->dev, "failed to probe eDP link: %d\n",
518 err);
519 return err;
520 }
314 } 521 }
315 522
316 err = clk_set_parent(sor->clk, sor->clk_safe); 523 err = clk_set_parent(sor->clk, sor->clk_safe);
317 if (err < 0) 524 if (err < 0)
318 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 525 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
319 526
527 memset(&config, 0, sizeof(config));
528 config.bits_per_pixel = 24; /* XXX: don't hardcode? */
529
530 err = tegra_sor_calc_config(sor, mode, &config, &link);
531 if (err < 0)
532 dev_err(sor->dev, "failed to compute link configuration: %d\n",
533 err);
534
320 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 535 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
321 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 536 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
322 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 537 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
@@ -385,7 +600,7 @@ static int tegra_output_sor_enable(struct tegra_output *output)
385 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS); 600 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
386 if (err < 0) { 601 if (err < 0) {
387 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err); 602 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
388 return err; 603 goto unlock;
389 } 604 }
390 605
391 usleep_range(5, 100); 606 usleep_range(5, 100);
@@ -419,15 +634,29 @@ static int tegra_output_sor_enable(struct tegra_output *output)
419 if (err < 0) 634 if (err < 0)
420 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err); 635 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
421 636
422 /* power dplanes (XXX parameterize based on link?) */ 637 /* power DP lanes */
423 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0); 638 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
424 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 639
425 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 640 if (link.num_lanes <= 2)
641 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
642 else
643 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
644
645 if (link.num_lanes <= 1)
646 value &= ~SOR_DP_PADCTL_PD_TXD_1;
647 else
648 value |= SOR_DP_PADCTL_PD_TXD_1;
649
650 if (link.num_lanes == 0)
651 value &= ~SOR_DP_PADCTL_PD_TXD_0;
652 else
653 value |= SOR_DP_PADCTL_PD_TXD_0;
654
426 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 655 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
427 656
428 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0); 657 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
429 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 658 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
430 value |= SOR_DP_LINKCTL_LANE_COUNT(4); 659 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
431 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 660 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
432 661
433 /* start lane sequencer */ 662 /* start lane sequencer */
@@ -443,10 +672,10 @@ static int tegra_output_sor_enable(struct tegra_output *output)
443 usleep_range(250, 1000); 672 usleep_range(250, 1000);
444 } 673 }
445 674
446 /* set link bandwidth (2.7 GHz, XXX: parameterize based on link?) */ 675 /* set link bandwidth */
447 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 676 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
448 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 677 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
449 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 678 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
450 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 679 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
451 680
452 /* set linkctl */ 681 /* set linkctl */
@@ -454,7 +683,7 @@ static int tegra_output_sor_enable(struct tegra_output *output)
454 value |= SOR_DP_LINKCTL_ENABLE; 683 value |= SOR_DP_LINKCTL_ENABLE;
455 684
456 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 685 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
457 value |= SOR_DP_LINKCTL_TU_SIZE(59); /* XXX: don't hardcode? */ 686 value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size);
458 687
459 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 688 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
460 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0); 689 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
@@ -470,28 +699,31 @@ static int tegra_output_sor_enable(struct tegra_output *output)
470 699
471 value = tegra_sor_readl(sor, SOR_DP_CONFIG_0); 700 value = tegra_sor_readl(sor, SOR_DP_CONFIG_0);
472 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 701 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
473 value |= SOR_DP_CONFIG_WATERMARK(14); /* XXX: don't hardcode? */ 702 value |= SOR_DP_CONFIG_WATERMARK(config.watermark);
474 703
475 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 704 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
476 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(47); /* XXX: don't hardcode? */ 705 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count);
477 706
478 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 707 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
479 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(9); /* XXX: don't hardcode? */ 708 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac);
480 709
481 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; /* XXX: don't hardcode? */ 710 if (config.active_polarity)
711 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
712 else
713 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
482 714
483 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 715 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
484 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; /* XXX: don't hardcode? */ 716 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
485 tegra_sor_writel(sor, value, SOR_DP_CONFIG_0); 717 tegra_sor_writel(sor, value, SOR_DP_CONFIG_0);
486 718
487 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 719 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
488 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 720 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
489 value |= 137; /* XXX: don't hardcode? */ 721 value |= config.hblank_symbols & 0xffff;
490 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 722 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
491 723
492 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 724 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
493 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 725 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
494 value |= 2368; /* XXX: don't hardcode? */ 726 value |= config.vblank_symbols & 0xffff;
495 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 727 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
496 728
497 /* enable pad calibration logic */ 729 /* enable pad calibration logic */
@@ -500,30 +732,27 @@ static int tegra_output_sor_enable(struct tegra_output *output)
500 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 732 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
501 733
502 if (sor->dpaux) { 734 if (sor->dpaux) {
503 /* FIXME: properly convert to struct drm_dp_aux */
504 struct drm_dp_aux *aux = (struct drm_dp_aux *)sor->dpaux;
505 struct drm_dp_link link;
506 u8 rate, lanes; 735 u8 rate, lanes;
507 736
508 err = drm_dp_link_probe(aux, &link); 737 err = drm_dp_link_probe(aux, &link);
509 if (err < 0) { 738 if (err < 0) {
510 dev_err(sor->dev, "failed to probe eDP link: %d\n", 739 dev_err(sor->dev, "failed to probe eDP link: %d\n",
511 err); 740 err);
512 return err; 741 goto unlock;
513 } 742 }
514 743
515 err = drm_dp_link_power_up(aux, &link); 744 err = drm_dp_link_power_up(aux, &link);
516 if (err < 0) { 745 if (err < 0) {
517 dev_err(sor->dev, "failed to power up eDP link: %d\n", 746 dev_err(sor->dev, "failed to power up eDP link: %d\n",
518 err); 747 err);
519 return err; 748 goto unlock;
520 } 749 }
521 750
522 err = drm_dp_link_configure(aux, &link); 751 err = drm_dp_link_configure(aux, &link);
523 if (err < 0) { 752 if (err < 0) {
524 dev_err(sor->dev, "failed to configure eDP link: %d\n", 753 dev_err(sor->dev, "failed to configure eDP link: %d\n",
525 err); 754 err);
526 return err; 755 goto unlock;
527 } 756 }
528 757
529 rate = drm_dp_link_rate_to_bw_code(link.rate); 758 rate = drm_dp_link_rate_to_bw_code(link.rate);
@@ -558,7 +787,7 @@ static int tegra_output_sor_enable(struct tegra_output *output)
558 if (err < 0) { 787 if (err < 0) {
559 dev_err(sor->dev, "DP fast link training failed: %d\n", 788 dev_err(sor->dev, "DP fast link training failed: %d\n",
560 err); 789 err);
561 return err; 790 goto unlock;
562 } 791 }
563 792
564 dev_dbg(sor->dev, "fast link training succeeded\n"); 793 dev_dbg(sor->dev, "fast link training succeeded\n");
@@ -567,7 +796,7 @@ static int tegra_output_sor_enable(struct tegra_output *output)
567 err = tegra_sor_power_up(sor, 250); 796 err = tegra_sor_power_up(sor, 250);
568 if (err < 0) { 797 if (err < 0) {
569 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 798 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
570 return err; 799 goto unlock;
571 } 800 }
572 801
573 /* start display controller in continuous mode */ 802 /* start display controller in continuous mode */
@@ -586,12 +815,26 @@ static int tegra_output_sor_enable(struct tegra_output *output)
586 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete 815 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
587 * raster, associate with display controller) 816 * raster, associate with display controller)
588 */ 817 */
589 value = SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 | 818 value = SOR_STATE_ASY_VSYNCPOL |
590 SOR_STATE_ASY_VSYNCPOL |
591 SOR_STATE_ASY_HSYNCPOL | 819 SOR_STATE_ASY_HSYNCPOL |
592 SOR_STATE_ASY_PROTOCOL_DP_A | 820 SOR_STATE_ASY_PROTOCOL_DP_A |
593 SOR_STATE_ASY_CRC_MODE_COMPLETE | 821 SOR_STATE_ASY_CRC_MODE_COMPLETE |
594 SOR_STATE_ASY_OWNER(dc->pipe + 1); 822 SOR_STATE_ASY_OWNER(dc->pipe + 1);
823
824 switch (config.bits_per_pixel) {
825 case 24:
826 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
827 break;
828
829 case 18:
830 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
831 break;
832
833 default:
834 BUG();
835 break;
836 }
837
595 tegra_sor_writel(sor, value, SOR_STATE_1); 838 tegra_sor_writel(sor, value, SOR_STATE_1);
596 839
597 /* 840 /*
@@ -620,11 +863,8 @@ static int tegra_output_sor_enable(struct tegra_output *output)
620 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 863 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
621 tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0)); 864 tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));
622 865
623 /* XXX interlaced mode */
624 tegra_sor_writel(sor, 0x00000001, SOR_HEAD_STATE_5(0));
625
626 /* CSTM (LVDS, link A/B, upper) */ 866 /* CSTM (LVDS, link A/B, upper) */
627 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_B | SOR_CSTM_LINK_ACT_B | 867 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
628 SOR_CSTM_UPPER; 868 SOR_CSTM_UPPER;
629 tegra_sor_writel(sor, value, SOR_CSTM); 869 tegra_sor_writel(sor, value, SOR_CSTM);
630 870
@@ -632,7 +872,7 @@ static int tegra_output_sor_enable(struct tegra_output *output)
632 err = tegra_sor_setup_pwm(sor, 250); 872 err = tegra_sor_setup_pwm(sor, 250);
633 if (err < 0) { 873 if (err < 0) {
634 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 874 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
635 return err; 875 goto unlock;
636 } 876 }
637 877
638 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 878 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
@@ -644,18 +884,20 @@ static int tegra_output_sor_enable(struct tegra_output *output)
644 err = tegra_sor_attach(sor); 884 err = tegra_sor_attach(sor);
645 if (err < 0) { 885 if (err < 0) {
646 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 886 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
647 return err; 887 goto unlock;
648 } 888 }
649 889
650 err = tegra_sor_wakeup(sor); 890 err = tegra_sor_wakeup(sor);
651 if (err < 0) { 891 if (err < 0) {
652 dev_err(sor->dev, "failed to enable DC: %d\n", err); 892 dev_err(sor->dev, "failed to enable DC: %d\n", err);
653 return err; 893 goto unlock;
654 } 894 }
655 895
656 sor->enabled = true; 896 sor->enabled = true;
657 897
658 return 0; 898unlock:
899 mutex_unlock(&sor->lock);
900 return err;
659} 901}
660 902
661static int tegra_sor_detach(struct tegra_sor *sor) 903static int tegra_sor_detach(struct tegra_sor *sor)
@@ -740,7 +982,7 @@ static int tegra_sor_power_down(struct tegra_sor *sor)
740 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0); 982 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
741 983
742 /* stop lane sequencer */ 984 /* stop lane sequencer */
743 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 985 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
744 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 986 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
745 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 987 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
746 988
@@ -783,15 +1025,17 @@ static int tegra_output_sor_disable(struct tegra_output *output)
783 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 1025 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
784 struct tegra_sor *sor = to_sor(output); 1026 struct tegra_sor *sor = to_sor(output);
785 unsigned long value; 1027 unsigned long value;
786 int err; 1028 int err = 0;
1029
1030 mutex_lock(&sor->lock);
787 1031
788 if (!sor->enabled) 1032 if (!sor->enabled)
789 return 0; 1033 goto unlock;
790 1034
791 err = tegra_sor_detach(sor); 1035 err = tegra_sor_detach(sor);
792 if (err < 0) { 1036 if (err < 0) {
793 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 1037 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
794 return err; 1038 goto unlock;
795 } 1039 }
796 1040
797 tegra_sor_writel(sor, 0, SOR_STATE_1); 1041 tegra_sor_writel(sor, 0, SOR_STATE_1);
@@ -832,21 +1076,21 @@ static int tegra_output_sor_disable(struct tegra_output *output)
832 err = tegra_sor_power_down(sor); 1076 err = tegra_sor_power_down(sor);
833 if (err < 0) { 1077 if (err < 0) {
834 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 1078 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
835 return err; 1079 goto unlock;
836 } 1080 }
837 1081
838 if (sor->dpaux) { 1082 if (sor->dpaux) {
839 err = tegra_dpaux_disable(sor->dpaux); 1083 err = tegra_dpaux_disable(sor->dpaux);
840 if (err < 0) { 1084 if (err < 0) {
841 dev_err(sor->dev, "failed to disable DP: %d\n", err); 1085 dev_err(sor->dev, "failed to disable DP: %d\n", err);
842 return err; 1086 goto unlock;
843 } 1087 }
844 } 1088 }
845 1089
846 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS); 1090 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
847 if (err < 0) { 1091 if (err < 0) {
848 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err); 1092 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
849 return err; 1093 goto unlock;
850 } 1094 }
851 1095
852 reset_control_assert(sor->rst); 1096 reset_control_assert(sor->rst);
@@ -854,18 +1098,18 @@ static int tegra_output_sor_disable(struct tegra_output *output)
854 1098
855 sor->enabled = false; 1099 sor->enabled = false;
856 1100
857 return 0; 1101unlock:
1102 mutex_unlock(&sor->lock);
1103 return err;
858} 1104}
859 1105
860static int tegra_output_sor_setup_clock(struct tegra_output *output, 1106static int tegra_output_sor_setup_clock(struct tegra_output *output,
861 struct clk *clk, unsigned long pclk) 1107 struct clk *clk, unsigned long pclk,
1108 unsigned int *div)
862{ 1109{
863 struct tegra_sor *sor = to_sor(output); 1110 struct tegra_sor *sor = to_sor(output);
864 int err; 1111 int err;
865 1112
866 /* round to next MHz */
867 pclk = DIV_ROUND_UP(pclk / 2, 1000000) * 1000000;
868
869 err = clk_set_parent(clk, sor->clk_parent); 1113 err = clk_set_parent(clk, sor->clk_parent);
870 if (err < 0) { 1114 if (err < 0) {
871 dev_err(sor->dev, "failed to set parent clock: %d\n", err); 1115 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
@@ -874,11 +1118,12 @@ static int tegra_output_sor_setup_clock(struct tegra_output *output,
874 1118
875 err = clk_set_rate(sor->clk_parent, pclk); 1119 err = clk_set_rate(sor->clk_parent, pclk);
876 if (err < 0) { 1120 if (err < 0) {
877 dev_err(sor->dev, "failed to set base clock rate to %lu Hz\n", 1121 dev_err(sor->dev, "failed to set clock rate to %lu Hz\n", pclk);
878 pclk * 2);
879 return err; 1122 return err;
880 } 1123 }
881 1124
1125 *div = 0;
1126
882 return 0; 1127 return 0;
883} 1128}
884 1129
@@ -914,9 +1159,124 @@ static const struct tegra_output_ops sor_ops = {
914 .detect = tegra_output_sor_detect, 1159 .detect = tegra_output_sor_detect,
915}; 1160};
916 1161
1162static int tegra_sor_crc_open(struct inode *inode, struct file *file)
1163{
1164 file->private_data = inode->i_private;
1165
1166 return 0;
1167}
1168
1169static int tegra_sor_crc_release(struct inode *inode, struct file *file)
1170{
1171 return 0;
1172}
1173
1174static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1175{
1176 u32 value;
1177
1178 timeout = jiffies + msecs_to_jiffies(timeout);
1179
1180 while (time_before(jiffies, timeout)) {
1181 value = tegra_sor_readl(sor, SOR_CRC_A);
1182 if (value & SOR_CRC_A_VALID)
1183 return 0;
1184
1185 usleep_range(100, 200);
1186 }
1187
1188 return -ETIMEDOUT;
1189}
1190
1191static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer,
1192 size_t size, loff_t *ppos)
1193{
1194 struct tegra_sor *sor = file->private_data;
1195 ssize_t num, err;
1196 char buf[10];
1197 u32 value;
1198
1199 mutex_lock(&sor->lock);
1200
1201 if (!sor->enabled) {
1202 err = -EAGAIN;
1203 goto unlock;
1204 }
1205
1206 value = tegra_sor_readl(sor, SOR_STATE_1);
1207 value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1208 tegra_sor_writel(sor, value, SOR_STATE_1);
1209
1210 value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1211 value |= SOR_CRC_CNTRL_ENABLE;
1212 tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1213
1214 value = tegra_sor_readl(sor, SOR_TEST);
1215 value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1216 tegra_sor_writel(sor, value, SOR_TEST);
1217
1218 err = tegra_sor_crc_wait(sor, 100);
1219 if (err < 0)
1220 goto unlock;
1221
1222 tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A);
1223 value = tegra_sor_readl(sor, SOR_CRC_B);
1224
1225 num = scnprintf(buf, sizeof(buf), "%08x\n", value);
1226
1227 err = simple_read_from_buffer(buffer, size, ppos, buf, num);
1228
1229unlock:
1230 mutex_unlock(&sor->lock);
1231 return err;
1232}
1233
1234static const struct file_operations tegra_sor_crc_fops = {
1235 .owner = THIS_MODULE,
1236 .open = tegra_sor_crc_open,
1237 .read = tegra_sor_crc_read,
1238 .release = tegra_sor_crc_release,
1239};
1240
1241static int tegra_sor_debugfs_init(struct tegra_sor *sor,
1242 struct drm_minor *minor)
1243{
1244 struct dentry *entry;
1245 int err = 0;
1246
1247 sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root);
1248 if (!sor->debugfs)
1249 return -ENOMEM;
1250
1251 entry = debugfs_create_file("crc", 0644, sor->debugfs, sor,
1252 &tegra_sor_crc_fops);
1253 if (!entry) {
1254 dev_err(sor->dev,
1255 "cannot create /sys/kernel/debug/dri/%s/sor/crc\n",
1256 minor->debugfs_root->d_name.name);
1257 err = -ENOMEM;
1258 goto remove;
1259 }
1260
1261 return err;
1262
1263remove:
1264 debugfs_remove(sor->debugfs);
1265 sor->debugfs = NULL;
1266 return err;
1267}
1268
1269static int tegra_sor_debugfs_exit(struct tegra_sor *sor)
1270{
1271 debugfs_remove_recursive(sor->debugfs);
1272 sor->debugfs = NULL;
1273
1274 return 0;
1275}
1276
917static int tegra_sor_init(struct host1x_client *client) 1277static int tegra_sor_init(struct host1x_client *client)
918{ 1278{
919 struct tegra_drm *tegra = dev_get_drvdata(client->parent); 1279 struct drm_device *drm = dev_get_drvdata(client->parent);
920 struct tegra_sor *sor = host1x_client_to_sor(client); 1280 struct tegra_sor *sor = host1x_client_to_sor(client);
921 int err; 1281 int err;
922 1282
@@ -928,12 +1288,18 @@ static int tegra_sor_init(struct host1x_client *client)
928 sor->output.dev = sor->dev; 1288 sor->output.dev = sor->dev;
929 sor->output.ops = &sor_ops; 1289 sor->output.ops = &sor_ops;
930 1290
931 err = tegra_output_init(tegra->drm, &sor->output); 1291 err = tegra_output_init(drm, &sor->output);
932 if (err < 0) { 1292 if (err < 0) {
933 dev_err(sor->dev, "output setup failed: %d\n", err); 1293 dev_err(sor->dev, "output setup failed: %d\n", err);
934 return err; 1294 return err;
935 } 1295 }
936 1296
1297 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1298 err = tegra_sor_debugfs_init(sor, drm->primary);
1299 if (err < 0)
1300 dev_err(sor->dev, "debugfs setup failed: %d\n", err);
1301 }
1302
937 if (sor->dpaux) { 1303 if (sor->dpaux) {
938 err = tegra_dpaux_attach(sor->dpaux, &sor->output); 1304 err = tegra_dpaux_attach(sor->dpaux, &sor->output);
939 if (err < 0) { 1305 if (err < 0) {
@@ -964,6 +1330,12 @@ static int tegra_sor_exit(struct host1x_client *client)
964 } 1330 }
965 } 1331 }
966 1332
1333 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1334 err = tegra_sor_debugfs_exit(sor);
1335 if (err < 0)
1336 dev_err(sor->dev, "debugfs cleanup failed: %d\n", err);
1337 }
1338
967 err = tegra_output_exit(&sor->output); 1339 err = tegra_output_exit(&sor->output);
968 if (err < 0) { 1340 if (err < 0) {
969 dev_err(sor->dev, "output cleanup failed: %d\n", err); 1341 dev_err(sor->dev, "output cleanup failed: %d\n", err);
@@ -1045,6 +1417,8 @@ static int tegra_sor_probe(struct platform_device *pdev)
1045 sor->client.ops = &sor_client_ops; 1417 sor->client.ops = &sor_client_ops;
1046 sor->client.dev = &pdev->dev; 1418 sor->client.dev = &pdev->dev;
1047 1419
1420 mutex_init(&sor->lock);
1421
1048 err = host1x_client_register(&sor->client); 1422 err = host1x_client_register(&sor->client);
1049 if (err < 0) { 1423 if (err < 0) {
1050 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1424 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
diff --git a/drivers/gpu/drm/tegra/sor.h b/drivers/gpu/drm/tegra/sor.h
index f4156d54cd05..a5f8853fedb5 100644
--- a/drivers/gpu/drm/tegra/sor.h
+++ b/drivers/gpu/drm/tegra/sor.h
@@ -47,6 +47,7 @@
47#define SOR_HEAD_STATE_4(x) (0x0d + (x)) 47#define SOR_HEAD_STATE_4(x) (0x0d + (x))
48#define SOR_HEAD_STATE_5(x) (0x0f + (x)) 48#define SOR_HEAD_STATE_5(x) (0x0f + (x))
49#define SOR_CRC_CNTRL 0x11 49#define SOR_CRC_CNTRL 0x11
50#define SOR_CRC_CNTRL_ENABLE (1 << 0)
50#define SOR_DP_DEBUG_MVID 0x12 51#define SOR_DP_DEBUG_MVID 0x12
51 52
52#define SOR_CLK_CNTRL 0x13 53#define SOR_CLK_CNTRL 0x13
@@ -69,6 +70,7 @@
69#define SOR_PWR_NORMAL_STATE_PU (1 << 0) 70#define SOR_PWR_NORMAL_STATE_PU (1 << 0)
70 71
71#define SOR_TEST 0x16 72#define SOR_TEST 0x16
73#define SOR_TEST_CRC_POST_SERIALIZE (1 << 23)
72#define SOR_TEST_ATTACHED (1 << 10) 74#define SOR_TEST_ATTACHED (1 << 10)
73#define SOR_TEST_HEAD_MODE_MASK (3 << 8) 75#define SOR_TEST_HEAD_MODE_MASK (3 << 8)
74#define SOR_TEST_HEAD_MODE_AWAKE (2 << 8) 76#define SOR_TEST_HEAD_MODE_AWAKE (2 << 8)
@@ -115,6 +117,8 @@
115 117
116#define SOR_LVDS 0x1c 118#define SOR_LVDS 0x1c
117#define SOR_CRC_A 0x1d 119#define SOR_CRC_A 0x1d
120#define SOR_CRC_A_VALID (1 << 0)
121#define SOR_CRC_A_RESET (1 << 0)
118#define SOR_CRC_B 0x1e 122#define SOR_CRC_B 0x1e
119#define SOR_BLANK 0x1f 123#define SOR_BLANK 0x1f
120#define SOR_SEQ_CTL 0x20 124#define SOR_SEQ_CTL 0x20
diff --git a/drivers/gpu/host1x/bus.c b/drivers/gpu/host1x/bus.c
index ccdd2e6da5e3..aaf54859adb0 100644
--- a/drivers/gpu/host1x/bus.c
+++ b/drivers/gpu/host1x/bus.c
@@ -216,8 +216,8 @@ int host1x_device_exit(struct host1x_device *device)
216} 216}
217EXPORT_SYMBOL(host1x_device_exit); 217EXPORT_SYMBOL(host1x_device_exit);
218 218
219static int host1x_register_client(struct host1x *host1x, 219static int host1x_add_client(struct host1x *host1x,
220 struct host1x_client *client) 220 struct host1x_client *client)
221{ 221{
222 struct host1x_device *device; 222 struct host1x_device *device;
223 struct host1x_subdev *subdev; 223 struct host1x_subdev *subdev;
@@ -238,8 +238,8 @@ static int host1x_register_client(struct host1x *host1x,
238 return -ENODEV; 238 return -ENODEV;
239} 239}
240 240
241static int host1x_unregister_client(struct host1x *host1x, 241static int host1x_del_client(struct host1x *host1x,
242 struct host1x_client *client) 242 struct host1x_client *client)
243{ 243{
244 struct host1x_device *device, *dt; 244 struct host1x_device *device, *dt;
245 struct host1x_subdev *subdev; 245 struct host1x_subdev *subdev;
@@ -503,7 +503,7 @@ int host1x_client_register(struct host1x_client *client)
503 mutex_lock(&devices_lock); 503 mutex_lock(&devices_lock);
504 504
505 list_for_each_entry(host1x, &devices, list) { 505 list_for_each_entry(host1x, &devices, list) {
506 err = host1x_register_client(host1x, client); 506 err = host1x_add_client(host1x, client);
507 if (!err) { 507 if (!err) {
508 mutex_unlock(&devices_lock); 508 mutex_unlock(&devices_lock);
509 return 0; 509 return 0;
@@ -529,7 +529,7 @@ int host1x_client_unregister(struct host1x_client *client)
529 mutex_lock(&devices_lock); 529 mutex_lock(&devices_lock);
530 530
531 list_for_each_entry(host1x, &devices, list) { 531 list_for_each_entry(host1x, &devices, list) {
532 err = host1x_unregister_client(host1x, client); 532 err = host1x_del_client(host1x, client);
533 if (!err) { 533 if (!err) {
534 mutex_unlock(&devices_lock); 534 mutex_unlock(&devices_lock);
535 return 0; 535 return 0;
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 475ca5cf3c20..83222db41566 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1058,6 +1058,7 @@ struct drm_device {
1058 struct drm_minor *render; /**< Render node */ 1058 struct drm_minor *render; /**< Render node */
1059 atomic_t unplugged; /**< Flag whether dev is dead */ 1059 atomic_t unplugged; /**< Flag whether dev is dead */
1060 struct inode *anon_inode; /**< inode for private address-space */ 1060 struct inode *anon_inode; /**< inode for private address-space */
1061 char *unique; /**< unique name of the device */
1061 /*@} */ 1062 /*@} */
1062 1063
1063 /** \name Locks */ 1064 /** \name Locks */
@@ -1617,6 +1618,7 @@ void drm_dev_ref(struct drm_device *dev);
1617void drm_dev_unref(struct drm_device *dev); 1618void drm_dev_unref(struct drm_device *dev);
1618int drm_dev_register(struct drm_device *dev, unsigned long flags); 1619int drm_dev_register(struct drm_device *dev, unsigned long flags);
1619void drm_dev_unregister(struct drm_device *dev); 1620void drm_dev_unregister(struct drm_device *dev);
1621int drm_dev_set_unique(struct drm_device *dev, const char *fmt, ...);
1620 1622
1621struct drm_minor *drm_minor_acquire(unsigned int minor_id); 1623struct drm_minor *drm_minor_acquire(unsigned int minor_id);
1622void drm_minor_release(struct drm_minor *minor); 1624void drm_minor_release(struct drm_minor *minor);
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-04 12:12:35 -0500