Merge tag 'ux500-dma40' of //git.linaro.org/people/fabiobaltieri/linux.git

Pull ste_dma40 fixes from Fabio

Signed-off-by: Vinod Koul <vinod.koul@intel.com>

4 files changed, 518 insertions, 143 deletions

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index e5e60bb68d9d..ad860a221c33 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -53,6 +53,8 @@
 #define D40_ALLOC_PHY           (1 << 30)
 #define D40_ALLOC_LOG_FREE      0
 
+#define MAX(a, b) (((a) < (b)) ? (b) : (a))
+
 /**
  * enum 40_command - The different commands and/or statuses.
  *
@@ -100,8 +102,19 @@ static u32 d40_backup_regs[] = {
 
 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
 
-/* TODO: Check if all these registers have to be saved/restored on dma40 v3 */
-static u32 d40_backup_regs_v3[] = {
+/*
+ * since 9540 and 8540 has the same HW revision
+ * use v4a for 9540 or ealier
+ * use v4b for 8540 or later
+ * HW revision:
+ * DB8500ed has revision 0
+ * DB8500v1 has revision 2
+ * DB8500v2 has revision 3
+ * AP9540v1 has revision 4
+ * DB8540v1 has revision 4
+ * TODO: Check if all these registers have to be saved/restored on dma40 v4a
+ */
+static u32 d40_backup_regs_v4a[] = {
         D40_DREG_PSEG1,
         D40_DREG_PSEG2,
         D40_DREG_PSEG3,
@@ -120,7 +133,32 @@ static u32 d40_backup_regs_v3[] = {
         D40_DREG_RCEG4,
 };
 
-#define BACKUP_REGS_SZ_V3 ARRAY_SIZE(d40_backup_regs_v3)
+#define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
+
+static u32 d40_backup_regs_v4b[] = {
+        D40_DREG_CPSEG1,
+        D40_DREG_CPSEG2,
+        D40_DREG_CPSEG3,
+        D40_DREG_CPSEG4,
+        D40_DREG_CPSEG5,
+        D40_DREG_CPCEG1,
+        D40_DREG_CPCEG2,
+        D40_DREG_CPCEG3,
+        D40_DREG_CPCEG4,
+        D40_DREG_CPCEG5,
+        D40_DREG_CRSEG1,
+        D40_DREG_CRSEG2,
+        D40_DREG_CRSEG3,
+        D40_DREG_CRSEG4,
+        D40_DREG_CRSEG5,
+        D40_DREG_CRCEG1,
+        D40_DREG_CRCEG2,
+        D40_DREG_CRCEG3,
+        D40_DREG_CRCEG4,
+        D40_DREG_CRCEG5,
+};
+
+#define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
 
 static u32 d40_backup_regs_chan[] = {
         D40_CHAN_REG_SSCFG,
@@ -134,6 +172,102 @@ static u32 d40_backup_regs_chan[] = {
 };
 
 /**
+ * struct d40_interrupt_lookup - lookup table for interrupt handler
+ *
+ * @src: Interrupt mask register.
+ * @clr: Interrupt clear register.
+ * @is_error: true if this is an error interrupt.
+ * @offset: start delta in the lookup_log_chans in d40_base. If equals to
+ * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
+ */
+struct d40_interrupt_lookup {
+        u32 src;
+        u32 clr;
+        bool is_error;
+        int offset;
+};
+
+
+static struct d40_interrupt_lookup il_v4a[] = {
+        {D40_DREG_LCTIS0, D40_DREG_LCICR0, false,  0},
+        {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
+        {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
+        {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
+        {D40_DREG_LCEIS0, D40_DREG_LCICR0, true,   0},
+        {D40_DREG_LCEIS1, D40_DREG_LCICR1, true,  32},
+        {D40_DREG_LCEIS2, D40_DREG_LCICR2, true,  64},
+        {D40_DREG_LCEIS3, D40_DREG_LCICR3, true,  96},
+        {D40_DREG_PCTIS,  D40_DREG_PCICR,  false, D40_PHY_CHAN},
+        {D40_DREG_PCEIS,  D40_DREG_PCICR,  true,  D40_PHY_CHAN},
+};
+
+static struct d40_interrupt_lookup il_v4b[] = {
+        {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false,  0},
+        {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
+        {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
+        {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
+        {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
+        {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true,   0},
+        {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true,  32},
+        {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true,  64},
+        {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true,  96},
+        {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true,  128},
+        {D40_DREG_CPCTIS,  D40_DREG_CPCICR,  false, D40_PHY_CHAN},
+        {D40_DREG_CPCEIS,  D40_DREG_CPCICR,  true,  D40_PHY_CHAN},
+};
+
+/**
+ * struct d40_reg_val - simple lookup struct
+ *
+ * @reg: The register.
+ * @val: The value that belongs to the register in reg.
+ */
+struct d40_reg_val {
+        unsigned int reg;
+        unsigned int val;
+};
+
+static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
+        /* Clock every part of the DMA block from start */
+        { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
+
+        /* Interrupts on all logical channels */
+        { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
+};
+static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
+        /* Clock every part of the DMA block from start */
+        { .reg = D40_DREG_GCC,    .val = D40_DREG_GCC_ENABLE_ALL},
+
+        /* Interrupts on all logical channels */
+        { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
+        { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
+};
+
+/**
  * struct d40_lli_pool - Structure for keeping LLIs in memory
  *
  * @base: Pointer to memory area when the pre_alloc_lli's are not large
@@ -221,6 +355,7 @@ struct d40_lcla_pool {
  * @allocated_dst: Same as for src but is dst.
  * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
  * event line number.
+ * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
  */
 struct d40_phy_res {
         spinlock_t lock;
@@ -228,6 +363,7 @@ struct d40_phy_res {
         int        num;
         u32        allocated_src;