diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-09-13 17:51:22 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-09-13 17:51:22 -0400 |
commit | 6bfb09a1005193be5c81ebac9f3ef85210142650 (patch) | |
tree | 1d833bdf0ba5ae99cd29a5eac8ca75b2621a7574 | |
parent | 7c22a3d853804d2716ef4f90cdd693a83819ba11 (diff) | |
parent | 88c381bf09d7b3f2c2e8749150087aff2c434be4 (diff) |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] Fix PCI_DMA_BUS_IS_PHYS for ARM
[ARM] 5247/1: tosa: SW_EAR_IN support
[ARM] 5246/1: tosa: add proper clock alias for tc6393xb clock
[ARM] 5245/1: Fix warning about unused return value in drivers/pcmcia
[ARM] OMAP: Fix MMC device data
imx serial: fix rts handling for non imx1 based hardware
imx serial: set RXD mux bit on i.MX27 and i.MX31
i.MX serial: fix init failure
pcm037: add rts/cts support for serial port
-rw-r--r-- | arch/arm/include/asm/pci.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-mx3/pcm037.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-pxa/tosa.c | 11 | ||||
-rw-r--r-- | arch/arm/plat-omap/devices.c | 123 | ||||
-rw-r--r-- | drivers/pcmcia/soc_common.c | 6 | ||||
-rw-r--r-- | drivers/serial/imx.c | 27 |
6 files changed, 131 insertions, 40 deletions
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h index 721c03d53f4b..918d0cbbf064 100644 --- a/arch/arm/include/asm/pci.h +++ b/arch/arm/include/asm/pci.h | |||
@@ -30,7 +30,7 @@ static inline void pcibios_penalize_isa_irq(int irq, int active) | |||
30 | * The networking and block device layers use this boolean for bounce | 30 | * The networking and block device layers use this boolean for bounce |
31 | * buffer decisions. | 31 | * buffer decisions. |
32 | */ | 32 | */ |
33 | #define PCI_DMA_BUS_IS_PHYS (0) | 33 | #define PCI_DMA_BUS_IS_PHYS (1) |
34 | 34 | ||
35 | /* | 35 | /* |
36 | * Whether pci_unmap_{single,page} is a nop depends upon the | 36 | * Whether pci_unmap_{single,page} is a nop depends upon the |
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c index 0a152ed15a85..df8582a6231b 100644 --- a/arch/arm/mach-mx3/pcm037.c +++ b/arch/arm/mach-mx3/pcm037.c | |||
@@ -54,7 +54,7 @@ static struct platform_device pcm037_flash = { | |||
54 | }; | 54 | }; |
55 | 55 | ||
56 | static struct imxuart_platform_data uart_pdata = { | 56 | static struct imxuart_platform_data uart_pdata = { |
57 | .flags = 0, | 57 | .flags = IMXUART_HAVE_RTSCTS, |
58 | }; | 58 | }; |
59 | 59 | ||
60 | static struct platform_device *devices[] __initdata = { | 60 | static struct platform_device *devices[] __initdata = { |
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 5dab30eafddc..9f3ef9eb32e3 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c | |||
@@ -50,6 +50,7 @@ | |||
50 | #include <asm/mach/sharpsl_param.h> | 50 | #include <asm/mach/sharpsl_param.h> |
51 | 51 | ||
52 | #include "generic.h" | 52 | #include "generic.h" |
53 | #include "clock.h" | ||
53 | #include "devices.h" | 54 | #include "devices.h" |
54 | 55 | ||
55 | static unsigned long tosa_pin_config[] = { | 56 | static unsigned long tosa_pin_config[] = { |
@@ -521,6 +522,14 @@ static struct gpio_keys_button tosa_gpio_keys[] = { | |||
521 | .wakeup = 1, | 522 | .wakeup = 1, |
522 | .active_low = 1, | 523 | .active_low = 1, |
523 | }, | 524 | }, |
525 | { | ||
526 | .type = EV_SW, | ||
527 | .code = SW_HEADPHONE_INSERT, | ||
528 | .gpio = TOSA_GPIO_EAR_IN, | ||
529 | .desc = "HeadPhone insert", | ||
530 | .active_low = 1, | ||
531 | .debounce_interval = 300, | ||
532 | }, | ||
524 | }; | 533 | }; |
525 | 534 | ||
526 | static struct gpio_keys_platform_data tosa_gpio_keys_platform_data = { | 535 | static struct gpio_keys_platform_data tosa_gpio_keys_platform_data = { |
@@ -792,6 +801,8 @@ static void __init tosa_init(void) | |||
792 | pxa_set_i2c_info(NULL); | 801 | pxa_set_i2c_info(NULL); |
793 | platform_scoop_config = &tosa_pcmcia_config; | 802 | platform_scoop_config = &tosa_pcmcia_config; |
794 | 803 | ||
804 | clk_add_alias("CLK_CK3P6MI", &tc6393xb_device.dev, "GPIO11_CLK", NULL); | ||
805 | |||
795 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 806 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
796 | } | 807 | } |
797 | 808 | ||
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 187e3d8bfdfe..bc1cf30c83e0 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c | |||
@@ -21,6 +21,7 @@ | |||
21 | 21 | ||
22 | #include <mach/tc.h> | 22 | #include <mach/tc.h> |
23 | #include <mach/board.h> | 23 | #include <mach/board.h> |
24 | #include <mach/mmc.h> | ||
24 | #include <mach/mux.h> | 25 | #include <mach/mux.h> |
25 | #include <mach/gpio.h> | 26 | #include <mach/gpio.h> |
26 | #include <mach/menelaus.h> | 27 | #include <mach/menelaus.h> |
@@ -194,25 +195,38 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, | |||
194 | 195 | ||
195 | /*-------------------------------------------------------------------------*/ | 196 | /*-------------------------------------------------------------------------*/ |
196 | 197 | ||
197 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) | 198 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \ |
199 | defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | ||
198 | 200 | ||
199 | #ifdef CONFIG_ARCH_OMAP24XX | 201 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
200 | #define OMAP_MMC1_BASE 0x4809c000 | 202 | #define OMAP_MMC1_BASE 0x4809c000 |
201 | #define OMAP_MMC1_INT INT_24XX_MMC_IRQ | 203 | #define OMAP_MMC1_END (OMAP_MMC1_BASE + 0x1fc) |
204 | #define OMAP_MMC1_INT INT_24XX_MMC_IRQ | ||
205 | |||
206 | #define OMAP_MMC2_BASE 0x480b4000 | ||
207 | #define OMAP_MMC2_END (OMAP_MMC2_BASE + 0x1fc) | ||
208 | #define OMAP_MMC2_INT INT_24XX_MMC2_IRQ | ||
209 | |||
202 | #else | 210 | #else |
211 | |||
203 | #define OMAP_MMC1_BASE 0xfffb7800 | 212 | #define OMAP_MMC1_BASE 0xfffb7800 |
213 | #define OMAP_MMC1_END (OMAP_MMC1_BASE + 0x7f) | ||
204 | #define OMAP_MMC1_INT INT_MMC | 214 | #define OMAP_MMC1_INT INT_MMC |
205 | #endif | 215 | |
206 | #define OMAP_MMC2_BASE 0xfffb7c00 /* omap16xx only */ | 216 | #define OMAP_MMC2_BASE 0xfffb7c00 /* omap16xx only */ |
217 | #define OMAP_MMC2_END (OMAP_MMC2_BASE + 0x7f) | ||
218 | #define OMAP_MMC2_INT INT_1610_MMC2 | ||
207 | 219 | ||
208 | static struct omap_mmc_conf mmc1_conf; | 220 | #endif |
221 | |||
222 | static struct omap_mmc_platform_data mmc1_data; | ||
209 | 223 | ||
210 | static u64 mmc1_dmamask = 0xffffffff; | 224 | static u64 mmc1_dmamask = 0xffffffff; |
211 | 225 | ||
212 | static struct resource mmc1_resources[] = { | 226 | static struct resource mmc1_resources[] = { |
213 | { | 227 | { |
214 | .start = OMAP_MMC1_BASE, | 228 | .start = OMAP_MMC1_BASE, |
215 | .end = OMAP_MMC1_BASE + 0x7f, | 229 | .end = OMAP_MMC1_END, |
216 | .flags = IORESOURCE_MEM, | 230 | .flags = IORESOURCE_MEM, |
217 | }, | 231 | }, |
218 | { | 232 | { |
@@ -226,26 +240,27 @@ static struct platform_device mmc_omap_device1 = { | |||
226 | .id = 1, | 240 | .id = 1, |
227 | .dev = { | 241 | .dev = { |
228 | .dma_mask = &mmc1_dmamask, | 242 | .dma_mask = &mmc1_dmamask, |
229 | .platform_data = &mmc1_conf, | 243 | .platform_data = &mmc1_data, |
230 | }, | 244 | }, |
231 | .num_resources = ARRAY_SIZE(mmc1_resources), | 245 | .num_resources = ARRAY_SIZE(mmc1_resources), |
232 | .resource = mmc1_resources, | 246 | .resource = mmc1_resources, |
233 | }; | 247 | }; |
234 | 248 | ||
235 | #ifdef CONFIG_ARCH_OMAP16XX | 249 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \ |
250 | defined(CONFIG_ARCH_OMAP34XX) | ||
236 | 251 | ||
237 | static struct omap_mmc_conf mmc2_conf; | 252 | static struct omap_mmc_platform_data mmc2_data; |
238 | 253 | ||
239 | static u64 mmc2_dmamask = 0xffffffff; | 254 | static u64 mmc2_dmamask = 0xffffffff; |
240 | 255 | ||
241 | static struct resource mmc2_resources[] = { | 256 | static struct resource mmc2_resources[] = { |
242 | { | 257 | { |
243 | .start = OMAP_MMC2_BASE, | 258 | .start = OMAP_MMC2_BASE, |
244 | .end = OMAP_MMC2_BASE + 0x7f, | 259 | .end = OMAP_MMC2_END, |
245 | .flags = IORESOURCE_MEM, | 260 | .flags = IORESOURCE_MEM, |
246 | }, | 261 | }, |
247 | { | 262 | { |
248 | .start = INT_1610_MMC2, | 263 | .start = OMAP_MMC2_INT, |
249 | .flags = IORESOURCE_IRQ, | 264 | .flags = IORESOURCE_IRQ, |
250 | }, | 265 | }, |
251 | }; | 266 | }; |
@@ -255,26 +270,19 @@ static struct platform_device mmc_omap_device2 = { | |||
255 | .id = 2, | 270 | .id = 2, |
256 | .dev = { | 271 | .dev = { |
257 | .dma_mask = &mmc2_dmamask, | 272 | .dma_mask = &mmc2_dmamask, |
258 | .platform_data = &mmc2_conf, | 273 | .platform_data = &mmc2_data, |
259 | }, | 274 | }, |
260 | .num_resources = ARRAY_SIZE(mmc2_resources), | 275 | .num_resources = ARRAY_SIZE(mmc2_resources), |
261 | .resource = mmc2_resources, | 276 | .resource = mmc2_resources, |
262 | }; | 277 | }; |
263 | #endif | 278 | #endif |
264 | 279 | ||
265 | static void __init omap_init_mmc(void) | 280 | static inline void omap_init_mmc_conf(const struct omap_mmc_config *mmc_conf) |
266 | { | 281 | { |
267 | const struct omap_mmc_config *mmc_conf; | 282 | if (cpu_is_omap2430() || cpu_is_omap34xx()) |
268 | const struct omap_mmc_conf *mmc; | ||
269 | |||
270 | /* NOTE: assumes MMC was never (wrongly) enabled */ | ||
271 | mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config); | ||
272 | if (!mmc_conf) | ||
273 | return; | 283 | return; |
274 | 284 | ||
275 | /* block 1 is always available and has just one pinout option */ | 285 | if (mmc_conf->mmc[0].enabled) { |
276 | mmc = &mmc_conf->mmc[0]; | ||
277 | if (mmc->enabled) { | ||
278 | if (cpu_is_omap24xx()) { | 286 | if (cpu_is_omap24xx()) { |
279 | omap_cfg_reg(H18_24XX_MMC_CMD); | 287 | omap_cfg_reg(H18_24XX_MMC_CMD); |
280 | omap_cfg_reg(H15_24XX_MMC_CLKI); | 288 | omap_cfg_reg(H15_24XX_MMC_CLKI); |
@@ -292,7 +300,7 @@ static void __init omap_init_mmc(void) | |||
292 | omap_cfg_reg(P20_1710_MMC_DATDIR0); | 300 | omap_cfg_reg(P20_1710_MMC_DATDIR0); |
293 | } | 301 | } |
294 | } | 302 | } |
295 | if (mmc->wire4) { | 303 | if (mmc_conf->mmc[0].wire4) { |
296 | if (cpu_is_omap24xx()) { | 304 | if (cpu_is_omap24xx()) { |
297 | omap_cfg_reg(H14_24XX_MMC_DAT1); | 305 | omap_cfg_reg(H14_24XX_MMC_DAT1); |
298 | omap_cfg_reg(E19_24XX_MMC_DAT2); | 306 | omap_cfg_reg(E19_24XX_MMC_DAT2); |
@@ -303,25 +311,35 @@ static void __init omap_init_mmc(void) | |||
303 | } else { | 311 | } else { |
304 | omap_cfg_reg(MMC_DAT1); | 312 | omap_cfg_reg(MMC_DAT1); |
305 | /* NOTE: DAT2 can be on W10 (here) or M15 */ | 313 | /* NOTE: DAT2 can be on W10 (here) or M15 */ |
306 | if (!mmc->nomux) | 314 | if (!mmc_conf->mmc[0].nomux) |
307 | omap_cfg_reg(MMC_DAT2); | 315 | omap_cfg_reg(MMC_DAT2); |
308 | omap_cfg_reg(MMC_DAT3); | 316 | omap_cfg_reg(MMC_DAT3); |
309 | } | 317 | } |
310 | } | 318 | } |
311 | mmc1_conf = *mmc; | 319 | #if defined(CONFIG_ARCH_OMAP2420) |
312 | (void) platform_device_register(&mmc_omap_device1); | 320 | if (mmc_conf->mmc[0].internal_clock) { |
321 | /* | ||
322 | * Use internal loop-back in MMC/SDIO | ||
323 | * Module Input Clock selection | ||
324 | */ | ||
325 | if (cpu_is_omap24xx()) { | ||
326 | u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
327 | v |= (1 << 24); /* not used in 243x */ | ||
328 | omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); | ||
329 | } | ||
330 | } | ||
331 | #endif | ||
313 | } | 332 | } |
314 | 333 | ||
315 | #ifdef CONFIG_ARCH_OMAP16XX | 334 | #ifdef CONFIG_ARCH_OMAP16XX |
316 | /* block 2 is on newer chips, and has many pinout options */ | 335 | /* block 2 is on newer chips, and has many pinout options */ |
317 | mmc = &mmc_conf->mmc[1]; | 336 | if (mmc_conf->mmc[1].enabled) { |
318 | if (mmc->enabled) { | 337 | if (!mmc_conf->mmc[1].nomux) { |
319 | if (!mmc->nomux) { | ||
320 | omap_cfg_reg(Y8_1610_MMC2_CMD); | 338 | omap_cfg_reg(Y8_1610_MMC2_CMD); |
321 | omap_cfg_reg(Y10_1610_MMC2_CLK); | 339 | omap_cfg_reg(Y10_1610_MMC2_CLK); |
322 | omap_cfg_reg(R18_1610_MMC2_CLKIN); | 340 | omap_cfg_reg(R18_1610_MMC2_CLKIN); |
323 | omap_cfg_reg(W8_1610_MMC2_DAT0); | 341 | omap_cfg_reg(W8_1610_MMC2_DAT0); |
324 | if (mmc->wire4) { | 342 | if (mmc_conf->mmc[1].wire4) { |
325 | omap_cfg_reg(V8_1610_MMC2_DAT1); | 343 | omap_cfg_reg(V8_1610_MMC2_DAT1); |
326 | omap_cfg_reg(W15_1610_MMC2_DAT2); | 344 | omap_cfg_reg(W15_1610_MMC2_DAT2); |
327 | omap_cfg_reg(R10_1610_MMC2_DAT3); | 345 | omap_cfg_reg(R10_1610_MMC2_DAT3); |
@@ -337,14 +355,55 @@ static void __init omap_init_mmc(void) | |||
337 | if (cpu_is_omap1710()) | 355 | if (cpu_is_omap1710()) |
338 | omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24), | 356 | omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24), |
339 | MOD_CONF_CTRL_1); | 357 | MOD_CONF_CTRL_1); |
340 | mmc2_conf = *mmc; | 358 | } |
359 | #endif | ||
360 | } | ||
361 | |||
362 | static void __init omap_init_mmc(void) | ||
363 | { | ||
364 | const struct omap_mmc_config *mmc_conf; | ||
365 | |||
366 | /* NOTE: assumes MMC was never (wrongly) enabled */ | ||
367 | mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config); | ||
368 | if (!mmc_conf) | ||
369 | return; | ||
370 | |||
371 | omap_init_mmc_conf(mmc_conf); | ||
372 | |||
373 | if (mmc_conf->mmc[0].enabled) { | ||
374 | mmc1_data.conf = mmc_conf->mmc[0]; | ||
375 | (void) platform_device_register(&mmc_omap_device1); | ||
376 | } | ||
377 | |||
378 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \ | ||
379 | defined(CONFIG_ARCH_OMAP34XX) | ||
380 | if (mmc_conf->mmc[1].enabled) { | ||
381 | mmc2_data.conf = mmc_conf->mmc[1]; | ||
341 | (void) platform_device_register(&mmc_omap_device2); | 382 | (void) platform_device_register(&mmc_omap_device2); |
342 | } | 383 | } |
343 | #endif | 384 | #endif |
344 | return; | ||
345 | } | 385 | } |
386 | |||
387 | void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info) | ||
388 | { | ||
389 | switch (host) { | ||
390 | case 1: | ||
391 | mmc1_data = *info; | ||
392 | break; | ||
393 | #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2430) || \ | ||
394 | defined(CONFIG_ARCH_OMAP34XX) | ||
395 | case 2: | ||
396 | mmc2_data = *info; | ||
397 | break; | ||
398 | #endif | ||
399 | default: | ||
400 | BUG(); | ||
401 | } | ||
402 | } | ||
403 | |||
346 | #else | 404 | #else |
347 | static inline void omap_init_mmc(void) {} | 405 | static inline void omap_init_mmc(void) {} |
406 | void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info) {} | ||
348 | #endif | 407 | #endif |
349 | 408 | ||
350 | /*-------------------------------------------------------------------------*/ | 409 | /*-------------------------------------------------------------------------*/ |
diff --git a/drivers/pcmcia/soc_common.c b/drivers/pcmcia/soc_common.c index c48f3f69bdaf..da3972153226 100644 --- a/drivers/pcmcia/soc_common.c +++ b/drivers/pcmcia/soc_common.c | |||
@@ -748,7 +748,9 @@ int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops | |||
748 | 748 | ||
749 | add_timer(&skt->poll_timer); | 749 | add_timer(&skt->poll_timer); |
750 | 750 | ||
751 | device_create_file(&skt->socket.dev, &dev_attr_status); | 751 | ret = device_create_file(&skt->socket.dev, &dev_attr_status); |
752 | if (ret) | ||
753 | goto out_err_8; | ||
752 | } | 754 | } |
753 | 755 | ||
754 | dev_set_drvdata(dev, sinfo); | 756 | dev_set_drvdata(dev, sinfo); |
@@ -758,6 +760,8 @@ int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops | |||
758 | do { | 760 | do { |
759 | skt = &sinfo->skt[i]; | 761 | skt = &sinfo->skt[i]; |
760 | 762 | ||
763 | device_remove_file(&skt->socket.dev, &dev_attr_status); | ||
764 | out_err_8: | ||
761 | del_timer_sync(&skt->poll_timer); | 765 | del_timer_sync(&skt->poll_timer); |
762 | pcmcia_unregister_socket(&skt->socket); | 766 | pcmcia_unregister_socket(&skt->socket); |
763 | 767 | ||
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 6a29f9330a73..3f90f1bbbbcd 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c | |||
@@ -127,8 +127,13 @@ | |||
127 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | 127 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ |
128 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | 128 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ |
129 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | 129 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ |
130 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ | 130 | #ifdef CONFIG_ARCH_IMX |
131 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ | 131 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */ |
132 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */ | ||
133 | #endif | ||
134 | #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3 | ||
135 | #define UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */ | ||
136 | #endif | ||
132 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ | 137 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ |
133 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ | 138 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ |
134 | #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ | 139 | #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ |
@@ -445,7 +450,7 @@ static irqreturn_t imx_int(int irq, void *dev_id) | |||
445 | readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) | 450 | readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) |
446 | imx_txint(irq, dev_id); | 451 | imx_txint(irq, dev_id); |
447 | 452 | ||
448 | if (sts & USR1_RTSS) | 453 | if (sts & USR1_RTSD) |
449 | imx_rtsint(irq, dev_id); | 454 | imx_rtsint(irq, dev_id); |
450 | 455 | ||
451 | return IRQ_HANDLED; | 456 | return IRQ_HANDLED; |
@@ -598,6 +603,12 @@ static int imx_startup(struct uart_port *port) | |||
598 | temp |= (UCR2_RXEN | UCR2_TXEN); | 603 | temp |= (UCR2_RXEN | UCR2_TXEN); |
599 | writel(temp, sport->port.membase + UCR2); | 604 | writel(temp, sport->port.membase + UCR2); |
600 | 605 | ||
606 | #if defined CONFIG_ARCH_MX2 || defined CONFIG_ARCH_MX3 | ||
607 | temp = readl(sport->port.membase + UCR3); | ||
608 | temp |= UCR3_RXDMUXSEL; | ||
609 | writel(temp, sport->port.membase + UCR3); | ||
610 | #endif | ||
611 | |||
601 | /* | 612 | /* |
602 | * Enable modem status interrupts | 613 | * Enable modem status interrupts |
603 | */ | 614 | */ |
@@ -1133,13 +1144,19 @@ static int serial_imx_probe(struct platform_device *pdev) | |||
1133 | if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS)) | 1144 | if(pdata && (pdata->flags & IMXUART_HAVE_RTSCTS)) |
1134 | sport->have_rtscts = 1; | 1145 | sport->have_rtscts = 1; |
1135 | 1146 | ||
1136 | if (pdata->init) | 1147 | if (pdata->init) { |
1137 | pdata->init(pdev); | 1148 | ret = pdata->init(pdev); |
1149 | if (ret) | ||
1150 | goto clkput; | ||
1151 | } | ||
1138 | 1152 | ||
1139 | uart_add_one_port(&imx_reg, &sport->port); | 1153 | uart_add_one_port(&imx_reg, &sport->port); |
1140 | platform_set_drvdata(pdev, &sport->port); | 1154 | platform_set_drvdata(pdev, &sport->port); |
1141 | 1155 | ||
1142 | return 0; | 1156 | return 0; |
1157 | clkput: | ||
1158 | clk_put(sport->clk); | ||
1159 | clk_disable(sport->clk); | ||
1143 | unmap: | 1160 | unmap: |
1144 | iounmap(sport->port.membase); | 1161 | iounmap(sport->port.membase); |
1145 | free: | 1162 | free: |