aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorThierry Reding <thierry.reding@gmail.com>2013-12-16 11:01:29 -0500
committerDave Airlie <airlied@redhat.com>2013-12-17 20:08:51 -0500
commit6b27f7f0e97b2819f5e272ffc2dda24881caebd6 (patch)
treef12c9b372bdc68c4941a68b99f0e126e5be3af90
parent05f51722a154e73019434bd020e50ddb941046c5 (diff)
drm/dp: Use AUX constants from specification
The current values seem to be defined in a format that's specific to the i915, gma500 and radeon drivers. To make this more generally useful, use the values as defined in the specification. While at it, prefix the constants with DP_ for improved namespacing. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/gma500/cdv_intel_dp.c37
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c37
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c36
-rw-r--r--include/drm/drm_dp_helper.h32
4 files changed, 73 insertions, 69 deletions
diff --git a/drivers/gpu/drm/gma500/cdv_intel_dp.c b/drivers/gpu/drm/gma500/cdv_intel_dp.c
index f88a1815d87c..6a7c2481d4ab 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_dp.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_dp.c
@@ -483,7 +483,7 @@ cdv_intel_dp_aux_native_write(struct gma_encoder *encoder,
483 483
484 if (send_bytes > 16) 484 if (send_bytes > 16)
485 return -1; 485 return -1;
486 msg[0] = AUX_NATIVE_WRITE << 4; 486 msg[0] = DP_AUX_NATIVE_WRITE << 4;
487 msg[1] = address >> 8; 487 msg[1] = address >> 8;
488 msg[2] = address & 0xff; 488 msg[2] = address & 0xff;
489 msg[3] = send_bytes - 1; 489 msg[3] = send_bytes - 1;
@@ -493,9 +493,10 @@ cdv_intel_dp_aux_native_write(struct gma_encoder *encoder,
493 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1); 493 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1);
494 if (ret < 0) 494 if (ret < 0)
495 return ret; 495 return ret;
496 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 496 ack >>= 4;
497 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
497 break; 498 break;
498 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 499 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
499 udelay(100); 500 udelay(100);
500 else 501 else
501 return -EIO; 502 return -EIO;
@@ -523,7 +524,7 @@ cdv_intel_dp_aux_native_read(struct gma_encoder *encoder,
523 uint8_t ack; 524 uint8_t ack;
524 int ret; 525 int ret;
525 526
526 msg[0] = AUX_NATIVE_READ << 4; 527 msg[0] = DP_AUX_NATIVE_READ << 4;
527 msg[1] = address >> 8; 528 msg[1] = address >> 8;
528 msg[2] = address & 0xff; 529 msg[2] = address & 0xff;
529 msg[3] = recv_bytes - 1; 530 msg[3] = recv_bytes - 1;
@@ -538,12 +539,12 @@ cdv_intel_dp_aux_native_read(struct gma_encoder *encoder,
538 return -EPROTO; 539 return -EPROTO;
539 if (ret < 0) 540 if (ret < 0)
540 return ret; 541 return ret;
541 ack = reply[0]; 542 ack = reply[0] >> 4;
542 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 543 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
543 memcpy(recv, reply + 1, ret - 1); 544 memcpy(recv, reply + 1, ret - 1);
544 return ret - 1; 545 return ret - 1;
545 } 546 }
546 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 547 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
547 udelay(100); 548 udelay(100);
548 else 549 else
549 return -EIO; 550 return -EIO;
@@ -569,12 +570,12 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
569 570
570 /* Set up the command byte */ 571 /* Set up the command byte */
571 if (mode & MODE_I2C_READ) 572 if (mode & MODE_I2C_READ)
572 msg[0] = AUX_I2C_READ << 4; 573 msg[0] = DP_AUX_I2C_READ << 4;
573 else 574 else
574 msg[0] = AUX_I2C_WRITE << 4; 575 msg[0] = DP_AUX_I2C_WRITE << 4;
575 576
576 if (!(mode & MODE_I2C_STOP)) 577 if (!(mode & MODE_I2C_STOP))
577 msg[0] |= AUX_I2C_MOT << 4; 578 msg[0] |= DP_AUX_I2C_MOT << 4;
578 579
579 msg[1] = address >> 8; 580 msg[1] = address >> 8;
580 msg[2] = address; 581 msg[2] = address;
@@ -606,16 +607,16 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
606 return ret; 607 return ret;
607 } 608 }
608 609
609 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 610 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
610 case AUX_NATIVE_REPLY_ACK: 611 case DP_AUX_NATIVE_REPLY_ACK:
611 /* I2C-over-AUX Reply field is only valid 612 /* I2C-over-AUX Reply field is only valid
612 * when paired with AUX ACK. 613 * when paired with AUX ACK.
613 */ 614 */
614 break; 615 break;
615 case AUX_NATIVE_REPLY_NACK: 616 case DP_AUX_NATIVE_REPLY_NACK:
616 DRM_DEBUG_KMS("aux_ch native nack\n"); 617 DRM_DEBUG_KMS("aux_ch native nack\n");
617 return -EREMOTEIO; 618 return -EREMOTEIO;
618 case AUX_NATIVE_REPLY_DEFER: 619 case DP_AUX_NATIVE_REPLY_DEFER:
619 udelay(100); 620 udelay(100);
620 continue; 621 continue;
621 default: 622 default:
@@ -624,16 +625,16 @@ cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
624 return -EREMOTEIO; 625 return -EREMOTEIO;
625 } 626 }
626 627
627 switch (reply[0] & AUX_I2C_REPLY_MASK) { 628 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
628 case AUX_I2C_REPLY_ACK: 629 case DP_AUX_I2C_REPLY_ACK:
629 if (mode == MODE_I2C_READ) { 630 if (mode == MODE_I2C_READ) {
630 *read_byte = reply[1]; 631 *read_byte = reply[1];
631 } 632 }
632 return reply_bytes - 1; 633 return reply_bytes - 1;
633 case AUX_I2C_REPLY_NACK: 634 case DP_AUX_I2C_REPLY_NACK:
634 DRM_DEBUG_KMS("aux_i2c nack\n"); 635 DRM_DEBUG_KMS("aux_i2c nack\n");
635 return -EREMOTEIO; 636 return -EREMOTEIO;
636 case AUX_I2C_REPLY_DEFER: 637 case DP_AUX_I2C_REPLY_DEFER:
637 DRM_DEBUG_KMS("aux_i2c defer\n"); 638 DRM_DEBUG_KMS("aux_i2c defer\n");
638 udelay(100); 639 udelay(100);
639 break; 640 break;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7c54f6267a1f..36f13c574571 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -542,7 +542,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
542 return -E2BIG; 542 return -E2BIG;
543 543
544 intel_dp_check_edp(intel_dp); 544 intel_dp_check_edp(intel_dp);
545 msg[0] = AUX_NATIVE_WRITE << 4; 545 msg[0] = DP_AUX_NATIVE_WRITE << 4;
546 msg[1] = address >> 8; 546 msg[1] = address >> 8;
547 msg[2] = address & 0xff; 547 msg[2] = address & 0xff;
548 msg[3] = send_bytes - 1; 548 msg[3] = send_bytes - 1;
@@ -552,9 +552,10 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 552 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
553 if (ret < 0) 553 if (ret < 0)
554 return ret; 554 return ret;
555 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 555 ack >>= 4;
556 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
556 break; 557 break;
557 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 558 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
558 udelay(100); 559 udelay(100);
559 else 560 else
560 return -EIO; 561 return -EIO;
@@ -586,7 +587,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
586 return -E2BIG; 587 return -E2BIG;
587 588
588 intel_dp_check_edp(intel_dp); 589 intel_dp_check_edp(intel_dp);
589 msg[0] = AUX_NATIVE_READ << 4; 590 msg[0] = DP_AUX_NATIVE_READ << 4;
590 msg[1] = address >> 8; 591 msg[1] = address >> 8;
591 msg[2] = address & 0xff; 592 msg[2] = address & 0xff;
592 msg[3] = recv_bytes - 1; 593 msg[3] = recv_bytes - 1;
@@ -601,12 +602,12 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
601 return -EPROTO; 602 return -EPROTO;
602 if (ret < 0) 603 if (ret < 0)
603 return ret; 604 return ret;
604 ack = reply[0]; 605 ack = reply[0] >> 4;
605 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 606 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
606 memcpy(recv, reply + 1, ret - 1); 607 memcpy(recv, reply + 1, ret - 1);
607 return ret - 1; 608 return ret - 1;
608 } 609 }
609 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 610 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
610 udelay(100); 611 udelay(100);
611 else 612 else
612 return -EIO; 613 return -EIO;
@@ -633,12 +634,12 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
633 intel_dp_check_edp(intel_dp); 634 intel_dp_check_edp(intel_dp);
634 /* Set up the command byte */ 635 /* Set up the command byte */
635 if (mode & MODE_I2C_READ) 636 if (mode & MODE_I2C_READ)
636 msg[0] = AUX_I2C_READ << 4; 637 msg[0] = DP_AUX_I2C_READ << 4;
637 else 638 else
638 msg[0] = AUX_I2C_WRITE << 4; 639 msg[0] = DP_AUX_I2C_WRITE << 4;
639 640
640 if (!(mode & MODE_I2C_STOP)) 641 if (!(mode & MODE_I2C_STOP))
641 msg[0] |= AUX_I2C_MOT << 4; 642 msg[0] |= DP_AUX_I2C_MOT << 4;
642 643
643 msg[1] = address >> 8; 644 msg[1] = address >> 8;
644 msg[2] = address; 645 msg[2] = address;
@@ -675,17 +676,17 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
675 goto out; 676 goto out;
676 } 677 }
677 678
678 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 679 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
679 case AUX_NATIVE_REPLY_ACK: 680 case DP_AUX_NATIVE_REPLY_ACK:
680 /* I2C-over-AUX Reply field is only valid 681 /* I2C-over-AUX Reply field is only valid
681 * when paired with AUX ACK. 682 * when paired with AUX ACK.
682 */ 683 */
683 break; 684 break;
684 case AUX_NATIVE_REPLY_NACK: 685 case DP_AUX_NATIVE_REPLY_NACK:
685 DRM_DEBUG_KMS("aux_ch native nack\n"); 686 DRM_DEBUG_KMS("aux_ch native nack\n");
686 ret = -EREMOTEIO; 687 ret = -EREMOTEIO;
687 goto out; 688 goto out;
688 case AUX_NATIVE_REPLY_DEFER: 689 case DP_AUX_NATIVE_REPLY_DEFER:
689 /* 690 /*
690 * For now, just give more slack to branch devices. We 691 * For now, just give more slack to branch devices. We
691 * could check the DPCD for I2C bit rate capabilities, 692 * could check the DPCD for I2C bit rate capabilities,
@@ -706,18 +707,18 @@ intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
706 goto out; 707 goto out;
707 } 708 }
708 709
709 switch (reply[0] & AUX_I2C_REPLY_MASK) { 710 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
710 case AUX_I2C_REPLY_ACK: 711 case DP_AUX_I2C_REPLY_ACK:
711 if (mode == MODE_I2C_READ) { 712 if (mode == MODE_I2C_READ) {
712 *read_byte = reply[1]; 713 *read_byte = reply[1];
713 } 714 }
714 ret = reply_bytes - 1; 715 ret = reply_bytes - 1;
715 goto out; 716 goto out;
716 case AUX_I2C_REPLY_NACK: 717 case DP_AUX_I2C_REPLY_NACK:
717 DRM_DEBUG_KMS("aux_i2c nack\n"); 718 DRM_DEBUG_KMS("aux_i2c nack\n");
718 ret = -EREMOTEIO; 719 ret = -EREMOTEIO;
719 goto out; 720 goto out;
720 case AUX_I2C_REPLY_DEFER: 721 case DP_AUX_I2C_REPLY_DEFER:
721 DRM_DEBUG_KMS("aux_i2c defer\n"); 722 DRM_DEBUG_KMS("aux_i2c defer\n");
722 udelay(100); 723 udelay(100);
723 break; 724 break;
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index fb3ae07a1469..37289f67f965 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -157,7 +157,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
157 157
158 msg[0] = address; 158 msg[0] = address;
159 msg[1] = address >> 8; 159 msg[1] = address >> 8;
160 msg[2] = AUX_NATIVE_WRITE << 4; 160 msg[2] = DP_AUX_NATIVE_WRITE << 4;
161 msg[3] = (msg_bytes << 4) | (send_bytes - 1); 161 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
162 memcpy(&msg[4], send, send_bytes); 162 memcpy(&msg[4], send, send_bytes);
163 163
@@ -168,9 +168,10 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
168 continue; 168 continue;
169 else if (ret < 0) 169 else if (ret < 0)
170 return ret; 170 return ret;
171 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 171 ack >>= 4;
172 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
172 return send_bytes; 173 return send_bytes;
173 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 174 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
174 udelay(400); 175 udelay(400);
175 else 176 else
176 return -EIO; 177 return -EIO;
@@ -191,7 +192,7 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
191 192
192 msg[0] = address; 193 msg[0] = address;
193 msg[1] = address >> 8; 194 msg[1] = address >> 8;
194 msg[2] = AUX_NATIVE_READ << 4; 195 msg[2] = DP_AUX_NATIVE_READ << 4;
195 msg[3] = (msg_bytes << 4) | (recv_bytes - 1); 196 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
196 197
197 for (retry = 0; retry < 4; retry++) { 198 for (retry = 0; retry < 4; retry++) {
@@ -201,9 +202,10 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
201 continue; 202 continue;
202 else if (ret < 0) 203 else if (ret < 0)
203 return ret; 204 return ret;
204 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 205 ack >>= 4;
206 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
205 return ret; 207 return ret;
206 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 208 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
207 udelay(400); 209 udelay(400);
208 else if (ret == 0) 210 else if (ret == 0)
209 return -EPROTO; 211 return -EPROTO;
@@ -246,12 +248,12 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
246 248
247 /* Set up the command byte */ 249 /* Set up the command byte */
248 if (mode & MODE_I2C_READ) 250 if (mode & MODE_I2C_READ)
249 msg[2] = AUX_I2C_READ << 4; 251 msg[2] = DP_AUX_I2C_READ << 4;
250 else 252 else
251 msg[2] = AUX_I2C_WRITE << 4; 253 msg[2] = DP_AUX_I2C_WRITE << 4;
252 254
253 if (!(mode & MODE_I2C_STOP)) 255 if (!(mode & MODE_I2C_STOP))
254 msg[2] |= AUX_I2C_MOT << 4; 256 msg[2] |= DP_AUX_I2C_MOT << 4;
255 257
256 msg[0] = address; 258 msg[0] = address;
257 msg[1] = address >> 8; 259 msg[1] = address >> 8;
@@ -282,16 +284,16 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
282 return ret; 284 return ret;
283 } 285 }
284 286
285 switch (ack & AUX_NATIVE_REPLY_MASK) { 287 switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
286 case AUX_NATIVE_REPLY_ACK: 288 case DP_AUX_NATIVE_REPLY_ACK:
287 /* I2C-over-AUX Reply field is only valid 289 /* I2C-over-AUX Reply field is only valid
288 * when paired with AUX ACK. 290 * when paired with AUX ACK.
289 */ 291 */
290 break; 292 break;
291 case AUX_NATIVE_REPLY_NACK: 293 case DP_AUX_NATIVE_REPLY_NACK:
292 DRM_DEBUG_KMS("aux_ch native nack\n"); 294 DRM_DEBUG_KMS("aux_ch native nack\n");
293 return -EREMOTEIO; 295 return -EREMOTEIO;
294 case AUX_NATIVE_REPLY_DEFER: 296 case DP_AUX_NATIVE_REPLY_DEFER:
295 DRM_DEBUG_KMS("aux_ch native defer\n"); 297 DRM_DEBUG_KMS("aux_ch native defer\n");
296 udelay(400); 298 udelay(400);
297 continue; 299 continue;
@@ -300,15 +302,15 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
300 return -EREMOTEIO; 302 return -EREMOTEIO;
301 } 303 }
302 304
303 switch (ack & AUX_I2C_REPLY_MASK) { 305 switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) {
304 case AUX_I2C_REPLY_ACK: 306 case DP_AUX_I2C_REPLY_ACK:
305 if (mode == MODE_I2C_READ) 307 if (mode == MODE_I2C_READ)
306 *read_byte = reply[0]; 308 *read_byte = reply[0];
307 return ret; 309 return ret;
308 case AUX_I2C_REPLY_NACK: 310 case DP_AUX_I2C_REPLY_NACK:
309 DRM_DEBUG_KMS("aux_i2c nack\n"); 311 DRM_DEBUG_KMS("aux_i2c nack\n");
310 return -EREMOTEIO; 312 return -EREMOTEIO;
311 case AUX_I2C_REPLY_DEFER: 313 case DP_AUX_I2C_REPLY_DEFER:
312 DRM_DEBUG_KMS("aux_i2c defer\n"); 314 DRM_DEBUG_KMS("aux_i2c defer\n");
313 udelay(400); 315 udelay(400);
314 break; 316 break;
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index a92c3754e3bb..c873f9ce5871 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -41,22 +41,22 @@
41 * 1.2 formally includes both eDP and DPI definitions. 41 * 1.2 formally includes both eDP and DPI definitions.
42 */ 42 */
43 43
44#define AUX_NATIVE_WRITE 0x8 44#define DP_AUX_I2C_WRITE 0x0
45#define AUX_NATIVE_READ 0x9 45#define DP_AUX_I2C_READ 0x1
46#define AUX_I2C_WRITE 0x0 46#define DP_AUX_I2C_STATUS 0x2
47#define AUX_I2C_READ 0x1 47#define DP_AUX_I2C_MOT 0x4
48#define AUX_I2C_STATUS 0x2 48#define DP_AUX_NATIVE_WRITE 0x8
49#define AUX_I2C_MOT 0x4 49#define DP_AUX_NATIVE_READ 0x9
50 50
51#define AUX_NATIVE_REPLY_ACK (0x0 << 4) 51#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
52#define AUX_NATIVE_REPLY_NACK (0x1 << 4) 52#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
53#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) 53#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
54#define AUX_NATIVE_REPLY_MASK (0x3 << 4) 54#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
55 55
56#define AUX_I2C_REPLY_ACK (0x0 << 6) 56#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
57#define AUX_I2C_REPLY_NACK (0x1 << 6) 57#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
58#define AUX_I2C_REPLY_DEFER (0x2 << 6) 58#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
59#define AUX_I2C_REPLY_MASK (0x3 << 6) 59#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
60 60
61/* AUX CH addresses */ 61/* AUX CH addresses */
62/* DPCD */ 62/* DPCD */