diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2014-09-23 09:40:24 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2014-10-01 09:00:06 -0400 |
commit | 6aff1e282a5d811904d3d74c8382080ee57ba4c7 (patch) | |
tree | adadf9ecec750d24492ac8547452206235342dd2 | |
parent | 186b1b2ba2a0684e3d2d3703427a993a3b35b16d (diff) |
drm/radeon/dpm: drop clk/voltage dependency filters for CI
Not sure this was ever necessary for CI, was just done
to be on the safe side.
bug:
https://bugs.freedesktop.org/show_bug.cgi?id=69721
Reviewed-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/radeon/ci_dpm.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index d416bb2ff48d..d199be32d5dc 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c | |||
@@ -162,8 +162,6 @@ static const struct ci_pt_config_reg didt_config_ci[] = | |||
162 | }; | 162 | }; |
163 | 163 | ||
164 | extern u8 rv770_get_memory_module_index(struct radeon_device *rdev); | 164 | extern u8 rv770_get_memory_module_index(struct radeon_device *rdev); |
165 | extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table, | ||
166 | u32 *max_clock); | ||
167 | extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, | 165 | extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev, |
168 | u32 arb_freq_src, u32 arb_freq_dest); | 166 | u32 arb_freq_src, u32 arb_freq_dest); |
169 | extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); | 167 | extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); |
@@ -748,7 +746,6 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev, | |||
748 | struct radeon_clock_and_voltage_limits *max_limits; | 746 | struct radeon_clock_and_voltage_limits *max_limits; |
749 | bool disable_mclk_switching; | 747 | bool disable_mclk_switching; |
750 | u32 sclk, mclk; | 748 | u32 sclk, mclk; |
751 | u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; | ||
752 | int i; | 749 | int i; |
753 | 750 | ||
754 | if (rps->vce_active) { | 751 | if (rps->vce_active) { |
@@ -784,29 +781,6 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev, | |||
784 | } | 781 | } |
785 | } | 782 | } |
786 | 783 | ||
787 | /* limit clocks to max supported clocks based on voltage dependency tables */ | ||
788 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, | ||
789 | &max_sclk_vddc); | ||
790 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, | ||
791 | &max_mclk_vddci); | ||
792 | btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, | ||
793 | &max_mclk_vddc); | ||
794 | |||
795 | for (i = 0; i < ps->performance_level_count; i++) { | ||
796 | if (max_sclk_vddc) { | ||
797 | if (ps->performance_levels[i].sclk > max_sclk_vddc) | ||
798 | ps->performance_levels[i].sclk = max_sclk_vddc; | ||
799 | } | ||
800 | if (max_mclk_vddci) { | ||
801 | if (ps->performance_levels[i].mclk > max_mclk_vddci) | ||
802 | ps->performance_levels[i].mclk = max_mclk_vddci; | ||
803 | } | ||
804 | if (max_mclk_vddc) { | ||
805 | if (ps->performance_levels[i].mclk > max_mclk_vddc) | ||
806 | ps->performance_levels[i].mclk = max_mclk_vddc; | ||
807 | } | ||
808 | } | ||
809 | |||
810 | /* XXX validate the min clocks required for display */ | 784 | /* XXX validate the min clocks required for display */ |
811 | 785 | ||
812 | if (disable_mclk_switching) { | 786 | if (disable_mclk_switching) { |